Etching method and etching apparatus

Abstract

To etch a silicon oxide film formed on the front surface of a substrate while suppressing etching of a silicon-containing film formed on the rear surface of the substrate. [Solution] The etching method of the present disclosure includes a step of repeating a cycle consisting of a first step of supplying a processing gas into a processing vessel storing substrates having a silicon oxide film formed on a front surface and a silicon-containing film formed on a back surface, to generate a reaction product between the silicon oxide film and the processing gas, and a second step of evacuating the processing vessel while stopping the supply of the processing gas into the processing vessel to remove the reaction product, and a step of performing the first step in a first of the cycles under processing conditions different from those of the first step in subsequent cycles in order to remove an oxide layer formed by oxidizing the silicon-containing film.

Description

[Technical Field]

[0001] The present disclosure relates to an etching method and an etching apparatus. [Background technology]

[0002] In manufacturing semiconductor devices, etching is performed on a film formed on the surface of a semiconductor wafer (hereinafter referred to as a wafer), which is a substrate. Patent Document 1 describes a method for performing ashing to remove a carbon-containing film adhering to the backside of the peripheral edge of the substrate during etching, without adhering the wafer to an electrostatic chuck or supplying a heat transfer gas that transfers heat from the electrostatic chuck to the backside of the wafer. This method promotes the ashing gas supplied to the front side of the wafer to reach the peripheral edge of the backside of the wafer. Patent Document 2 describes an apparatus for forming a local plasma in a region extending from the peripheral edge of the front side of the wafer, across the side, to the peripheral edge of the backside of the wafer, and removing a film formed in that region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-93558 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-120875 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a technique that can etch a silicon oxide film formed on a front surface of a substrate while suppressing etching of a silicon-containing film formed on the rear surface of the substrate. [Means for solving the problem]

[0005] The etching method of the present disclosure includes a first step of supplying a processing gas into a processing vessel storing a substrate having a silicon oxide film formed on a front surface and a silicon-containing film formed on a rear surface thereof, to generate a reaction product between the silicon oxide film and the processing gas, and a second step of evacuating the processing vessel while stopping the supply of the processing gas into the processing vessel to remove the reaction product, the second step comprising: performing a first step in a first cycle of the cycles under different processing conditions from the first step in a subsequent cycle to remove an oxide layer formed by oxidizing the silicon-containing film; Includes. [Effects of the Invention]

[0006] The present disclosure makes it possible to etch a silicon oxide film formed on a front surface of a substrate while suppressing etching of a silicon-containing film formed on a rear surface of the substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a vertical cross-sectional side view of an etching module for performing an etching process according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a longitudinal sectional side view of a wafer being processed in the etching module. [Figure 3] FIG. 2 is a vertical cross-sectional side view showing the configuration of the front surface side of the wafer. [Figure 4] FIG. 10 is a flowchart showing a process flow in a comparative example. [Figure 5] FIG. 10 is a schematic diagram showing a wafer that changes in a comparative example. [Figure 6] FIG. 10 is a schematic diagram of a processed wafer in a comparative example. [Figure 7] FIG. 1 is a flowchart showing a processing flow in an embodiment. [Figure 8] 1A to 1C are process diagrams showing wafer processing steps in an embodiment. [Figure 9] 1A to 1C are process diagrams showing wafer processing steps in an embodiment. [Figure 10] FIG. 10 is a vertical cross-sectional side view of a wafer after processing in an embodiment. [Figure 11] FIG. 4 is a chart illustrating the state inside the processing container in the processing of the example. [Figure 12] FIG. 2 is a plan view of the substrate processing apparatus including the etching module. [Figure 13] FIG. 10 is a graph showing the results of an evaluation test. DETAILED DESCRIPTION OF THE INVENTION

[0008] In one embodiment of the etching method of the present disclosure, etching is performed using a processing gas to remove an SiO2 (silicon oxide) film formed on the surface of a wafer W. More specifically, etching called COR (Chemical Oxide Removal) is performed by supplying HF (hydrogen fluoride) gas, which is a halogen-containing gas, and NH3 (ammonia) gas, which is a basic gas, to the wafer W as processing gases, thereby generating reaction products between these gases and the SiO2 film, and vaporizing and removing these reaction products.

[0009] FIG. 1 is a longitudinal side view of an etching module 1, which is an example of an etching apparatus for performing the COR process. Reference numeral 11 in the figure denotes a processing chamber constituting the etching module 1. Reference numeral 12 denotes a wafer W transfer port opening in the sidewall of the processing chamber 11 and opened and closed by a gate valve 13. A stage 21 on which the wafer W is placed is provided within the processing chamber 11. A plurality of protruding pins 22 are distributed on the upper surface of the stage 21, and the backside of the wafer W is supported by each of the pins 22. Support by the pins 22 reduces the contact area of ​​the backside of the wafer W with the stage 21, thereby suppressing the adhesion of foreign matter to the backside. A gap is formed between an area on the upper surface of the stage 21 where the pins 22 are not formed and an area on the backside of the wafer W that is not in contact with the pins 22. The stage 21 is provided with a support member (not shown) that is raised and lowered by a lifting mechanism. The wafer W is transferred between the stage 21 and a second substrate transfer mechanism 72 (described later) via the support member.

[0010] A temperature adjustment unit 23 is embedded in the stage 21, and the wafer W placed on the stage 21 is heated to a predetermined temperature, for example, a temperature of 50° C. or higher. The temperature adjustment unit 23 is configured as a flow path that forms part of a circulation path through which a temperature adjustment fluid, such as water, flows, and adjusts the temperature of the wafer W by heat exchange with the fluid. However, the temperature adjustment unit 23 is not limited to being a flow path for such a fluid, and may be configured as, for example, a heater for performing resistance heating.

[0011] One end of an exhaust pipe 14 opens into the processing vessel 11, and the other end of the exhaust pipe 14 is connected to an exhaust mechanism 16, which is constituted by, for example, a vacuum pump, via a valve 15, which is a pressure change mechanism. By adjusting the opening of the valve 15, the pressure inside the processing vessel 11 is set to a pressure range described below, and processing is performed.

[0012] A gas shower head 17 is provided at the upper side of the processing vessel 11 so as to face the stage 21. is provided, and the gas shower head 17 discharges gas toward the surface of the wafer W on the stage 21. The downstream sides of gas supply paths 31 to 34 are connected to the gas shower head 17, and the upstream sides of the gas supply paths 31 to 34 are connected to gas supply sources 36 to 39 via flow rate adjusters 35, respectively. Each flow rate adjuster 35 includes a valve and a mass flow controller. The gas supplied from the gas supply sources 36 to 39 is supplied downstream and cut off by opening and closing the valves included in the flow rate adjuster 35.

[0013] Gas supply sources 36, 37, 38, and 39 supply HF gas, NH3 gas, N2 (nitrogen) gas, and Ar (argon) gas, respectively. Therefore, HF gas, NH3 gas, N2 gas, and Ar gas can be supplied into the processing vessel 11 from the gas shower head 17. The gas supply sources 36 and 37 and the flow rate adjusters 35 provided on the gas supply paths 31 and 32 correspond to a processing gas supply mechanism. Ar gas and N2 gas are supplied as carrier gases into the processing vessel 11 together with the processing gases HF gas and NH3 gas. Furthermore, N2 gas and Ar gas are supplied after the supply of the processing gas into the processing vessel 11 is stopped, and also function as purge gases for purging the processing gas remaining in the processing vessel 11. In the following description, the value obtained by dividing the flow rate of HF gas supplied into the processing vessel 11 by the flow rate of NH3 gas supplied into the processing vessel 11 (i.e., the ratio of the flow rate of HF gas supplied into the processing vessel 11 to the flow rate of NH3 gas supplied into the processing vessel 11) may be referred to as HF gas flow rate / NH3 gas flow rate.

[0014] 2 shows a longitudinal cross-sectional side view of a wafer W placed on the stage 21 before processing in the etching module 1. The front surface of the wafer W faces upward. More specifically, this front surface (top surface) is the device formation surface on which semiconductor devices are formed. The above-mentioned SiO2 film 41 is formed on this front surface, while a SiN (silicon nitride) film 42, which is a silicon-containing film, is formed on the back surface (bottom surface) of the wafer W. The surface layer of this SiN film 42 is oxidized to form an oxide layer 43. This oxide layer 43 is formed, for example, by processing the wafer W before processing in the etching module 1 or by natural oxidation.

[0015] 3 is a longitudinal side view showing an example of the structure of the surface of a wafer W, with the upper side of FIG. 3 showing the wafer W before processing by the etching module 1 and the lower side of FIG. 3 showing the wafer W after processing by the etching module 1. A plurality of recesses 46 are formed in a layer 45 made of, for example, Si (silicon) provided on the surface of the wafer W. The recesses 46 have different widths, and narrow recesses 46 may be referred to as recesses 46A and wide recesses 46 may be referred to as recesses 46B. An SiO2 film 41 is embedded in each recess 46.

[0016] When etching the SiO2 film 41, it is necessary to suppress etching of the SiN film 42. As will be shown in the evaluation tests described later, the process of this embodiment (hereinafter sometimes referred to as the process of the example) can meet this requirement. Furthermore, the SiO2 film 41 is etched, for example, so that a portion of the film remains in each recess 46. When performing the etching so that a portion remains, it is necessary to uniform the height of the remaining SiO2 film 41 at each position within the same recess 46. In other words, it is necessary to increase the flatness of the top surface of the SiO2 film 41 remaining in the recess 46. It is also necessary to uniform the amount of etching between the recesses 46A and 46B, which have different widths. As will be described in the evaluation tests, the process of the example can also meet the requirement of improving the post-etching condition of the SiO2 film 41. The lower part of FIG. 3 shows the etching performed so that the post-etching condition of the SiO2 film 41 is good.

[0017] In order to clearly show the effect of suppressing etching of the SiN film 42 in the process of the embodiment, the process of the comparative example will first be described with reference to Fig. 4 and Figs. 5 to 6. Fig. 4 is a flowchart of the process of the comparative example. Figs. 5 to 6 are schematic diagrams showing the wafer W on the stage 21 as it changes during the process of the comparative example. In Figs. 5 and 6, HF gas is indicated as 51 and NH3 gas as 52. Also, the sublimate of the reaction product between these process gases (HF gas 51 and NH3 gas 52) and the film on the wafer W is indicated as 50.

[0018] 2 is placed on the stage 21 and heated to a predetermined temperature, and the interior of the processing chamber 11 is maintained at a predetermined vacuum pressure. Then, HF gas 51, NH gas 52, N gas, and Ar gas are supplied into the processing chamber 11 at predetermined flow rates (step S11, left side of FIG. 5). These gases react with the SiO film 41 on the surface of the wafer W, and the surface layer of the SiO film 41 becomes an altered layer 44 containing AFS, which is a reaction product.

[0019] While the front surface of the wafer W is changing in this way, a gap is formed between the back surface of the wafer W supported by the pins 22 and the stage 21, so the HF gas 51 and the NH3 gas 52 move from the front surface to the back surface of the wafer W and react with the oxide layer 43. The oxide layer 43 then changes into an altered layer 44 containing AFS. Note that the front surface-side altered layer 44 and the back surface-side altered layer 44 are layers formed from oxides of the SiO2 film 41 and the SiN film 42, respectively, and therefore may contain different components. However, for convenience, they are not distinguished from each other and are referred to as the same altered layer 44.

[0020] Since the HF gas 51 and the NH3 gas 52 are supplied in large amounts to the peripheral portion of the rear surface of the wafer W, the amount of change to the above-mentioned altered layer 44 is large. The amount of AFS generated is large in the peripheral portion of the rear surface of the wafer W. Since the AFS is reactive with the SiN film 42, the portion of the SiN film 42 in the peripheral portion of the rear surface of the wafer W is also altered to become the altered layer 44.

[0021] After a predetermined time has elapsed since the start of supplying HF gas 51 and NH3 gas 52 into processing chamber 11, the supply of HF gas 51 and NH3 gas 52 into processing chamber 11 is stopped, and N2 gas and Ar gas continue to be supplied into processing chamber 11 as purge gases to purge the HF gas and NH3 gas remaining in processing chamber 11 (step S12, center of FIG. 5). The affected layers 44 formed on the front and back surfaces of wafer W are sublimated and removed by the action of the exhaust flow of the purge gas inside processing chamber 11 and heating by stage 21. Therefore, not only the SiO2 film 41 on the front surface of wafer W but also the SiN film 42 on the peripheral edge of the back surface of wafer W is etched.

[0022] After a predetermined time has elapsed since the supply of the HF gas 51 and the NH3 gas 52 into the processing chamber 11 was stopped, the supply of the HF gas 51 and the NH3 gas 52 into the processing chamber 11 is resumed. That is, step S11 is performed again. Thereafter, the supply of the HF gas 51 and the NH3 gas 52 is stopped, and step S12 is performed again. Thereafter, the cycle consisting of steps S11 and S12 is repeated, and the SiO2 film 41 on the front surface of the wafer W is etched, while the SiN film 42 on the peripheral portion of the back surface of the wafer W is etched.

[0023] When the control unit 100, which controls the operation of the etching module 1 described below, determines that the cycle consisting of steps S11 and S12 has been performed a predetermined number of times (step S13), the repetition of steps S11 and S12 stops, and the wafer W is unloaded from the processing chamber 11. The wafer W is then transferred to a heat treatment module 70 described below and subjected to a heat treatment at a relatively high temperature, whereby the affected layer 44 remaining on the wafer W is removed as a sublimate 50 (step S14, right side of FIG. 5). FIG. 6 shows the wafer W after step S14 is completed.

[0024] As described above, the oxide layer 43 formed on the back surface of the wafer W contains silicon and oxygen, just like the SiO2 film 41 to be etched on the front surface of the wafer W, and therefore reacts with the processing gas (HF gas and NH3 gas) to generate reaction products, which react with the SiN film 42 and alter the SiN film 42. As a result, the etching amount of the SiN film 42 becomes relatively large at the peripheral portion of the wafer W, where a large amount of processing gas is supplied.

[0025] Therefore, in the process of this embodiment, processing conditions suitable for removing the oxide layer 43 are set and processing is performed, and then the processing conditions are changed to remove the SiO2 film 41. The process of this embodiment will be described below with reference to Figures 7 to 11. Figure 7 is a flowchart showing the processing flow of this embodiment, and Figures 8 to 10 are schematic diagrams showing the wafer W on the stage 21 that change during the processing of this embodiment. Figure 11 is a time chart showing the timing of supplying processing gases (HF gas and NH3 gas), pressure changes within the processing vessel 11, the HF gas flow rate / NH3 gas flow rate at each step during processing, and the steps that are performed.

[0026] The wafer W shown in FIG. 2 is placed on the stage 21 and heated to a predetermined temperature. Then, the pressure inside the processing chamber 11 is set to a relatively low pressure A1 Torr to increase the gas diffusibility. Specifically, this pressure A1 Torr is set to, for example, 11 Torr (1.47×10 3 The pressure is lower than 3 Torr (400 Pa), more specifically, for example, 3 Torr (400 Pa) or lower. Then, HF gas 51, NH gas 52, N gas, and Ar gas are supplied into the processing chamber 11 at predetermined flow rates of D1 sccm, D2 sccm, D3 sccm, and D4 sccm, respectively (step S1, time t1).

[0027] The SiO2 film 41 on the front surface of the wafer W reacts with the processing gas (HF gas 51 and NH3 gas 52), and the surface layer becomes an altered layer 44. Meanwhile, because the pressure inside the processing vessel 11 is low, a relatively large amount of the processing gas supplied to the front surface of the wafer W flows around to the back surface of the wafer W and is supplied not only to the peripheral portion of the wafer W but also toward the center. As a result, the processing gas is sufficiently supplied to the entire back surface of the wafer W, and the entire oxide layer 43 becomes an altered layer 44 (left side of FIG. 8).

[0028] At time t2, a predetermined time after time t1, the supply of processing gases (HF gas 51 and NH3 gas 52) into the processing vessel 11 is stopped, and the pressure is reduced from A1 Torr to A2 Torr (step S2). N2 gas and Ar gas continue to be supplied into the processing vessel 11 as purge gases. Due to the action of the exhaust flow inside the processing vessel 11 caused by this purge gas and the heating by the stage 21, the affected layers 44 on the front and back surfaces of the wafer W are sublimated and removed (right side of FIG. 8). Because the pressure inside the processing vessel 11 is relatively low, the affected layers 44 are removed efficiently. This step S2 is performed for a sufficiently long time so that all of the affected layer 44 on the back surface of the wafer W is removed.

[0029] At time t3, a predetermined time after time t2, the supply of processing gases (HF gas 51 and NH3 gas 52) into the processing vessel 11 is resumed, and the pressure inside the processing vessel 11 is increased to A3 Torr, which is higher than A1 Torr, thereby completing step S2 and starting step S3. The above-mentioned A3 Torr is, for example, 11 Torr or higher. In step S3, HF gas 51, NH3 gas 52, N2 gas, and Ar gas are supplied into the processing vessel 11 at predetermined flow rates of E1 sccm, E2 sccm, E3 sccm, and E4 sccm, respectively. To ensure a relatively high pressure inside the processing vessel 11, the flow rates of these gases are higher than those of the gases in step S1. That is, E1>D1, E2>D2, E3>D3, and E4>D4.

[0030] The process of step S3 is the same as step S11 described in the comparative example, and the surface layer of the SiO2 film 41 on the front surface of the wafer W is transformed into an altered layer 44 (left side of FIG. 9). However, unlike step S11, step S3 removes the oxide layer 43 on the rear surface of the wafer W, so that even if the processing gas reaches the rear surface of the wafer W, a new altered layer 44 is prevented from being generated on the rear surface. Therefore, the SiN film 42 is prevented from reacting with the altered layer 44 and becoming the altered layer 44.

[0031] At time t4, a predetermined time after time t3, the supply of HF gas 51 and NH3 gas 52 into the processing chamber 11 is stopped, and the affected layer 44 on the front surface of the wafer W is removed by the action of the exhaust flow in the processing chamber 11 caused by the purge gas (N2 gas and Ar gas) and heating by the stage 21 (step S4, center of FIG. 9). The pressure in the processing chamber 11 in step S4 is set to, for example, A3 Torr, the same as in step S3. The process in step S4 is the same as step S12 described in the comparative example. However, since the affected layer 44 is not formed on the back surface of the wafer W, sublimation of the affected layer 44 from the back surface of the wafer W does not occur.

[0032] Then, at time t5, when a predetermined time has elapsed since time t4, the HF gas 51 and the NH3 gas 52 are supplied into the processing vessel 11 again, and step S3 is resumed. After step S3, step S4 is performed again. Thereafter, steps S3 and S4 are repeatedly performed.

[0033] Here, the processes of steps S1 to S4 will be explained in more detail. As will be described later in the evaluation test, in order to improve the state of the SiO2 film 41 after etching (to increase the flatness of the upper surface of the SiO2 film 41 and reduce the difference in the amount of etching between the recesses 46A and 46B), it is preferable to set the flow rate of the HF gas 51 (E1 sccm) / the flow rate of the NH3 gas 52 (E2 sccm) to a relatively high value in step S3. Specifically, E1 / E2 in step S3 is set to, for example, 8 or more. However, the process gas has the effect of reacting with and altering not only the SiO2 film 41 but also the SiN film 42. The greater the value of the flow rate of the HF gas 51 / the flow rate of the NH3 gas 52, the higher the reactivity of the process gas with the SiN film 42. Therefore, in step S1, where the pressure is set to a relatively low value so that the gas flows around to the backside of the wafer W, it is preferable to set the flow rate of the HF gas 51 / the flow rate of the NH3 gas 52 to a relatively low value so as to suppress etching of the SiN film 42. Therefore, when comparing the flow rate of HF gas 51 / NH3 gas 52 (=D1 / D2) in step S1 with the flow rate of HF gas 51 / NH3 gas 52 (=E1 / E2) in step S3, it is preferable to set D1 / D2 to be smaller.

[0034] Furthermore, as described above, the processing gas alters the SiN film 42. As will be shown later in the evaluation test, increasing the pressure in the processing vessel 11 directs the processing gas that has reached the backside of the wafer W toward the center, preventing the SiN film 42 in the center from being altered and ultimately removed. Therefore, the pressure in the processing vessel 11 is set relatively high in step S3. Therefore, the pressure A1 in the processing vessel 11 in step S1, which allows the processing gas to sufficiently reach the backside of the wafer W to remove the oxide layer 43, is lower than the pressure A3 in the processing vessel 11 in step S3. In other words, setting the pressure A1 in step S1 lower than the pressure A3 in step S3 is preferable because it allows the oxide layer 43 to be removed more reliably in step S1 and also prevents etching of the SiN film in the center of the wafer W in step S3.

[0035] Even if the pressure in the processing chamber 11 is increased in step S3, the SiN film 42 is more likely to be etched at the peripheral portion of the wafer W than at the center of the wafer W. To suppress etching of the SiN film 42 at the peripheral portion, the execution time of step S3 (times t3 to t4) is set relatively short. On the other hand, to reliably convert the oxide layer 43 into the altered layer 44 and remove it, a sufficient execution time (times t1 to t2) must be ensured in step S1. For these reasons, the execution time (the supply time of the processing gas) of step S1 is set longer than that of step S3, for example. In other words, by making the execution time of step S1 longer than that of step S3, the oxide layer 43 can be removed more reliably in step S1 and etching of the SiN film 42 can be suppressed in step S3, which is preferable. Based on the evaluation test described below, the execution time of step S3 is preferably set to, for example, 3 seconds or less.

[0036] Furthermore, if the altered layer 44 remains on the back surface of the wafer W, it will alter the SiN film 42, so to reliably prevent this, the implementation time of step S2 (times t2 to t3) is longer than the implementation time of step S4 (times t4 to t5). For example, if the implementation time of step S4 is L1, the implementation time of step S2 is, for example, at least twice L1, and more specifically, at least six times L1.

[0037] When the control unit 100 determines that steps S3 and S4 have been performed a predetermined number of times (step S5), the repeated cycle of steps S3 and S4 stops, and the wafer W is unloaded from the processing chamber 11 and transferred to the heat treatment module 70 where it is subjected to a heat treatment at a relatively high temperature. As a result, the affected layer 44 remaining on the wafer W is removed as a sublimate 50 (step S6, right side of FIG. 9). FIG. 10 shows the wafer W after step S6 is completed.

[0038] As described above, in the process of this embodiment, a cycle consisting of supplying a process gas into the process chamber 11 and exhausting the process chamber 11 without supplying the process gas is repeatedly performed. The process conditions during the process gas supply period (step S1) in the first cycle are different from the process conditions during the process gas supply period (step S3) in each cycle thereafter, and are set as process conditions for removing the entire oxide layer 43. Therefore, from the second cycle onwards, the SiO film 41 is etched without the oxide layer 43 present, and etching of the SiN film 42 by the altered layer 44 formed from the oxide layer 43 is prevented. Therefore, etching of the SiN film 42 is suppressed. In particular, etching of the SiN film 42 is suppressed at the peripheral portion of the wafer W, where a large amount of process gas is supplied due to the wraparound from the surface.

[0039] Furthermore, if the period during which the processing vessel 11 is evacuated without supplying processing gas is defined as a purge period, when the above-described cycle is repeated, the processing conditions for the purge period (step S2) in the first cycle are set to be different from the processing conditions for the purge period (step S4) in each cycle from the second cycle onwards. Specifically, the processing conditions are set to be different with respect to the length of the purge period and the pressure inside the processing vessel 11. By setting different processing conditions in this way, the affected layer 44 on the backside of the wafer W is removed with high reliability in step S2, and the execution time of step S4 is prevented from being longer than necessary.

[0040] As described above, steps S3 and S4 are steps for etching the SiO2 film 41, and the process performed in step S3 may be referred to as the main etching process. Steps S1 and S2 are pre-processing steps for the main etching process, and the process performed in step S1 may be referred to as the pre-etching process. The process performed in step S11 of the comparative example may also be referred to as the main etching process. Steps S1 and S3 are the first process, and steps S2 and S4 are the second process. The execution time of step S1 or S3 (the length of the processing gas supply period) corresponds to the execution time of the first process, and the execution time of step S2 or S4 (the length of the purge period) corresponds to the execution time of the second process. In the above processing example, both the pressure in the processing vessel 11 and the execution time of steps S2 and S4 are different to more reliably remove the altered layer 44. However, only one of these may be different.

[0041] In the above processing example, the processing conditions for the pre-etching and the main etching are different: the pressure inside the processing vessel 11, the flow rate of the HF gas 51 / the flow rate of the NH3 gas 52, and the length of the processing gas supply period (i.e., the length of time for performing steps S1 and S3). However, it is not necessary to make all of these elements different. For example, only the pressure inside the processing vessel 11 may be different. Even in this case, it is possible to remove the oxide layer 43 in step S1 and to prevent the gas from flowing around to the backside of the wafer W in step S3.

[0042] Although the process conditions for the process gas supply period and the purge period are different between the first cycle and the second and subsequent cycles, this is not a limitation. The process conditions for the process gas supply period or the purge period may be different between the first cycle through the Nth cycle and the (N+1)th cycle through the final cycle. N is an integer greater than or equal to 2. That is, the removal of the oxide layer 43 described above may not end with the first cycle but may be performed over multiple cycles. Therefore, for example, steps S1 and S2 may be repeated, followed by step S3 and subsequent steps. As described above, in this technology, the process conditions are different between the first cycle and subsequent cycles. However, the subsequent cycle is not limited to the second cycle. The final cycle may be the (N+1)th cycle. That is, depending on the target etching amount of the SiO2 film 41 to be etched, steps S3 and S4 may be performed only once after the process conditions are changed, without being repeated.

[0043] Next, a substrate processing apparatus 6, which is one embodiment of an apparatus including the etching module 1 and performing steps S1 to S6, will be described with reference to the plan view of Fig. 12. The substrate processing apparatus 6 includes a load / unload section 61 for loading and unloading wafers W, two load lock chambers 71 provided adjacent to the load / unload section 61, two heat treatment modules 70 provided adjacent to the two load lock chambers 71, respectively, and two etching modules 1 provided adjacent to the two heat treatment modules 70, respectively.

[0044] The load / unload section 61 includes an atmospheric pressure transfer chamber 63 in which a first substrate transfer mechanism 62 is installed and which is kept under atmospheric pressure, and a carrier mounting table 65 on the side of the atmospheric pressure transfer chamber 63 on which a carrier 64 for accommodating a wafer W is mounted. In the figure, reference numeral 66 denotes an aligner adjacent to the atmospheric pressure transfer chamber 63, which is provided to rotate the wafer W to optically determine the amount of eccentricity and to align the wafer W with the first substrate transfer mechanism 62. The first substrate transfer mechanism 62 transfers the wafer W between the carrier 64 on the carrier mounting table 65, the aligner 66, and the load lock chamber 71.

[0045] A second substrate transfer mechanism 72 having, for example, an articulated arm structure is provided in each load lock chamber 71, and the second substrate transfer mechanism 72 transfers wafers W between the load lock chamber 71, the heat treatment module 70, and the etching module 1. The interior of the processing vessel constituting the heat treatment module 70 is in a vacuum atmosphere, similar to the interior of the processing vessel 11 constituting the etching module 1, and the interior of the load lock chamber 71 can be switched between a normal pressure atmosphere and a vacuum atmosphere so that wafers W can be transferred between these vacuum atmosphere processing vessels and the normal pressure transfer chamber 63.

[0046] In the figure, reference numeral 73 denotes openable and closable gate valves, which are respectively provided between the atmospheric pressure transfer chamber 63 and the load lock chamber 71, between the load lock chamber 71 and the heat treatment module 70, and between the heat treatment module 70 and the etching module 1. The gate valve 73 provided between the heat treatment module 70 and the etching module 1 corresponds to the gate valve 13 shown in Fig. 1. The heat treatment module 70 includes the above-mentioned processing vessel, an exhaust mechanism for evacuating the processing vessel to form a vacuum atmosphere, and a stage provided within the processing vessel and capable of heating the wafer W placed thereon, and is configured to be able to perform the heat treatment of step S6 described above under vacuum pressure.

[0047] The transfer path of the wafer W in the substrate processing apparatus 6 will now be described. As explained in FIG. 2, the carrier 64 storing the wafer W on which each film has been formed is placed on the carrier mounting table 65. The wafer W is then transferred in the order of atmospheric pressure transfer chamber 63 → aligner 66 → atmospheric pressure transfer chamber 63 → load lock chamber 71, and then transferred to the etching module 1 via the heat treatment module 70. Then, steps S1 to S4 are performed as explained in the flow of FIG. 7. Subsequently, after the determination in step S5, the wafer W is transferred to the heat treatment module 70, where sublimation is performed in step S6.

[0048] The substrate processing apparatus 6 also includes a control unit 100, which is a computer, and the control unit 100 includes a program, a memory, and a CPU. The program contains instructions (steps) for processing the wafer W and transporting the wafer W as described above. The program is stored on a storage medium, such as a compact disc, a hard disk, a magneto-optical disc, or a DVD, and is then installed in the control unit 100. The control unit 100 outputs control signals to each component of the substrate processing apparatus 6 based on the program, thereby controlling the operation of each component. Specifically, the operations of the substrate processing apparatus 6 controlled in this manner include, for example, adjusting the temperature of the fluid supplied to the stage 21 (i.e., the processing temperature of the wafer W), supplying each gas from the gas supply sources 36 to 39 to the processing chamber 11, switching between supplying and stopping each gas to the processing chamber 11 and adjusting the flow rate by each flow rate adjuster 35, adjusting the exhaust flow rate by the valve 15 (i.e., adjusting the pressure inside the processing chamber 11), and operating the first substrate transport mechanism 62 and the second substrate transport mechanism 72.

[0049] In the process described in the flow chart of FIG. 7 , the wafer W remains in the same processing chamber 11 from the start of step S1 through the repeated steps S3 and S4 until the final step S4 is completed, and the wafer W is not removed from the processing chamber 11. However, the wafer W is not limited to remaining in the same processing chamber 11 in this manner. For example, after the completion of step S2, the wafer W is removed from the processing chamber 11 and heated in the thermal processing module 70 to remove the damaged layer 44 on the backside of the wafer W. The wafer W may then be transported back to the etching module 1 to perform steps S3 and S4. However, from the viewpoint of preventing a decrease in the throughput of the apparatus, it is preferable to perform the processing by remaining the wafer W in the same processing chamber 11 from step S1 to the final step S4, as in the process described in the flow chart of FIG. 7 . To enable the processing in the same processing chamber 11 in this manner, different processing conditions are set for step S2 than for step S4, thereby ensuring the removal of the damaged layer 44 from the backside of the wafer W.

[0050] The silicon-containing film formed on the backside of the wafer W is not limited to the SiN film 12, and may be another silicon-containing film. Even when a silicon-containing film other than a SiN film is formed, if the film is oxidized to form an oxide layer 43, the oxide layer 43 may become an altered layer 44 when the SiO2 film 41 is etched, which may result in etching of the silicon-containing film, and therefore, application of the present technology is effective. Note that the silicon-containing film does not mean that the film contains silicon as an impurity that inevitably contains silicon, but means that the film contains silicon as a constituent component.

[0051] In the process of the above embodiment, the supply start timing and the supply end timing of HF gas and NH3 gas into the processing vessel 11 are synchronized in step S1 (pre-etching) and step S3 (main etching), but the gases are not limited to being supplied in this manner. That is, there may be a difference between the start timing of the supply of HF gas and the start timing of the supply of NH3 gas, and there may be a difference between the end timing of the supply of HF gas and the end timing of the supply of NH3 gas.

[0052] Although the same process gas is used for the pre-etching and main etching, the halogen-containing gas is not limited to HF gas; instead, gases of halogen-containing compounds such as HCl, HBr, HI, and SF4 can be used. Note that the term "containing halogen" does not mean that the halogen is contained as an impurity, but rather that the halogen is contained as a constituent. Furthermore, the basic gas in the process gas is not limited to NH3 gas; instead, various amine compound gases such as trimethylamine, dimethylamine, dimethylethylamine, diethylamine, triethylamine, monotertiarybutylamine, pyrrolidine, and pyridine can be used. Other specific examples of amine compounds include various amine gases, such as compounds in which some or all of the C—H bonds in the above compounds are replaced with C—F bonds (e.g., 1,1,1-trifluorodimethylamine).

[0053] Although the foregoing description has been given using wafers as an example of the substrate to be processed, substrates processed in the processing chamber 11 include, in addition to wafers, substrates used in manufacturing flat panel displays, substrates used in manufacturing exposure masks used in photolithography, and dummy substrates processed for the purpose of testing or setting processing parameters in the substrate processing apparatus. Furthermore, the embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The above-described embodiments may be omitted, substituted, modified, or combined in various ways without departing from the scope and spirit of the appended claims.

[0054] [Evaluation test] An evaluation test carried out in relation to this embodiment will be described. Evaluation Test 1 2 was transferred to the etching module 1, and the process described as an example was performed. That is, pre-etching (step S1), purging after pre-etching (step S2), main etching (step S3), and purging after main etching (step S4) were performed, and steps S3 and S4 were repeated a predetermined number of times. Then, after the heating process of step S6, the etching amount of the SiN film 42 at each in-plane portion on the back surface of the wafer W was measured.

[0055] As evaluation test 1-2, a test similar to evaluation test 1-1 was conducted, except that only pre-etching and purging after pre-etching were conducted. Therefore, in evaluation test 1-2, the processes of steps S3 and S4 were not conducted. Also, as evaluation test 1-3, a test similar to evaluation test 1-1 was conducted, except that only main etching and purging after main etching were conducted. Therefore, in evaluation test 1-3, the process of the comparative example described in FIG. 4 was conducted, and the processes of steps S1 and S2 were not conducted.

[0056] The results of this evaluation test 1 are as follows. The average values ​​of the normalized values ​​obtained by dividing the measured etching amounts of the SiN film 42 by a predetermined value were 0.52 for evaluation test 1-1, 0.46 for evaluation test 1-2, and 2.38 for evaluation test 1-3. The larger the normalized value, the larger the measured etching amount. Therefore, in evaluation tests 1-1 and 1-2, in which pre-etching was performed, the etching amount of the SiN film 42 within the surface of the wafer W was reduced compared to the evaluation test in which pre-etching was not performed. Note that in the explanation of the evaluation tests that follows, all etching amounts shown are normalized.

[0057] In each of Evaluation Tests 1-1 to 1-3, the etching amount of the SiN film 42 at the center of the wafer W was zero or approximately zero, and the etching amount of the SiN film 42 at the peripheral portion of the wafer W was greater than that at the center. Fig. 13 is a graph showing the etching amount of the SiN film 42 at each position along the diameter of the wafer W for Evaluation Tests 1-1 to 1-3. The horizontal axis of the graph represents the distance from the center of the wafer W, and the vertical axis of the graph represents the normalized etching amount of the SiN film 42.

[0058] The graph waveforms are substantially the same in Evaluation Tests 1-1 and 1-2. Furthermore, with respect to the peripheral portion of the wafer W, the etching amount of the SiN film 42 at the peripheral portion is reduced in Evaluation Tests 1-1 and 1-2, in which steps S1 and S2 are performed, compared to Evaluation Test 1-3, in which steps S1 and S2 are not performed. The results of Evaluation Test 1 above indicate that the processing of steps S1 and S2 can reduce the etching amount of the SiN film 42 at the peripheral portion of the back surface of the wafer W more than the processing of steps S3 and S4. Furthermore, it was shown that when steps S3 and S4 are performed after steps S1 and S2, the etching amount of the SiN film 42 at the peripheral portion of the back surface of the wafer W can be reduced. Therefore, Evaluation Test 1 confirmed the effectiveness of the processing of the embodiment.

[0059] Evaluation Test 2 In evaluation test 2, the wafer W described in FIG. 2 was subjected to the process described as the comparative example using etching module 1, and then the heating process of step S6 was performed. Then, as in evaluation test 1, the etching amount of the SiN film 42 at each portion of the rear surface of the wafer W was measured. The processing conditions for the main etching (step S11) were changed for each wafer W.

[0060] Of the evaluation tests 2, evaluation test 2-1 was conducted under the conditions of 3 Torr pressure in the processing vessel 11, HF gas flow rate / NH3 gas flow rate = 5 / 1, and processing gas supply time (time required for step S11) = 10 seconds. Evaluation test 2-2 was conducted under the conditions of 11 Torr pressure in the processing vessel 11, 11 Torr pressure in the processing vessel 11, HF gas flow rate / NH3 gas flow rate = 2 / 1, and processing gas supply time (time required for step S11) = 10.8 seconds. The number of cycles of steps S11 and S12 was the same for evaluation tests 2-1 and 2-2, and the wafer W temperature was also the same.

[0061] The results of Evaluation Tests 2-1 and 2-2 show that the etching amount of the SiN film 42 in various parts of the wafer W was 0.40 to 2.78 in Evaluation Test 2-1 and 0.04 to 5.69 in Evaluation Test 2-2. In Evaluation Test 2-1, the etching amount of the SiN film 42 was greater at the periphery of the wafer W than at the center, but the center was also relatively heavily etched. In Evaluation Test 2-2, the etching amount of the SiN film 42 at the center of the wafer W was reduced compared to Evaluation Test 2-1, but the SiN film 42 was etched relatively heavily in a relatively narrow area at the periphery of the wafer W. Comparing the etching amount of the SiN film 42 at the periphery of the wafer W, Evaluation Test 2-2 was found to be greater than Evaluation Test 2-1.

[0062] As described above, the results of evaluation test 2, in which pre-etching was not performed, confirmed that by relatively increasing the pressure inside the processing vessel 11, it is possible to suppress the process gas from flowing around to the backside of the wafer W and thereby suppress the amount of etching at the center of the wafer W, but that the SiN film 42 at the peripheral edge of the wafer W is etched relatively largely. Furthermore, evaluation test 2-2 showed a small amount of etching at the center of the wafer W, while evaluation test 2-1 showed a large amount of etching at the center of the wafer W. In view of these results, when pre-etching is performed, it can be said that the pressure inside the processing vessel 11 in step S1 is preferably set to be lower than 11 Torr, for example, and more preferably 3 Torr or less, in order to remove the entire oxide layer 43.

[0063] Evaluation Test 3 Evaluation Tests 3-1 and 3-2 were similar to Evaluation Test 2, except for the main etching (step S11) process conditions. In Evaluation Tests 3-1 and 3-2, the pressure in the processing chamber 11 in step S11 was set to 11 Torr, as in Evaluation Test 2-2, to prevent the process gas from reaching the backside of the wafer W. Furthermore, the duration of step S11 was shorter than in Evaluation Test 2-2. Specifically, in Evaluation Tests 3-1 and 3-3, step S11 was performed for 3 seconds. Other process conditions included a HF gas flow rate / NH3 gas flow rate ratio of 2 / 1 in Evaluation Test 3-1 and a HF gas flow rate / NH3 gas flow rate ratio of 8 / 1 in Evaluation Test 3-2. The number of cycles of steps S11 and S12 was set to be greater than the number of cycles in Evaluation Test 2, with Evaluation Test 3-1 being slightly greater than Evaluation Test 3-2. The wafer W temperature was the same in Evaluation Tests 3-1 and 3-2.

[0064] The results of evaluation test 3-1 showed that the etching amount of the SiN film 42 in various parts of the wafer W was 0.05 to 0.62. That is, in evaluation test 3-1, although the number of cycles was greater than the results of evaluation test 2-2 described above, the etching amount of the SiN film 42 in the peripheral part of the back surface of the wafer W was suppressed, which was a desirable result. However, the results showed that improvement was desired regarding the flatness of the top surface of the SiO2 film 41 remaining in the recessed parts 46 on the surface of the wafer W, as described in FIG. 3, and the variation in the etching amount of the SiO2 film 41 between the recessed parts 46A and 46B.

[0065] The results of Evaluation Test 3-2 showed that the etching amount of the SiN film 42 in various parts of the wafer W ranged from 0.06 to 4.71. In Evaluation Test 3-2, in which the HF gas flow rate / NH3 gas flow rate ratio was set to a relatively high value as described above, the flatness of the top surface of the SiO2 film 41 remaining in the recesses 46 on the wafer W surface was higher than in Evaluation Test 3-1, and the variation in the etching amount of the SiO2 film 41 between the recesses 46A and 46B was reduced. However, the etching amount of the SiN film 42 at the peripheral portion of the wafer W was greater than in Evaluation Test 3-1. From the results of Evaluation Test 3, it appears that when only main etching is performed, it is difficult to achieve both a good post-etching state of the SiO2 film 41 and a reduced etching amount at the peripheral portion of the SiN film 42 on the back surface of the wafer W.

[0066] Evaluation Test 4 As Evaluation Test 4, processing of the Example was performed. In Evaluation Test 4, wafers W were processed in the same manner as in Evaluation Test 3-2, except that pre-etching (Step S1) was performed before the main etching (Step S3) and that purging in Step S2 was performed in conjunction with the pre-etching. The pre-etching processing conditions in Evaluation Test 4 were as follows: HF gas flow rate / NH3 gas flow rate = 5, the execution time of Step S1 (times t1 to t2 in FIG. 11) was 5.5 seconds, and the pressure in the processing chamber was 3 Torr. The execution time of Step S2 (times t2 to t3 in FIG. 11) was set to 120 seconds, which was six times longer than the execution time of Step S4 (times t4 to t5 in FIG. 11).

[0067] The results of Evaluation Test 4 showed that the etching amount of the SiN film 42 in various parts of the wafer W was 0.07 to 0.97. In other words, the etching amount of the SiN film 42 was relatively small throughout the entire surface of the wafer W, and the etching amount of the SiN film 42 in the peripheral part of the wafer W was suppressed compared to Evaluation Test 3-2. Note that the range of relatively large etching amounts within the above etching amount range (0.07 to 0.97) was limited to a relatively narrow range in the peripheral part of the wafer W. In other words, the process gas was prevented from flowing around to the back surface of the wafer W and moving toward the center during the main etching. Furthermore, when comparing the state of the SiO2 film 41 after etching with Evaluation Test 3-1, in which etching of the SiN film 42 was suppressed, Evaluation Test 4 was better.

[0068] The results of Evaluation Test 4 above confirmed the effect of the present technology in suppressing etching of the SiN film 42 on the back surface of the wafer W. It was also confirmed that the present technology can increase the flatness of the top surface of the SiO2 film 41 remaining on the surface of the wafer W after processing while suppressing etching of the SiN film 42, and can suppress the difference in the amount of etching between the recesses 46A and 46B. [Explanation of symbols]

[0069] W wafer 41 Silicon oxide film (SiO2 film) 42 Silicon nitride film (SiN film) 43 Oxide layer 44 Altered layer 51 HF (hydrogen fluoride) gas 52 NH3 (ammonia) gas

Claims

1. a first step of supplying a processing gas into a processing vessel storing a substrate having a silicon oxide film formed on a front surface and a silicon-containing film formed on a rear surface thereof to generate a reaction product between the silicon oxide film and the processing gas; and a second step of evacuating the processing vessel while stopping the supply of the processing gas into the processing vessel to remove the reaction product; performing a first step in a first cycle of the cycles under different processing conditions from the first step in a subsequent cycle to remove an oxide layer formed by oxidizing the silicon-containing film; An etching method comprising:

2. 2. The etching method according to claim 1, wherein the step of repeating the cycle is performed without removing the substrate from the processing chamber.

3. 3. The etching method according to claim 2, wherein the second step of the first cycle is performed under different processing conditions from the second step of the subsequent cycle.

4. the processing conditions that differ between the second step of the first cycle and the second step of the subsequent cycle include at least one of an implementation time of the second step and a pressure inside the processing vessel; The pressure in the processing vessel in the second step of the first cycle is lower than the pressure in the processing vessel in the second step of the subsequent cycle; or 4. The etching method according to claim 3, wherein the second step of the first cycle is performed for a longer period of time than the second step of the subsequent cycle.

5. 5. The etching method according to claim 4, wherein the subsequent cycle is the second or subsequent cycle.

6. the processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include at least the pressure in the processing vessel; 6. The etching method according to claim 5, wherein the pressure in the processing vessel in the first step of the first cycle is higher than the pressure in the processing vessel in the first step of the subsequent cycle.

7. The processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include an implementation time of the first step, 7. The etching method according to claim 6, wherein the first step of the first cycle is performed for a longer period of time than the first step of the subsequent cycle.

8. the process gas includes a halogen-containing gas and a basic gas; the processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include a ratio of a flow rate of the halogen-containing gas supplied into the processing vessel to a flow rate of the basic gas supplied into the processing vessel; 7. The etching method of claim 6, wherein the rate in the first cycle is lower than the rate in the subsequent cycles.

9. 9. The etching method according to claim 8, wherein the halogen-containing gas is hydrogen fluoride gas, and the basic gas is ammonia gas.

10. 2. The etching method according to claim 1, wherein the silicon-containing film is a silicon nitride film.

11. a processing vessel for storing therein a substrate having a silicon oxide film formed on a front surface and a silicon-containing film formed on a rear surface; a process gas supply mechanism for supplying a process gas into the process chamber that reacts with the silicon oxide film to generate a reaction product; an exhaust mechanism for exhausting the inside of the processing vessel; a control unit that outputs a control signal to repeat a cycle including a first step of supplying the processing gas into the processing vessel to generate the reaction product and a second step of evacuating the processing vessel while stopping the supply of the processing gas into the processing vessel to remove the reaction product, and to perform the first step in a first cycle of each of the cycles under different processing conditions from the first step in a subsequent cycle in order to remove an oxide layer formed by oxidizing the silicon-containing film; An etching apparatus comprising:

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