Analog-to-digital conversion circuit and semiconductor chip equipped therewith

Abstract

Reduce the power consumption of the analog-to-digital conversion circuit. [Solution] The analog-to-digital conversion circuit 30, which converts the supply voltage into a digital signal, is provided with a first state in which it outputs an output voltage corresponding to the input voltage when the input voltage based on the supply voltage is above a predetermined threshold, and a second state in which it outputs a fixed output voltage when the input voltage is below a predetermined threshold, and a thermobinary encoder 35 which outputs a digital signal corresponding to the number of buffers 32 to 34 that are in the first state.

Description

[Technical Field]

[0001] This disclosure relates to an analog-to-digital conversion circuit that converts a supply voltage into a digital signal, and a semiconductor chip equipped therewith. [Background technology]

[0002] Non-patent document 1 discloses an analog-to-digital conversion circuit that converts a supply voltage into a digital signal. This analog-to-digital conversion circuit includes a first oscillator that outputs a variable clock with a frequency corresponding to the supply voltage, a second oscillator that outputs a fixed clock with a constant frequency, and a counter that counts the number of times the variable clock is turned on at timings generated based on the fixed clock. [Prior art documents] [Patent Documents]

[0003] [Non-Patent Document 1] A. Kobayashi, K. Hayashi, S. Arata, S. Murakami, G. Xu, and K. Niitsu, "Design of a Self-Controlled Dual-Oscillator-Based Supply Voltage Monitor for Biofuel-Cell-Combined Biosensing Systems in 65-nm CMOS and 55-nm DDC CMOS", IEEE Transactions on Biomedical Circuits and Systems, December 2019, vol.13, no.6, p. 1152-1162 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] However, the analog-to-digital conversion circuit disclosed in Patent Document 1 requires a stable DC (Direct Current) voltage to be supplied to the second oscillator. Therefore, it is necessary to provide and operate a DC / DC converter that generates such a stable DC voltage within the analog-to-digital conversion circuit, which increases power consumption.

[0005] This disclosure has been made in view of the above, and its purpose is to reduce the power consumption of analog-to-digital conversion circuits. [Means for solving the problem]

[0006] To achieve the above objective, the first invention is an analog-to-digital conversion circuit that converts a supply voltage into a digital signal, comprising a plurality of transistor circuits whose predetermined thresholds are different from each other, and an encoder that outputs a digital signal corresponding to the number of transistor circuits in the first state, wherein the circuit enters a first state in which an output voltage corresponding to the input voltage is output when the input voltage based on the supply voltage is above a predetermined threshold, and enters a second state in which a fixed output voltage is output when the input voltage is below a predetermined threshold.

[0007] This allows the input voltage to be converted into a digital signal without the need for a stable DC voltage. Therefore, since there is no need to provide and operate a DC / DC converter to generate a stable DC voltage, the power consumption of the analog-to-digital conversion circuit can be reduced.

[0008] Furthermore, the second invention comprises an analog-to-digital conversion circuit according to the first invention and a storage unit, wherein the analog-to-digital conversion circuit further comprises an oscillator that outputs an oscillation voltage with a frequency corresponding to the supply voltage, and the storage unit is a semiconductor chip that stores the digital signal output by the encoder for each period of the oscillation voltage.

[0009] As a result, a user or device that prestores the correspondence between the value of a digital signal and the period of an oscillation voltage can identify the period of the oscillation voltage when each digital signal was stored in the storage unit by reading the digital signal from the storage unit. Therefore, the user or device can acquire information regarding the timing at which the supply voltage corresponding to each digital signal was supplied.

Advantages of the Invention

[0010] According to the present disclosure, the power consumption of an analog-to-digital conversion circuit can be reduced.

Brief Description of the Drawings

[0011] [Figure 1] FIG. 1 is a schematic perspective view of a contact lens including a semiconductor chip having an analog-to-digital conversion circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a functional block diagram of a semiconductor chip having an analog-to-digital conversion circuit according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic circuit diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of an oscillator. [Figure 5] [[ID=​​​​​​​​​​​​​​​​​Figure 11 is a timing chart illustrating the supply voltage, oscillation voltage, output voltage of the first buffer, output voltage of the second buffer, output voltage of the third buffer, output voltage of the first encoder, and output voltage of the second encoder. [Figure 12] Figure 12 is a timing chart illustrating the supply voltage, oscillation voltage amplitude, output voltage of the first buffer, output voltage of the second buffer, output voltage of the third buffer, output voltage of the first encoder, and output voltage of the second encoder. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described below with reference to the drawings. The following description of preferred embodiments is essentially illustrative and is not intended to limit the present invention, its applications, or its uses in any way.

[0013] Figure 1 shows a contact lens 1. This contact lens 1 comprises a lens body 10 that forms its main component and a semiconductor chip 20 embedded in the lens body 10.

[0014] As shown in Figure 2, the semiconductor chip 20 includes an analog-to-digital conversion circuit 30 according to the embodiment of this disclosure, a memory 40 as a storage unit, a transmitter (TX) 50, and a biofuel cell 60.

[0015] The analog-to-digital conversion circuit 30 uses a supply voltage V IN (See Figure 3) is converted into a digital signal. As shown in Figure 3, the analog-to-digital conversion circuit 30 includes an oscillator 31, a first buffer 32 as a transistor circuit, a second buffer 33 as a transistor circuit, a third buffer 34 as a transistor circuit, a thermobinary encoder 35, and first to third output terminals 36 to 38.

[0016] Oscillator 31 is a ring oscillator. Oscillator 31 is supplied with voltage V IN It outputs an oscillating voltage with a frequency corresponding to the supply voltage V. INThe amplitude is equal to the amplitude of the oscillator. The oscillation voltage output by the oscillator 31 is output from the third output terminal 38. Specifically, as shown in Figure 4, the oscillator 31 includes first to fifth inverter circuits (NOT gates) 311, 314, 317, 3110, 3111, first to third capacitors 312, 315, 318, and first to third oscillator buffers 313, 316, 319. Thus, the oscillator 31 has five inverter circuits 311, 314, 317, 3110, 3111, but the number of inverter circuits is not limited to five; it can be an odd number. The number of oscillator buffers is also not limited to three.

[0017] The input terminal of the first inverter circuit 311 is connected to the supply voltage V IN The following is entered.

[0018] One end of the first capacitor 312 is connected to the output terminal of the first inverter circuit 311, and the other end of the first capacitor 312 is grounded.

[0019] As shown in Figure 5, the first oscillator buffer 313 has a first input terminal IN, a second input terminal INB, a first output terminal OUT, and a second output terminal OUTB. The first oscillator buffer 313 delays the voltage input to the first input terminal IN and outputs it from the first output terminal OUT. The first input terminal IN is supplied with voltage V IN The following is input: the output terminal of the first inverter circuit 311 is connected to the second input terminal INB. In this embodiment, the voltage output from the second output terminal OUTB is not used.

[0020] The first oscillator buffer 313 is powered by the power supply V, as shown in Figure 5. DD Power supply V between and the reference potential point DD The oscillator consists of a first P-channel MOSFET (metal-oxide-semiconductor field-effect transistor) 313a, a second P-channel MOSFET 313b, a first N-channel MOSFET 313c, and a second N-channel MOSFET 313d, all connected in series from one side to the other, and a power supply VDD and a power supply V between it and the reference potential point DD On the A side, there are a third P-channel MOSFET 313e for oscillator, a fourth P-channel MOSFET 313f for oscillator, a third N-channel MOSFET 313g for oscillator, and a fourth N-channel MOSFET 313h for oscillator, which are connected to each other in series in this order. The gate of the first P-channel MOSFET 313a for oscillator and the gate of the second N-channel MOSFET 313d for oscillator are connected to the first input terminal IN. The gate of the third P-channel MOSFET 313e for oscillator and the gate of the fourth N-channel MOSFET 313h for oscillator are connected to the second input terminal INB. The gate of the second P-channel MOSFET 313b for oscillator, the gate of the first N-channel MOSFET 313c for oscillator, the drain of the fourth P-channel MOSFET 313f for oscillator, and the drain of the third N-channel MOSFET 313g for oscillator are connected to the first output terminal OUT. The drain of the second P-channel MOSFET 313b for oscillator, the drain of the first N-channel MOSFET 313c for oscillator, the gate of the fourth P-channel MOSFET 313f for oscillator, and the gate of the third N-channel MOSFET 313g for oscillator are connected to the second output terminal OUTB. To the power supply V DD is input the supply voltage V which is the input of the oscillator 31 IN is inputted.

[0021] The second and third oscillator buffers 316, 319 also have the same configuration as the first oscillator buffer 313.

[0022] The input terminal of the second inverter circuit 314 is connected to the first output terminal OUT of the first oscillator buffer 313.

[0023] One end of the second capacitor 315 is connected to the output terminal of the second inverter circuit 314, and the other end of the second capacitor 315 is grounded.

[0024] The first input terminal IN of the second oscillator buffer 316 is connected to the first output terminal OUT of the first oscillator buffer 313, and the second input terminal INB of the second oscillator buffer 316 is connected to the output terminal of the second inverter circuit 314.

[0025] The input terminal of the third inverter circuit 317 is connected to the first output terminal OUT of the second oscillator buffer 316.

[0026] One end of the third capacitor 318 is connected to the output terminal of the third inverter circuit 317, and the other end of the third capacitor 318 is grounded.

[0027] The first input terminal IN of the third oscillator buffer 319 is connected to the first output terminal OUT of the second oscillator buffer 316, and the second input terminal INB of the third oscillator buffer 319 is connected to the output terminal of the third inverter circuit 317.

[0028] The input terminal of the fourth inverter circuit 3110 is connected to the first output terminal OUT of the third oscillator buffer 319.

[0029] The input terminal of the fifth inverter circuit 3111 is connected to the output terminal of the fourth inverter circuit 3110, the first input terminal IN of the first oscillator buffer 313, and the input terminal of the first inverter circuit 311.

[0030] As shown in Figure 3, the oscillation voltage output by the oscillator 31 is supplied to the first buffer 32, the second buffer 33, and the third buffer 34 via the supply voltage V INThe input voltage is received based on the following. The first buffer 32 enters a first state in which it outputs the oscillation voltage as is if the oscillation voltage output by the oscillator 31 is greater than or equal to a predetermined first threshold, while entering a second state in which it outputs 0V (a fixed output voltage) if the oscillation voltage is less than the first threshold. The second buffer 33 enters a first state in which it outputs the oscillation voltage as is if the oscillation voltage output by the oscillator 31 is greater than or equal to a predetermined second threshold, while entering a second state in which it outputs 0V (a fixed output voltage) if the oscillation voltage is less than the second threshold. The third buffer 34 enters a first state in which it outputs the oscillation voltage as is if the oscillation voltage output by the oscillator 31 is greater than or equal to a predetermined third threshold, while entering a second state in which it outputs 0V (a fixed output voltage) if the oscillation voltage is less than the third threshold. The first threshold, the second threshold, and the third threshold are different from each other. In the first state, the first buffer 32, the second buffer 33, and the third buffer 34 output the oscillation voltage as is, but they may also output it with a changed amplitude. The first buffer 32, the second buffer 33, and the third buffer 34 should each output a voltage corresponding to the input voltage in the first state.

[0031] As shown in Figure 6, the first buffer 32 receives power supply V DD Power supply V between and the reference potential point DD The first buffer's first N-channel MOSFET 321, the first buffer's first P-channel MOSFET 322, eight first buffer's second N-channel MOSFETs 323 and the first buffer's second P-channel MOSFET 324 are connected in series from the left, and the power supply V DD Power supply V between and the reference potential point DDThe first buffer has a third N-channel MOSFET 325, eight third P-channel MOSFETs 326, a fourth N-channel MOSFET 327, and a fourth P-channel MOSFET 328, all connected in series from one side to the other. The gates of the first P-channel MOSFET 322 and the eight second N-channel MOSFETs 323 are input to the oscillator 31 as input voltages. The gate of the first N-channel MOSFET 321, the drain of the first P-channel MOSFET 322, the gates of the eight third P-channel MOSFETs 326, and the gate of the fourth N-channel MOSFET 327 are all connected to each other. The gate of the third N-channel MOSFET 325, the drain of the fourth N-channel MOSFET 327, and the gate of the fourth P-channel MOSFET 328 are all connected to each other. The voltages at the gate of the third N-channel MOSFET 325 for the first buffer, the drain of the fourth N-channel MOSFET 327 for the first buffer, and the gate of the fourth P-channel MOSFET 328 for the first buffer become the output voltage of the first buffer 32.

[0032] As shown in Figure 7, the second buffer 33 receives power supply V DD Power supply V between and the reference potential point DD The first N-channel MOSFET 331 for the second buffer, the first P-channel MOSFET 332 for the second buffer, three second N-channel MOSFETs 333 and two P-channel MOSFETs 334 for the second buffer, are connected in series from the left, and the power supply V DD Power supply V between and the reference potential point DDThe second buffer has, in order from the left, a third N-channel MOSFET 335 for the second buffer, three third P-channel MOSFETs 336 for the second buffer, a fourth N-channel MOSFET 337 for the second buffer, and a fourth P-channel MOSFET 338 for the second buffer, all connected in series. The gates of the first P-channel MOSFET 332 for the second buffer and the gates of the three second N-channel MOSFETs 333 for the second buffer receive the oscillation voltage output by the oscillator 31 as input voltages. The gate of the first N-channel MOSFET 331 for the second buffer, the drain of the first P-channel MOSFET 332 for the second buffer, the gates of the three third P-channel MOSFETs 336 for the second buffer, and the gate of the fourth N-channel MOSFET 337 for the second buffer are connected to each other. The gate of the third N-channel MOSFET 335 for the second buffer, the drain of the fourth N-channel MOSFET 337 for the second buffer, and the gate of the fourth P-channel MOSFET 338 for the second buffer are connected to each other. The voltages at the gate of the third N-channel MOSFET 335 for the second buffer, the drain of the fourth N-channel MOSFET 337 for the second buffer, and the gate of the fourth P-channel MOSFET 338 for the second buffer become the output voltage of the second buffer 33.

[0033] As shown in Figure 8, the third buffer 34 is powered by the V DD Power supply V between and the reference potential point DD The components connected in series from the left are, in order: a first N-channel MOSFET 341 for the third buffer, a first P-channel MOSFET 342 for the third buffer, three second N-channel MOSFETs 343 for the third buffer, and a second P-channel MOSFET 344 for the third buffer, and a power supply V DD Power supply V between and the reference potential point DDThe third buffer has, in order from the left, a third N-channel MOSFET 345 for the third buffer, three third P-channel MOSFETs 346 for the third buffer, a fourth N-channel MOSFET 347 for the third buffer, and a fourth P-channel MOSFET 348 for the third buffer, all connected in series. The gates of the first P-channel MOSFET 342 for the third buffer and the gates of the three second N-channel MOSFETs 343 for the third buffer receive the oscillation voltage output by the oscillator 31 as input voltages. The gate of the first N-channel MOSFET 341 for the third buffer, the drain of the first P-channel MOSFET 342 for the third buffer, the gates of the three third P-channel MOSFETs 346 for the third buffer, and the gate of the fourth N-channel MOSFET 347 for the third buffer are connected to each other. The gate of the third N-channel MOSFET 345 for the third buffer, the drain of the fourth N-channel MOSFET 347 for the third buffer, and the gate of the fourth P-channel MOSFET 348 for the third buffer are connected to each other. The voltages at the gate of the third N-channel MOSFET 345 for the third buffer, the drain of the fourth N-channel MOSFET 347 for the third buffer, and the gate of the fourth P-channel MOSFET 348 for the third buffer become the output voltage of the third buffer 34.

[0034] As described above, the number of second N-channel MOSFETs 323 and third P-channel MOSFETs 326 for the first buffer are equal, and their polarities are opposite. Also, the number of first P-channel MOSFETs 322 and fourth N-channel MOSFETs 327 for the first buffer are equal, and their polarities are opposite. This configuration mitigates glitches in the first buffer 32. The same applies to the second buffer 33 and the third buffer 34.

[0035] Furthermore, the gate widths of the first N-channel MOSFET 321 for the first buffer, the second P-channel MOSFET 324 for the first buffer, the third N-channel MOSFET 325 for the first buffer, and the fourth P-channel MOSFET 328 for the first buffer are narrower than the gate widths of the first N-channel MOSFET 331 for the second buffer, the second P-channel MOSFET 334 for the second buffer, the third N-channel MOSFET 335 for the second buffer, and the fourth P-channel MOSFET 338 for the second buffer.

[0036] Furthermore, the gate widths of the third buffer's first N-channel MOSFET 341, the third buffer's second P-channel MOSFET 344, the third buffer's third N-channel MOSFET 345, and the third buffer's fourth P-channel MOSFET 348 are narrower than the gate widths of the second buffer's first N-channel MOSFET 331, the second buffer's second P-channel MOSFET 334, the second buffer's third N-channel MOSFET 335, and the second buffer's fourth P-channel MOSFET 338.

[0037] Figure 9 shows the relationship between the input voltage and power consumption of the first buffer 32, the second buffer 33, and the third buffer 34. In Figure 9, V DDth_high The first threshold of the first buffer 32, V DDth_medium The second threshold of the second buffer 33, V DDth_low This indicates the third threshold value of the third buffer 34. The first threshold value is higher than the second threshold value, and the second threshold value is higher than the third threshold value. These threshold values ​​for each buffer 32 to 34 can be adjusted by adjusting the gate width and the number of MOSFETs.

[0038] The thermobinary encoder 35 outputs digital signals from the first and second output terminals 36 and 37 corresponding to the number of buffers 32 to 34 in the first state. The thermobinary encoder 35 is a logic circuit and is a DLS (Dynamic Leakage Suppression).

[0039] As shown in Figure 10, the thermobinary encoder 35 has first to third input terminals 351 to 353, first to fourth encoder inverter circuits 354, 357, 358, and 359, and first and second NOR circuits 355 and 356.

[0040] The output voltage of the first buffer 32 is input to the first input terminal 351.

[0041] The output voltage of the second buffer 33 is input to the second input terminal 352.

[0042] The output voltage of the third buffer 34 is input to the third input terminal 353.

[0043] The input to the first encoder inverter circuit 354 is connected to the third input terminal 353.

[0044] One input of the first NOR circuit 355 is connected to the second input terminal 352, and the other input of the first NOR circuit 355 is connected to the output of the first encoder inverter circuit 354.

[0045] One input of the second NOR circuit 356 is connected to the first input terminal 351, and the other input of the second NOR circuit 356 is connected to the output of the first NOR circuit 355.

[0046] The input of the second encoder inverter circuit 357 is connected to the output of the second NOR circuit 356. The output of the second encoder inverter circuit 357 is output from the first output terminal 36.

[0047] The input to the third encoder inverter circuit 358 is connected to the second input terminal 352.

[0048] The input of the fourth encoder inverter circuit 359 is connected to the output of the third encoder inverter circuit 358. The output of the fourth encoder inverter circuit 359 is output from the second output terminal 37.

[0049] The memory 40 stores the digital signals output from the first and second output terminals 36 and 37 by the thermobinary encoder 35 for each period of the oscillation voltage output from the third output terminal 38.

[0050] The transmitter 50 transmits the digital signal stored in the memory 40 to an external receiving device via wireless communication.

[0051] The biofuel cell 60 uses glucose (sugar) contained in tear fluid as fuel and operates at the supply voltage V IN Outputs.

[0052] Figure 11 shows the supply voltage V IN Examples of the oscillator voltage, the output voltage of the first buffer 32, the output voltage of the second buffer 33, the output voltage of the third buffer 34, the first encoder output, and the second encoder output are shown. The first encoder output is the output from the first output terminal 36, and the second encoder output is the output from the second output terminal 37.

[0053] During the period indicated by symbol T1, the supply voltage V IN The value is lower than the first and second thresholds, but greater than or equal to the third threshold. Therefore, the first buffer 32 and the second buffer 33 enter the second state, which outputs 0V. On the other hand, only the third buffer 34 enters the first state, which outputs the oscillation voltage. Then, the first encoder output becomes the oscillation voltage, and the second encoder output is fixed at a low level. When the first encoder output is at a high level, the 2-bit digital signal, with the first encoder output and the second encoder output as the bits, becomes 10.

[0054] During the period indicated by symbol T2, the supply voltage V IN This is lower than the first, second, and third thresholds. Therefore, the first buffer 32, second buffer 33, and third buffer 34 enter the second state, outputting 0V. The first encoder output and the second encoder output are then fixed at a low level. The 2-bit digital signal, with the first encoder output and the second encoder output as the bits, is always 00.

[0055] During the period indicated by symbol T3, the supply voltage V IN The value is above the first threshold. Therefore, the first buffer 32, the second buffer 33, and the third buffer 34 enter the first state where they output an oscillation voltage. The first encoder output and the second encoder output then become the oscillation voltage. When the first encoder output and the second encoder output are at a high level, the 2-bit digital signal, with the first encoder output and the second encoder output as the bits, becomes 11.

[0056] During the period indicated by symbol T4, the supply voltage V IN The value is lower than the first threshold and greater than or equal to the second threshold. Therefore, the first buffer 32 enters the second state, outputting 0V. On the other hand, the second buffer 33 and the third buffer 34 enter the first state, outputting the oscillation voltage. The first encoder output is fixed at a low level, and the second encoder output becomes the oscillation voltage. When the second encoder output is at a high level, the 2-bit digital signal, with the first and second encoder outputs as the bits, becomes 0 and 1.

[0057] Memory 40 stores the digital signals output by the thermobinary encoder 35, namely the first encoder output and the second encoder output, for each period of the oscillation voltage output from the third output terminal 38. For example, memory 40 stores the first encoder output and the second encoder output each time the oscillation voltage rises. In the example in Figure 11, memory 40 stores "10" twice as the digital signal for the period indicated by code T1. Memory 40 also stores "00" once as the digital signal for the period indicated by code T2. Memory 40 also stores "11" four times as the digital signal for the period indicated by code T3. Memory 40 also stores "01" three times as the digital signal for the period indicated by code T4.

[0058] A user or device that pre-stores the correspondence between the value of a digital signal and the period of the oscillation voltage can identify the period of the oscillation voltage when each digital signal was stored in memory 40 by reading the digital signal from memory 40. Therefore, the user or device can identify the supply voltage V corresponding to each digital signal. IN Information regarding the timing of the supply can be obtained. For example, the user or device can refer to the fact that two sets of "10" digital signals are stored consecutively in memory 40 and obtain a supply voltage V at the level corresponding to "10". IN However, it can be recognized that the supply was provided continuously for a period of more than two cycles corresponding to the "10" cycle.

[0059] Figure 12 shows the supply voltage V IN Another example of the oscillation voltage amplitude, the output voltage of the first buffer 32, the output voltage of the second buffer 33, the output voltage of the third buffer 34, the first encoder output, and the second encoder output is shown.

[0060] In this example, the first threshold (V DDth_high ) to 0.266V, second threshold (V DDth_medium ) set to 0.183V, third threshold (V DDth_low The voltage is set to 0.108V.

[0061] Therefore, according to this embodiment, the analog-to-digital conversion circuit 30 can convert the input voltage into a digital signal without using a stable DC voltage. Consequently, since it is not necessary to provide and operate a DC / DC converter in the analog-to-digital conversion circuit 30 to generate a stable DC voltage, the analog-to-digital conversion circuit 30 can be miniaturized and power consumption reduced.

[0062] Also, the supply voltage V IN Since it is not necessary to provide an oscillator that outputs a fixed clock of a constant frequency in order to obtain information about the timing of the supply, the analog-to-digital conversion circuit 30 can be operated at a low voltage. In addition, the circuit area can be reduced.

[0063] In the above embodiment, the semiconductor chip 20 was provided on the contact lens 1, but it may also be provided on a tablet, a stent, or the like.

[0064] Furthermore, in the above embodiment, the power supplied by the biofuel cell 60 was converted into a digital signal, but the present invention can also be applied when the power supplied by a thermal power generation element is converted into a digital signal.

[0065] Furthermore, in the above embodiment, the digital signal is set to 2 bits and three buffers 32-34 are provided, but the number of bits in the digital signal and the number of buffers are not limited to these. For example, the number of bits in the digital signal can be N bits other than 2 bits, and the number of buffers can be 2 N -1 is also acceptable. As the number of buffers increases, the influence of PVT (process, temperature, voltage) fluctuations becomes greater. For example, when a certain buffer is in the second state, other buffers that should have had a higher threshold set are more likely to enter the first state. However, by referring to the digital signal and recognizing the number of buffers in the first state, the supply voltage V IN You can get a sense of their level to some extent. [Industrial applicability]

[0066] This disclosure is useful as an analog-to-digital conversion circuit that converts a supplied analog voltage into a digital signal, and as a semiconductor chip equipped therewith. [Explanation of Symbols]

[0067] 20 semiconductor chips 30 Analog-to-Digital Conversion Circuits 31 Oscillator 32. First Buffer (Transistor Circuit) 33. Second buffer (transistor circuit) 34. Third Buffer (Transistor Circuit) 35 Thermobinary Encoder 40 Memory (storage unit) V IN Supply voltage

Claims

1. An analog-to-digital conversion circuit that converts a supply voltage into a digital signal, When the input voltage based on the supply voltage is above a predetermined threshold, the system enters a first state in which an output voltage corresponding to the input voltage is output, while when the input voltage is below a predetermined threshold, the system enters a second state in which a fixed output voltage is output, and the predetermined thresholds are different for each of the multiple transistor circuits, An analog-to-digital conversion circuit comprising an encoder that outputs a digital signal corresponding to the number of transistor circuits in the first state.

2. The analog-to-digital conversion circuit described in claim 1 and a storage unit are provided, The analog-to-digital conversion circuit further includes an oscillator that outputs an oscillation voltage with a frequency corresponding to the supply voltage, The storage unit is a semiconductor chip that stores the digital signal output by the encoder for each period of the oscillation voltage.

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