Semiconductor equipment

Abstract

To provide a semiconductor device that can improve the performance of electrostatic protection circuits. [Solution] The semiconductor device 1 includes a protection transistor 21 connected between a power supply and GND, a trigger circuit 10 that detects the application of ESD and outputs a drive signal to the gate of the protection transistor 21, and a switch SW11 provided between the power supply or GND and the gate of the protection transistor 21, which electrically connects the power supply or GND and the gate of the protection transistor 21 when ESD is applied to GND.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a protection function against ESD (Electro Static Discharge).

Background Art

[0002] Semiconductor devices are equipped with an electrostatic protection circuit for protecting internal circuits from external electrostatic discharges.

[0003] Examples of this type of electrostatic protection circuit include those composed of an RC timer, an inverter, and a protection transistor sized to discharge an applied ESD (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The circuit composed of the above-described RC timer and inverter operates when an electrostatic discharge is applied to the power supply line, but does not operate when an electrostatic discharge is applied to a reference potential line such as GND or Vss.

[0006] When electrostatic discharge is applied to the reference potential line, the current is discharged mainly through the body diode formed between the drain and guard ring of the protection transistor. However, in the SOI (Silicon On Insulator) process, the source / drain / channel of the transistor are isolated from the Si substrate by the BOX (Buried Oxide) layer, so a body diode is not formed. As a result, the stress voltage between the power line and the reference potential line increases, raising the risk of device failure due to electrostatic discharge.

[0007] Adding a diode between the power line and the reference potential line is also an option, but this would require increasing the size of the added diode, which would increase the chip area.

[0008] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a protection transistor connected between a power line and a reference potential line, a trigger circuit that detects the application of electrostatic discharge to the power line and outputs a drive signal to the gate of the protection transistor, and a switching circuit provided between the power line or reference potential line and the gate of the protection transistor, which electrically connects the power line or reference potential line and the gate of the protection transistor when electrostatic discharge is applied to the reference potential line. [Effects of the Invention]

[0010] According to the above embodiment, the performance of the electrostatic protection circuit can be improved. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 shows a schematic circuit example of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 shows the operation of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 shows the operation of the semiconductor device shown in Figure 1. [Figure 4] Figure 4 shows the operation of the semiconductor device shown in Figure 1. [Figure 5] Figure 5 shows a detailed circuit example of the semiconductor device shown in Figure 1. [Figure 6] Figure 6 shows a modified example of the semiconductor device shown in Figure 1. [Figure 7] Figure 7 shows an example circuit of a semiconductor device according to the second embodiment. [Figure 8] Figure 8 shows a modified example of the semiconductor device shown in Figure 7. [Figure 9] Figure 9 shows an example circuit of a semiconductor device according to the third embodiment. [Figure 10] Figure 10 shows the operation of the semiconductor device shown in Figure 9. [Figure 11] Figure 11 shows a modified example of the semiconductor device shown in Figure 9. [Figure 12] Figure 12 shows the operation of the semiconductor device shown in Figure 11. [Figure 13] Figure 13 shows an example circuit of a semiconductor device according to the fourth embodiment. [Figure 14] Figure 14 shows the operation of the semiconductor device shown in Figure 13. [Figure 15] Figure 15 shows the operation of the semiconductor device shown in Figure 13. [Modes for carrying out the invention]

[0012] In the following embodiments, when necessary for convenience, they are described by being divided into a plurality of sections or embodiments. However, unless otherwise explicitly stated, they are not unrelated to each other, and one is related to a part or all of the other as a modification example, details, supplementary explanation, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise explicitly stated or limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0013] Furthermore, in the following embodiments, it is needless to say that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise explicitly stated or considered to be essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise explicitly stated or considered not to be so in principle, it includes those substantially approximated or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0014] Also, the circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by an integrated circuit technology such as known CMOS (complementary MOS transistor). In the embodiment, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as MOS transistor) is used as an example of MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as the gate insulating film. Further, in the embodiment, a p-channel type MOSFET and an n-channel type MOSFET are respectively referred to as a pMOS transistor and an nMOS transistor.

[0015] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated description thereof will be omitted.

[0016] (First Embodiment) FIG. 1 shows a schematic diagram of a semiconductor device according to this embodiment. FIG. 1 is a schematic circuit example of an electrostatic protection circuit portion of a semiconductor device 1 according to this embodiment. The semiconductor device 1 includes a trigger circuit 10, a protection transistor 21, and a switch SW11.

[0017] The trigger circuit 10 includes an ESD detection circuit 11 and an inverter 12. The ESD detection circuit 11 detects the application of electrostatic discharge (hereinafter referred to as ESD) to the power supply line and outputs a detection signal to the inverter 12. The inverter 12 outputs a drive signal to the gate of the protection transistor 21 based on the detection signal. Further, the ESD detection circuit 11 and the inverter 12 are connected between a power supply node N11 (power supply line) and a power supply node N12 (GND: reference potential line). Here, the power supply node N11 is a node to which a power supply voltage on the high potential side is applied with respect to the ESD detection circuit 11 and the inverter 12, and the power supply node N12 is a node to which a power supply voltage on the low potential side is applied with respect to the ESD detection circuit 11 and the inverter 12.

[0018] Note that the power supply line (power supply node N11) shown in FIG. 1 is a node to which a power supply voltage (for example, Vdd) having a higher potential than the GND in FIG. 1 is supplied. GND (power supply node N12) is a node to which a power supply voltage (also referred to as a reference potential) having a lower potential than the power supply line is supplied.

[0019] The protection transistor 21 is composed of an nMOS transistor and is connected between the power supply node N11 and the power supply node N12. That is, the drain of the protection transistor 21 is connected to the power supply node N11, and the source of the protection transistor 21 is connected to the power supply node N12. The protection transistor 21 turns on when ESD is applied to the power supply line or GND, and discharges the current accompanying the ESD application.

[0020] Switch SW11 is located between the power node N12 and the gate of the protection transistor 21. Switch SW11 electrically connects or disconnects the power node N12 and the gate of the protection transistor 21. Switch SW11 can be configured as a transistor, for example, as shown in Figure 5. Switch SW11 is switched on or off by the potential of the power node N11, for example, as shown in Figure 5.

[0021] In other words, in the configuration shown in Figure 1, the ESD detection circuit 11 corresponds to the detection circuit, the inverter 12 corresponds to the drive circuit, and the switch SW 11 corresponds to the switching circuit.

[0022] [Operation of this embodiment] Next, the operation of the electrostatic protection circuit in the semiconductor device 1 with the above configuration will be explained with reference to Figures 2 to 4.

[0023] Figure 2 shows the case where ESD is applied to GND (power node N12: reference potential line). In this case, Vesd is applied as a voltage to GND (power node N12). On the other hand, the power line (power node N11) is 0V. In this case, the ESD detection circuit 11 cannot detect the application of ESD.

[0024] Therefore, switch SW11 is turned ON. This electrically connects (short-circuits) the power node N12 (GND) and the gate of the protection transistor 21, causing the potential of the gate of the protection transistor 21 to rise to approximately the same level as that of the power node N12 (GND). Consequently, the gate-drain voltage Vgd of the protection transistor 21 expands to Vesd, driving it with a voltage sufficient to allow the current (ESD current) associated with ESD application to flow. Thus, even if a body diode is not formed, sufficient clamping performance can be maintained. In other words, when ESD is applied to GND (reference potential line), switch SW11 electrically connects GND (reference potential line) and the gate of the protection transistor 21.

[0025] Figure 3 shows the case where ESD is applied to the power line (power node N11). In this case, a voltage of Vesd is applied to the power line (power node N11). On the other hand, GND (power node N12) is 0V. In this case, the ESD detection circuit 11 outputs a Lo level indicating ESD application, and the inverter 12 outputs a Hi level. Therefore, the protection transistor 21 is in the ON state, that is, the gate-source voltage Vgs of the protection transistor 21 becomes Vesd, and the current associated with the application of ESD is discharged.

[0026] In the case of Figure 3, switch SW11 is turned off. Therefore, when ESD is applied to the power line (power node N11), switch SW11 will not interfere with the output signal of the trigger circuit 10 (inverter 12).

[0027] Figure 4 shows the state when the power is turned on (when no ESD is applied). At this time, a voltage Vdd is applied to the power line (power node N11). On the other hand, GND (power node N12) is 0V. In this case, the ESD detection circuit 11 outputs a Hi level, and the inverter 12 outputs a Lo level. Therefore, the protection transistor 21 is in the OFF state, that is, the gate-source voltage Vgd of the protection transistor 21 becomes 0V, and no current discharge occurs.

[0028] In the case of Figure 4, switch SW11 is turned off. Therefore, when the power is turned on (when ESD is not applied), switch SW11 does not interfere with the output signal of the trigger circuit 10 (inverter 12).

[0029] [Detailed circuit diagram of this embodiment] Next, a detailed circuit example of the configuration shown in Figure 1 will be described. In the detailed circuit shown in Figure 5, the ESD detection circuit 11 consists of a resistor 11a and a capacitive element 11b. The resistor 11a and the capacitive element 11b are connected in series between power supply node N11 and power supply node N12. That is, one end of the resistor 11a is connected to power supply node N11, and the other end is connected to one end of the capacitive element 11b. The other end of the capacitive element 11b is connected to power supply node N12. The connection point between the resistor 11a and the capacitive element 11b is connected to the input of inverter 12. The ESD detection circuit 11 is a well-known RC timer, and a time constant is set so that it reacts only in the case of a high slew rate such as ESD application.

[0030] Switch SW11 is composed of pMOS transistors. The source of switch SW11 is connected to the gate of protection transistor 21, and the drain is connected to power node N12. Power node N11 is also connected to the gate of switch SW11. When ESD is applied to GND (power node N12) and the potential rises, the drain-gate voltage Vdg of the pMOS transistor constituting switch SW11 increases, and switch SW11 turns on. In other words, switch SW11 turns on when ESD is applied to GND. When switch SW11 is turned on, as described above, it electrically connects power node N12 and the gate of protection transistor 21. That is, switch SW11 electrically connects the reference potential line and the gate of protection transistor 21 based on the potential of the power line.

[0031] On the other hand, switch SW11 is turned off when no ESD is applied to GND. When switch SW11 is turned off, it electrically disconnects the power node N12 from the gate of the protection transistor 21.

[0032] Furthermore, when ESD is applied to the power line (power node N11), the trigger circuit 10 operates, and the inverter 12 outputs a high level. At this time, the gate and source of the pMOS transistor constituting the switch SW11 become at the same potential and turn off, so the switch SW11 does not affect the output signal of the inverter 12.

[0033] Furthermore, when the power is turned on, the inverter 12 outputs a Lo level (0V). At this time, the source and drain of the pMOS transistor that makes up the switch SW11 become 0V, and the gate becomes Vdd, which puts it in the off state.

[0034] [Differentiation] Next, a modified version of this embodiment will be described. Figure 6 shows an example circuit when the protection transistor 21 is made of a pMOS transistor. In the circuit of Figure 6, the configuration of the ESD detection circuit 11 and the switch SW11 are different from those in Figure 5.

[0035] In the ESD detection circuit 11, the connection relationship between the capacitive element 11b and the resistive element 11a is reversed compared to Figure 5. That is, one end of the capacitive element 11b is connected to the power node N11, and the other end is connected to one end of the resistive element 11a. The other end of the resistive element 11a is connected to the power node N12. The connection point between the capacitive element 11b and the resistive element 11a is connected to the input of the inverter 12.

[0036] Switch SW11 is composed of an nMOS transistor. The drain of switch SW11 is connected to power node N11, and the source is connected to the gate of protection transistor 21. In other words, switch SW11 is connected between the power line and the gate of protection transistor 21. Power node N12 is also connected to the gate of switch SW11.

[0037] When ESD is applied to GND (power node N12) and the potential rises, switch SW11 turns on as the gate-drain voltage Vgd of the nMOS transistor constituting switch SW11 increases. When switch SW11 is turned on, it electrically connects power node N11 and the gate of protection transistor 21. Then, the power line (power node N11) and the gate of the protection transistor 21, which is a pMOS transistor, are connected, and the drain-gate voltage Vdg of the protection transistor 21 increases, driving it with a voltage sufficient for ESD current to flow. In other words, when ESD is applied to GND (reference potential line), switch SW11 electrically connects the power line and the gate of protection transistor 21. Furthermore, switch SW11 electrically connects the power line and the gate of protection transistor 21 based on the potential of the reference potential line.

[0038] On the other hand, switch SW11 is turned off when no ESD is applied to GND. When switch SW11 is turned off, it electrically disconnects the power node N11 from the gate of the protection transistor 21.

[0039] Furthermore, when ESD is applied to the power line (power node N11), the trigger circuit 10 operates, and the inverter 12 outputs a low level. At this time, the gate and source of the nMOS transistor constituting the switch SW11 become at the same potential and turn off, so the switch SW11 does not affect the output signal of the inverter 12.

[0040] Furthermore, when the power is turned on, the inverter 12 outputs a high level (Vdd). At this time, the source and drain of the nMOS transistor constituting the switch SW11 are at Vdd, and the gate is at 0V, putting it in the off state.

[0041] With the above configuration, the semiconductor device 1 can electrically connect the power line (when the protection transistor 21 is a pMOS transistor) or the reference potential line (when the protection transistor 21 is an nMOS transistor) to the gate of the protection transistor 21 using the switch SW11. Therefore, only a small switch is added, minimizing the increase in chip area compared to adding a large protection diode. Consequently, the clamping performance against ESD application from GND to the power supply can be improved. This is particularly effective for semiconductor devices manufactured by processes that do not form body diodes, such as SOI processes.

[0042] (Second embodiment) Next, a second embodiment will be described. In principle, sections that overlap with the previously described embodiment will be omitted from the description below.

[0043] [Circuit configuration of this embodiment] Figure 7 shows a schematic diagram of the semiconductor device according to this embodiment. Figure 7 is an example of the electrostatic protection circuit portion of the semiconductor device 1A according to this embodiment. The semiconductor device 1A includes a resistor 31, a protection transistor 41, and a switch SW21. The circuit shown in this embodiment is, for example, an electrostatic protection circuit for a circuit to which an internal power supply is provided. The internal power supply is, for example, a power supply obtained by stepping down an externally supplied primary power supply using an internal power supply circuit such as a power supply IP.

[0044] The protection transistor 41 is composed of an nMOS transistor and is connected between power node N11 (power line) and power node N12 (GND). In other words, the drain of the protection transistor 41 is connected to power node N11, and the source of the protection transistor 41 is connected to power node N12. The protection transistor 41 turns on when ESD is applied to the power line or GND, and discharges the current associated with the ESD application.

[0045] One end of the resistor 31 is connected to the gate of the protection transistor 41, and the other end is connected to GND (power node N12). The resistor 31 functions as a trigger circuit in this embodiment in conjunction with the parasitic capacitance formed between the drain and gate of the protection transistor 41. In this embodiment, as described above, internal power is supplied from a power supply IP or the like. If the internal power supply rises quickly, the trigger circuit shown in Figure 5 may react and cause a rush current to flow. Therefore, instead of the trigger circuit configured in Figure 5, an RC circuit with a short time constant is formed using the resistor 31 and the parasitic capacitance.

[0046] Switch SW21 is composed of pMOS transistors. The source of switch SW21 is connected to the gate of protection transistor 41, and the drain is connected to power node N12. Power node N11 is also connected to the gate of switch SW21. When ESD is applied to GND (power node N12) and the potential rises, the drain-gate voltage Vdg of the pMOS transistor constituting switch SW21 increases, and switch SW21 turns on. In other words, switch SW21 turns on when ESD is applied to GND. When switch SW21 is turned on, it electrically connects power node N12 and the gate of protection transistor 41, as described above.

[0047] When switch SW21 is turned ON, the gate-drain voltage Vgd of the protection transistor 41 increases to Vesd, driving it with a voltage sufficient to allow the current (ESD current) to flow due to the application of ESD. Therefore, even if a body diode is not formed, sufficient clamping performance can be maintained.

[0048] On the other hand, switch SW21 is turned off when no ESD is applied to GND (power node N12). When switch SW21 is turned off, it electrically disconnects power node N12 from the gate of protection transistor 41.

[0049] [Differentiation] Next, a modified version of this embodiment will be described. Figure 8 shows an example circuit when the protection transistor 41 is made of a pMOS transistor. In the circuit of Figure 8, the connection of the resistor element 31 and the switch SW21 are different from those in Figure 7.

[0050] The resistor 31 has one end connected to a power line (power node N11) and the other end connected to the gate of the protection transistor 41.

[0051] Switch SW21 is composed of nMOS transistors. The drain of switch SW21 is connected to power node N11, and the source is connected to the gate of protection transistor 41. Power node N12 is also connected to the gate of switch SW21. When ESD is applied to GND (power node N12) and the potential rises, the gate-drain voltage Vgd of the nMOS transistors constituting switch SW21 increases, and switch SW21 turns on. When switch SW21 is turned on, it electrically connects power node N11 and the gate of protection transistor 41. Then, the power line and the gate of protection transistor 41, which is a pMOS transistor, are connected, and the drain-gate voltage Vdg of protection transistor 41 increases, driving it with a voltage sufficient for ESD current to flow.

[0052] On the other hand, switch SW21 is turned off when no ESD is applied to GND (power node N12). When switch SW21 is turned off, it electrically disconnects power node N11 from the gate of protection transistor 41.

[0053] With the above configuration, even in circuits that utilize an internal power supply, such as semiconductor device 1A, the increase in chip area can be minimized, and the clamping performance against ESD application from GND to the power supply can be improved.

[0054] (Third embodiment) Next, a third embodiment will be described. In principle, sections that overlap with the previously described embodiments will be omitted from the following description.

[0055] This embodiment applies to a configuration in which protection transistors are stacked vertically. In recent years, while the breakdown voltage of devices has decreased with process miniaturization, the voltage of the external interface has not decreased. Therefore, to protect a power supply that is supplied with a voltage higher than the breakdown voltage of the devices, a configuration in which protection transistors are stacked vertically is used to reduce the voltage applied to each protection transistor to below the breakdown voltage of the devices. In this embodiment, even in such a configuration in which protection transistors are stacked vertically (connected in series), the clamping performance against ESD application from GND to the power supply can be improved.

[0056] [Circuit configuration of this embodiment] Figure 9 shows an example of the electrostatic protection circuit portion of the semiconductor device according to this embodiment. The semiconductor device 1B shown in Figure 9 includes resistors R11 and R12, trigger circuits 50 and 60, protection transistors 71 and 72, and switches SW31, SW32, and SW33.

[0057] Resistors R11 and R12 are connected in series between the power line and GND. Resistors R11 and R12 divide the voltage between the power line and GND and supply it to the power node N13. In Figure 9, resistors R11 and R12 have the same resistance value, and the power node N13, which is the connection point of resistors R11 and R12, is supplied with a voltage that is half the power supply voltage. Note that resistors R11 and R12 are not limited to resistors but may be composed of transistors. Also, the voltage division ratio by resistors R11 and R12 does not necessarily have to be 1 / 2 (1:1) as long as a potential difference that allows the inverter 52 to operate normally can be secured. Note that in this embodiment, a voltage higher than the individual breakdown voltage of the transistors that make up the protection transistors 71 and 72 and switches SW31, SW32, and SW33 is applied to the power line.

[0058] The trigger circuit 50 includes an ESD detection circuit 51 and an inverter 52. The ESD detection circuit 51 detects the application of ESD to the power line (power node N11) and outputs a detection signal to the inverter 52. Based on the detection signal, the inverter 52 outputs a drive signal to the gate of the protection transistor 71. The ESD detection circuit 51 and the inverter 52 are connected between power node N11 and power node N13.

[0059] The ESD detection circuit 51 consists of a resistor 51a and a capacitive element 51b. The resistor 51a and the capacitive element 51b are connected in series between power supply node N11 and power supply node N13. That is, one end of the resistor 51a is connected to power supply node N11, and the other end is connected to one end of the capacitive element 51b. The other end of the capacitive element 51b is connected to power supply node N13. The connection point between the resistor 51a and the capacitive element 51b is connected to the input of the inverter 52.

[0060] The trigger circuit 60 includes an ESD detection circuit 61 and an inverter 62. The ESD detection circuit 61 detects the application of ESD to the power line (power node N11) and outputs a detection signal to the inverter 62. Based on the detection signal, the inverter 62 outputs a drive signal to the gate of the protection transistor 72. The ESD detection circuit 61 and the inverter 62 are connected between power node N13 and power node N12.

[0061] The ESD detection circuit 61 consists of a resistive element 61a and a capacitive element 61b. The resistive element 61a and the capacitive element 61b are connected in series between power supply node N13 and power supply node N12. That is, one end of the resistive element 61a is connected to power supply node N13, and the other end is connected to one end of the capacitive element 61b. The other end of the capacitive element 61b is connected to power supply node N12. The connection point between the resistive element 61a and the capacitive element 61b is connected to the input of the inverter 62.

[0062] Switch SW31 is composed of a pMOS transistor. The source of switch SW31 is connected to the gate of protection transistor 72, and the drain is connected to power node N12. Power node N13 is connected to the gate of switch SW33.

[0063] Switch SW32 is composed of an nMOS transistor. The drain of switch SW32 is connected to power node N13, and the source is connected to the gate of protection transistor 72. Power node N12 is also connected to the gate of switch SW32.

[0064] Switch SW33 is composed of pMOS transistors. The source of switch SW33 is connected to the gate of protection transistor 71, and the drain is connected to power node N13. Power node N11 is connected to the gate of switch SW31.

[0065] [Operation of this embodiment] Next, the operation of the electrostatic protection circuit in the semiconductor device 1B with the above-described configuration will be explained with reference to Figure 10. Figure 10 shows the case when ESD is applied to GND (power node N12). Note that in Figure 10, the outlines indicating the trigger circuits 50 and 60 and the outlines indicating the ESD detection circuits 51 and 61 are omitted from the illustration.

[0066] In the case of Figure 10, a voltage of Vesd is applied to GND (power node N12). On the other hand, the power line (power node N11) is 0V. In this case, the ESD detection circuits 51 and 61 cannot detect the application of ESD. Here, when ESD is applied to GND (power node N12) and the potential rises, the drain-gate voltage Vdg of the pMOS transistor constituting the switch SW31 increases (Vdg = Vesd) and the switch SW31 turns ON. In other words, the switch SW31 turns ON when ESD is applied to GND. When the switch SW31 is ON, it electrically connects the power node N12 and the gate of the protection transistor 72. On the other hand, the switch SW31 turns OFF when no ESD is applied to GND. When the switch SW31 is OFF, it electrically disconnects the power node N12 and the gate of the protection transistor 72.

[0067] When ESD is applied to GND (power node N12) and the potential rises, switch SW32 turns ON as the gate-drain voltage Vgd of the nMOS transistor constituting switch SW32 increases (Vgd = Vesd). In other words, switch SW32 turns ON when ESD is applied to GND. When switch SW32 is ON, it electrically connects the gate of protection transistor 72 to power node N13. On the other hand, switch SW32 turns OFF when ESD is not applied to GND. When switch SW32 is OFF, it electrically disconnects the gate of protection transistor 72 from power node N13.

[0068] Switch SW33 turns ON when ESD is applied to GND (power node N12) and the potential of the power line (power node N11) drops to 0V. This causes the drain-gate voltage Vdg of the pMOS transistor constituting switch SW33 to increase (Vdg = Vesd), turning it ON. In other words, switch SW33 turns ON when ESD is applied to GND. When switch SW33 is ON, it electrically connects power node N13 and the gate of protection transistor 71. On the other hand, switch SW33 turns OFF when ESD is not applied to GND. When switch SW33 is OFF, it electrically disconnects power node N13 and the gate of protection transistor 71.

[0069] Therefore, when switch SW31 is turned ON, the gate of protection transistor 72 is electrically connected to GND (power node N12). As a result, the gate-drain voltage Vgd of protection transistor 72 increases to Vesd. Also, when switches SW31, SW32, and SW33 are turned ON, the gate of protection transistor 71 is electrically connected to GND. As a result, the gate-drain voltage Vgd of protection transistor 71 increases to Vesd. Thus, protection transistors 71 and 72 are driven with a voltage sufficient to allow the current (ESD current) to flow due to the application of ESD.

[0070] In other words, switches SW31, SW32, and SW33 function as multiple switching elements that electrically connect the reference potential line and the gate of the protection transistor 71.

[0071] Furthermore, when ESD is applied to the power line (power node N11) or when the power is turned on, switches SW31, SW32, and SW33 are all turned off, so switches SW31, SW32, and SW33 do not affect the output signals of inverters 52 and 62.

[0072] [Differentiation] Next, a modified version of this embodiment will be described. Figure 11 shows an example circuit where the protection transistors 71 and 72 are made of pMOS transistors. In the circuit of Figure 11, the configuration of the ESD detection circuits 51 and 61 differs from that of Figure 9. Also, switches SW41, SW42, and SW43 are provided instead of switches SW31, SW32, and SW33.

[0073] In the ESD detection circuit 51, the connection relationship between the capacitive element 51b and the resistive element 51a is reversed compared to Figure 9. That is, one end of the capacitive element 51b is connected to the power node N11, and the other end is connected to one end of the resistive element 51a. The other end of the resistive element 51a is connected to the power node N13. The connection point between the capacitive element 51b and the resistive element 51a is connected to the input of the inverter 52.

[0074] In the ESD detection circuit 61, the connection relationship between the capacitive element 61b and the resistive element 61a is reversed compared to Figure 9. That is, one end of the capacitive element 61b is connected to the power node N13, and the other end is connected to one end of the resistive element 61a. The other end of the resistive element 61a is connected to the power node N12. The connection point between the capacitive element 61b and the resistive element 61a is connected to the input of the inverter 62.

[0075] Switch SW41 is composed of an nMOS transistor. The drain of switch SW41 is connected to power node N11, and the source is connected to the gate of protection transistor 71. Power node N13 is also connected to the gate of switch SW41.

[0076] Switch SW42 is composed of pMOS transistors. The source of switch SW42 is connected to the gate of protection transistor 71, and the drain is connected to power node N13. Power node N11 is also connected to the gate of switch SW42.

[0077] Switch SW43 is composed of an nMOS transistor. The drain of switch SW43 is connected to power node N13, and the source is connected to the gate of protection transistor 72. Power node N12 is connected to the gate of switch SW41.

[0078] Next, the operation of the electrostatic protection circuit in this modified example will be explained with reference to Figure 12. Figure 12 shows the case when ESD is applied to GND.

[0079] In the case of Figure 12, a voltage of Vesd is applied to GND (power node N12). On the other hand, the power line (power node N11) is at 0V. In this case, the ESD detection circuits 51 and 61 cannot detect the application of ESD. Here, when ESD is applied to GND (power node N12) and the potential of the power line (power node N11) drops (to 0V), the gate-drain voltage Vgd of the nMOS transistor constituting switch SW41 increases (Vgd = Vesd) and the switch SW41 turns ON. In other words, switch SW41 turns ON when ESD is applied to GND. When switch SW41 is ON, it electrically connects power node N11 and the gate of protection transistor 71. On the other hand, switch SW41 turns OFF when no ESD is applied to GND. When switch SW41 is OFF, it electrically disconnects power node N11 and the gate of protection transistor 71.

[0080] Switch SW42 turns ON when ESD is applied to GND (power node N12) and the potential of the power line (power node N11) drops (to 0V), causing the drain-gate voltage Vdg of the pMOS transistor constituting switch SW42 to increase (Vdg = Vesd). In other words, switch SW42 turns ON when ESD is applied to GND. When switch SW42 is ON, it electrically connects the gate of the protection transistor 71 to power node N13. On the other hand, switch SW42 turns OFF when ESD is not applied to GND. When switch SW42 is OFF, it electrically disconnects the gate of the protection transistor 71 from power node N13.

[0081] When ESD is applied to GND (power node N12) and the potential rises, switch SW43 turns ON as the gate-drain voltage Vgd of the nMOS transistor constituting switch SW43 increases (Vgd = Vesd). In other words, switch SW43 turns ON when ESD is applied to GND. When switch SW43 is ON, it electrically connects power node N13 and the gate of protection transistor 72. On the other hand, switch SW43 turns OFF when ESD is not applied to GND. When switch SW43 is OFF, it electrically disconnects power node N13 and the gate of protection transistor 72.

[0082] Therefore, when switch SW41 is turned ON, the gate of protection transistor 71 is electrically connected to the power line (power node N11). As a result, the drain-gate voltage Vdg of protection transistor 71 increases to Vesd. Also, when switches SW41, SW42, and SW43 are turned ON, the gate of protection transistor 72 is electrically connected to the power line. As a result, the drain-gate voltage Vdg of protection transistor 72 increases to Vesd. Thus, protection transistors 71 and 72 are driven with a voltage sufficient to allow the current (ESD current) to flow due to the application of ESD.

[0083] Furthermore, when ESD is applied to the power line (power node N11) or when the power is turned on, switches SW41, SW42, and SW43 are all turned off, so switches SW41, SW42, and SW43 do not affect the output signals of inverters 52 and 62.

[0084] With the above configuration, even in circuits that stack protection transistors vertically, such as semiconductor device 1B, the increase in chip area can be minimized, and the clamping performance against ESD application from GND to power supply can be improved.

[0085] Furthermore, although this embodiment was described using the case where the vertical product is 2, it may be 3 or more. Even in the case of 3 or more, the same effect can be obtained by providing a MOS transistor that acts as a switch, in the same manner as in the case of 2.

[0086] (Fourth embodiment) Next, a fourth embodiment will be described. In principle, sections that overlap with the previously described embodiments will be omitted from the description below.

[0087] This embodiment is applied to an output driver connected to the I / O terminal of a semiconductor device.

[0088] Figure 13 shows an example circuit of the output driver portion of the semiconductor device according to this embodiment. The semiconductor device 1C shown in Figure 13 includes output transistors 81 and 82, a pre-driver 90, and switches SW51 and SW52.

[0089] The output transistor 81 is composed of a pMOS transistor. The source of the output transistor 81 is connected to power node N11, and the drain is connected to node N14. The gate of the output transistor 81 is connected to the pre-driver 90. In other words, the output transistor 81 is connected between the output terminal (IO terminal) and the power line (power node N11). Here, node N14 is the node to which the IO terminal is connected.

[0090] The output transistor 82 is an nMOS transistor. The drain of the output transistor 82 is connected to node N14, and the source is connected to power supply node N12. The gate of the output transistor 82 is connected to the pre-driver 90. In other words, the output transistor 82 is connected between the output terminal and the reference potential line (power supply node N12).

[0091] The pre-driver 90 drives output transistors 81 and 82 according to the signal level output to the IO terminal.

[0092] Switch SW51 is composed of an nMOS transistor. The drain of switch SW51 is connected to power node N11, and the source is connected to the gate of output transistor 81. Additionally, the gate of switch SW51 is connected to node N14. In other words, switch SW51 is located between the power line (power node N11) and the gate of output transistor 81.

[0093] Switch SW52 is composed of a pMOS transistor. The source of switch SW52 is connected to the gate of output transistor 82, and the drain is connected to power node N12. Switch SW52 also has its gate connected to node N14. In other words, switch SW51 is located between the reference potential line (power node N12) and the gate of output transistor 82.

[0094] Next, the operation of the circuit shown in Figure 13 will be explained. Figure 14 shows the case when ESD is applied to the IO terminal. In Figure 14, the voltage Vesd is applied to the IO terminal (node ​​N14). On the other hand, the power line (power node N11) is 0V. In this case, since Vesd is applied to the gate of switch SW51, the gate-drain voltage Vgd of the nMOS transistor constituting switch SW51 increases (becomes Vesd) and turns it ON. When switch SW51 is ON, the power node N11 and the gate of output transistor 81 are electrically connected, and the drain-gate voltage Vdg of output transistor 81 increases and turns it ON.

[0095] Therefore, the output transistor 81 is driven with a voltage sufficient to allow the current (ESD current) to flow due to the application of ESD.

[0096] In other words, switch SW51 functions as a switching circuit that electrically connects power node N11 (power line) and the gate of output transistor 81 when ESD application to the IO terminal (output terminal) is detected.

[0097] Figure 15 shows the case where ESD is applied to GND. In Figure 15, a voltage of Vesd is applied to GND (power node N12). On the other hand, the IO terminal (node ​​N14) is 0V. In this case, 0V is applied to the gate of switch SW52, so the drain-gate voltage Vdg of the pMOS transistor constituting switch SW52 increases (to Vesd) and turns it ON. When switch SW52 is ON, the power node N12 and the gate of output transistor 82 are electrically connected, and the gate-drain voltage Vgd of output transistor 82 increases and turns it ON.

[0098] Therefore, the output transistor 82 is driven with a voltage sufficient to allow the ESD current to flow.

[0099] In other words, switch SW52 functions as a switching circuit that electrically connects GND (reference potential line) and the gate of output transistor 82 when it detects the application of ESD to GND (reference potential line).

[0100] Furthermore, in this embodiment, the configuration may be such that only one of switch SW51 or switch SW52 is provided. For output transistors that do not have a corresponding switch, a diode may be provided in parallel, as in the conventional configuration.

[0101] With the above configuration, in the output driver of semiconductor device 1C, the output transistors 81 and 82 constituting the driver circuit can be driven with a voltage sufficient to allow ESD current to flow and utilized as ESD protection elements. Therefore, it becomes possible to reduce the size of the protection diode or even eliminate the diode itself, contributing to a reduction in chip area.

[0102] Furthermore, the embodiments described above are suitable not only for SOI processes but also for processes where a body diode is not formed due to its structure, such as GAA (Gate All Around) structures. However, even when applied to conventional bulk processes, a large amount of current can be supplied from the channel in addition to the body diode, thus further reducing the stress voltage between the power line and GND.

[0103] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0104] 1, 1A, 1B, 1C Semiconductor devices 10 Trigger Circuit 11 ESD detection circuit (detection circuit) 12. Inverter (drive circuit) 21 Protection transistors 31 Resistors 41 Protection transistors 50 Trigger Circuit 51 ESD detection circuit (detection circuit) 52 Inverter (drive circuit) 60 Trigger Circuit 61 ESD detection circuit (detection circuit) 62 Inverter (Drive Circuit) 71 Protection transistors 72 Protection transistors 81 Output transistors 82 Output transistors N11 Power node (power line) N12 Power node (reference potential line) SW11 Switch (Switching Circuit) SW21 Switch (Switching Circuit) SW31 Switch (Switching Circuit) SW32 Switch (Switching Circuit) SW33 Switch (Switching Circuit) SW41 Switch (Switching Circuit) SW42 Switch (Switching Circuit) SW43 Switch (Switching Circuit) SW51 Switch (Switching Circuit) SW52 Switch (Switching Circuit)

Claims

1. A protection transistor connected between the power line and the reference potential line, A trigger circuit that detects the application of electrostatic discharge to the power line and outputs a drive signal to the gate of the protection transistor, A switching circuit is provided between the power line or the reference potential line and the gate of the protection transistor, and electrically connects the power line or the reference potential line and the gate of the protection transistor when the electrostatic discharge is applied to the reference potential line. A semiconductor device equipped with a semiconductor device.

2. In the semiconductor device described in claim 1, The trigger circuit described above is The detection circuit for detecting the electrostatic discharge, A drive circuit that drives the gate of the protection transistor based on the detection result of the detection circuit, A semiconductor device equipped with a semiconductor device.

3. In the semiconductor device described in claim 1, The switching circuit electrically connects the power line or the reference potential line to the gate of the protection transistor based on the potential of the power line or the reference potential line. Semiconductor equipment.

4. In the semiconductor device described in claim 1, The trigger circuit comprises a resistive element connected to the gate of the protection transistor and a parasitic capacitance formed between the drain and gate of the protection transistor. Semiconductor equipment.

5. In the semiconductor device described in claim 1, Multiple protection transistors are connected in series, The switching circuit is composed of multiple switching elements, The plurality of switching elements electrically connect the power line or the reference potential line to the gate of one of the plurality of protection transistors. Semiconductor equipment.

6. The output transistor is connected between the output terminal and the power line, A switching circuit is provided between the power line and the gate of the output transistor, which electrically connects the power line and the gate of the output transistor when it detects the application of electrostatic discharge to the output terminal, A semiconductor device equipped with a semiconductor device.

7. An output transistor connected between the output terminal and the reference potential line, A switching circuit is provided between the reference potential line and the gate of the output transistor, which electrically connects the reference potential line and the gate of the output transistor when it detects the application of electrostatic discharge to the reference potential line. A semiconductor device equipped with a semiconductor device.

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