Switching control circuit, power supply circuit

Abstract

This invention provides a switching control circuit capable of suppressing power loss in the power supply circuit. [Solution] The switching control circuit controls the switching of the transistor in a power supply circuit that generates an output voltage obtained by boosting the rectified voltage, and includes a transformer having a first winding to which a rectified voltage obtained by rectifying an AC voltage is applied, and a second winding to which a voltage corresponding to the voltage generated in the first winding is generated, and a transistor that controls the inductor current flowing through the first winding. The switching control circuit controls the switching of the transistor in a power supply circuit that generates an output voltage obtained by boosting the rectified voltage, and includes a first error voltage generation circuit that generates a first error voltage corresponding to the error between a first voltage obtained by smoothing the voltage generated in the second winding and a first reference voltage, and a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined current value, determines the on period of the transistor based on the first error voltage, and outputs the drive signal to turn off the transistor.

Description

Technical Field

[0001] The present invention relates to a switching control circuit and a power supply circuit.

Background Art

[0002] A boost chopper type boost circuit generates a DC voltage of a predetermined voltage level from an AC voltage (for example, Patent Documents 1 to 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when the amplitude of the AC voltage is small, a boost chopper type boost circuit needs to increase the boost ratio to generate a DC voltage of a predetermined voltage level. However, increasing the boost ratio causes an increase in power loss due to an increase in conduction loss and switching loss of the transistor.

[0005] The present invention has been made in view of the above conventional problems, and an object thereof is to provide a switching control circuit capable of suppressing power loss of a power supply circuit.

Means for Solving the Problems

[0006] The switching control circuit according to the present invention, which solves the aforementioned problems, is a switching control circuit that controls the switching of the transistor of a power supply circuit that generates an output voltage obtained by boosting the rectified voltage, comprising: a transformer having a first winding to which a rectified voltage obtained by rectifying an AC voltage is applied, and a second winding to which a voltage corresponding to the voltage generated in the first winding is generated; and a transistor that controls the inductor current flowing through the first winding, the switching control circuit that controls the switching of the transistor of the power supply circuit that generates an output voltage obtained by boosting the rectified voltage, comprising: a first error voltage generation circuit that generates a first error voltage corresponding to the error between a first voltage obtained by smoothing the voltage generated in the second winding and a first reference voltage; and a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined current value, determines the on period of the transistor based on the first error voltage, and outputs the drive signal to turn off the transistor.

[0007] The power supply circuit according to the present invention, which solves the aforementioned problems, comprises a transformer having a first winding to which a rectified voltage obtained by rectifying an AC voltage is applied, and a second winding to which a voltage corresponding to the voltage generated in the first winding is generated; a transistor that controls the inductor current flowing through the first winding; and a switching control circuit that controls the switching of the transistor, and the power supply circuit generates an output voltage obtained by boosting the rectified voltage, wherein the switching control circuit includes a first error voltage generation circuit that generates a first error voltage corresponding to the error between a first voltage obtained by smoothing the voltage generated in the second winding and a first reference voltage; a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined current value, determines the on period of the transistor based on the first error voltage, and outputs the drive signal to turn off the transistor, and the power supply circuit is a power supply circuit that includes a voltage generation circuit that generates the first voltage obtained by smoothing the voltage generated in the second winding. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that can suppress power loss in a power supply circuit. [Brief explanation of the drawing]

[0009] [Figure 1] It is a diagram showing an example of an AC-DC converter 10a. [Figure 2] It is a diagram showing an example of an integrated circuit 30a. [Figure 3] It is a diagram showing an example of the operation waveform of the integrated circuit 30a. [Figure 4] It is a diagram showing the relationship between the rectified voltage Vrec1 and the switching of the NMOS transistor 25. [Figure 5] It is a diagram showing the relationship between the AC voltage Vac (peak value), the peak voltage of the AC voltage Vac, the output voltage, and the boost ratio. [Figure 6] It is a diagram showing an example of an AC-DC converter 10b. [Figure 7] It is a diagram showing an example of an integrated circuit 30b. [Figure 8] It is a diagram showing the relationship between the AC voltage Vac (peak value), the peak voltage of the AC voltage Vac, the output voltage, and the boost ratio.

Embodiments for Carrying Out the Invention

[0010] From the description in this specification and the accompanying drawings, at least the following matters become clear. =====This Embodiment===== FIG. 1 is a diagram showing an example of an AC-DC converter 10a according to an embodiment of the present invention. The AC-DC converter 10a is a boost chopper type power supply circuit that generates an output voltage Vout from the AC voltage Vac of a commercial power supply 11.

[0011] The load 12 is, for example, a DC-DC converter or an electronic device operating with a DC voltage.

[0012] <<<Outline of the AC-DC Converter 10a>>> The AC-DC converter 10a is composed of a full-wave rectifier circuit 20, capacitors 21 and 24, a transformer 22 including coils L1 and L2, a diode 23, an NMOS transistor 25, and a control block 26a.

[0013] The full-wave rectifier circuit 20 full-wave rectifies the AC voltage Vac and applies it as the rectified voltage Vrec1 to the capacitor 21 and the primary coil L1 of the transformer 22 (described later). Also, the current flowing through the primary coil L1 is defined as the inductor current IL, and the current value of the inductor current IL flowing in the direction of the arrow shown in FIG. 1 is set as a positive current value.

[0014] Although the rectified voltage Vrec1 is directly applied to one end of the primary coil L1, for example, it may be applied to the coil L1 via an element such as a resistor (not shown). Also, in this embodiment, "applied" includes not only directly supplying a voltage to a predetermined node but also indirectly supplying a voltage via an element such as a resistor (not shown) and supplying a divided voltage.

[0015] The capacitor 21 is an element that filters the high-frequency ripple current flowing through the primary coil L1 and the switching noise generated by the on / off of the NMOS transistor 25.

[0016] The transformer 22 has a primary coil L1 and a secondary coil L2 magnetically coupled to the primary coil L1. Here, the secondary coil L2 is wound such that the voltage generated in the secondary coil L2 becomes a voltage corresponding to (for example, of opposite polarity) the voltage generated in the primary coil L1. Also, the output voltage Vzcd of the secondary coil L2 becomes a negative voltage while the NMOS transistor 25 (described later) is on, and becomes a positive voltage when the NMOS transistor 25 is off. The primary coil L1 corresponds to the "first winding", and the secondary coil L2 corresponds to the "second winding".

[0017] Also, the primary coil L1 forms a boost chopper circuit together with the diode 23, the capacitor 24, and the NMOS transistor 25. Therefore, the charging voltage of the capacitor 24 becomes the DC output voltage Vout.

[0018] The NMOS transistor 25 is a transistor for controlling the power supplied to the load 12 of the AC-DC converter 10a. In this embodiment, the NMOS transistor 25 is assumed to be a MOS (Metal Oxide Semiconductor) transistor, but it is not limited thereto. The NMOS transistor 25 may be, for example, a bipolar transistor as long as it is a transistor capable of controlling power. Also, the gate electrode of the NMOS transistor 25 is connected to be driven by a drive signal Vdr from the terminal OUT of the integrated circuit 30a described later.

[0019] The control block 26a controls the NMOS transistor 25 based on the voltage Vzcd. The control block 26a includes an integrated circuit 30a, a voltage generation circuit 31, a resistor 32, and capacitors 33 and 34. Note that the integrated circuit 30a corresponds to a "switching control circuit".

[0020] The integrated circuit 30a is an integrated circuit that controls the switching of the NMOS transistor 25 so as to generate the output voltage Vout from the AC voltage Vac. Specifically, the integrated circuit 30a drives the NMOS transistor 25 so that the duty ratio of the signal Vdr becomes a predetermined value based on the inductor current IL flowing through the primary coil L1 and a voltage Vfb described later. Here, the duty ratio is defined as the ratio of the period during which the NMOS transistor 25 is on to the period during which the NMOS transistor 25 turns on and off.

[0021] Details of the integrated circuit 30a will be described later, but the integrated circuit 30a is provided with terminals FB, ZCD, COMP, and OUT. Note that the integrated circuit 30a has terminals other than the four terminals FB, ZCD, COMP, and OUT described above, but they are omitted here for convenience.

[0022] The voltage generation circuit 31 generates a voltage Vfb by smoothing the voltage Vzcd generated in the secondary coil L2. The voltage generation circuit 31 is composed of a diode 40, resistors 41 and 42, and a capacitor 43.

[0023] Diode 40 is a component that interrupts the current when its anode is connected to the secondary coil L2, the NMOS transistor 25 is turned on, and the voltage Vzcd becomes a negative voltage.

[0024] Resistors 41 and 42 are connected in series between the cathode of diode 40 and ground, forming a voltage divider circuit that divides the positive voltage Vzcd, and together with capacitor 43, generates the voltage Vfb used when switching the NMOS transistor 25. Capacitor 43 is connected in parallel with resistor 42, and together with resistor 41, forms a smoothing circuit that smooths the positive voltage Vzcd. The voltage Vfb generated at the node to which resistors 41 and 42 are connected is applied to terminal FB. Resistor 41 corresponds to the "first resistor," and resistor 42 corresponds to the "second resistor."

[0025] The resistor 32 and capacitors 33 and 34 are phase compensation elements for the feedback-controlled integrated circuit 30a. The resistor 32 and capacitor 33 are connected in series between terminal COMP and ground, and capacitor 34 is connected in parallel with them.

[0026] <<<Configuration of Integrated Circuit 30a>>> Figure 2 shows an example of an integrated circuit 30a. The integrated circuit 30a includes a drive signal output circuit 50a, an error voltage generation circuit 51, and a buffer 52. In Figure 2, for convenience, terminals are drawn in different positions than in Figure 1, but the wiring, components, etc. connected to each terminal are the same in Figures 1 and 2.

[0027] <<<Drive signal output circuit 50a>>> The drive signal output circuit 50a outputs a drive signal Vq1 based on the inductor current IL and the voltage Vcomp at terminal COMP. Specifically, the drive signal output circuit 50a outputs a drive signal Vq1 that turns on the NMOS transistor 25 when the inductor current IL becomes approximately zero. On the other hand, the drive signal output circuit 50a outputs a drive signal Vq1 that turns off the NMOS transistor 25 when the oscillation voltage Vr from the oscillation circuit 73 (described later) becomes voltage Vcomp. In other words, the drive signal output circuit 50a determines the on-period of the NMOS transistor 25 based on voltage Vcomp. Furthermore, as will be described in detail later, the drive signal output circuit 50a determines the on-period of the NMOS transistor 25 so that the duty cycle of the drive signal Vq1 becomes a predetermined value by turning off the NMOS transistor 25 when the oscillation voltage Vr becomes voltage Vcomp. The drive signal output circuit 50a is composed of a comparator 60 and a signal output circuit 61a.

[0028] Comparator 60 is a circuit that detects whether the current value of the inductor current IL has become "current value Ia" (hereinafter, for convenience, "approximately zero" will simply be referred to as zero) based on the voltage Vzcd. When the current value of the inductor current IL becomes "zero" (current value Ia) and the voltage Vzcd becomes lower than the reference voltage VREF0, comparator 60 outputs a high-level signal Vz (hereinafter referred to as "H level"). Comparator 60 corresponds to the "current detection circuit," and the signal Vz corresponds to the "detection result."

[0029] The signal output circuit 61a outputs a drive signal Vq1 to drive the NMOS transistor 25. Specifically, when the comparator 60 outputs a high-level signal Vz, the signal output circuit 61a outputs a high-level drive signal Vq1 to turn on the NMOS transistor 25. On the other hand, when the oscillation voltage Vr from the oscillation circuit 73 becomes voltage Vcomp, the signal output circuit 61a outputs a low-level (hereinafter referred to as "L-level") drive signal Vq1 to turn off the NMOS transistor 25.

[0030] The signal output circuit 61a comprises a pulse circuit 71, an SR flip-flop 72, an oscillator circuit 73, and a comparator 74.

[0031] When the comparator 60 outputs a high-level signal Vz, the pulse circuit 71 outputs a high-level pulse signal Vp1.

[0032] The SR flip-flop 72 outputs a high-level drive signal Vq1 when the pulse circuit 71 outputs a high-level pulse signal Vp1. On the other hand, the SR flip-flop 72 outputs a low-level drive signal Vq1 when the comparator 74, described later, outputs a high-level signal Vc1.

[0033] The oscillator circuit 73 is a circuit that generates the oscillation voltage Vr necessary for switching the NMOS transistor 25 on and off. Specifically, when the inductor current IL becomes less than zero and a drive signal Vq1 of the "H" level is input, the oscillator circuit 73 outputs an oscillation voltage Vr whose amplitude gradually increases with a predetermined slope.

[0034] Comparator 74 is a circuit that compares the voltage Vcomp with the oscillating voltage Vr. Specifically, the voltage Vcomp is applied to the inverting input terminal of comparator 74, and the oscillating voltage Vr is applied to the non-inverting input terminal of comparator 74. Therefore, when the level of the oscillating voltage Vr is lower than the level of the voltage Vcomp, comparator 74 outputs a "L" level signal Vc1, and when the level of the oscillating voltage Vr is higher than the level of the voltage Vcomp, it outputs a "H" level signal Vc1.

[0035] <<<Error voltage generation circuit 51>>> The error voltage generation circuit 51 is a transconductance amplifier and generates an error current Ie according to the error between a reference voltage VREF1, which sets the duty cycle to a predetermined value, and a voltage Vfb. The error voltage generation circuit 51 also charges and discharges capacitors 33 and 34 via terminal COMP with the error current Ie1, generating a voltage Vcomp. Thus, based on the voltage Vzcd, the error voltage generation circuit 51 generates a voltage Vcomp according to the error between the (averaged) voltage Vfb, which corresponds to the duty cycle of the signal Vdr, and the reference voltage VREF1. The error voltage generation circuit 51 corresponds to the "first error voltage generation circuit," and the voltage Vcomp generated by the error voltage generation circuit 51 corresponds to the "first error voltage." The reference voltage VREF1 corresponds to the "first reference voltage," and the voltage Vfb corresponds to the "first voltage."

[0036] The buffer 52 drives the NMOS transistor 25 based on the drive signal Vq1. Specifically, the buffer 52 drives the NMOS transistor 25, which has a large gate capacitance, etc., with a signal Vdr of the same logic level as the input signal. The buffer 52 also turns on the NMOS transistor 25 based on the "H" level drive signal Vq1 and turns off the NMOS transistor 25 based on the "L" level drive signal Vq1.

[0037] <<<Operation of integrated circuit 30a>>> Figure 3 shows an example of the operation of the integrated circuit 30a. First, at time t0, when the inductor current IL decreases and the current value becomes "zero", the comparator 60 outputs a "H" level signal Vz. Then, the pulse circuit 71 outputs a pulse signal Vp1.

[0038] When the pulse signal Vp1 is output, the SR flip-flop 72 outputs a drive signal Vq1 at the "H" level, so the signal Vdr also becomes "H" level. When the SR flip-flop 72 outputs the "H" level signal Vq1, the oscillator circuit 73 begins to output an oscillation voltage Vr that gradually increases. The NMOS transistor 25 turns on when the integrated circuit 30a outputs the "H" level signal Vdr. The inductor current IL gradually increases with a slope corresponding to the inductor value of the primary coil L1 and the rectified voltage Vrec1.

[0039] At time t1, when the oscillation voltage Vr becomes voltage Vcomp, the comparator 74 outputs a high-level signal Vc1. As a result, the SR flip-flop 72 outputs a low-level drive signal Vq1, and the signal Vdr also becomes low. The NMOS transistor 25 also turns off when the integrated circuit 30a outputs a low-level signal Vdr. Then, a back electromotive force corresponding to the inductor current IL when the NMOS transistor 25 is on is generated in the primary coil L1, and begins to supply the inductor current IL to the capacitor 24 via the diode 23.

[0040] At time t2, when the inductor current IL becomes "zero", the comparator 60 outputs a "high" level signal Vz. The operation from time t0 onward is then repeated.

[0041] Figure 4 shows the relationship between the rectified voltage Vrec1 and the switching of the NMOS transistor 25. In Figure 4, it is assumed that a constant current flows through the load 12 in Figure 1, and that periods P1, P2, and P3 are the periods when the phase angle of the rectified voltage Vrec1 is approximately 0 degrees, approximately 90 degrees, and approximately 180 degrees, respectively.

[0042] During period P1, as will be explained in detail later, the voltage Vcomp becomes low, shortening the on-period of the NMOS transistor 25, and consequently increasing the switching frequency of the NMOS transistor 25. Also, the rectified voltage Vrec1 is low, and when the NMOS transistor 25 is switched with a predetermined duty cycle, the boost ratio reaches the predetermined value, but because the on-period of the NMOS transistor 25 is short, the capacitor 24 in Figure 1 cannot be sufficiently charged. Furthermore, since a constant current flows through the load 12, the output voltage Vout decreases.

[0043] During period P1, as the phase angle of the rectified voltage Vrec1 gradually approaches 90 degrees, the rectified voltage Vrec1 gradually increases, and the boost ratio reaches a predetermined value. However, the output voltage Vout gradually decreases because a constant current flows through the load 12. As the output voltage Vout decreases, the voltage Vzcd when the NMOS transistor 25 is off also decreases, and the voltage Vfb, which is the average of the voltages Vzcd, also decreases. As the voltage Vfb decreases, the voltage Vcomp gradually increases.

[0044] During period P2, the voltage Vcomp increases, which lengthens the on-period of the NMOS transistor 25, and consequently lowers the switching frequency of the NMOS transistor 25. Also, the rectified voltage Vrec1 is high, and when the NMOS transistor 25 is switched with a predetermined duty cycle, the boost ratio becomes predetermined, and because the on-period of the NMOS transistor 25 is long, the capacitor 24 can be sufficiently charged. Furthermore, although a constant current flows through the load 12, the output voltage Vout increases.

[0045] During period P2, as the phase angle of the rectified voltage Vrec1 gradually approaches 180 degrees, the rectified voltage Vrec1 gradually decreases, the boost ratio reaches a predetermined value, and the output voltage Vout gradually increases, although a constant current flows through the load 12. As the output voltage Vout increases, the voltage Vzcd when the NMOS transistor 25 is off also increases, and the voltage Vfb, which is the average of voltage Vzcd, also increases. As voltage Vfb increases, voltage Vcomp gradually decreases.

[0046] During period P3, the voltage Vcomp becomes low, so, similar to period P1, the on-period of the NMOS transistor 25 becomes shorter, and consequently, the switching frequency of the NMOS transistor 25 increases. Also, the rectified voltage Vrec1 is low, and when the NMOS transistor 25 is switched with a predetermined duty cycle, the boost ratio is set to a predetermined value, but because the on-period of the NMOS transistor 25 is short, the capacitor 24 cannot be sufficiently charged. Furthermore, since a constant current flows through the load 12, the output voltage Vout decreases.

[0047] During period P3, as the phase angle of the rectified voltage Vrec1 gradually approaches 180 degrees, the rectified voltage Vrec1 gradually decreases, and the boost ratio reaches a predetermined value. However, the output voltage Vout gradually decreases because a constant current flows through the load 12. As the output voltage Vout decreases, the voltage Vzcd when the NMOS transistor 25 is off also decreases, and the voltage Vfb, which is the average of the voltages Vzcd, also decreases. As the voltage Vfb decreases, the voltage Vcomp gradually increases.

[0048] Therefore, when the integrated circuit 30a is operating, and for example the on-period during which the NMOS transistor 25 is turned on becomes longer than the appropriate on-period, the voltage Vfb obtained by smoothing the positive voltage Vzcd increases, the error voltage generation circuit 51 discharges the capacitors 33 and 34, and as a result the voltage Vcomp decreases. Consequently, the on-period of the NMOS transistor 25 becomes shorter.

[0049] Conversely, if the on-period of the NMOS transistor 25 becomes shorter than the appropriate on-period, the voltage Vfb decreases, the error voltage generation circuit 51 charges capacitors 33 and 34, and as a result, the voltage Vcomp increases. Therefore, the on-period of the NMOS transistor 25 becomes longer. In this way, the integrated circuit 30a controls the voltage level of the voltage Vfb to a predetermined level, and since the voltage Vfb is a voltage obtained by smoothing the positive voltage Vzcd, the duty cycle of the NMOS transistor 25 becomes a predetermined value.

[0050] <<<Relationship between AC voltage Vac and output voltage Vout, etc.>>> FIG. 5 is a diagram showing the relationship among the peak voltage of the AC voltage Vac, the output voltage, and the boost ratio. The boost ratio is represented by D for the duty ratio, and when the forward voltage of the diode 23 is ignored, it is a ratio represented by 1 / (1 - D).

[0051] Since the integrated circuit 30a operates to set the duty ratio to a predetermined value, the boost ratio obtained from the duty ratio also becomes a predetermined value. Therefore, the output voltage Vout increases as the peak value of the AC voltage Vac increases. Also, unlike the method of outputting an output voltage corresponding to the peak value of the AC voltage based on the voltage obtained by smoothing the signal Vdr and corresponding to the duty ratio of the signal Vdr, there is no need to connect a circuit for smoothing the signal Vdr to the line where the signal Vdr is output. Therefore, noise that affects the signal Vdr is suppressed.

[0052] <<<Overview of AC-DC converter 10b>>> FIG. 6 is a diagram showing an example of the AC-DC converter 10b. By the way, the capacitor 24 may be damaged when the output voltage Vout greatly exceeds the rated voltage (for example, 450V). Therefore, when the peak value of the AC voltage Vac is small, the AC-DC converter 10b changes the output voltage Vout according to the peak value of the AC voltage Vac; on the other hand, when the peak value of the AC voltage Vac becomes large, the AC-DC converter 10b maintains the output voltage Vout at a predetermined level (for example, 400V). Also, the AC-DC converter 10b is a power supply circuit in which a voltage dividing circuit 27 for dividing the output voltage Vout is added to the AC-DC converter 10a and the control block 26a is changed to the control block 26b.

[0053] Control block 26b is a modified version of control block 26a, with integrated circuit 30a replaced by integrated circuit 30b. Details of integrated circuit 30b will be described later, but it is provided with terminals FB1, FB2, ZCD, COMP, and OUT. While integrated circuit 30b also has terminals other than the five mentioned above (FB1, FB2, ZCD, COMP, OUT), these are omitted here for convenience. Furthermore, the external circuits connected to terminals ZCD, COMP, and OUT are the same as those in integrated circuit 30a.

[0054] A voltage generation circuit 31 is connected to terminal FB1, similar to terminal FB of the integrated circuit 30a, and a voltage Vfb1 is applied to it. In addition, a voltage Vfb2 from a voltage divider circuit 27 consisting of resistors 28 and 29 is applied to terminal FB2.

[0055] <<<Configuration of Integrated Circuit 30b>>> Figure 7 shows an example of an integrated circuit 30b. The integrated circuit 30b comprises a drive signal output circuit 50b, error voltage generation circuits 51 and 53, and a buffer 52. The drive signal output circuit 50b comprises a comparator 60 and a signal output circuit 61b.

[0056] When the output voltage Vout level falls below a predetermined level, the signal output circuit 61b outputs a drive signal Vq1 to turn off the NMOS transistor 25, based on the voltage Vcomp generated by the error voltage generation circuit 51, so that the duty cycle of the drive signal Vq1 becomes a predetermined value. On the other hand, when the output voltage Vout level rises above a predetermined level, the signal output circuit 61b outputs a drive signal Vq1 to turn off the NMOS transistor 25, based on the voltage Vcomp generated by the error voltage generation circuit 53 (described later), so that the output voltage Vout level becomes a predetermined level.

[0057] Furthermore, the signal output circuit 61b is composed of a selection circuit 75 and an output circuit 76. Note that, for convenience, terminals are depicted in different positions in Figure 7 compared to Figure 6, but the wiring, components, etc., connected to each terminal are the same in Figures 6 and 7. Also, components with the same reference numerals are the same as those in the integrated circuit 30a in Figure 2.

[0058] The selection circuit 75 selects whether to generate the voltage Vcomp based on the error currents Ie1 and Ie2 supplied by the error voltage generation circuit 51 and the error voltage generation circuit 53, which will be described later.

[0059] Specifically, the selection circuit 75 discharges capacitors 33 and 34 with error currents Ie1 or Ie2, and charges them with the bias current Ib of the constant current source 82, depending on which of the diodes 80 and 81 (described later) is turned on. For example, the selection circuit 75 selects that when the output voltage Vout level falls below a predetermined level, a voltage Vcomp is generated by error current Ie1, and when the output voltage Vout level rises above a predetermined level, a voltage Vcomp is generated by error current Ie2.

[0060] The selection circuit 75 includes diodes 80 and 81 and a constant current source 82. Diode 80 has its cathode connected to the output of the error voltage generation circuit 51 and its anode connected to terminal COMP. Similarly, diode 81 has its cathode connected to the output of the error voltage generation circuit 53 (described later) and its anode connected to terminal COMP. The constant current source 82 supplies a bias current Ib to terminal COMP from an internal power supply (not shown) based on the power supply voltage Vdd.

[0061] Therefore, capacitors 33 and 34 are charged by the bias current Ib while being discharged by the error current Ie1 from the error voltage generation circuit 51 or the error current Ie2 from the error voltage generation circuit 53 described later. The selection circuit 75 also selects either the output voltage of the error voltage generation circuit 51 or the output voltage of the error voltage generation circuit 53 as the selection result.

[0062] The output circuit 76 outputs a drive signal Vq1 to turn on the NMOS transistor 25 based on the signal Vz from the comparator 60, and outputs a drive signal Vq1 to turn off the NMOS transistor 25 based on the selection result (i.e., voltage Vcomp) of the selection circuit 75.

[0063] The output circuit 76 is composed of a pulse circuit 91, an SR flip-flop 92, an oscillator circuit 93, and a comparator 94. Note that the pulse circuit 91, SR flip-flop 92, oscillator circuit 93, and comparator 94 are the same as those shown in Figure 2, and therefore their descriptions are omitted.

[0064] The error voltage generation circuit 51 has terminal FB1 connected to the inverting input terminal, and voltage Vfb1 is applied to it. In addition, the error voltage generation circuit 51 has a reference voltage VREF1 applied to the non-inverting input terminal.

[0065] Furthermore, the error voltage generation circuit 51 supplies an error current Ie1 to the output based on the error between the voltage Vfb1 and the reference voltage VREF1. Specifically, when the output voltage of the error voltage generation circuit 51 is lower than the voltage Vcomp by the forward voltage of the diode 80 and the diode 80 is turned on, the circuit causes a current corresponding to the error current Ie1 to flow through terminal COMP to capacitors 33 and 34. In this case, capacitors 33 and 34 are discharged by the current corresponding to the error current Ie1, so the voltage Vcomp decreases due to the current corresponding to the error current Ie1.

[0066] On the other hand, when the diode 80 is off, the error voltage generation circuit 51 cannot supply current corresponding to the error current Ie1 to capacitors 33 and 34 via terminal COMP. Note that voltage Vfb1 corresponds to the "first voltage," and reference voltage VREF1 corresponds to the "first reference voltage."

[0067] The error voltage generation circuit 53 generates a voltage Vcomp that corresponds to the error between a voltage Vfb2 corresponding to the level of the output voltage Vout and a reference voltage VREF2 used to set the output voltage Vout to a predetermined level. Furthermore, terminal FB2 is connected to the inverting input terminal of the error voltage generation circuit 53, and the voltage Vfb2 is applied to it. Also, the reference voltage VREF2 is applied to the non-inverting input terminal of the error voltage generation circuit 53. The reference voltage VREF2 is defined to be the voltage Vfb2 generated at the connection point of resistors 28 and 29 when the output voltage Vout reaches a predetermined level.

[0068] Furthermore, the error voltage generation circuit 53 supplies an error current Ie2 to the output based on the error between the voltage Vfb2 and the reference voltage VREF2. Specifically, when the output voltage of the error voltage generation circuit 53 is lower than the voltage Vcomp by the forward voltage of the diode 81 and the diode 81 is turned on, the circuit causes a current corresponding to the error current Ie2 to flow through terminal COMP to capacitors 33 and 34. In this case, capacitors 33 and 34 are discharged by the current corresponding to the error current Ie2, so the voltage Vcomp decreases due to the current corresponding to the error current Ie2.

[0069] On the other hand, when diode 81 is off, the error voltage generation circuit 53 cannot supply current corresponding to the error current Ie2 to capacitors 33 and 34 via terminal COMP. Note that the error voltage generation circuit 53 corresponds to the "second error voltage generation circuit," and the voltage Vcomp generated by the error voltage generation circuit 53 corresponds to the "second error voltage." Also, the voltage Vfb2 corresponds to the "second voltage," and the reference voltage VREF2 corresponds to the "second reference voltage."

[0070] <<<Operation of integrated circuit 30b>>> The operation of the integrated circuit 30b is described below. As mentioned above, in the AC-DC converter 10a, the output voltage Vout was controlled to increase as the peak value of the AC voltage Vac increased. Therefore, if the output voltage Vout significantly exceeds a predetermined level, the capacitor 24 may be destroyed. In the AC-DC converter 10b, in order to suppress the destruction of the capacitor 24, if the output voltage Vout exceeds a predetermined level, the error voltage generation circuit 53 is activated to maintain the output voltage Vout at a predetermined level. Accordingly, the constants of the circuits that generate the voltages Vfb1 and Vfb2, and the reference voltages VREF1 and VREF2 are determined so that this operation is achieved.

[0071] If the output voltage Vout is below a predetermined level, the error voltage generation circuit 51 reduces the output voltage based on the voltage Vfb1 to turn on the diode 80. The selection circuit 75 then selects the output voltage of the error voltage generation circuit 51 because the diode 80 is turned on. If the output voltage Vout exceeds a predetermined level, the error voltage generation circuit 53 operates and reduces the duty cycle, causing the voltage Vfb1 to decrease, and the error voltage generation circuit 51 increases the output voltage. As a result, the cathode voltage becomes higher, and the diode 80 turns off.

[0072] As a result, the error voltage generation circuit 51 stops generating the voltage Vcomp, and the selection circuit 75 stops selecting the output voltage of the error voltage generation circuit 51. When the selection circuit 75 selects the output voltage of the error voltage generation circuit 51, the operation of the integrated circuit 30b is the same as that of the integrated circuit 30a, and the integrated circuit 30b causes the AC-DC converter 10b to output an output voltage Vout that increases as the peak value of the AC voltage Vac increases, as shown in the region in Figure 8 where the peak value of the AC voltage Vac is less than 310V.

[0073] Furthermore, if the output voltage Vout exceeds a predetermined level, the error voltage generation circuit 53 lowers the output voltage based on the voltage Vfb2 to turn on the diode 81. The selection circuit 75 also selects the output voltage of the error voltage generation circuit 53. When the output voltage Vout falls below the predetermined level, the voltage Vfb2 decreases, so the error voltage generation circuit 53 increases the output voltage. As a result, the cathode voltage increases, and the diode 81 turns off.

[0074] As a result, the error voltage generation circuit 53 stops generating the voltage Vcomp, and the selection circuit 75 stops selecting the output voltage of the error voltage generation circuit 53. Also, when the selection circuit 75 selects the output voltage of the error voltage generation circuit 53, the integrated circuit 30b maintains the output voltage Vout at a predetermined level. In this case, the integrated circuit 30b causes the AC-DC converter 10b to output an output voltage Vout at a predetermined level, even when the peak value becomes large, as shown in the region where the peak value of the AC voltage Vac is 310V or higher in Figure 8.

[0075] ===Summary=== The AC-DC converters 10a and 10b of this embodiment have been described above. The integrated circuit 30a is configured to include an error voltage generation circuit 51 and a drive signal output circuit 50a. The error voltage generation circuit 51 generates a voltage Vcomp that determines the on-period of the NMOS transistor 25 according to the error between the voltage Vfb from the voltage generation circuit 31 that smooths the voltage generated in the secondary coil L2 and the reference voltage VREF1. This makes it possible to provide a switching control circuit that can suppress power loss in the power supply circuit without generating noise in the line on which the drive signal is output.

[0076] Furthermore, the drive signal output circuit 50a is configured to include a comparator 60 and a signal output circuit 61a. The comparator 60 can detect whether the inductor current IL has become "zero" based on the voltage Vzcd generated in the secondary coil L2. In this way, the secondary coil L2 is used to set the duty cycle of the drive signal Vq1 to a predetermined value and to detect when the inductor current IL becomes "zero," eliminating the need for extra components.

[0077] Furthermore, the integrated circuit 30b further includes an error voltage generation circuit 53. This suppresses the output voltage Vout to a predetermined level (e.g., 400V) even if the peak value of the AC voltage Vac becomes high, thereby preventing the breakdown of the capacitor 24, which has a breakdown voltage of, for example, 450V.

[0078] Furthermore, the signal output circuit 61b includes a selection circuit 75 and an output circuit 76. This allows the duty cycle of the signal Vdr to be set to a predetermined value when the peak value of the AC voltage Vac is low and the breakdown of the capacitor 24 is suppressed even when the boost ratio is controlled to a predetermined value. Conversely, when the peak value of the AC voltage Vac is high and there is a possibility that the capacitor 24 will be broken if the boost ratio is set to a predetermined value, the output voltage Vout can be maintained at a predetermined level.

[0079] Furthermore, the selection circuit 75 is composed of a diode 40, resistors 41 and 42, and a capacitor 43. As a result, when the NMOS transistor 25 is turned on, the diode 40 blocks the current based on the negative voltage Vzcd generated in the secondary coil L2, allowing the voltage generation circuit 31 to generate voltages Vfb and Vfb1 with a current based on the positive voltage Vzcd.

[0080] Furthermore, the secondary coil L2 is wound such that it generates a voltage with the opposite polarity to the voltage generated in the primary coil L1. As a result, when the NMOS transistor 25 is off, a positive voltage Vzcd is generated, and the integrated circuit 30a operates as shown in Figure 4. However, this is not the only example; even if the secondary coil L2 is wound so that it generates a voltage with the opposite polarity to the voltage generated in the primary coil L1, the integrated circuit 30a can achieve the same effect as in this embodiment by making some modifications to the integrated circuit 30a.

[0081] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0082] 10a, 10b AC-DC converter 11 Commercial power supply 12 loads 20 Full wave rectifier circuit 21, 24, 33, 34, 43 Capacitors 22 transformers 23, 40, 80, 81 diodes 25 NMOS transistors 26a, 26b Control Blocks 27. Voltage divider circuit 28, 29, 32, 41, 42 resistors 30a, 30b integrated circuits 31 Voltage Generation Circuit 50a, 50b Drive signal output circuit 51, 53 Error voltage generation circuit 52 buffers 60, 74, 94 comparators 61a, 61b Signal output circuit 71,91 pulse circuit 72,92 SR flip-flop 73,93 Oscillator Circuit 75 Selection Circuit 76 output circuit 82 Constant Current Source

Claims

1. A switching control circuit for a power supply circuit that generates an output voltage obtained by boosting the rectified voltage, comprising a transformer having a first winding to which a rectified voltage obtained by rectifying an AC voltage is applied, and a second winding to which a voltage corresponding to the voltage generated in the first winding is generated, and a transistor for controlling the inductor current flowing through the first winding, wherein the switching control circuit controls the switching of the transistor in the power supply circuit that generates an output voltage obtained by boosting the rectified voltage, A first error voltage generation circuit generates a first error voltage corresponding to the error between a first voltage obtained by smoothing the voltage generated in the second winding and a first reference voltage, A drive signal output circuit outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined current value, determines the on period of the transistor based on the first error voltage, and outputs the drive signal to turn off the transistor. A switching control circuit equipped with the following features.

2. A switching control circuit according to claim 1, The aforementioned drive signal output circuit is A current detection circuit that detects whether the inductor current has reached a predetermined current value based on the voltage generated in the second winding, A signal output circuit that outputs the drive signal to turn on the transistor based on the detection result of the current detection circuit, determines the on period based on the first error voltage so that the duty cycle of the drive signal becomes a predetermined value, and outputs the drive signal to turn off the transistor, A switching control circuit equipped with the following features.

3. A switching control circuit according to claim 2, The circuit further comprises a second error voltage generation circuit that generates a second error voltage corresponding to the error between a second voltage corresponding to the level of the output voltage and a second reference voltage for setting the level of the output voltage to a predetermined level. The aforementioned signal output circuit is When the output voltage level exceeds the predetermined level, the drive signal to turn off the transistor is output based on the second error voltage so that the output voltage level becomes the predetermined level. Switching control circuit.

4. A switching control circuit according to claim 3, The aforementioned signal output circuit is A selection circuit that selects the first error voltage when the output voltage level falls below the predetermined level, and selects the second error voltage when the output voltage level rises above the predetermined level. An output circuit that outputs the drive signal to turn on the transistor based on the detection result of the current detection circuit, and outputs the drive signal to turn off the transistor based on the selection result of the selection circuit, A switching control circuit equipped with the following features.

5. A switching control circuit according to any one of claims 1 to 4, The aforementioned power supply circuit is A voltage generation circuit that generates the first voltage by smoothing the voltage generated in the second winding, A switching control circuit equipped with the following features.

6. A switching control circuit according to claim 5, The voltage generation circuit is A diode with the anode connected to the second winding, A first resistor connected in series with the cathode of the diode, A second resistor is provided between the first resistor and ground, A capacitor is provided in parallel with the second resistor, Includes, The first voltage is the voltage generated at the connection point of the first and second resistors. Switching control circuit.

7. A switching control circuit according to claim 1, The second winding is wound such that it generates a voltage with the opposite polarity to the voltage generated in the first winding. Switching control circuit.

8. A transformer having a first winding to which a rectified voltage obtained by rectifying an AC voltage is applied, and a second winding to which a voltage corresponding to the voltage generated in the first winding is generated, A transistor that controls the inductor current flowing through the first winding, A switching control circuit for controlling the switching of the transistor, A power supply circuit comprising the above, which generates an output voltage obtained by boosting the rectified voltage, The aforementioned switching control circuit is A first error voltage generation circuit generates a first error voltage corresponding to the error between a first voltage obtained by smoothing the voltage generated in the second winding and a first reference voltage, A drive signal output circuit outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined current value, determines the on period of the transistor based on the first error voltage, and outputs the drive signal to turn off the transistor. Includes, The aforementioned power supply circuit is A voltage generation circuit that generates the first voltage by smoothing the voltage generated in the second winding, A power supply circuit including this.

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