Etching method for Group III nitride semiconductors

Abstract

This invention provides an etching method for group III nitride semiconductors that can be implemented using a simple etching apparatus. [Solution] The etching method for a group III nitride semiconductor according to this disclosure is 1E+19 / cm 3 The method includes a first step of preparing a group III nitride semiconductor having the above carrier concentration, and a second step of etching at least a portion of the group III nitride semiconductor by applying a voltage between the group III nitride semiconductor and the counter electrode while the semiconductor is immersed in an electrolyte.

Description

[Technical Field]

[0001] This disclosure relates to an etching method for group III nitride semiconductors. [Background technology]

[0002] Conventionally, photoelectrochemical etching has been used as a wet etching method for chemically stable group III nitride semiconductors. A technique for etching group III nitride semiconductors using photoelectrochemical etching is disclosed, for example, in Patent Document 1. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2007-227450 [Overview of the project] [Problems that the invention aims to solve]

[0004] Patent Document 1 proposes a method for selectively etching a group III nitride semiconductor by irradiating the semiconductor with light that is lower in band gap energy than the etch stop layer and higher in band gap energy than the layer to be etched.

[0005] However, the photoelectrochemical etching method described in Patent Document 1 requires the installation of an optical system that includes a light source that emits light in the ultraviolet region and a bandpass filter that selectively transmits only light near a specific wavelength range, which makes the etching apparatus complex and increases costs.

[0006] In light of these circumstances, this disclosure aims to provide an etching method for group III nitride semiconductors that can be implemented with a simple etching apparatus. [Means for solving the problem]

[0007] To achieve the above objective, the etching method for group III nitride semiconductors according to this disclosure is 1E+19 / cm 3 The method includes a first step of preparing a group III nitride semiconductor having the above carrier concentration, and a second step of etching at least a portion of the group III nitride semiconductor by applying a voltage between the group III nitride semiconductor and the counter electrode while the semiconductor is immersed in an electrolyte. [Effects of the Invention]

[0008] According to one aspect of this disclosure, a method for etching a group III nitride semiconductor that can be implemented with a simple etching apparatus can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] A graph showing the carrier concentration dependence of the etching rate in electrochemical etching of Group III nitride semiconductors. [Figure 2] Flowchart showing an etching method for a group III nitride semiconductor according to an embodiment of the present disclosure. [Figure 3] Schematic diagram showing an example of the configuration of an apparatus for fabricating Group III nitride semiconductors. [Figure 4] Flowchart showing the process for fabricating Group III nitride semiconductors. [Figure 5] A schematic diagram illustrating the electrochemical etching apparatus for Group III nitride semiconductors. [Figure 6] A schematic diagram showing a cross-section of a group III nitride semiconductor after etching. [Figure 7A] Cross-sectional SEM images obtained by scanning electron microscope after etching of a group III nitride semiconductor according to the example. [Figure 7B] Graph showing the change in current density during etching of a group III nitride semiconductor according to the examples. [Figure 8A] A schematic cross-sectional diagram conceptually illustrating a group III nitride semiconductor device according to an embodiment of the present disclosure. [Figure 8B]Schematic cross-sectional view conceptually showing an example in which a wafer of a group-III nitride semiconductor device in FIG. 8A is thinned using the etching method according to the embodiment [Figure 9A] Schematic cross-sectional view conceptually showing a group-III nitride semiconductor stacked device according to an embodiment of the present disclosure [Figure 9B] Schematic cross-sectional view conceptually showing an example in which a substrate of a group-III nitride semiconductor stacked device in FIG. 9A is etched using the etching method according to the embodiment [Figure 10A] Schematic cross-sectional view conceptually showing the configuration of an N-polarity GaN-HEMT [Figure 10B] Diagram conceptually showing the manufacturing process of an N-polarity GaN-HEMT to which the etching method according to the embodiment is applied

Mode for Carrying Out the Invention

[0010] (Knowledge on which the present disclosure is based) The inventors of the present application have obtained new findings regarding the relationship between the etching rate and the carrier concentration of the etching target in the electrochemical etching of group-III nitride semiconductors. This will be described with reference to FIG. 1. FIG. 1 is a graph showing the carrier concentration dependence of the etching rate in the electrochemical etching of group-III nitride semiconductors.

[0011] It is generally known that the etching rate of electrochemical etching changes depending on the electrical conductivity of the etching target. The inventors of the present application examined the relationship between the etching rate and the carrier concentration of the etching target in the electrochemical etching of group-III nitride semiconductors. FIG. 1 shows that the carrier concentrations are GaN substrate A less than 1E+15 / cm 3 and GaN substrate B of about 2E+18 / cm 3 and GaN substrate C of about 1E+19 / cm 3 and GaN substrate D of about 5E+19 / cm 3 and GaN substrate E of about 1E+20 / cm 3These are the results of measuring the etching rates when electrochemical etching was performed using the GaN substrates E and [omitted text]. In this specification, E represents a power of 10. For example, 1E+19 represents 10 19 means

[0012] As shown in FIG. 1, the etching rate of the GaN substrate A with a carrier concentration of less than 1E+15 / cm 3 is almost zero, and for the GaN substrate B with 2E+18 / cm 3 , the etching rate is 200 μm / h, but this is etched in a porous state and substantially no electrochemical etching is progressing. On the other hand, when the carrier concentration is about 1E+19 / cm 3 is used as the threshold, the etching rate clearly increases, and for the GaN substrate C with a carrier concentration of about 1E+19 / cm 3 , the etching rate exceeded 600 μm / h. Furthermore, it was found that for the GaN substrates D and E with a carrier concentration of 5E+19 / cm 3 or more, the etching rate increased significantly and reached 3,000 μm / h or more. Note that FIG. 1 shows the results at an applied voltage of 13V. Even when the applied voltage to the GaN substrate B was increased to 33V, it resulted in layered peeling and no good electrochemical etching progressed.

[0013] In this specification, in the electrochemical etching of group III nitride semiconductors, the carrier concentration at which the etching rate clearly starts to increase is referred to as the "etching threshold". The inventors of the present application found that in the electrochemical etching of group III nitride semiconductors, the etching threshold exists around 1E+19 / cm 3 . Based on this novel finding, the inventors of the present application arrived at the invention according to the following disclosure.

[0014] According to the first aspect of the present disclosure, 1E+19 / cm 3The present invention provides an etching method for a group III nitride semiconductor, comprising: a first step of preparing a group III nitride semiconductor having the above-mentioned carrier concentration; and a second step of applying a voltage between the group III nitride semiconductor and a counter electrode while immersed in an electrolyte to etch at least a portion of the group III nitride semiconductor.

[0015] According to this embodiment, a method for etching a group III nitride semiconductor that can be implemented with a simple etching apparatus can be provided.

[0016] According to a second aspect of this disclosure, the carrier concentration is 5E+19 / cm³. 3 The above provides an etching method for a group III nitride semiconductor as described in the first embodiment.

[0017] A third aspect of this disclosure provides an etching method for a group III nitride semiconductor according to the first or second aspect, wherein the first step includes supplying a nitrogen-containing gas and a group III element oxide gas into a chamber and growing a group III nitride crystal in the chamber to produce a group III nitride semiconductor.

[0018] A fourth aspect of this disclosure provides an etching method for a group III nitride semiconductor according to the third aspect, further comprising adjusting the supply amount of group III element oxide gas with respect to the amount of nitrogen element-containing gas supplied into the chamber.

[0019] According to a fifth aspect of this disclosure, the second step provides an etching method for a group III nitride semiconductor according to any one of the first to fourth aspects, having an etching rate of 1 mm / h or more.

[0020] According to a sixth aspect of this disclosure, the method for etching a group III nitride semiconductor is provided as described in any one of the first to fifth aspects, wherein the group III nitride semiconductor is gallium nitride, and among the impurities contained in the group III nitride semiconductor, the impurity with the highest concentration is oxygen, Ge, or Sn.

[0021] According to a seventh aspect of this disclosure, an etching method for a group III nitride semiconductor according to the sixth aspect is provided, wherein the impurity with the highest concentration is oxygen.

[0022] According to the eighth aspect of this disclosure, the etching method for a group III nitride semiconductor described in any one of the first to seventh aspects is provided, wherein the group III nitride semiconductor constitutes a semiconductor film, semiconductor crystal layer, semiconductor wafer, or semiconductor substrate containing a nitride of a group III element.

[0023] Furthermore, by appropriately combining any of the above various embodiments, the effects of each can be achieved.

[0024] The embodiments will be described in detail below, with reference to the drawings as appropriate. However, unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters and redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding for those skilled in the art.

[0025] An etching method for a group III nitride semiconductor according to an embodiment of the present disclosure will be described with reference to Figures 1 to 9B. The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present disclosure and are not intended to limit the subject matter described in the claims. In addition, elements in each figure are exaggerated for the sake of clarity. Substantially identical components in the drawings are denoted by the same reference numerals.

[0026] <Embodiment 1> (Etching method for Group III nitride semiconductors) Referring to Figure 2, the etching method for a group III nitride semiconductor according to Embodiment 1 of this disclosure will be described. Figure 2 is a flowchart of the etching method for a group III nitride semiconductor according to an embodiment of this disclosure.

[0027] As shown in FIG. 2, the method for etching a group-III nitride semiconductor according to an embodiment of the present disclosure can include a step (S01) of preparing a group-III nitride semiconductor having a carrier concentration equal to or higher than an etching threshold, and a step (S02) of etching a desired portion of the prepared group-III nitride semiconductor by electrochemical etching. Hereinafter, each step will be described in detail.

[0028] (Step S01 of preparing a group-III nitride semiconductor) The group-III nitride semiconductor according to an embodiment of the present disclosure can constitute a semiconductor film, a semiconductor crystal layer, a semiconductor wafer, or a semiconductor substrate containing a nitride of a group-III element. Further, in the embodiment of the present disclosure, step S01 of preparing a group-III nitride semiconductor can include growing a group-III nitride crystal to fabricate a group-III nitride semiconductor. Hereinafter, step S01 will be described with reference to FIGS. 3 and 4 together. FIG. 3 is a schematic diagram showing a configuration example of an apparatus 150 for fabricating a group-III nitride semiconductor, and FIG. 4 is a flowchart showing a process 200 for fabricating a group-III nitride semiconductor.

[0029] <Overview of apparatus for fabricating group-III nitride semiconductor> The overview of an apparatus 150 for fabricating a group-III nitride semiconductor will be described with reference to FIG. 3. Note that in FIG. 3, the sizes, ratios, etc. of each component member may be different from the actual ones.

[0030] In an apparatus 150 for fabricating a group-III nitride semiconductor according to the present embodiment, a raw material reaction chamber 101 is disposed in a raw material chamber 100, and a raw material boat 104 on which a starting group-III element source 105 is placed is disposed in the raw material reaction chamber 101. A reactive gas supply pipe 103 for supplying a reactive gas that reacts with the starting group-III element source 105 is connected to the raw material reaction chamber 101, and it also has a group-III oxide gas discharge port 107. Here, when the starting group-III source is an oxide, a reducing gas is used as the reactive gas, and when the starting group-III source is a metal, an oxidizing gas is used as the reactive gas. Further, the raw material chamber 100 is further provided with a first carrier gas supply port 102.

[0031] The group-III oxide gas generated in the raw material reaction chamber 101 is discharged into the raw material chamber 100 through the group-III oxide gas discharge port 107, passes through the connecting pipe 109 from the carrier gas discharge port 108 together with the carrier gas, and flows into the growth chamber 111.

[0032] The growth chamber 111 includes a group-III oxide gas and carrier gas supply port 118, an oxidizable gas supply port 113, a nitrogen element-containing gas supply port 112, a second carrier gas supply port 114, and an exhaust port 119. A susceptor 117 on which a support substrate 116 is disposed is provided in the growth chamber 111, and a group-III nitride semiconductor can be fabricated by growing a group-III nitride crystal on the support substrate 116.

[0033] <Fabrication Process of Group-III Nitride Semiconductor> Using FIGS. 3 and 4, the fabrication process 200 of the group-III nitride semiconductor according to the present embodiment will be described in detail. In the process 200, a group-III nitride semiconductor is fabricated by growing a group-III nitride crystal by an Oxide Vapor Phase Epitaxy (OVPE) method using a group-III element oxide gas as a raw material. In the present embodiment, for example, the group-III nitride semiconductor is a gallium nitride semiconductor and is composed of gallium nitride crystals. In the following description, the group-III nitride semiconductor is referred to as a "GaN semiconductor". Also, the formation process of the GaN semiconductor will be described by taking the case where metallic Ga is used as the starting group-III element source 105 as an example.

[0034] The process 200 for fabricating the group-III nitride semiconductor shown in FIG. 4 can include a reactive gas supply step (S201), a group-III element oxide gas generation step (S202), a group-III element oxide gas supply step (S203), a nitrogen element-containing gas supply step (S204), a group-III nitride crystal generation step (S205), and a residual gas discharge step (S206). Each step will be described below.

[0035] (1) In the reactive gas supply process S201, the reactive gas is supplied to the raw material reaction chamber 101 from the reactive gas supply pipe 103.

[0036] There are two main methods for generating Group III oxide gases: one that reduces the starting Ga source 105, and another that oxidizes the starting Ga source 105. For example, in the reduction method, an oxide (e.g., Ga2O3) is used as the starting Ga source 105, and a reducing gas (e.g., H2 gas, CO gas, CH4 gas, C2H6 gas, H2S gas, SO2 gas) is used as the reactive gas. On the other hand, in the oxidation method, a non-oxide (e.g., liquid Ga) is used as the starting Ga source 105, and an oxidizing gas (e.g., H2O gas, O2 gas, CO gas) is used as the reactive gas. In step S201, the reactive gas corresponding to the starting Ga source 105 used can be supplied to the raw material reaction chamber 101. In this embodiment, for example, when metallic Ga is used as the starting Group III element source 105, an oxidizing gas is supplied to the raw material reaction chamber 101 from the reactive gas supply pipe 103.

[0037] (2) In the Group III element oxide gas generation step S202, the reactive gas supplied to the raw material reaction chamber 101 in the reactive gas supply step reacts with the metal Ga, which is the starting Group III element source 105, to produce Ga2O gas, which is a Group III oxide gas. The generated Ga2O gas is discharged from the raw material reaction chamber 101 to the raw material chamber 100 via the Group III oxide gas outlet 107. The discharged Ga2O gas is mixed with the first conveying gas supplied to the raw material chamber from the first conveying gas supply port 102 and supplied to the Group III oxide gas and conveying gas outlet 108. Here, an inert gas or H2 gas can be used as the first conveying gas.

[0038] In this embodiment, when H2O gas, an oxidizing gas, is supplied to the raw material reaction chamber 101 as the reactive gas, a group III oxide gas is generated, for example, by the following formula (1).

[0039] [ka]

[0040] Here, the temperature of the first heater 106 is set to 800°C or higher from the viewpoint of the boiling point of Ga2O gas, and to less than 1800°C to be lower than that of the second heater 115. The starting Ga source is placed inside the raw material boat 104. The raw material boat 104 is preferably shaped to maximize the contact area between the reactive gas and the starting Ga source.

[0041] (3) In the Group III element oxide gas supply step S203, the Ga2O gas generated in the Group III element oxide gas generation step S202 is supplied to the growth chamber 111 via the Group III oxide gas and transport gas outlet 108, the connecting pipe 109, and the Group III oxide gas and transport gas supply port 118. In this embodiment, the amount of Group III element oxide gas Ga2O gas supplied to the growth chamber 111 can be adjusted.

[0042] Furthermore, if the temperature of the connecting pipe 109, which connects the raw material chamber 100 and the growth chamber 111, drops below the temperature of the raw material chamber 100, the reverse reaction of the reaction that produces group III oxide gas occurs, and the starting Ga source 105 precipitates in the connecting pipe 109. Therefore, the connecting pipe 109 is heated to a higher temperature than the first heater 106 by the third heater 110 so that its temperature does not drop below the temperature of the raw material chamber 100.

[0043] (4) In the nitrogen element-containing gas supply process S204, nitrogen element-containing gas is supplied to the growth chamber 111 from the nitrogen element-containing gas supply port 112. As the nitrogen element-containing gas, NH3 gas, NO gas, NO2 gas, N2O gas, N2H2 gas, N2H4 gas, etc. can be used.

[0044] (5) In the Group III nitride crystal formation process S205, the raw material gas supplied to the growth chamber via each supply process is synthesized to form Group III nitride crystals. The growth chamber 111 is heated to a temperature at which the Group III oxide gas and nitrogen element-containing gas react using the second heater 115. At this time, the temperature of the growth chamber 111 is heated so as not to fall below the temperature of the raw material chamber 100 in order to prevent the reverse reaction of the reaction that produces the Group III oxide gas from occurring.

[0045] In this embodiment, the temperature of the second heater 115 can be set to, for example, 1200°C or higher. Furthermore, the temperature of the third heater 110 can be set according to the set temperature of the second heater 115 in order to suppress temperature fluctuations in the growth chamber 111 caused by the Ga2O gas generated in the raw material chamber 100 and the first transport gas. As a result, the support substrate 116 placed in the growth chamber 111 is maintained at a temperature of 1200°C or higher, and GaN crystals can be grown on the support substrate 116.

[0046] In this embodiment, in step S205, a GaN semiconductor can be fabricated by growing a GaN crystal on the support substrate 116 according to the following formula (2) by mixing Ga2O gas, which is a group III oxide gas supplied to the growth chamber 111 via the group III element oxide gas supply step S203, and NH3 gas, which is a nitrogen element-containing gas supplied to the growth chamber 111 via the nitrogen element-containing gas supply step S204, upstream of the support substrate 116.

[0047] [ka]

[0048] In step S205, for example, the carrier concentration of the generated group III nitride GaN crystal can be adjusted by adjusting the amount of group III oxide gas Ga2O gas supplied to the nitrogen element-containing gas NH3 supplied to the growth chamber 111.

[0049] Furthermore, in order to suppress the decomposition of the nitrogen-containing gas shown in Figure 3 by the heat from the growth chamber 111, it is preferable to cover the nitrogen-containing gas supply port 112 and the outer wall of the growth chamber 111 with an insulating material.

[0050] Furthermore, parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 is a problem. Therefore, by controlling the concentration of group III oxide gas and nitrogen element-containing gas with the second transport gas supplied to the growth chamber 111 from the second transport gas supply port 114, parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 can be suppressed. Here, an inert gas or H2 gas can be used as the second transport gas.

[0051] (6) In the residual gas discharge process S206, the transport gas that does not contribute to the generation of GaN crystals and unreacted gases are discharged from the exhaust port 117.

[0052] The carrier concentration of a group III nitride semiconductor depends on the concentration of impurity elements contained in the group III nitride semiconductor. Among the impurities contained in a group III nitride semiconductor, oxygen, germanium (Ge), or tin (Sn) can be added at the highest concentration and can be contained in the group III nitride semiconductor. In this embodiment, the GaN semiconductor fabricated by the OVPE method has oxygen as the most concentrated impurity, and because it has a very high oxygen concentration, it can have a high carrier concentration. In this embodiment, for example, by adjusting the supply amount of group III oxide gas Ga2O gas in process 200, the fabricated GaN semiconductor can have a carrier concentration of 5E+19 / cm². 3 It is possible to have a carrier concentration higher than the above. Thus, the group III nitride semiconductors fabricated by the OVPE method have a carrier concentration above the etching threshold shown in Figure 1 and can be etched at a high etching rate using electrochemical etching.

[0053] In the OVPE method, the growth temperature and growth time of the GaN crystal can be set as needed, and the GaN crystal can be grown to the required thickness. Although the production of GaN crystals has been described as an example, this disclosure is not limited to this. For example, in the Group III nitride semiconductor fabrication apparatus 150 shown in Figure 3, in addition to the Ga source, an In source and an Al source can also be used as the starting Group III element source 105. This makes it possible to grow Group III nitride crystals such as InN (indium nitride) and AlN (aluminum nitride). In this way, by growing Group III nitride crystals using the OVPE method, semiconductor films, semiconductor crystal layers, semiconductor wafers, and semiconductor substrates containing nitrides of various Group III elements can be fabricated.

[0054] It should be noted that preparing a group III nitride semiconductor having a carrier concentration above the etching threshold according to the embodiments of this disclosure is not limited to the OVPE method. For example, it is also possible to prepare a group III nitride semiconductor film having a carrier concentration above the etching threshold using the sputtering method.

[0055] (Step S02: Etching of a group III nitride semiconductor by electrochemical etching) Returning to Figure 2, we will now explain step S02, in which a desired portion of the prepared group III nitride semiconductor is etched by electrochemical etching, with reference to Figures 5 and 6. Figure 5 is a schematic diagram showing the electrochemical etching apparatus 250 for the group III nitride semiconductor 126. Figure 6 is a schematic diagram showing a cross-section of the group III nitride semiconductor 126A after etching.

[0056] Step S02 is performed using the electrochemical etching apparatus 250 shown in Figure 5. As shown in Figure 5, the GaN semiconductor 126 prepared in step S01 is immersed in the electrolyte 30 stored in the container 40 of the electrochemical etching apparatus 250. With the GaN semiconductor 126 immersed in the electrolyte 30, it is connected to the positive terminal of the power supply unit 60 via the current detector 50, and the platinum (Pt) counter electrode 20, which is immersed in the electrolyte 30, is connected to the negative terminal of the power supply unit 60. The power supply unit 60 outputs a DC voltage, and by applying the voltage between the GaN semiconductor 126 and the Pt counter electrode 20, the GaN semiconductor 126 can be etched.

[0057] A current detector 50, positioned between the power supply 60 and the GaN semiconductor 126, detects the current flowing through the etching circuit, and the detected signal can be sent to, for example, a control device (not shown). By sending a command signal to the power supply 60 via the control device, the value of the applied voltage can be changed, and etching can be started or stopped by starting or stopping the output of the DC voltage. Alternatively, the applied voltage may be controlled manually based on the detection result of the current detector 50 without using a control device.

[0058] The electrolyte 30 can be a solution obtained by dissolving an alkali such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or an acid such as hydrochloric acid (HCl), in water, glycol, etc., and can be maintained at a predetermined temperature in the container 40 during etching.

[0059] As shown in Figure 6, when etching a desired portion of the GaN semiconductor 126, an etching mask 127, pre-made of SiO2 or a SiN film, can be placed on the upper surface 126a of the GaN semiconductor 126 in the area that is not to be etched. When a voltage is applied by the power supply 60, etching proceeds, and the electrolyte 30 dissolves the upper surface 126a of the GaN semiconductor 126a starting from the portion corresponding to the opening 127a of the etching mask, forming a recess 128 in the GaN semiconductor 126A after etching. The etching depth D from the upper surface 126a to the bottom surface 128a of the recess 128 can be controlled, for example, by changing the amount of current flowing through the etching circuit.

[0060] The etching method described above enables etching of group III nitride semiconductors using a simple electrochemical etching apparatus 250 as shown in Figure 5.

[0061] In the above explanation, the carrier concentration of a group III nitride semiconductor was described using the case where oxygen is added as an impurity element as an example, but this disclosure is not limited to this. For example, the impurity element added to the group III nitride semiconductor may be germanium (Ge) or tin (Sn) in addition to oxygen, and multiple types of impurity elements may coexist.

[0062] (Etching of Group III nitride semiconductors by example) Etching of a group III nitride semiconductor was performed using the etching method according to the embodiment of this disclosure. Hereinafter, an example according to the embodiment of this disclosure will be described with reference to Figures 7A and 7B. Figure 7A is a cross-sectional SEM image taken with a scanning electron microscope of the group III nitride semiconductor after etching according to the embodiment. Figure 7B is a graph showing the change in current density during etching of the group III nitride semiconductor according to the embodiment.

[0063] In this embodiment, a GaN crystal was grown on a commercially available HVPE-GaN substrate 135 using the OVPE method, thereby fabricating an OVPE-GaN semiconductor layer 136. The fabricated sample 130 was immersed in a 1 mol / L KOH aqueous solution, with the OVPE-GaN semiconductor layer side as the anode and a platinum (Pt) counter electrode as the cathode, and electrochemical etching was performed at an applied voltage of 7 V. After electrochemical etching, the sample 130 was observed using a scanning electron microscope (SEM) to evaluate the etching.

[0064] (Evaluation of etching of group III nitride semiconductors by example) The carrier concentration of sample 130 was measured using the Hall assay method. In this example, the HVPE-GaN substrate 135, fabricated by the HVPE method, mainly contained silicon (Si) as an impurity, and its carrier concentration was 2E+18 / cm³. 3 The OVPE-GaN semiconductor layer 136, fabricated by the OVPE method, mainly contains oxygen as an impurity, and its carrier concentration is 5E+19 / cm³. 3 It was found that the carrier concentration was above the etching threshold.

[0065] In the cross-sectional SEM image shown in Figure 7A, the portion indicated by symbol A is portion 136A of the OVPE-GaN semiconductor layer with an etching mask placed on its upper surface, and the portion indicated by symbol B is portion 136B of the etched OVPE-GaN semiconductor layer. As shown in the figure, it can be seen that portion 136B was dissolved by the electrolyte.

[0066] Furthermore, as shown in Figure 7A, in portion 136B, etching progressed to the interface 136a between the OVPE-GaN semiconductor layer 136 and the HVPE-GaN substrate 135. In the cross-sectional SEM image of Figure 7A, the cross-sectional portion of portion 136B is etched up to the interface 136a, but in the depth direction, a "cliff" of portion 136A of the OVPE-GaN semiconductor layer, where the etching mask was placed and left unetched, can be observed. On the other hand, in the HVPE-GaN substrate 135, etching did not progress, and it can be seen that the HVPE-GaN substrate 135, which has a carrier concentration lower than the etching threshold, effectively functioned as an etch stop layer. Observation of the cross-sectional SEM image of Figure 7A shows that the etching depth D was approximately 270 μm.

[0067] Next, as shown in Figure 7B, during period T1 from the start of etching to approximately 800 seconds, the current density was 2 mA / mm². 2 As described above, the etched OVPE-GaN semiconductor layer 136 exhibited good electrical conductivity because it had a high carrier concentration. During period T1, the OVPE-GaN semiconductor layer of portion 136B was almost completely etched at a high etching rate.

[0068] At point E1 shown in Figure 7B, the current density decreases sharply to 0.5 mA / mm². 2 The etching rate fell below a certain level. At this point, etching reached the vicinity of the interface 136a between the OVPE-GaN semiconductor layer 136 and the HVPE-GaN substrate 135. It is thought that the thin, early-stage OVPE-GaN semiconductor layer near interface 136a has a relatively low oxygen concentration, causing an increase in electrical resistance and a sharp decrease in the etching rate.

[0069] During the period T2 from point E1 to point E2 (approximately 1600 seconds), etching did not progress significantly, and at point E2, etching self-stopped and was completed. Assuming that etching progressed to an etching depth of D270 μm during the 800-second period T1 shown in Figure 7B, in this embodiment, the etching rate of the OVPE-GaN semiconductor layer 136 was approximately 1227 μm / h, achieving an etching rate of 1 mm / h or more. Compared to Figure 1, the carrier concentration was 5E+19 / cm³. 3 The etching rate was lower than that obtained in Figure 1, because electrochemical etching was performed with an applied voltage of 7V in this embodiment, whereas Figure 1 shows the results obtained with an applied voltage of 13V.

[0070] This embodiment confirms that etching of group III nitride semiconductors can be achieved using a simple etching apparatus with the etching method according to the embodiment of this disclosure, and that a high etching rate can be achieved. Furthermore, the etching method according to the embodiment of this disclosure can avoid the risk of damage that may occur during machining, significantly improve the processing speed of group III nitride semiconductors, and reduce processing costs.

[0071] The etching method of this disclosure can be applied, for example, to thinning of group III nitride semiconductor wafers, selective etching of group III nitride semiconductor substrates, or fabrication of N-polarity GaN-HEMTs. Examples of these applications will be described below with reference to Figures 8A to 9B.

[0072] (Application Example 1: Thinning of Group III nitride semiconductor wafers) Examples of the etching method of this disclosure being applied to the thinning of a group III nitride semiconductor wafer are conceptually shown in Figures 8A and 8B. Figure 8A is a schematic cross-sectional view conceptually showing a group III nitride semiconductor device 300 according to an embodiment of this disclosure, and Figure 8B is a schematic cross-sectional view conceptually showing an example of thinning the wafer of the group III nitride semiconductor device 300 of Figure 8A using the etching method according to the embodiment.

[0073] Group III nitride semiconductors are widely used in optical semiconductor devices such as light-emitting diodes (LEDs) or semiconductor laser diodes (LDs), and electronic devices such as power devices. For example, the Group III nitride semiconductor device 300 conceptually shown in Figure 8A can be constructed by providing a functional layer 320 on the front surface 310a of a semiconductor wafer 310. In the case of an optical semiconductor device, the functional layer 320 may include, for example, a light-emitting layer (not shown) containing a Group III nitride element, and in the case of a power device, it may include, for example, a channel layer (not shown) containing a Group III nitride element.

[0074] To reduce the thermal resistance of these Group III nitride semiconductor devices, the semiconductor wafer 310 can be thinned. However, thinning the semiconductor wafer by mechanical grinding and polishing, or by chemical mechanical polishing (CMP), requires long processing times of several hours, resulting in increased costs and also creating a risk of damage to semiconductor elements in the functional layer during processing.

[0075] Therefore, the wafer of the group III nitride semiconductor device 300 can be thinned using the etching method according to the embodiment of this disclosure. Specifically, for example, a group III nitride semiconductor wafer 310 having a carrier concentration above the etching threshold is fabricated by the OVPE method, and a functional layer 320 is placed on its front surface 310a. Next, the group III nitride semiconductor wafer 310 can be thinned by electrochemical etching from the back surface 310b using electrochemical etching.

[0076] In electrochemical etching, a group III nitride semiconductor wafer 310 having a carrier concentration above the etching threshold enables a high etching rate (Figure 1). Therefore, for example, etching to a depth of approximately 300-400 μm can be completed within one hour, allowing for the thinning of a group III nitride semiconductor wafer 310 with a thickness of 400-500 μm to 50-100 μm. Furthermore, since non-contact etching can be performed on the functional layer 320 provided on the front surface 310a of the wafer 310, the risk of damage that may occur during mechanical grinding / polishing or chemical mechanical polishing (CMP) can be significantly reduced.

[0077] The group III nitride semiconductor device 300A, conceptually shown in Figure 8B, is formed by thinning the central portion of a group III nitride semiconductor wafer 310 with a thickness of H1 to a thickness of h1, attaching electrodes 330 to the back surface 310b, and then mounting it to a heat dissipation die 350 via high thermal conductivity solder 340. In this way, by thinning a portion of the wafer 310, the thermal resistance can be reduced while maintaining sufficient wafer strength by leaving the support portion intact. Furthermore, good ohmic electrodes can be formed on a group III nitride semiconductor wafer 310 with a high carrier concentration fabricated by the OVPE method without alloying treatment. Since thermal degradation during alloying treatment can be avoided, surface processes such as cleaning and oxide film removal can be carried out without constraints, enabling the fabrication of high-performance, high-yield semiconductor devices.

[0078] (Application Example 2: Selective Etching of Group III Nitride Semiconductor Substrates) Examples of the application of the etching method of this disclosure to the selective etching of a group III nitride semiconductor substrate are conceptually shown in Figures 9A and 9B. Figure 9A is a schematic cross-sectional view conceptually showing a group III nitride semiconductor multilayer device 400 according to an embodiment of this disclosure, and Figure 9B is a schematic cross-sectional view conceptually showing an example in which the substrate of the group III nitride semiconductor multilayer device 400 of Figure 9A is etched using the etching method according to the embodiment.

[0079] Field-effect transistors (FIELD-EVERYS) are electronic devices that utilize Group III nitride semiconductors. For example, HEMTs (High Electron Mobility Transistors) are constructed by stacking multiple Group III nitride semiconductor layers with different compositions on a semi-insulating self-supporting substrate. In HEMT manufacturing, contamination of the substrate surface by silicon (Si) is a challenge. For instance, during HEMT manufacturing, surface contaminants such as siloxanes can lead to high concentrations of Si being incorporated at the interface between the substrate and the Group III nitride semiconductor layer (epitaxial layer), resulting in the formation of conductive leak paths (Si pile-up).

[0080] Furthermore, in high-frequency devices, a process of thinning the substrate is carried out to achieve impedance matching. However, when substrate thinning is performed by mechanical grinding and polishing or chemical mechanical polishing (CMP), not only is it time-consuming, but there is also a risk of damage to the epitaxial layer during processing.

[0081] The above problems can be addressed and a HEMT can be manufactured by selectively etching a group III nitride semiconductor substrate using the etching method according to the embodiments of this disclosure. The group III nitride semiconductor stacked device 400 conceptually shown in Figure 9A is constructed by sequentially stacking a high-resistance layer 420, a channel layer 430, and an electron supply layer 440 on the upper surface of a group III nitride semiconductor substrate 410 having a carrier concentration above an etching threshold, which is fabricated by the OVPE method.

[0082] The high-resistance layer 420 can be composed of, for example, an iron (Fe)-doped Fe-GaN buffer layer. The channel layer 430 can be composed of, for example, a GaN layer, and the electron supply layer 440 can be composed of, for example, AlGaN. The high-resistance layer 420, the channel layer 430, and the electron supply layer 440 can be continuously laminated on the front surface 410a of the group III nitride semiconductor substrate 410 in an MOCVD apparatus without exposure to the outside air.

[0083] After laminating a high-resistance layer 420, a channel layer 430, and an electron supply layer 440 on the front surface 410a of a group III nitride semiconductor substrate 410, the group III nitride semiconductor substrate 410 can be thinned by etching from the back surface 410b using electrochemical etching. For example, a group III nitride semiconductor substrate 410 having a carrier concentration above the etching threshold, fabricated by the OVPE method, can achieve a high etching rate (Figure 1).

[0084] During the manufacturing process of the multilayer device 400, Si may be incorporated into the front surface 410a of the substrate 410, but this Si can be removed by etching from the back surface 410b of the substrate 410. This effectively suppresses Si pile-up. Furthermore, the high-resistance layer 420 laminated on the front surface 410a of the substrate 410 has a low carrier concentration and can effectively function as an etch-stopping layer. In addition, by etching the group III nitride semiconductor substrate 410 using electrochemical etching, the group III nitride semiconductor substrate can be thinned in a short time, avoiding the risk of damage to the epitaxial layer that may occur during mechanical grinding / polishing or chemical mechanical polishing (CMP).

[0085] As conceptually shown in Figure 9B, for example, by etching away the central portion of a group III nitride semiconductor substrate 410 with a thickness of H2 and leaving a substrate portion 410A with a thickness of h2 on the outer periphery, a group III nitride semiconductor multilayer device 400A with a thin substrate and sufficient handling properties can be constructed. Furthermore, although not shown, it is also possible to completely remove the group III nitride semiconductor substrate 410 using electrochemical etching to realize a thin-film and Si pile-up-free GaN on GaN HEMT.

[0086] In this way, by selectively etching the group III nitride semiconductor substrate, Si pile-up can be suppressed, and the group III nitride semiconductor multilayer device can be thinned at low cost without damaging the high-resistance layer 420, enabling the fabrication of high-efficiency, high-power HEMT devices.

[0087] (Application Example 3: Fabrication of N-polarity GaN-HEMTs) An example of applying the etching method of this disclosure to the fabrication of an N-polar GaN-HEMT will be described with reference to Figures 10A and 10B. Figure 10A is a schematic cross-sectional view conceptually showing the configuration of an N-polar GaN-HEMT 500, and Figure 10B is a diagram conceptually showing the fabrication process of an N-polar GaN-HEMT 500A to which the etching method according to the embodiment is applied.

[0088] Conventional nitride semiconductor devices have been fabricated on (0001) plane (+c plane) GaN. The most stable phase of nitride semiconductors is the wurtzite structure, and they lack inversion symmetry in the c-axis direction. Therefore, the c plane has polarity, with the (0001) plane (+c plane) being Ga polar, and the opposite (000-1) plane (-c plane) being N polar. Hereinafter, HEMTs using Ga polar GaN and HEMTs using N polar GaN will be referred to as "Ga polar GaN-HEMT" and "N polar GaN-HEMT" (also called "reverse HEMT"), respectively.

[0089] In recent years, N-polarity GaN has attracted considerable attention. One reason for this is that power amplifiers for fifth-generation mobile communication systems require high-frequency operation, and N-polarity GaN-HEMTs are advantageous for high-frequency operation. As conceptually shown in Figure 10A, an N-polarity GaN-HEMT is constructed by sequentially hetero-growing an AlGaN barrier layer 540 and a GaN channel layer 530 on an N-polarity semi-insulating substrate 550. At this time, a two-dimensional electron gas (2DEG) with a high electron density is formed at the heterointerface between the AlGaN barrier layer 540 and the GaN channel layer 530.

[0090] To achieve high-frequency operation of a device, the distance between the gate electrode and the channel must be shortened. In a Ga polar GaN-HEMT structure, for example, if we refer to device 400 in Figure 9A as an example of a Ga polar device configuration, the AlGaN barrier layer (electron supply layer 440) on the channel layer 430 must be thinned in order to shorten the distance between the gate electrode and the channel. However, as the AlGaN barrier layer is thinned, the electron concentration in 2DEG also decreases, and the electrical resistance increases. Therefore, in a Ga polar GaN-HEMT structure, shortening the channel is difficult due to the trade-off between operating frequency and electrical resistance.

[0091] On the other hand, in the N-polarity GaN-HEMT 500 shown in Figure 10A, the distance between the gate electrode 570b and the channel can be shortened by thinning the top layer GaN channel layer 530 without using the AlGaN barrier layer 540. Therefore, it is possible to shorten the channel while maintaining the thickness of the AlGaN barrier layer 540. In addition, in the N-polarity GaN-HEMT structure, as shown in the figure, the AlGaN barrier layer 540 is located below the GaN channel layer 530, so 2DEG is strongly confined in the GaN channel layer 530, and low contact resistance can be expected because the top layer is GaN.

[0092] To commercialize the highly anticipated N-polar GaN devices, high-quality N-polar GaN epitaxial growth technology is required. However, GaN epitaxial growth in the N-polarity direction (-c direction) presents significant challenges. One challenge is that N-polar GaN is prone to hillock formation on its surface, making it difficult to obtain a flat surface. Furthermore, among the residual impurities present in N-polar GaN, oxygen is the most concentrated impurity, and the oxygen concentration in N-polar GaN tends to be higher than in Ga-polar GaN. Oxygen acts as a shallow donor, negatively affecting device characteristics. Therefore, achieving high purity in N-polar GaN crystals is another factor hindering commercialization.

[0093] Therefore, by applying the etching method according to the embodiment of this disclosure, the above problems can be addressed and an N-polarity GaN-HEMT can be fabricated. The fabrication process for an N-polarity GaN-HEMT 500A using the etching method according to the embodiment of this disclosure will now be described with reference to Figure 10B. In the fabrication process conceptually shown in Figure 10B, an N-polarity GaN-HEMT 500A can be fabricated through steps (a) to (c).

[0094] In step (a), an inverse HEMT structure is epitaxially grown on a Ga-polarized GaN substrate. Here, the Ga-polarized GaN substrate is, for example, a GaN substrate 510 having a carrier concentration above the etching threshold, which is fabricated by the OVPE method described above. An inverse HEMT structure can be obtained by sequentially heterogrowing, for example, a GaN channel layer 530, an AlGaN barrier layer 540, and an Fe-GaN buffer layer 520 on the OVPE-Ga-polarized GaN substrate 510.

[0095] Next, in step (b), after bonding the upper surface of the inverted HEMT structure obtained in step (a) to the support substrate 560, the OVPE-Ga polar GaN substrate 510 is completely removed from the back surface 510b by electrochemical etching. Since the Ga polar GaN substrate 510 fabricated by the OVPE method has a carrier concentration above the etching threshold, the Ga polar GaN substrate 510 can be completely removed in a short time at a high etching rate (Figure 1), exposing the surface 530a of the GaN channel layer 530. At this time, a portion of the Ga polar GaN film may be left in the area where the ohmic electrode is formed.

[0096] Next, in step (c), a source electrode 570a, a gate electrode 570b, and a drain electrode 570c are formed on the surface 530a of the GaN channel layer 530 exposed in step (b) to complete the N-polarity GaN-HEMT500A.

[0097] In the fabrication process for the N-polarity GaN-HEMT conceptually shown in Figure 10B, epitaxial growth is performed in the Ga polarity direction (+c direction in the figure), thus improving the problems of flatness and purity present in GaN epitaxial growth in the N polarity direction (-c direction), and enabling high-purity and flat epitaxial growth. Furthermore, because a GaN substrate 510 is used, defects are reduced in heterogeneous growth, enabling higher power output of the device. Moreover, if the support substrate 560 is made of a highly thermally conductive material such as diamond or SiC, an N-polarity GaN-HEMT with excellent heat dissipation can be fabricated.

[0098] As described above, the attached drawings and detailed description are provided to illustrate the embodiments of the technology described herein. Therefore, the components described in the attached drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem, in order to illustrate the technology described above. Therefore, the mere presence of such non-essential components in the attached drawings and detailed description should not be immediately assumed to mean that those non-essential components are essential.

[0099] While this disclosure is fully described in relation to preferred embodiments with reference to the accompanying drawings, various modifications are possible within the scope of the claims. Such modifications, as well as embodiments obtained by appropriately combining the technical means disclosed in different embodiments, are also included in the technical scope of this disclosure. [Industrial applicability]

[0100] This disclosure is applicable to the manufacture of Group III nitride semiconductor devices. According to the etching method for Group III nitride semiconductors described herein, etching of Group III nitride semiconductors can be achieved using a simple etching apparatus. [Explanation of symbols]

[0101] 20 Counter electrode 30 Electrolyte 40 containers 50 Current detectors 60 Power supply 100 Raw Material Chambers 101 Raw Material Reaction Room 102 First conveying gas supply port 103 Reactive gas supply pipe 104 Raw material boat 105 Starting Group III element source (Starting Ga source) 106 First Heater 107 Group III oxide gas outlet 108 Group III oxide gas and transport gas outlet 109 Connecting pipe 110 Third Heater 111 Rearing Chamber 112 Nitrogen-containing gas supply port 113 Oxidizable gas supply port 114 Second transport gas supply port 115 Second heater 116 Support substrate 117 PCB Susceptor 118 Group III oxide gas and transport gas supply port 119 Exhaust vent 126 Group III Nitride Semiconductors 127 Etching Mask 128 recesses 130 samples 135 HVPE-GaN substrate 136 OVPE-GaN semiconductor layer Fabrication apparatus for Group III nitride semiconductors (150) Fabrication process for Group III nitride semiconductors 250 Electrochemical etching apparatus 300 Group III Nitride Semiconductor Devices 310 Group III nitride semiconductor wafer 320 Functional Layers 330 electrode 340 solder 350 heat dissipation dies 400 Group III Nitride Semiconductor Multilayer Devices 410 Group III nitride semiconductor substrate 420 High resistance layer 430 channel layer 440 Electron supply layer 500 N-polarity GaN-HEMT 510Ga polarized GaN substrate 520 Fe-GaN buffer layer 530 GaN channel layer 540 AlGaN barrier layer 550 N-polarity semi-insulating substrate 560 Support substrate 570a Source electrode 570b Guard gate 570c ​​drain electrode

Claims

1. 1E+19 / cm ３ The first step is to prepare a group III nitride semiconductor having the above carrier concentrations, A second step involves applying a voltage between the group III nitride semiconductor and the counter electrode while immersed in an electrolyte solution to etch at least a portion of the group III nitride semiconductor, including, Etching method for group III nitride semiconductors.

2. The carrier concentration is 5E + 19 / cm³. ３ That's all. The etching method for a group III nitride semiconductor according to claim 1.

3. The first step is, The method includes supplying a nitrogen-containing gas and a group III element oxide gas into a chamber, and growing a group III nitride crystal in the chamber to produce the group III nitride semiconductor. The etching method for a group III nitride semiconductor according to claim 1 or 2.

4. The first step further includes adjusting the amount of the group III element oxide gas supplied with respect to the amount of the nitrogen element-containing gas supplied into the chamber. The etching method for a group III nitride semiconductor according to claim 3.

5. The second step has an etching rate of 1 mm / h or more. The etching method for a group III nitride semiconductor according to claim 1 or 2.

6. The aforementioned group III nitride semiconductor is gallium nitride, Among the impurities contained in the aforementioned Group III nitride semiconductor, the impurity with the highest concentration is either oxygen, Ge, or Sn. The etching method for a group III nitride semiconductor according to claim 1 or 2.

7. The impurity with the highest concentration is oxygen. The etching method for a group III nitride semiconductor according to claim 6.

8. The aforementioned Group III nitride semiconductor comprises a nitride of a Group III element and constitutes a semiconductor film, semiconductor crystal layer, semiconductor wafer, or semiconductor substrate. The etching method for a group III nitride semiconductor according to claim 1 or 2.

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