Method for manufacturing Group III nitride semiconductor devices

Abstract

This invention provides a method for manufacturing group III nitride semiconductor devices that facilitates p-type conversion by ion implantation. [Solution] A method for manufacturing a group III nitride semiconductor device according to the present disclosure includes: a first step of arranging a second impurity in a predetermined region near the surface of a first group III nitride semiconductor layer containing a first impurity by ion implantation; a second step of forming a protective layer of a second group III nitride semiconductor containing a third impurity on the surface of the first group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step of removing at least a portion of the protective layer to expose the region on the surface of the first group III nitride semiconductor layer.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a group III nitride semiconductor device, and more specifically, to a method for manufacturing a group III nitride semiconductor device that facilitates p-type conversion by ion implantation. [Background technology]

[0002] In realizing vertical Group III nitride power devices, localized p-type conductivity control technology using ion implantation is crucial. In the process of creating p-type regions by ion implantation, activation annealing is performed to restore the crystal after ion implantation. However, a challenge with nitride semiconductors is that nitrogen is desorbed from the substrate surface by thermal decomposition at high heat treatment temperatures, leading to a deterioration of crystallinity. For example, in the case of GaN, thermal decomposition occurs at temperatures above 850°C. If an annealing process at temperatures above 1200°C is performed to activate the ion-implanted region, GaN decomposition (nitrogen desorption) occurs during the annealing process. Therefore, p-type formation by ion implantation is extremely difficult for Group III nitride semiconductors.

[0003] A technique for suppressing nitrogen desorption of nitride semiconductors and achieving p-type formation by ion implantation is disclosed, for example, in Patent Document 1. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-155468 [Overview of the project] [Problems that the invention aims to solve]

[0005] Patent Document 1 proposes a method for suppressing nitrogen desorption and achieving p-type conversion by ion implantation through high-pressure annealing, which is performed in a high-pressure environment above the saturated vapor pressure of GaN.

[0006] However, in the high-pressure annealing described in Patent Document 1, for example, when annealing at 1400°C, the saturated vapor pressure of GaN is 600 MPa at 1400°C. Therefore, it is necessary to maintain a high pressure of 600 MPa or more inside the crucible where the GaN substrate is placed. Technically, it is difficult to construct a pressurized vessel that can withstand the harsh conditions of high pressure of 600 MPa or more and high temperature of 1400°C, especially a large pressurized vessel capable of handling large-area nitride semiconductor substrates. For this reason, there is still room for improvement in the conventional method of achieving p-type formation by ion implantation in the manufacturing of group III nitride semiconductor devices.

[0007] Therefore, this disclosure aims to solve the above-mentioned conventional problems and to provide a method for manufacturing a group III nitride semiconductor device that facilitates p-type conversion by ion implantation. [Means for solving the problem]

[0008] To achieve the above objective, the method for manufacturing a group III nitride semiconductor device according to the present disclosure includes: a first step of arranging a second impurity in a predetermined region near the surface of a first group III nitride semiconductor layer containing a first impurity by ion implantation; a second step of forming a protective layer of a second group III nitride semiconductor containing a third impurity on the surface of the first group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step of removing at least a portion of the protective layer to expose the region on the surface of the first group III nitride semiconductor layer. [Effects of the Invention]

[0009] According to one aspect of this disclosure, a method for manufacturing a group III nitride semiconductor device that facilitates p-type conversion by ion implantation can be provided. [Brief explanation of the drawing]

[0010] [Figure 1] Flowchart of the p-type conversion process in the manufacture of a group III nitride semiconductor device according to an embodiment of the present disclosure [Figure 2]An image diagram showing a process of disposing p-type impurities in a layer of a group-III nitride semiconductor by ion implantation in the process of FIG. 1 [Figure 3] A schematic diagram showing the configuration of an apparatus for forming a protective layer of a group-III nitride semiconductor [Figure 4] A flowchart showing a process of forming a protective layer of a group-III nitride semiconductor [Figure 5] An image diagram showing a process of forming a protective layer of a group-III nitride semiconductor and activating an impurity implantation region in the process of FIG. 1 [Figure 6] An image diagram showing a process of removing a protective layer of a group-III nitride semiconductor and exposing a p-type region in the process of FIG. 1 [Figure 7] A graph showing the dependence of the etching rate on the carrier concentration in the electrochemical etching of a group-III nitride semiconductor [Figure 8] A low-temperature photoluminescence (PL) spectrum of the surface of an n-type GaN layer from which a GaN protective layer has been removed according to an example [Embodiments for Carrying Out the Invention]

[0011] According to a first aspect of the present disclosure, a first step of disposing a second impurity by ion implantation in a predetermined region near the surface of a layer of a first group-III nitride semiconductor containing a first impurity, a second step of forming a protective layer of a second group-III nitride semiconductor containing a third impurity on the surface of the layer of the first group-III nitride semiconductor at a temperature of 1200° C. or higher, and a third step of removing at least a part of the protective layer and exposing a region on the surface of the layer of the first group-III nitride semiconductor are provided, and a method for manufacturing a group-III nitride semiconductor device is provided.

[0012] According to this aspect, a method for manufacturing a group-III nitride semiconductor device that facilitates p-type doping by ion implantation can be provided.

[0013] A second aspect of this disclosure provides a method for manufacturing a group III nitride semiconductor device as described in the first aspect, comprising a second step of supplying a nitrogen-containing gas and a group III element oxide gas into a chamber at near atmospheric pressure and growing a second group III nitride crystal constituting a protective layer on the surface of a first group III nitride semiconductor layer placed in the chamber.

[0014] According to a third aspect of this disclosure, the third step is an electrochemical etching step, wherein the carrier concentration of the protective layer of the second group III nitride semiconductor is 5E+19 / cm³. 3 Therefore, the carrier concentration of the first group III nitride semiconductor layer is 5E+19 / cm³. 3 The present invention provides a method for manufacturing a group III nitride semiconductor device according to the first or second embodiment, wherein the value is less than [value missing].

[0015] According to a fourth aspect of this disclosure, the carrier concentration in the region is 5E+19 / cm³. 3 The present invention provides a method for manufacturing a group III nitride semiconductor device according to the third embodiment, wherein the value is less than [value missing].

[0016] A fifth aspect of this disclosure provides a method for manufacturing a group III nitride semiconductor device according to any one of the first to fourth aspects, wherein the second group III nitride semiconductor is gallium nitride and the third impurity is oxygen.

[0017] According to a sixth aspect of this disclosure, a method for manufacturing a group III nitride semiconductor device according to any one of the first to fifth aspects is provided, wherein the second impurity is a p-type impurity, and is at least one selected from the group consisting of magnesium, calcium, beryllium, and zinc.

[0018] According to a seventh aspect of this disclosure, a method for manufacturing a group III nitride semiconductor device according to any one of the first to sixth aspects is provided, wherein the first impurity is at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese.

[0019] Furthermore, by appropriately combining any of the above various embodiments, the effects of each can be achieved.

[0020] The embodiments will be described in detail below, with reference to the drawings as appropriate. However, unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters and redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding for those skilled in the art.

[0021] A method for manufacturing a group III nitride semiconductor device according to embodiments of this disclosure will be described with reference to Figures 1 to 8. The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand this disclosure and are not intended to limit the subject matter described in the claims. In addition, elements in each figure are exaggerated for the sake of clarity. Substantially identical components in the drawings are denoted by the same reference numerals.

[0022] <Embodiment 1> (p-type conversion process in the manufacturing of Group III nitride semiconductor devices) Referring to Figure 1, the p-type conversion process in the manufacturing of a group III nitride semiconductor device according to Embodiment 1 of this disclosure will be explained. Figure 1 is a flowchart of the p-type conversion process in the manufacturing of a group III nitride semiconductor device according to Embodiment 1 of this disclosure.

[0023] Group III nitride semiconductor devices include light-emitting devices that utilize Group III nitride semiconductors, such as light-emitting diodes, and electronic devices that utilize Group III nitride semiconductors, such as field-effect transistors. In the manufacturing of Group III nitride semiconductor devices, a local p-type region can be constructed by the process shown in the flowchart of Figure 1.

[0024] The p-type conversion process shown in Figure 1 may include the steps of forming a layer of group III nitride semiconductor (S01), placing p-type impurities in the group III nitride semiconductor layer (S02), forming a protective layer of group III nitride semiconductor at a temperature of 1200°C or higher and activating the impurity implantation region (S03), and removing the protective layer of group III nitride semiconductor to expose the p-type region (S04). Each of these steps will be described below.

[0025] (Step S01: Forming a layer of Group III nitride semiconductor) In step S01, a layer of group III nitride semiconductor is formed on the support substrate. In this embodiment, the support substrate may be, for example, a substrate usable as a substrate for epitaxial growth, such as a GaN freestanding substrate, an AlN freestanding substrate, a sapphire substrate, or a silicon substrate. The layer of group III nitride semiconductor can be composed of, for example, gallium nitride containing n-type impurities (hereinafter referred to as the "n-type GaN layer"). The n-type impurities contained in the n-type GaN layer may be at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese. The n-type GaN layer can be formed by epitaxial growth, for example, generally by the HVPE method, and the n-type GaN layer formed by the HVPE method contains n-type impurities and has a density of 5E+19 / cm². 3 It has a carrier concentration of less than 10. In this specification, E represents a power of 10. For example, 1E+19 is 10 19 It means...

[0026] Since the formation of the n-type GaN layer using the HVPE method can employ conventionally known techniques, a detailed explanation will be omitted.

[0027] (Step S02: Placing p-type impurities) Next, step S02, which involves placing p-type impurities in the group III nitride semiconductor layer, will be explained with reference to Figure 2. Figure 2 is an illustrative diagram showing the process of placing p-type impurities M in the group III nitride semiconductor layer 10 by ion implantation in the process shown in Figure 1. Note that the support substrate supporting the group III nitride semiconductor layer 10 is not shown in Figure 2.

[0028] The group III nitride semiconductor layer 10 shown in Figure 2 is an n-type GaN layer. In step S02, where p-type impurities are placed in the n-type GaN layer, p-type impurities M are ion-implanted from the surface 10a of the n-type GaN layer. At this time, for example, a resist mask can be used to locally implant ions at a predetermined position on the surface 10a of the n-type GaN layer. After ion implantation is performed, the resist mask is removed.

[0029] The ionic species of p-type impurity M implanted into the n-type GaN layer may be at least one selected from the group consisting of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In this embodiment, Mg is used as the p-type impurity, and Mg ions can be implanted into the impurity implantation region 20 near the surface 10a of the n-type GaN layer.

[0030] The ion implantation acceleration voltage can be set according to the implantation depth. The higher the acceleration voltage, the deeper the Mg is implanted. In this embodiment, the impurity implantation region 20 having a depth D can be formed by implanting Mg ions multiple times while varying the implantation depth with different acceleration voltages. In this embodiment, the concentration of p-type impurity Mg in the impurity implantation region 20 is 5E+20 / cm² across the depth D. 3 It is less than . At this time, due to the self-compensation effect in the n-type GaN layer, the carrier concentration in the impurity implantation region 20 is 5E+19 / cm³. 3 It is less than.

[0031] Alternatively, nitrogen may be implanted along with Mg ion implantation. Co-implanting p-type impurities with nitrogen can reduce the amount of nitrogen vacancies that may be generated during ion implantation.

[0032] (Process S03 for Forming a protective layer of a Group III nitride semiconductor and activating an impurity implantation region) Subsequently, the process S03 of forming a protective layer on a Group III nitride semiconductor at a temperature of 1200 ° C or higher and activating the impurity implantation region will be described with reference to FIGS. 3 to 5 together. FIG. 3 is a schematic diagram showing the configuration of an apparatus 150 for forming a protective layer of a Group III nitride semiconductor, and FIG. 4 is a flowchart showing a forming process 300 of the protective layer of the Group III nitride semiconductor. FIG. 5 is an image diagram showing the process of forming the protective layer 30 of the Group III nitride semiconductor and activating the impurity implantation region 20 in the process of FIG. 1.

[0033] <Overview of an apparatus for forming a protective layer of a Group III nitride semiconductor> The outline of an apparatus 150 for forming a protective layer of a Group III nitride semiconductor according to an embodiment of the present disclosure will be described with reference to FIG. 3. In FIG. 3, the size, ratio, etc. of each component may be different from the actual ones.

[0034] In an apparatus 150 for forming a protective layer of a Group III nitride semiconductor according to an embodiment of the present disclosure, a raw material reaction chamber 101 is disposed in a raw material chamber 100, and a raw material boat 104 on which a starting Group III element source 105 is placed is disposed in the raw material reaction chamber 101. A reactive gas supply pipe 103 for supplying a reactive gas that reacts with the starting Group III element source 105 is connected to the raw material reaction chamber 101, and it also has a Group III oxide gas discharge port 107. Here, when the starting Group III source is an oxide, a reducing gas is used as the reactive gas, and when the starting Group III source is a metal, an oxidizing gas is used. The raw material chamber 100 is further provided with a first carrier gas supply port 102.

[0035] The Group III oxide gas generated in the raw material reaction chamber 101 is discharged into the raw material chamber 100 through the Group III oxide gas discharge port 107, passes through the connecting pipe 109 from the carrier gas discharge port 108 together with the carrier gas, and flows into the growth chamber 111.

[0036] The growth chamber 111 includes a group III oxide gas and carrier gas supply port 118, an oxidizable gas supply port 113, a nitrogen element-containing gas supply port 112, a second carrier gas supply port 114, and an exhaust port 119. Inside the growth chamber 111, a substrate susceptor 117 is provided, and a support substrate 116 on which an n-type GaN layer 10 having an impurity region 20 is formed is disposed on the substrate susceptor 117. In the process of forming a protective layer of a group III nitride semiconductor, a protective layer of a group III nitride semiconductor is formed on the surface 10a of the n-type GaN layer 10.

[0037] <Process of Forming a Protective Layer of a Group III Nitride Semiconductor> Using FIGS. 3 and 4, the process 300 of forming a protective layer of a group III nitride semiconductor according to this embodiment will be described in detail. In the process 300, group III nitride crystals are grown by the Oxide Vapor Phase Epitaxy (oxide vapor phase growth method OVPE) method using a group III element oxide gas as a raw material to form a protective layer of a group III nitride semiconductor. In this embodiment, the protective layer of the group III nitride semiconductor is a gallium nitride crystal layer and is composed of gallium nitride crystals. In the following description, the protective layer of the group III nitride semiconductor is referred to as a "GaN protective layer". Further, the process of forming a GaN protective layer will be described by taking the case where metallic Ga is used as the starting group III element source 105 as an example.

[0038] The process 300 of forming a protective layer of a group III nitride semiconductor shown in FIG. 4 can include a reactive gas supply step (S301), a group III element oxide gas generation step (S302), a group III element oxide gas supply step (S303), a nitrogen element-containing gas supply step (S304), a group III nitride crystal generation step (S305), and a residual gas discharge step (S306). Each of the steps will be described below. All steps of the process 300 of forming a protective layer of a group III nitride semiconductor can be performed near atmospheric pressure. In this specification, "near atmospheric pressure" means an atmospheric pressure range including an atmospheric pressure fluctuation of ±10% centered on the atmospheric pressure, that is, within a range of 0.9 atm to 1.1 atm.

[0039] (1) In the reactive gas supply process S301, the reactive gas is supplied to the raw material reaction chamber 101 from the reactive gas supply pipe 103.

[0040] There are two main methods for generating Group III oxide gases: one that reduces the starting Ga source 105, and another that oxidizes the starting Ga source 105. For example, in the reduction method, an oxide (e.g., Ga2O3) is used as the starting Ga source 105, and a reducing gas (e.g., H2 gas, CO gas, CH4 gas, C2H6 gas, H2S gas, SO2 gas) is used as the reactive gas. On the other hand, in the oxidation method, a non-oxide (e.g., liquid Ga) is used as the starting Ga source 105, and an oxidizing gas (e.g., H2O gas, O2 gas, CO gas) is used as the reactive gas. In step S301, the reactive gas corresponding to the starting Ga source 105 used can be supplied to the raw material reaction chamber 101. In this embodiment, for example, when metallic Ga is used as the starting Group III element source 105, an oxidizing gas is supplied to the raw material reaction chamber 101 from the reactive gas supply pipe 103.

[0041] (2) In the Group III element oxide gas generation step S302, the reactive gas supplied to the raw material reaction chamber 101 in the reactive gas supply step reacts with the metal Ga, which is the starting Group III element source 105, to produce Ga2O gas, which is a Group III oxide gas. The generated Ga2O gas is discharged from the raw material reaction chamber 101 to the raw material chamber 100 via the Group III oxide gas outlet 107. The discharged Ga2O gas is mixed with the first conveying gas supplied to the raw material chamber from the first conveying gas supply port 102 and supplied to the Group III oxide gas and conveying gas outlet 108. Here, an inert gas or H2 gas can be used as the first conveying gas.

[0042] In this embodiment, when H2O gas, an oxidizing gas, is supplied to the raw material reaction chamber 101 as the reactive gas, a group III oxide gas is generated, for example, by the following formula (1).

[0043] [ka]

[0044] Here, the temperature of the first heater 106 is set to 800°C or higher from the viewpoint of the boiling point of Ga2O gas, and to less than 1800°C to be lower than that of the second heater 115. The starting Ga source is placed inside the raw material boat 104. The raw material boat 104 is preferably shaped to maximize the contact area between the reactive gas and the starting Ga source.

[0045] (3) In the Group III element oxide gas supply step S303, the Ga2O gas generated in the Group III element oxide gas generation step S302 is supplied to the growth chamber 111 via the Group III oxide gas and transport gas outlet 108, the connecting pipe 109, and the Group III oxide gas and transport gas supply port 118. In this embodiment, the amount of Group III element oxide gas Ga2O gas supplied to the growth chamber 111 can be adjusted.

[0046] Furthermore, if the temperature of the connecting pipe 109, which connects the raw material chamber 100 and the growth chamber 111, drops below the temperature of the raw material chamber 100, the reverse reaction of the reaction that produces group III oxide gas occurs, and the starting Ga source 105 precipitates in the connecting pipe 109. Therefore, the connecting pipe 109 is heated to a higher temperature than the first heater 106 by the third heater 110 so that its temperature does not drop below the temperature of the raw material chamber 100.

[0047] (4) In the nitrogen element-containing gas supply process S304, nitrogen element-containing gas is supplied to the growth chamber 111 from the nitrogen element-containing gas supply port 112. NH3 gas, NO gas, NO2 gas, N2O gas, N2H2 gas, N2H4 gas, etc., can be used as the nitrogen element-containing gas.

[0048] (5) In the Group III nitride crystal formation process S305, the raw material gas supplied to the growth chamber via each supply process is synthesized to form Group III nitride crystals. The growth chamber 111 is heated to a temperature at which the Group III oxide gas and nitrogen element-containing gas react using the second heater 115. At this time, the temperature of the growth chamber 111 is heated so as not to fall below the temperature of the raw material chamber 100 in order to prevent the reverse reaction of the reaction that produces the Group III oxide gas from occurring.

[0049] In this embodiment, the temperature of the second heater 115 can be set so that the support substrate 116 placed in the growth chamber 111 reaches 1200°C or higher. Furthermore, the temperature of the third heater 110 can be set according to the set temperature of the second heater 115 in order to suppress temperature fluctuations in the growth chamber 111 caused by the Ga2O gas generated in the raw material chamber 100 and the first transport gas. As a result, the support substrate 116 placed in the growth chamber 111 is maintained at a temperature of 1200°C or higher, and GaN crystals can be grown on the support substrate 116. At the same time, a temperature of 1200°C or higher is reached as the temperature condition for activating the impurity implantation region 20 of the n-type GaN layer 10 on the support substrate 116, so the impurity implantation region 20 can be activated.

[0050] In this embodiment, in step S305, Ga2O gas, which is a group III oxide gas supplied to the growth chamber 111 via the group III element oxide gas supply step S303, and NH3 gas, which is a nitrogen element-containing gas supplied to the growth chamber 111 via the nitrogen element-containing gas supply step S304, are mixed upstream of the support substrate 116. By growing GaN crystals on the support substrate 116 according to the following formula (2), a GaN protective layer composed of GaN crystals can be formed on the surface 10a of the n-type GaN layer 10.

[0051] [ka]

[0052] In step S205, for example, the carrier concentration of the generated group III nitride GaN crystal can be adjusted by adjusting the amount of group III oxide gas Ga2O gas supplied to the nitrogen element-containing gas NH3 supplied to the growth chamber 111.

[0053] As shown in Figure 5, in the group III nitride crystal growth step S305, GaN crystals can be grown at a temperature of 1200°C or higher to form a GaN protective layer 30 on the surface 10a of the n-type GaN layer 10, and the impurity implantation region 20 can be activated to form a p-type region 20A. The growth of GaN crystals on the surface 10a of the n-type GaN layer 10 means that the equilibrium between adsorption and desorption on the surface is tilted towards adsorption. Therefore, the growth driving force of the GaN protective layer can suppress nitrogen desorption of the n-type GaN layer 10, while activating the impurity implantation region 20 to form a p-type region 20A.

[0054] Furthermore, in order to suppress the decomposition of the nitrogen-containing gas shown in Figure 3 by the heat from the growth chamber 111, it is preferable to cover the nitrogen-containing gas supply port 112 and the outer wall of the growth chamber 111 with an insulating material.

[0055] Furthermore, parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 is a problem. Therefore, by controlling the concentration of group III oxide gas and nitrogen element-containing gas with the second transport gas supplied to the growth chamber 111 from the second transport gas supply port 114, parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 can be suppressed. Here, an inert gas or H2 gas can be used as the second transport gas.

[0056] (6) In the residual gas discharge process S306, the transport gas that does not contribute to the generation of GaN crystals and unreacted gases are discharged from the exhaust port 119.

[0057] The carrier concentration of a group III nitride semiconductor depends on the concentration of impurity elements contained in the group III nitride semiconductor. A GaN protective layer formed by the OVPE method can contain high concentrations of impurity elements and therefore has a very high carrier concentration, which can be higher than, for example, an n-type GaN layer formed by the HVPE method. Specifically, in this embodiment, the impurity contained in the GaN protective layer 30 may be oxygen, and the GaN protective layer 30 has a carrier concentration of 5E+19 / cm². 3It is possible to have the above high carrier concentration. On the other hand, an n-type GaN layer formed by the HVPE method or the like has a carrier concentration of less than 5E+19 / cm 3 3.

[0058] Thus, in the step S03 of forming the protective layer of the group III nitride semiconductor and activating the impurity implantation region, by forming the GaN protective layer by the OVPE method at a temperature of 1200° C. or higher, it is possible to activate the impurity implantation region while suppressing nitrogen desorption. According to the OVPE method that can be performed near atmospheric pressure, it is possible to activate the impurity implantation region without requiring the harsh conditions of high-pressure annealing. In addition, the OVPE method, which is a vapor-phase growth method, can easily cope with, for example, a nitride semiconductor substrate with a large area up to 12 inches.

[0059] Note that the time required to activate the impurity implantation region 20 varies depending on the concentration of the impurity contained in the impurity implantation region 20 and the depth D of the impurity implantation region 20. In the OVPE method, the formation time of the GaN protective layer can be set as necessary, and long-time annealing as necessary is also possible.

[0060] In addition, the thickness T of the GaN protective layer formed in the step S03 can be changed depending on the time required to activate the impurity implantation region 20 and the temperature of the group III nitride crystal growth step S305 of the OVPE method. In principle, the GaN protective layer can be formed with a uniform thickness T by the OVPE method. The present disclosure is not limited to the thickness T of the GaN protective layer.

[0061] (Step S04 of removing the protective layer of the group III nitride semiconductor and exposing the p-type region) Returning to FIG. 1, subsequently, referring to FIGS. 6 and 7 together, the step S04 of removing the protective layer of the group III nitride semiconductor and exposing the p-type region will be described. FIG. 6 is an image diagram showing the step of removing the protective layer of the group III nitride semiconductor and exposing the p-type region in the process of FIG. 1. FIG. 7 is a graph showing the carrier concentration dependence of the etching rate in the electrochemical etching of the group III nitride semiconductor.

[0062] In this embodiment, step S04 is performed by electrochemical etching. It is generally known that the etching rate of electrochemical etching varies depending on the electrical conductivity of the material being etched. The inventors of this application investigated the relationship between the etching rate and the carrier concentration of the material being etched in the electrochemical etching of a group III nitride semiconductor. Figure 7 shows the results for carrier concentrations of 1E+15 / cm³, respectively. 3 GaN substrate A is less than 2E+18 / cm² 3 GaN substrate B and approximately 1E+19 / cm 3 The GaN substrate C and approximately 5E+19 / cm 3 The GaN substrate D, and approximately 1E+20 / cm 3 These are the results of measuring the etching rates when electrochemical etching was performed using GaN substrate E and .

[0063] As shown in Figure 7, the carrier concentration is 1E+15 / cm³. 3 The etching rate of GaN substrate A is nearly zero, at 2E+18 / cm². 3 In GaN substrate B, the etching rate is 200 μm / h, but this is due to etching into a porous state, and in effect, electrochemical etching is not progressing. On the other hand, the carrier concentration is approximately 1 E+19 / cm³. 3 The etching rate of the GaN substrate C increased to approximately 600 μm / h. Furthermore, the carrier concentration increased to 5E+19 / cm³. 3 Beyond a certain point, the etching rate increases significantly, and the carrier concentration becomes 5E+19 / cm³. 3 We have found that the etching rates of GaN substrates D and E reach 3000 μm / h or higher. Based on this finding, in this embodiment, the GaN protective layer 30 with a high carrier concentration can be selectively removed using electrochemical etching.

[0064] As shown in Figure 6, in step S04, electrochemical etching is performed at 5E+19 / cm 3At least a portion of the GaN protective layer 30 having such a high carrier concentration can be etched away to expose the p-type region 20A on the surface 10a of the n-type GaN layer 10. On the other hand, if the carrier concentration is 5E+19 / cm³ 3 The n-type GaN layer 10, with a carrier concentration of less than 5E+19 / cm³, has a low etching rate and can effectively function as an etch stop layer. Furthermore, the p-type region 20A has a carrier concentration of 5E+19 / cm³. 3 It is formed at a minimum level, has a low etching rate, and can be exposed without being substantially etched.

[0065] Electrochemical etching can be performed using conventional methods with solutions prepared by dissolving alkalis such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or acids such as hydrochloric acid (HCl), in water, glycol, etc. A detailed explanation is omitted here.

[0066] As described above, the process including steps S01 to S04 makes it possible to suppress nitrogen desorption and achieve p-type conversion by ion implantation in the manufacturing of group III nitride semiconductor devices without requiring high-pressure annealing.

[0067] (Preparation of p-type regions according to the examples) Using the method for manufacturing a group III nitride semiconductor device according to the embodiments of this disclosure, a localized p-type region was formed by ion implantation. Examples of embodiments according to this disclosure are described below.

[0068] In this embodiment, an impurity region was formed on the surface of an n-type GaN layer containing n-type impurity silicon (Si) by ion implantation. At this time, an acceleration voltage of 30 keV was used, and the dose was 5.8E+13 / cm². 2 By implantation, Mg and nitrogen were co-implanted from the surface of the n-type GaN layer in the order of N → Mg.

[0069] Next, a GaN protective layer was formed on the surface of the n-type GaN layer using the OVPE method, and the impurity implantation region was activated. During this process, GaN film deposition was carried out at a temperature of 1200°C for 1 hour.

[0070] Next, a portion of the GaN protective layer was removed by electrochemical etching. In this process, an n-type GaN substrate with the GaN protective layer formed on it was immersed in a 1M KOH aqueous solution. The substrate was used as the anode, and a platinum (Pt) electrode as the cathode. Electrochemical etching was performed at an applied voltage of 13V. After the GaN protective layer was removed, the surface flatness of the substrate was confirmed by AFM, and a low-temperature photoluminescence (PL) spectrum was obtained.

[0071] (Evaluation of the p-type region by example)

[0072] In this example, an n-type GaN layer that was not intentionally doped with impurities was subjected to a peak concentration of 1E+19 / cm³. 3 Mg was injected. Furthermore, the carrier concentration of the GaN protective layer formed by the OVPE method was measured using the Hall assay method, and the result was 5E+19 / cm³. 3 That was all.

[0073] Scanning electron microscopy (SEM) observation revealed that the GaN protective layer formed by the OVPE method was polycrystalline and had a thickness of approximately 40 μm. Electrochemical etching successfully removed most of the GaN protective layer, although some remained. Surface flatness of the substrate after removal was evaluated by AFM, and the RMS value was 0.4 nm, indicating no surface roughness.

[0074] Figure 8 shows the results of low-temperature photoluminescence measurements of the substrate surface exposed after removing the GaN protective layer. Figure 8 is the low-temperature photoluminescence (PL) spectrum of the surface of the n-type GaN layer after removing the GaN protective layer according to the example. As shown in Figure 8, a peak P1 caused by Mg was clearly observed at a photon energy of approximately 3.28 eV, confirming that Mg was activated.

[0075] According to the p-type conversion process in this embodiment, it is possible to manufacture a group III nitride semiconductor device in which a localized p-type region can be formed by ion implantation.

[0076] In the above description, the group III nitride semiconductor layer formed on the support substrate was described as a gallium nitride crystal layer (n-type GaN layer), but this disclosure is not limited thereto. For example, the group III nitride semiconductor layer may be composed of AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), or a mixed crystal thereof.

[0077] Furthermore, although the protective layer of the group III nitride semiconductor formed by the OVPE method has been described as a gallium nitride crystal layer (GaN protective layer), this disclosure is not limited thereto. For example, in the apparatus 150 for forming the protective layer of the group III nitride semiconductor shown in Figure 3, in addition to the Ga source, an In source or an Al source can be used as the starting group III element source 105. The formed group III nitride crystal layer may be composed of, for example, InN (indium nitride), AlN (aluminum nitride), etc.

[0078] Furthermore, although step S04, which removes the protective layer of the group III nitride semiconductor shown in Figure 1 and exposes the p-type region, has been described as being performed by electrochemical etching, this disclosure is not limited thereto. For example, the protective layer of the group III nitride semiconductor can also be removed by photoelectrochemical etching or machining.

[0079] As described above, the attached drawings and detailed description are provided to illustrate the embodiments of the technology described herein. Therefore, the components described in the attached drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem, in order to illustrate the technology described above. Therefore, the mere presence of such non-essential components in the attached drawings and detailed description should not be immediately assumed to mean that those non-essential components are essential.

[0080] While this disclosure is fully described in relation to preferred embodiments with reference to the accompanying drawings, various modifications are possible within the scope of the claims. Such modifications, as well as embodiments obtained by appropriately combining the technical means disclosed in different embodiments, are also included in the technical scope of this disclosure. [Industrial applicability]

[0081] This disclosure is applicable to the manufacture of Group III nitride semiconductor devices. The method for manufacturing Group III nitride semiconductor devices according to this disclosure makes it possible to suppress nitrogen desorption without requiring high-pressure annealing and to achieve p-type conversion by ion implantation. [Explanation of symbols]

[0082] 10. Layer of Group III nitride semiconductor (n-type GaN layer) 20 Impurity implantation region 20A p-type region 30 Group III nitride semiconductor protective layer (GaN protective layer) 100 Raw Material Chambers 101 Raw Material Reaction Room 102 First conveying gas supply port 103 Reactive gas supply pipe 104 Raw material boat 105 Starting Group III element source (Starting Ga source) 106 First Heater 107 Group III oxide gas outlet 108 Group III oxide gas and transport gas outlet 109 Connecting pipe 110 Third Heater 111 Rearing Chamber 112 Nitrogen-containing gas supply port 113 Oxidizable gas supply port 114 Second transport gas supply port 115 Second heater 116 Support substrate 117 PCB Susceptor 118 Group III oxide gas and transport gas supply port 119 Exhaust vent Apparatus for forming protective layers of 150 group III nitride semiconductors Process for forming protective layers in 300 group III nitride semiconductors

Claims

1. A first step involves arranging a second impurity in a predetermined region near the surface of a first group III nitride semiconductor layer containing a first impurity by ion implantation. A second step of forming a protective layer of a second group III nitride semiconductor containing a third impurity on the surface of the first group III nitride semiconductor layer at a temperature of 1200°C or higher, A third step involves removing at least a portion of the protective layer to expose the region on the surface of the first group III nitride semiconductor layer, including, A method for manufacturing group III nitride semiconductor devices.

2. The second step is, The process involves supplying a nitrogen-containing gas and a group III element oxide gas into a chamber at near atmospheric pressure, and growing a second group III nitride crystal constituting the protective layer on the surface of the first group III nitride semiconductor layer placed in the chamber. A method for manufacturing a group III nitride semiconductor device according to claim 1.

3. The third step described above is an electrochemical etching step, The carrier concentration of the protective layer of the second group III nitride semiconductor is 5E + 19 / cm². ３ That's all, The carrier concentration of the first group III nitride semiconductor layer is 5E + 19 / cm². ３ Less than, A method for manufacturing a group III nitride semiconductor device according to claim 1 or 2.

4. The carrier concentration in the aforementioned region is 5E + 19 / cm³. ３ Less than, A method for manufacturing a group III nitride semiconductor device according to claim 3.

5. The second group III nitride semiconductor is gallium nitride, and the third impurity is oxygen. A method for manufacturing a group III nitride semiconductor device according to claim 1 or 2.

6. The second impurity is a p-type impurity, and is at least one selected from the group consisting of magnesium, calcium, beryllium, and zinc. A method for manufacturing a group III nitride semiconductor device according to claim 1 or 2.

7. The first impurity is at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese. A method for manufacturing a group III nitride semiconductor device according to claim 1 or 2.

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