Fan-out type wafer-level packaging unit

Abstract

This invention provides a fan-out wafer-level packaging (FOWLP) unit that effectively reduces thickness, simplifies the process, lowers manufacturing costs, and effectively improves usability and reliability. [Solution] A FOWLP unit 1 mainly consists of one substrate 10, one first dielectric layer 20, multiple first conductive wires 30, at least one first die 40, one second dielectric layer 50, at least one conductive pillar 60, multiple second conductive wires 70, one third dielectric layer 80, multiple third conductive wires 90, and at least one second die 100, wherein each first die and each second die are electrically connected to the outside via each first solder pad 91 around the die region on the second surface of each first die. Each first conductive wire, each second conductive wire, and each third conductive wire are manufactured by first filling a recess with metal paste and then polishing it to form a conductive wire.

Description

Technical Field

[0001] The present invention relates to a sealing unit, and particularly to a fan-out wafer level packaging (FOWLP) unit.

Background Art

[0002] In FOWLP, an advanced packaging technology, the redistribution layer (RDL) is considered the most important because each conductive wire in the RDL can electrically extend and interconnect in the XY plane direction with respect to a plurality of die pads on the die, and can form a plurality of solder pads dispersed around the die, thereby more effectively improving the design space and reliability of each conductive wire. However, for each conductive wire in the RDL, in order to maintain or achieve lightweight, thin, and miniaturized to a certain extent simultaneously, the formation of each conductive wire in the RDL is the most important.

[0003] However, in the RDL technology applied in the conventional FOWLP packaging technology, as a method for forming each conductive wire, a chemical plating technology or an electroplating forming technology is adopted. In such a method, not only the material cost and manufacturing cost become relatively high, but also the process in the conventional technology does not meet the environmental requirements or is disadvantageous in terms of environmental protection.

[0004] Also, in the FOWLP unit, when it is necessary to improve the performance or computing power, it is essential to add the number of dies separately. Therefore, how to realize the external or internal electrical connection between the dies inside and outside the FOWLP unit is the most important issue to be improved.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] The main object of the present invention is to provide a FOWLP unit which includes a substrate, a first dielectric layer, a plurality of first conductive wires, at least one first die, a second dielectric layer, at least one conductive pillar, a plurality of second conductive wires, a third dielectric layer, a plurality of third conductive wires, and at least one second die. Each of the first and second dies is electrically connected to the outside via each of the first solder pads around the die region located on the second surface of each of the first dies. Each of the first, second, and third conductive wires is manufactured by a technique in which metal paste is first filled into recesses and then polished to form conductive wires. This provides a fan-out wafer-level packaging unit which can effectively solve the problems of higher manufacturing costs and environmental disadvantages that tend to occur when manufacturing each conductive wire in conventional FOWLP technology modules. [Means for solving the problem]

[0007] To solve the above-mentioned objectives, the present invention provides a FOWLP unit. A first embodiment of the present invention includes one substrate, one first dielectric layer, a plurality of first conductive wires, at least one first die, one second dielectric layer, at least one conductive pillar, a plurality of second conductive wires, one third dielectric layer, a plurality of third conductive wires, and at least one second die.

[0008] The substrate has one first surface and one opposing second surface, and a substrate dielectric layer is provided on the second surface.

[0009] The first dielectric layer is provided on the substrate dielectric layer of the substrate and has at least one first recess formed by stretching it horizontally.

[0010] Each of the first conductive wires is provided by filling each of the first recesses with metal paste.

[0011] Each of the first dies is divided from a single wafer and has one first surface and one opposing second surface, with a plurality of first die pads on the first surface, and the vertical range of the chips on the second surface is defined as a die region. Each of the first dies has at least one chip conductive pillar that penetrates the first surface and the second surface, so that the first surface is electrically connected to the second surface via each chip conductive pillar. Each of the first dies electrically connects each die pad and each first conductive wire of each first die by positioning the first surface on each first conductive wire using flip-chip technology.

[0012] The second dielectric layer is provided on the first dielectric layer and covers each of the first dies. It has at least one second recess and at least one through hole formed by extending horizontally, each second recess communicating with each through hole, and each through hole communicating with each first recess.

[0013] Each of the conductive pillars is formed within each of the through holes and is exposed to the outside through each of the through holes. Each of the conductive pillars is electrically connected to each of the first conductive wires.

[0014] Each of the second conductive wires is provided by filling each of the second recesses with metal paste and is electrically connected to each of the conductive pillars.

[0015] The third dielectric layer is provided on the second dielectric layer and each of the second conductive wires, and has at least one opening formed by extending it horizontally, with metal paste filling each of the openings. The at least one opening is located around the die region on the second surface of each of the first die.

[0016] Each of the third conductive wires is exposed to the outside through each opening, and a first solder pad is formed within each opening, electrically connecting each of the second conductive wires.

[0017] Each of the second dies is divided from a single wafer and has one first surface and one opposing second surface, with a plurality of first die pads on the first surface. Each of the second dies has at least one chip conductive pillar that penetrates the first surface and the second surface, so that the first surface is electrically connected to the second surface via each chip conductive pillar. Each of the second dies electrically connects each die pad to each third conductive wire by positioning the first surface on each third conductive wire using flip-chip technology.

[0018] Each of the second dies is electrically connected to each of the first dies via, in order, each die pad of each of the second dies, each third conductive wire, each second conductive wire, each conductive pillar, each first conductive wire, and each first die pad of each of the first dies.

[0019] Each of the second dies is electrically connected to the outside via, in order, each die pad of the second die, each third conductive wire, each second conductive wire, each third conductive wire, and each first solder pad around the die region located on the second surface of the first die. Each of the first dies is electrically connected to the outside via, in order, each die pad of the first die, each first conductive wire, each conductive pillar, each second conductive wire, each third conductive wire, and each first solder pad around the die region located on the second surface of the first die, thereby forming the FOWLP unit.

[0020] The method for manufacturing the FOWLP unit 1 includes the following steps.

[0021] Step S1: A substrate is provided. The substrate has one first surface and one opposing second surface. A substrate dielectric layer is provided on the second surface.

[0022] Step S2: Multiple first conductive wires are formed on the dielectric layer of the substrate using a technique that involves filling recesses with metal paste and then polishing it to form conductive wires. First, one first dielectric layer is laid on the second surface of the substrate. Next, multiple first recesses are formed horizontally on the first dielectric layer, and then metal paste is filled into each of the first recesses, with the thickness of the metal paste being higher than the surface of the first dielectric layer. Finally, the metal paste that is higher than the surface of the first dielectric layer is polished so that the surface of the metal paste is aligned with the surface of the first dielectric layer, thereby forming multiple first conductive wires.

[0023] Step S3: Multiple first dies, separated from at least one wafer, are placed on the second surface of the substrate at intervals. Each first die has one first surface and one opposing second surface, and on the first surface, there are multiple first die pads, defining the vertical extent of the chips on the second surface as the die region. Each first die has at least one chip conductive pillar that penetrates the first surface and the second surface of each first die. Each first die can be electrically connected to each first conductive wire by using flip-chip technology to position the first surface of each first die on each first conductive wire.

[0024] Step S4: After filling the metal paste into the recesses, a plurality of second conductive lines are formed on the second surface of each of the first dies by using a technique of polishing to form conductive lines. First, a second dielectric layer is laid on the second surface of the substrate and on each of the first dies, and the second dielectric layer covers each of the first dies. Next, a plurality of second recesses in the horizontal direction and a plurality of through holes penetrating the second dielectric layer downward are formed on the second dielectric layer. Further, each die pad of each of the first dies can be exposed to the outside through each of the second recesses. And each of the through holes communicates with each of the first recesses and each of the second recesses. Then, first, a conductive pillar is formed in each of the communicating through holes, and then the metal paste is filled into each of the second recesses, and the thickness of the metal paste is made higher than the surface of the second dielectric layer. Finally, by polishing the metal paste that is higher than the surface of the second dielectric layer, the surface of the metal paste is aligned with the same plane as the surface of the second dielectric layer, thereby constituting a plurality of the second conductive lines.

[0025] Step S5: After filling the metal paste into the recesses, a plurality of third conductive lines are formed on the second dielectric layer by using a technique of polishing to form conductive lines. First, a third dielectric layer is laid on the second dielectric layer. Next, a plurality of openings in the horizontal direction are formed on the third dielectric layer. Then, the metal paste is filled into each of the openings, and the thickness of the metal paste is made higher than the surface of the third dielectric layer. Finally, by polishing the metal paste that is higher than the surface of the third dielectric layer, the surface of the metal paste is aligned with the same plane as the surface of the third dielectric layer, thereby constituting a plurality of the third conductive lines. The at least one opening is located around the die area on the second surface of each of the first dies. Each of the third conductive lines is exposed to the outside from each of the openings, and a solder pad is formed in each of the openings.

[0026] Step S6: Place a plurality of second dies separated from at least one wafer at intervals on each of the third conductive lines. Each of the second dies has one first surface and one opposite second surface, and has a plurality of die pads on the first surface. Each of the second dies has at least one chip conductive pillar penetrating the first surface and the second surface of each of the second dies. Each of the second dies can electrically connect each of the die pads to each of the third conductive lines by using flip chip technology to provide the first surface of each of the second dies on each of the third conductive lines.

[0027] Step S7: Perform a splitting operation to form a plurality of FOWLP units.

[0028] In one preferred embodiment of the present invention, the substrate includes a silicon substrate, a glass substrate, or a ceramic substrate.

[0029] In one preferred embodiment of the present invention, the metal paste constituting each of the first conductive lines, each of the second conductive lines, and each of the third conductive lines includes a silver paste, a nano silver paste, a copper paste, or a nano copper paste.

[0030] In one preferred embodiment of the present invention, further provide one solder ball on each of the openings, and each of the solder balls can be electrically connected to each of the first solder pads in each of the openings. Thereby, the FOWLP unit can be electrically connected to a printed circuit board (PCB) through each of the solder balls.

[0031] The present invention further provides an FOWLP unit as a second embodiment. The components included in the second embodiment are the same as those in the first embodiment. Regarding the structure of the FOWLP unit and the steps included in its manufacturing method, the differences between the second embodiment and the first embodiment in the structure and each step of its manufacturing method are only the following parts shown.

[0032] In terms of structure, the substrate further has at least one substrate conductive pillar penetrating the substrate dielectric layer, the first surface, and the second surface of the substrate. Each of the substrate conductive pillars is exposed to the outside from the substrate and forms a second solder pad on the substrate.

[0033] Each of the second dies is further electrically connected to the outside via, in order, each die pad of each second die, each third conductive wire, each second conductive wire, each conductive pillar, each first conductive wire, each substrate conductive pillar, and each second solder pad.

[0034] Each of the first dies is further electrically connected to the outside via, in order, each die pad, each first conductive wire, each substrate conductive pillar, and each second solder pad of each of the first dies.

[0035] In step S1 of the manufacturing method, the substrate further has at least one substrate conductive pillar penetrating the substrate dielectric layer, the first surface, and the second surface of the substrate. Each of the substrate conductive pillars is exposed to the outside from the substrate and forms a second solder pad on the substrate. [Effects of the Invention]

[0036] The FOWLP unit manufactured by the manufacturing process of the present invention can not only be effectively thinned, but the process can be simplified, manufacturing costs can be reduced, and usage efficiency and reliability can be effectively improved. Furthermore, since the process of the present invention does not employ conventional technologies such as chemical plating or electroplating, costs and contamination can be reduced. In addition, through the structural design of each component in the present invention and their interconnection relationships, external and internal electrical connections between the die inside the FOWLP unit and the die outside can be fully realized. This makes it possible to provide a higher performance and more multifunctional product by increasing the number of dies, thereby enhancing the market competitiveness of the product. Each die of the present invention has at least one chip conductive pillar that penetrates the first surface and the second surface, so that the first surface of each first / second die can be electrically connected to the second surface via each chip conductive pillar. This increases the versatility of the external electrical connections of the product. [Brief explanation of the drawing]

[0037] [Figure 1] This is a schematic side cross-sectional view of the first embodiment of the FOWLP unit of the present invention. [Figure 2] This is a schematic cross-sectional view of the substrate according to the first embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view of the first dielectric layer to be placed on the substrate shown in Figure 2. [Figure 4] Figure 3 is a schematic side cross-sectional view showing the filling of the first recess with metal paste. [Figure 5] Figure 4 is a schematic side cross-sectional view showing the metal paste being polished to form the first conductive wire. [Figure 6] This is a schematic side cross-sectional view of the first die, which is installed on the first conductive wire in Figure 5. [Figure 7] This is a schematic cross-sectional view of the second dielectric layer, which is installed on the first die shown in Figure 6. [Figure 8] Figure 7 is a schematic side cross-sectional view showing the installation of a conductive pillar in the through-hole. [Figure 9]Figure 8 is a schematic side cross-sectional view showing the filling of the second recess with metal paste. [Figure 10] Figure 9 is a schematic side cross-sectional view showing the metal paste being polished to form the second conductive wire. [Figure 11] This is a schematic side cross-sectional view of the third dielectric layer installed on the second conductive wire in Figure 10. [Figure 12] Figure 11 is a schematic side cross-sectional view showing the filling of the third recess with metal paste. [Figure 13] Figure 12 is a schematic side cross-sectional view showing the metal paste being polished to form the third conductive wire. [Figure 14] This is a schematic side cross-sectional view of the second die, which is installed on the third conductive wire in Figure 13. [Figure 15] Figure 14 is a schematic side cross-sectional view showing the placement of a solder ball on the first solder pad. [Figure 16] This is a schematic side cross-sectional view of a second embodiment of the FOWLP unit of the present invention. [Figure 17] This is a schematic cross-sectional view of the substrate according to the second embodiment of the present invention. [Figure 18] This is a schematic cross-sectional view of the first dielectric layer to be placed on the substrate shown in Figure 17. [Figure 19] Figure 18 is a schematic side cross-sectional view showing the filling of the first recess with metal paste. [Figure 20] Figure 19 is a schematic side cross-sectional view showing the metal paste being polished to form the first conductive wire. [Figure 21] This is a schematic side cross-sectional view of the first die, which is installed on the first conductive wire in Figure 20. [Figure 22] This is a schematic side cross-sectional view of the second dielectric layer installed on the first die shown in Figure 21. [Figure 23] Figure 22 is a schematic side cross-sectional view showing the installation of a conductive pillar in the through-hole. [Figure 24] This is a schematic side cross-sectional view showing the filling of the second recess in Figure 23 with metal paste. [Figure 25] Figure 24 is a schematic side cross-sectional view showing the metal paste being polished to form the second conductive wire. [Figure 26]This is a schematic side cross-sectional view of the third dielectric layer installed on the second conductive wire in Figure 25. [Figure 27] Figure 26 is a schematic side cross-sectional view showing the filling of the third recess with metal paste. [Figure 28] Figure 27 is a schematic side cross-sectional view showing the metal paste being polished to form the third conductive wire. [Figure 29] This is a schematic side cross-sectional view of the second die, which is installed on the third conductive wire in Figure 28. [Figure 30] Figure 29 is a schematic side cross-sectional view showing the placement of a solder ball on the first solder pad. [Modes for carrying out the invention]

[0038] Embodiments of the present invention will now be described with reference to the drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals, and in the description of these embodiments, the descriptions of the same or corresponding parts will be omitted or simplified as appropriate.

[0039] Referring to Figures 1, 15, 16, and 30, the present invention provides a FOWLP unit, the FOWLP unit 1 comprising a substrate 10, a first dielectric layer 20, a plurality of first conductive wires 30, at least one first die 40, a second dielectric layer 50, at least one conductive pillar 60, a plurality of second conductive wires 70, a third dielectric layer 80, a plurality of third conductive wires 90, and at least one second die 100. Based on the structural form of the substrate 10 in the FOWLP unit 1 and the difference in the electrical connection method with the outside of the FOWLP unit 1, the present invention is classified into a first embodiment shown in Figures 1 and 15 and a second embodiment shown in Figures 16 and 30.

[0040] The first embodiment of the FOWLP unit 1 shown in Figures 1 and 15 is described below.

[0041] Referring to Figure 2, the substrate 10 has one first surface 11 and one opposing second surface 12, and a substrate dielectric layer 13 is provided on the second surface 12.

[0042] Referring to Figure 3, the first dielectric layer 20 is provided on the substrate dielectric layer 13 of the substrate 10, and the first dielectric layer 20 has at least one first recess 21 formed by stretching in the horizontal direction.

[0043] Referring to Figure 5, each of the first conductive wires 30 is provided by filling each of the first recesses 21 with metal paste 30a.

[0044] Referring to Figure 6, each first die 40 is divided from a single wafer and has one first surface 41 and one opposing second surface 22, and has a plurality of first die pads 43 on the first surface 41, and the vertical range of the chip on the second surface 42 is defined as one die region 1a. As shown in Figure 6, each first die 40 has at least one chip conductive pillar 44 that penetrates the first surface 41 and the second surface 42, so that the first surface 41 is electrically connected to the second surface 42 via each chip conductive pillar 44. Each first die 40 uses flip-chip technology to place the first surface 41 on each first conductive wire 30 so that each die pad 43 is electrically connected to each first conductive wire 30. Each first die 40 shown in Figure 6 has two chip conductive pillars 44, but this is not limiting to the present invention.

[0045] Referring to Figure 7, the second dielectric layer 50 is provided on the first dielectric layer 20 and covers each of the first dies 40. The second dielectric layer 50 has at least one second recess 51 and at least one through hole 52 formed by extending horizontally, with each second recess 51 communicating with each through hole 52, and each through hole 52 communicating with each first recess 21.

[0046] Referring to Figure 8, each conductive pillar 60 is formed within each through-hole 52 and is exposed to the outside through each through-hole 52. Each conductive pillar 60 is electrically connected to each first conductive wire 30.

[0047] Referring to Figure 10, each second conductive wire 70 is provided by filling each second recess 51 with metal paste 70a. Each second conductive wire 70 is electrically connected to each conductive pillar 60.

[0048] Referring to Figure 11, the third dielectric layer 80 is provided on the second dielectric layer 50 and each of the second conductive wires 70, and the third dielectric layer 80 has at least one opening 81 formed by extending in the horizontal direction.

[0049] Referring to Figures 13 and 14, each third conductive wire 90 is provided by filling each of the openings 81 with metal paste 30a. At least one of the openings 81 is located around the die region 1a on the second surface 42 of each first die 40. Each third conductive wire 90 is exposed to the outside through each opening 81, and a first solder pad 91 is formed within each opening 81. Each third conductive wire 90 is electrically connected to each second conductive wire 70. The FOWLP unit 1 shown in Figure 13 has three of the openings 81, but this is not limited to the present invention.

[0050] Referring to Figure 14, each second die 100 is divided from a single wafer and has one first surface 101 and one opposing second surface 102, with a plurality of first die pads 103 on the first surface 101. Each second die 100 has at least one chip conductive pillar 104 that penetrates the first surface 101 and the second surface 102, so that the first surface 101 is electrically connected to the second surface 102 via each chip conductive pillar 104. Each second die 100 electrically connects each die pad 103 to each third conductive wire 90 by using flip-chip technology to position the first surface 101 on each third conductive wire 90. Each second die 100 shown in Figure 29 has two chip conductive pillars 104, but this is not limiting to the present invention.

[0051] Referring to Figure 14, each second die 100 is electrically connected to each first die 40 via each die pad 103, each third conductive wire 90, each second conductive wire 70, each conductive pillar 60, each first conductive wire 30, and each first die pad 43 of each first die 40.

[0052] Referring to Figure 14, each second die 100 is electrically connected to the outside via each die pad 103, each third conductive wire 90, each second conductive wire 70, each third conductive wire 90, and each first solder pad 91 around the die region 1a located on the second surface 42 of each first die 40.

[0053] Referring to Figure 14, each of the first dies 40 is electrically connected to the outside world via each of the die pads 103 of each of the first dies 40, each of the first conductive wires 30, each of the conductive pillars 60, each of the second conductive wires 70, each of the third conductive wires 90, and each of the first solder pads 91 around the die region 1a located on the second surface 42 of each of the first dies 40, thereby forming the FOWLP unit 1.

[0054] The method for manufacturing the FOWLP unit 1 includes the following steps.

[0055] Step S1: A substrate 10 is provided. The substrate 10 has one first surface 11 and one opposing second surface 12. As shown in Figure 2, a substrate dielectric layer 13 is provided on the second surface 12.

[0056] Step S2: Multiple first conductive wires 30 are formed on the substrate dielectric layer 13 of the substrate 10 using a technique that involves filling recesses with metal paste and then polishing it to form conductive wires. As shown in Figure 3, first, one first dielectric layer 30 is laid on the second surface 12 of the substrate 10. Next, as shown in Figure 4, multiple first recesses 21 are formed horizontally on the first dielectric layer 20, and then metal paste 30a is filled into each of the first recesses 21, and the thickness of the metal paste 30a is made higher than the surface of the first dielectric layer 20. Finally, as shown in Figure 5, the metal paste 30a that is higher than the surface of the first dielectric layer 20 is polished so that the surface of the metal paste 30a is aligned with the surface of the first dielectric layer 20, thereby forming multiple first conductive wires 30.

[0057] Step S3: As shown in Figure 6, a plurality of first dies 40, separated from at least one wafer, are placed on the second surface 12 of the substrate 10 at intervals. Each first die 40 has one first surface 41 and one opposing second surface 42, and on the first surface 41, there are a plurality of first die pads 43, and the vertical extent of the chip on the second surface 42 is defined as the die region 1a. Each first die 40 has at least one chip conductive pillar 44 that penetrates the first surface 41 and the second surface 42. Each first die 40 can be electrically connected to each first conductive wire 30 by using flip-chip technology to position the first surface 41 on each first conductive wire 30, thereby connecting each first die pad 43 to each first conductive wire 30.

[0058] Step S4: Multiple second conductive wires 70 are formed on the second surface 42 of each first die 40 using a technique that involves filling the recesses with metal paste and then polishing it to form conductive wires. As shown in Figure 7, first a second dielectric layer 50 is laid on the second surface 12 of the substrate 10 and on each first die 40, and the second dielectric layer 50 covers each first die 40. Next, multiple second recesses 51 are formed horizontally on the second dielectric layer 50, and multiple through holes 52 penetrate the second dielectric layer 50 downwards. Furthermore, each die pad 43 of each first die 40 can be exposed to the outside through each second recess 51. As shown in Figure 8, each through-hole 52, each first recess 21, and each second recess 51 are in communication. Then, one conductive pillar 60 is first formed in each of the communicating through-holes 52. After that, as shown in Figure 9, metal paste 70a is further filled into each of the second recesses 51, and the thickness of the metal paste 70a is made higher than the surface of the second dielectric layer 50. Finally, as shown in Figure 10, the metal paste 70a that is higher than the surface of the second dielectric layer 50 is polished so that the surface of the metal paste 70a is aligned with the surface of the second dielectric layer 50, thereby forming multiple second conductive wires 70.

[0059] Step S5: Multiple third conductive wires 90 are formed on the second dielectric layer 50 using a technique that involves filling recesses with metal paste and then polishing it to form conductive wires. As shown in Figure 11, first, one third dielectric layer 80 is laid on the second dielectric layer 50, and then multiple openings 81 are formed horizontally on the third dielectric layer 80. Then, as shown in Figure 12, metal paste 90a is filled into each of the openings 81, and the thickness of the metal paste 90a is made higher than the surface of the third dielectric layer 80. Finally, as shown in Figure 13, the metal paste 90a that is higher than the surface of the third dielectric layer 80 is polished so that the surface of the metal paste 90a is aligned with the surface of the third dielectric layer 80, thereby forming multiple third conductive wires 90. As shown in Figure 14, at least one of the openings 81 is located around the die region 1a on the second surface 42 of each first die 40. As shown in Figure 14, each of the third conductive wires 90 is exposed to the outside through each of the openings 81, and one solder pad 91 is formed within each of the openings 81.

[0060] Step S6: As shown in Figure 14, a plurality of second dies 100, separated from at least one wafer, are placed on each of the third conductive wires 90 at intervals. Each second die 100 has one first surface 101 and one opposing second surface 102, and has a plurality of die pads 103 on the first surface 101. Each second die 100 has at least one chip conductive pillar 104 that penetrates the first surface 101 and the second surface 102. Each second die 100 can be electrically connected to each of the third conductive wires 90 by using flip-chip technology to position the first surface 101 on each of the third conductive wires 90.

[0061] Step S7: As shown in Figure 14, the division process is performed to form multiple FOWLP units 1.

[0062] The processes of steps S2, S4, and S5 described above can be considered important steps for forming the redistribution layer (RDL) of the FOWLP unit 1, and all of them are processes that can be easily and precisely carried out. Therefore, the process can be further simplified, and even when each of the first conductive wires 30, each of the second conductive wires 70, and each of the third conductive wires 90 in the RDL are electrically extended and interconnected in the XY plane, the FOWLP unit 1 can still simultaneously achieve a certain degree of lightness, thinness, and compactness. Second Embodiment

[0063] The second embodiment of the FOWLP unit 1 shown in Figures 16 and 30 is described below.

[0064] The second embodiment and the first embodiment differ only slightly in the structural form of the substrate 10 and the method by which the FOWLP unit 1 makes electrical connections to the outside. Figures 16 to 20 are shown for comparison with Figures 1 to 15 and illustrate the structural form and process of the second embodiment. Therefore, the common parts of the structural form and process in the second embodiment and the first embodiment will not be described in detail here. Below, only the main differences between the second embodiment and the first embodiment will be explained.

[0065] As shown in Figure 17, the substrate 10 of the second embodiment further has at least one substrate conductive pillar 14 that penetrates the substrate dielectric layer 13, the first surface 11, and the second surface 12. As shown in Figure 29, each substrate conductive pillar 14 is exposed to the outside from the first surface 11 of the substrate 10 and forms a second solder pad 15 on the substrate 10.

[0066] As shown in Figure 20, each of the first conductive wires 30 in the second embodiment is provided by filling each of the first recesses 21 with metal paste 30a. As shown in Figure 20, each of the first conductive wires 30 is further electrically connected to each of the substrate conductive pillars 14.

[0067] As shown in Figure 29, each of the second dies 100 in the second embodiment is further electrically connected to the outside via each die pad 103, each third conductive wire 90, each second conductive wire 70, each conductive pillar 60, each first conductive wire 30, each substrate conductive pillar 14, and each second solder pad 15 of each second die 100.

[0068] As shown in Figure 29, each of the first dies 40 in the second embodiment is further electrically connected to the outside via each die pad 103, each first conductive wire 30, each substrate conductive pillar 14, and each second solder pad 15 of each first die 40.

[0069] As shown in Figure 17, in step S1 of the manufacturing method of the FOWLP unit 1 of the second embodiment, the substrate 10 further has at least one substrate conductive pillar 14 that penetrates the substrate dielectric layer 13, the first surface 11, and the second surface 12 of the substrate 10. As shown in Figure 17, each of the substrate conductive pillars 14 is exposed to the outside from the substrate 10 and forms a second solder pad 15 on the substrate 10.

[0070] In the second embodiment, each of the first die 40 is as shown in Figure 21, the second dielectric layer 50 is as shown in Figure 22, each of the conductive pillars 60 is as shown in Figure 23, each of the second conductive wires 70 is as shown in Figure 25, the third dielectric layer 80 is as shown in Figure 26, each of the third conductive wires 90 is as shown in Figure 28, and each of the second die 100 is as shown in Figure 29. The explanation of steps S2 to S7 in the manufacturing method is the same as in the first embodiment and will not be described in detail here.

[0071] Referring to Figures 2 and 17, the substrate 10 includes, but is not limited to, a silicon substrate, a glass substrate, or a ceramic substrate, and is intended to facilitate the development and application of a variety of products.

[0072] Referring to Figures 5, 10, 13, 19, 24, and 27, the metal pastes 30a, 70a, and 90a constituting the first conductive wire 30, second conductive wire 70, and third conductive wire 90, respectively, include, but are not limited to, silver paste, nanosilver paste, copper paste, or nanocopper paste, in order to facilitate diverse product development and applications. The material of the nanosilver paste has properties such as low cost, high conductivity, and the ability to sinter at low temperatures, but since nanosilver paste is a known common material, it will not be described in detail here.

[0073] Referring to Figures 15 and 30, a further solder ball 110 is provided on each of the openings 81, and each of the solder balls 110 can be electrically connected to each of the first solder pads 91 located within each of the openings 81.

[0074] Referring to Figures 1 and 16, the FOWLP unit 1 can be electrically connected to a single printed circuit board (PCB) 2 via each of the solder balls 110, but is not limited thereto.

[0075] The FOWLP unit 1 of the present invention has the following advantages when compared to conventional FOWLP unit technology.

[0076] (1) The FOWLP unit 1 manufactured by the process of steps S2, S4, and S5 of the present invention can not only effectively reduce the thickness of the FOWLP unit, but also simplify the process and reduce manufacturing costs. Furthermore, it can effectively improve the usage efficiency and reliability of the FOWLP unit 1.

[0077] (2) The processes of steps S2, S4, and S5 of the present invention do not employ conventional technologies such as chemical plating or electroplating, and therefore the costs and contamination caused by the process can be reduced.

[0078] (3) Through the structural design of each component in the present invention and the relationships between them, sufficient external and internal electrical connections between the dies inside the FOWLP unit and the dies outside can be achieved. This makes it possible to provide a higher performance and more multifunctional product by increasing the number of dies, thereby enhancing the market competitiveness of the product.

[0079] (4) Each of the first / second dies 40 / 100 of the present invention has at least one chip conductive pillar 44 / 104 that penetrates the first surface 41 / 101 and the second surface 42 / 102, so that the first surface 41 / 101 of each first / second die 40 / 100 can be electrically connected to the second surface 42 / 102 via each chip conductive pillar 44 / 104. This increases the versatility of the external electrical connections of the product. [Explanation of symbols]

[0080] 1. Fan-out type wafer-level packaging unit 1a Die area 10 circuit boards 11 Page 1 12 Side 2 13. Substrate dielectric layer 14. Conductive Pillars on Substrates 15. Second solder pad 20 First Dielectric Layer 21 First recess 30 First conductive wire 30a Metal Paste 40 First Die 41 Page 1 42 Side 2 43. First die pad 44 Chip conductive pillars 50 Second dielectric layer 51 Second recess 52 Through hole 60 Conductive Pillars 70 Second conductive wire 70a Metal Paste 80 Third Dielectric Layer 81 Aperture 90 Third conductive wire 90a Metal Paste 91 First solder pad 100 Second Die 101 Page 1 102 2nd page 103 Die Pad 104 Chip conductive pillar 110 solder balls 2 Printed circuit boards

Claims

1. The system includes one substrate, one first dielectric layer, multiple first conductive wires, at least one first die, one second dielectric layer, at least one conductive pillar, multiple second conductive wires, one third dielectric layer, multiple third conductive wires, and at least one second die. The substrate has one first surface and one opposing second surface, and a substrate dielectric layer is provided on the second surface. The first dielectric layer is provided on the substrate dielectric layer of the substrate, and the first dielectric layer has at least one first recess formed by stretching in the horizontal direction. Each of the first conductive wires is constructed by filling each of the first recesses with metal paste. Each first die is divided from a single wafer and has one first surface and one opposing second surface, and has a plurality of first die pads on the first surface, and the vertical range of the chips on the second surface is defined as one die region, and each first die has at least one chip conductive pillar that penetrates the first surface and the second surface, so that the first surface is electrically connected to the second surface via each chip conductive pillar, and each first die is electrically connected to each die pad and each first conductive wire by positioning the first surface on each first conductive wire using flip-chip technology, The second dielectric layer is provided on the first dielectric layer and covers each of the first dies, and the second dielectric layer has at least one second recess and at least one through hole formed by extending horizontally, each of the second recesses communicating with each of the through holes, and each of the through holes communicating with each of the first recesses, Each conductive pillar is formed within each through-hole and is exposed to the outside through each through-hole, and each conductive pillar is electrically connected to each first conductive wire. Each second conductive wire is provided by filling each second recess with metal paste, and each second conductive wire is electrically connected to each conductive pillar. The third dielectric layer is provided on the second dielectric layer and each of the second conductive wires, and the third dielectric layer has at least one opening formed by extending in the horizontal direction. Each third conductive wire is provided by filling each opening with metal paste, the at least one opening being located around the die region on the second surface of each first die, each third conductive wire being exposed to the outside from each opening, and each opening forming a first solder pad, each third conductive wire being electrically connected to each second conductive wire, and Each second die is divided from a single wafer and has one first surface and one opposing second surface, and has a plurality of first die pads on the first surface, and each second die has at least one chip conductive pillar that penetrates the first surface and the second surface, so that the first surface is electrically connected to the second surface via each chip conductive pillar, and each second die is electrically connected to each die pad and each third conductive wire by using flip-chip technology to position the first surface on each third conductive wire, Each of the second dies is electrically connected to each of the first dies via, in order, each die pad of each of the second dies, each third conductive wire, each second conductive wire, each conductive pillar, each first conductive wire, and each first die pad of each of the first dies. Each of the second dies is electrically connected to the outside, in order, via each die pad of each second die, each third conductive wire, each second conductive wire, each third conductive wire, and each first solder pad around the die region located on the second surface of each first die. Each of the first dies is electrically connected to the outside, in order, via each die pad of each of the first dies, each first conductive wire, each conductive pillar, each second conductive wire, each third conductive wire, and each first solder pad around the die region located on the second surface of each of the first dies, thereby forming the FOWLP unit. The method for manufacturing the FOWLP unit includes the following steps: Step S1: Provide a substrate having one first surface and one opposing second surface, and provide a substrate dielectric layer on the second surface. Step S2: Using a technique in which metal paste is filled into recesses and then polished to form conductive wires, multiple first conductive wires are formed on the substrate dielectric layer of the substrate. First, one first dielectric layer is laid on the second surface of the substrate. Next, multiple first recesses are formed horizontally on the first dielectric layer. Then, metal paste is filled into each of the first recesses, and the thickness of the metal paste is made higher than the surface of the first dielectric layer. Finally, the metal paste that is higher than the surface of the first dielectric layer is polished so that the surface of the metal paste is aligned with the surface of the first dielectric layer, thereby forming multiple first conductive wires. Step S3: A plurality of first dies, separated from at least one wafer, are placed on the second surface of the substrate at intervals, each first die having one first surface and one opposing second surface, and having a plurality of first die pads on the first surface, the vertical range of the chips on the second surface is defined as the die region, each first die has at least one chip conductive pillar penetrating the first surface and the second surface, and each first die can be electrically connected to each first conductive wire by using flip-chip technology to position the first surface on each first conductive wire, Step S4: After filling the recesses with metal paste, a plurality of second conductive wires are formed on the second surface of each first die using a technique of polishing to form conductive wires. First, a second dielectric layer is laid on the second surface of the substrate and on each first die, and the second dielectric layer covers each first die. Next, a plurality of second recesses are formed horizontally on the second dielectric layer, and a plurality of through holes are formed that penetrate the second dielectric layer downwards. Furthermore, each die pad of each first die is made to exit through each second recess. The through-holes can be exposed, and each of the first recesses and each of the second recesses are in communication. Then, a conductive pillar is first formed in each of the communicating through-holes, and then metal paste is filled into each of the second recesses, and the thickness of the metal paste is made higher than the surface of the second dielectric layer. Finally, the metal paste that is higher than the surface of the second dielectric layer is polished so that the surface of the metal paste is aligned with the surface of the second dielectric layer, thereby forming a plurality of second conductive wires. Step S5: Form multiple third conductive wires on the second dielectric layer using a technique that involves filling recesses with metal paste and then polishing it to form conductive wires, first laying one third dielectric layer on the second dielectric layer, then forming multiple horizontal openings on the third dielectric layer, then filling each opening with metal paste and making the thickness of the metal paste higher than the surface of the third dielectric layer, and finally polishing the metal paste that is higher than the surface of the third dielectric layer so that the surface of the metal paste is aligned with the surface of the third dielectric layer, thereby forming multiple third conductive wires, at least one of the openings is located around the die region on the second surface of each first die, each of the third conductive wires is exposed to the outside from each opening, and one solder pad is formed within each opening. Step S6: A plurality of second dies, separated from at least one wafer, are placed on each third conductive wire at intervals, each second die having one first surface and one opposing second surface, with a plurality of die pads on the first surface, each second die having at least one chip conductive pillar penetrating the first surface and the second surface, and each second die can be electrically connected to each third conductive wire by using flip-chip technology to position the first surface on each third conductive wire, and Step S7: A fan-out type wafer-level packaging (FOWLP) unit characterized by performing a splitting operation to form multiple FOWLP units.

2. The FOWLP unit according to claim 1, characterized in that the substrate includes a silicon substrate, a glass substrate, or a ceramic substrate.

3. The FOWLP unit according to claim 1, characterized in that the metal paste constituting each of the first conductive wires, each of the second conductive wires, and each of the third conductive wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

4. The FOWLP unit according to claim 1, characterized in that a further solder ball is provided on each of the aforementioned openings, and each solder ball is electrically connected to each of the first solder pads located within each of the respective openings.

5. The FOWLP unit according to claim 4, characterized in that each FOWLP unit can be electrically connected to a single printed circuit board (PCB) via each of the solder balls.

6. The substrate further has at least one substrate conductive pillar penetrating the substrate dielectric layer, the first surface and the second surface, each of the substrate conductive pillars being exposed to the outside from the first surface of the substrate and forming a second solder pad on the substrate, each of the first conductive wires further electrically connected to each of the substrate conductive pillars, and each of the second dies further sequentially has each die pad of each second die, each third conductive wire, each second conductive wire, each conductive pillar, each first conductive wire, each substrate conductive pillar and each The FOWLP unit according to claim 1, wherein the FOWLP unit is electrically connected to the outside via the second solder pad, and each of the first dies is further electrically connected to the outside via, in order, each die pad of each of the first dies, each first conductive wire, each substrate conductive pillar and each second solder pad, and in step S1 of the manufacturing method of the FOWLP unit, the substrate further has at least one substrate conductive pillar penetrating the substrate dielectric layer, the first surface and the second surface of the substrate.

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