Substrate having a glass core and a glass build-up layer

Abstract

A substrate having a glass core and a glass build-up layer, and a method for forming said substrate are described herein. In one example, the substrate includes a glass core, glass layers above and below the glass core, conductive traces located inside at least some of the glass core and glass layers, and conductive contacts on the surface of the substrate.

Description

Background Art

[0001] [Cross - Reference to Related Applications] This application claims priority to U.S. Patent Application No. 18 / 194,550, filed Mar. 31, 2023, entitled "Substrate Having a Glass Core and a Glass Build - Up Layer", which is hereby incorporated by reference in its entirety.

[0002] The demand for miniaturization of the computing device form factor and improvement of the integration level to achieve high performance in computing devices has helped drive the development of sophisticated packaging approaches in the semiconductor industry. Scaling down electrical input / output (I / O) interconnects has continued to be one of the most significant factors for performance improvement. However, for micro - bump - based interconnects, scaling down the bump pitch beyond 10 micrometers (μm) has faced technological challenges. As a result, other more scalable interconnect technologies, such as hybrid bonding, which is a combination of dielectric bonding and direct copper - to - copper bonding, have been gaining momentum. Hybrid bonding is used for silicon - to - silicon bonding, such as bonding of multiple silicon dies, wafers, etc. However, the interconnects between silicon dies and package substrates are still mainly implemented using micro - bumps.

Brief Description of the Drawings

[0003] [Figure 1] Shows a glass package substrate for a hybrid - bonded silicon die.

[0004] [Figure 2A] Shows a process flow for forming a glass package substrate for a hybrid - bonded silicon die. [Figure 2B] Shows a process flow for forming a glass package substrate for a hybrid - bonded silicon die. [Figure 2C]This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2D] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2E] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2F] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2G] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2H] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2I] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die. [Figure 2J] This shows the processing flow for forming a glass package substrate for a hybrid junction silicon die.

[0005] [Figure 3] This shows an embedded die package within a glass substrate.

[0006] [Figure 4A] This shows the processing flow for forming an embedded die package within a glass substrate. [Figure 4B] This shows the processing flow for forming an embedded die package within a glass substrate. [Figure 4C] This shows the processing flow for forming an embedded die package within a glass substrate. [Figure 4D] This shows the processing flow for forming an embedded die package within a glass substrate. [Figure 4E] This shows the processing flow for forming an embedded die package within a glass substrate. [Figure 4F]Shows a process flow for forming an embedded die package within a glass substrate. [Figure 4G] Shows a process flow for forming an embedded die package within a glass substrate. [Figure 4H] Shows a process flow for forming an embedded die package within a glass substrate. [Figure 4I] Shows a process flow for forming an embedded die package within a glass substrate.

[0007] [Figure 5] Shows an embedded die package within a glass substrate using through-silicon vias.

[0008] [Figure 6A] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6B] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6C] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6D] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6E] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6F] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6G] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6H] Shows a process flow for forming an embedded die package within a glass substrate using through-silicon vias. [Figure 6I]This shows the processing flow for forming an embedded die package in a glass substrate using through-silicon vias.

[0009] [Figure 7A] Various embodiments of glass substrates and packages having microbumps are shown. [Figure 7B] Various embodiments of glass substrates and packages having microbumps are shown. [Figure 7C] Various embodiments of glass substrates and packages having microbumps are shown.

[0010] [Figure 8] A flowchart is shown for forming an integrated circuit (IC) package on a substrate having a glass core and a glass build-up layer.

[0011] [Figure 9] This is a top view of a wafer and die that may be included in a microelectronic assembly.

[0012] [Figure 10] This is a lateral cross-sectional view of an integrated circuit device that may be included in a microelectronic assembly.

[0013] [Figure 11] This is a lateral cross-sectional view of an integrated circuit device assembly that may include a microelectronic assembly.

[0014] [Figure 12] This is a block diagram of an exemplary electrical device that may include a microelectronic assembly. [Modes for carrying out the invention]

[0015] Competition in high-performance computing has intensified over the past decade. The demand for smaller form factors and higher integration levels in computing devices to achieve high performance has helped drive the development of sophisticated packaging approaches in the semiconductor industry.

[0016] Scaling down electrical input / output (I / O) interconnects has consistently been one of the biggest drivers of performance improvement. However, for microbump-based interconnects, scaling down bump pitches beyond 10 microns (μm) presents a significant technical challenge. As a result, other interconnect technologies are gaining momentum. For example, direct copper-copper junctions (e.g., solderless) are a promising alternative to microbumps for bump pitches below 10 μm. Another promising alternative is hybrid junctions, which are a combination of dielectric junctions and copper-copper junctions.

[0017] Current hybrid bonding technologies are limited to silicon-to-silicon bonding, such as wafer-to-wafer, die-to-wafer, and die-to-die / die-stack bonding. However, package substrates are typically made from non-silicon materials. As a result, interconnections between silicon dies and (non-silicon) package substrates are still primarily implemented using microbumps.

[0018] Package substrates are typically made of organic materials, or a combination of glass and organic materials. For example, organic substrates typically contain an organic core with multiple organic build-up layers, and glass substrates typically contain a glass core with multiple organic build-up layers. For both types of substrates, the organic build-up layers are typically formed of organic films, such as Ajinomoto build-up film (ABF) and polyimide (PI). Organic materials have a high coefficient of thermal expansion (CTE), which means they expand significantly at high temperatures. As a result, these substrates are unsuitable for hybrid bonding because the expansion of the organic materials within them can create stress on the package, potentially leading to defects.

[0019] Accordingly, this disclosure presents embodiments of all-glass (or predominantly glass) substrates suitable for both microbump bonding and hybrid die-substrate bonding (e.g., copper-copper / dielectric bonding). Current glass-based substrates use only glass in the substrate core, but the build-up layer is formed using organic materials (e.g., ABF, PI) which are unsuitable candidates for hybrid bonding. However, the glass substrates in this disclosure include a glass core and a glass build-up layer, and therefore fully utilize the electrical and mechanical benefits of glass.

[0020] These glass substrates can be formed by starting with a glass core and replacing conventional organic build-up layers with glass layers, for example, by forming a silicon oxide layer on the glass core using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other similar techniques.

[0021] Processes typically used only on glass cores, such as laser-based etching techniques (e.g., laser-inductive selective etching (LISE)) and through-glass via (TGV) formation using conductive seeding and plating (e.g., titanium / copper seeding with copper plating), can also be used on glass build-up layers to form electrical interconnections.

[0022] The trailing edge of the substrate may have microbumps for conventional die mounting using thermal compression bonding and mass reflow, or alternatively, recessed Cu bumps within a glass (e.g., silicon oxide) layer for direct hybrid bonding with a silicon chip.

[0023] These glass substrates offer several advantages. For example, organic build-up layers can be replaced with glass layers that can closely match the glass core. This provides greater flexibility in substrate design, which was previously limited by manufacturing capabilities.

[0024] This all-glass substrate more effectively utilizes the mechanical and electrical benefits of glass compared to conventional glass-based substrates that use glass only in the core. For example, the resulting glass substrate has better electrical and mechanical properties, such as lower dielectric loss, higher bandwidth, lower CTE, and less warpage.

[0025] Furthermore, this all-glass design can be used for both microbump bonding and hybrid bonding. In particular, this design enables hybrid bonding between die and substrate for lower latency and higher bandwidth communication. For example, the mechanical properties of the glass layer can be fine-tuned to match the mechanical properties of silicon for hybrid bonding. Significant performance benefits are obtained from direct copper-copper bonding between the monolithic die or die stack and the substrate. Moreover, this all-glass substrate can be manufactured and hybrid-bonded using silicon chips at the panel or wafer level.

[0026] Figure 1 shows a glass package substrate 100 for a hybrid bonded silicon die. In some embodiments, for example, the glass substrate 100 may be used in an integrated circuit package in which one or more integrated circuit dies are hybrid bonded to the glass substrate 100.

[0027] The glass substrate 100 includes a glass core 102 having glass build-up layers 104 above and below the core. In various embodiments, the glass core 102 is made of silicon oxide (SiO2). x The glass substrate may be made from any suitable glass (e.g., amorphous) material, including but not limited to silicon dioxide (SiO2), also known as silica, fused silica, alkali glass, non-alkali glass, borosilicate glass, float borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass.

[0028] Therefore, in various embodiments, the glass core 102 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3), but not limited to any combination of these elements.

[0029] The glass build-up layer 104 is made of silicon oxide (SiO xThe dielectric layer may be made from any suitable glass material, including but not limited to silicon dioxide (SiO2), also known as silica, or fused silica, and spin-on glass (such as silica (SiO2) containing dopants such as boron, phosphorus, titanium, and / or zinc). Therefore, in some embodiments, the glass build-up layer 104 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, and alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 104 (e.g., CTE) may be adjusted to match those of silicon for hybrid bonding with a silicon die.

[0030] The package substrate 100 also includes conductive traces 106 patterned within the glass core 102 and glass build-up layer 104, including vias and horizontal traces within the glass layer 104. In some embodiments, the conductive traces 106 may be made of a metal (e.g., copper and / or titanium).

[0031] The conductive trace 106 electrically connects a recessed pad 108 at the top of the package substrate 100 to a bump 110 at the bottom of the substrate. The recessed pad 108 and bump 110 are conductive contacts used to electrically connect other components to the package substrate 100. The recessed pad 108 may be a copper pad recessed slightly below the dielectric glass layer 104, and the bump 110 may be a solder ball, bump, or microbump. The package substrate 100 also includes a layer of solder resist 109 at the bottom of the substrate where the bump 110 is located.

[0032] In some embodiments, for example, one or more integrated circuit dies (not shown) may be bonded to the upper side of the package substrate 100 and hybrid-bonded to recessed pads 108 (e.g., via a combination of dielectric and copper-copper junctions). Furthermore, the package substrate 100 may be bonded to a circuit board (e.g., a motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 110 at the bottom of the package substrate 100.

[0033] Figures 2A to 2J show the process flow for forming the glass package substrate 100 of Figure 1. In particular, the process flow shown can be used for the panel-level or wafer-level manufacturing of glass substrates for hybrid bonded silicon dies (e.g., substrate-die hybrid bonded dies). However, this process flow is only one exemplary methodology for manufacturing such substrates.

[0034] In Figure 2A, an amorphous glass panel (or wafer) of appropriate thickness is used as the substrate core 102. In some embodiments, the glass panel may have a thickness ranging from 100 microns (μm) to 1000 μm or 1 millimeter (mm). Among other examples, a variety of glass compositions, including but not limited to alkali glass, non-alkali glass, borosilicate glass, float borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, and / or quartz, may be used depending on these processing requirements.

[0035] In Figure 2B, through-holes 103 are formed within the glass core 102. In some embodiments, the through-holes 103 are formed using laser-based techniques, such as laser-inductive selective etching (LISE). LISE is a two-step process in which the glass is locally modified using ultrafast laser pulses, and this modified portion is etched away using wet chemical etching techniques (e.g., an etching bath containing hydrogen fluoride (HF), potassium hydroxide (KOH), or sodium hydroxide (NaOH)). The laser-impacted areas have a much faster etching rate compared to non-impacted areas, which enables the formation of through-holes 103 with a high aspect ratio.

[0036] In Figure 2C, metal seeding and plating are performed to form conductive paths 106 that pass through the core 102 and are above / below the core 102. For example, titanium and copper may be deposited on the surface of the core 102 and through holes 103 to form a seed layer, and copper may be deposited in the seed layer to form conductive layers 106 above and below the core 102 (e.g., by filling through holes 103) through glass vias (TGV) 106 within the core 102. Polishing techniques may be used to planarize the surface of the conductive layers on the core 102 (e.g., grinding, chemical mechanical planarization (CMP)).

[0037] In Figure 2D, the conductive layers on the top and bottom of the core 102 are patterned onto the conductive trace 106 by etching away the undesirable metal. In some embodiments, conventional lithography processes such as dry film resist (DFR) lamination, photoexposure, photoresist development, and copper etching may be used to etch away the undesirable metal.

[0038] In Figure 2E, a glass build-up layer 104 is formed above and below the core 102. For example, instead of laminating an organic build-up layer on the core (e.g., using an ABF film), a glass layer 104 with an appropriate thickness (e.g., 10-50 μm) is formed above and below the core 102 by depositing an appropriate material for forming glass.

[0039] In some embodiments, the glass layer 104 solidifies into glass using silicon oxide (SiO2) (also known as silica) or other silicon oxides (SiO2). x The silicon oxide layer may be formed by depositing a silicon oxide film on the core 102 using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Different doping materials and concentrations may be carefully selected to modify the silicon oxide film forming agent and modifier to obtain the desired electrical and mechanical properties of the resulting glass layer 104.

[0040] Next, polishing techniques may be used to planarize the surface of the glass layer 104 (e.g., grinding, chemical mechanical planarization (CMP)).

[0041] In Figure 2F, via holes 105 are formed within the glass layer 104. For example, instead of forming conventional via holes within an organic build-up layer (e.g., ABF) using laser drilling, via holes 105 are formed within the glass build-up layer 104. As a result, the via holes 105 within the glass layer 104 may be formed using the same LISE process as the via holes 103 within the glass core 102 in Figure 2B, which means that the same tooling set can be used.

[0042] In Figure 2G, a second set of via / conductive layers 106 is formed on the glass layer 104 above and below the core 102 using metallization and surface planarization techniques similar to those used for the first set of via / conductive layers in Figure 2C.

[0043] Similarly, in Figure 2H, the conductive layers 106 at the top and bottom are patterned into conductive traces 106 using the same etching technique as in Figure 2D.

[0044] In Figure 2I, the steps in Figures 2E to 2H are repeated to form another set of glass build-up layers 104 and conductive build-up layers 106 on the top and bottom surfaces. These steps may be repeated until an appropriate number of glass / conductive build-up layers are formed for a particular substrate.

[0045] In Figure 2J, in order to create a second-level interconnect, another glass layer 104 is formed on the bottom surface and flattened (for example, coplanar with the trace 106 layer), a solder resist layer 109 is formed on the glass layer 104, and bumps or microbumps 110 are formed on the trace 106.

[0046] Furthermore, another glass layer 104 is formed on a slightly raised upper surface relative to the trace layer 106, and is then planarized (e.g., using CMP) to form an extremely flat dielectric glass surface 104, and the copper pad 108 is recessed slightly below the surface 104 (e.g., by only 5-20 nm). The recessed copper pad 108 forms a first-level interconnection for a hybrid bond having one or more silicon dies (not shown). In some embodiments, hybrid bonding can be performed at the panel level between the glass substrate 100 and the silicon die. As described above, the properties of the dielectric glass layer 104, such as CTE, can be fine-tuned to match those of silicon by adding silicon forming agents, substitutes and / or modifiers. As a result, the glass substrate 100 can be hybrid bonded to the silicon die without causing stress or damage to the substrate 100.

[0047] The processing flow is described at a high level in the examples shown. Without departing from the scope of the embodiments described, certain steps may be omitted for brevity and / or differ from those described herein. For brevity, only a limited number of glass / conductive build-up layers 104, 106 are shown within the substrate 100. In actual embodiments, the number of build-up layers may be up to 20 or more. Furthermore, the number of build-up layers above and below the core does not necessarily have to be the same.

[0048] Compared to substrates having a glass core and an organic build-up layer, the all-glass (or mostly glass) substrates described herein offer numerous advantages. For example, the embodiments described support hybrid bonding between the glass substrate and the silicon die, which allows for a higher interconnect density and shorter interconnect distances between the substrate and the die compared to microbump interconnects. In addition, since the material used for the glass build-up layer can be very similar to that used for the glass core, these glass substrates also have various mechanical / structural advantages, such as less warping, which leads to increased yield. Furthermore, the embodiments described result in significant cost savings because fewer tools are required for manufacturing.

[0049] Figure 3 shows an embedded die package 300 within a glass substrate 301. The embedded die package 300 is an integrated circuit package having a silicon die 312 embedded within the glass substrate 301.

[0050] In the embodiment shown, the glass substrate 301 is made of silicon oxide (SiO xThe glass core 302 may be a glass substrate made from any suitable glass (e.g., amorphous) material, including but not limited to silicon dioxide (SiO2), also known as silica, fused silica, alkali glass, non-alkali glass, borosilicate glass, float borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass. Thus, in various embodiments, the glass core 302 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of those elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0051] Furthermore, the glass core 302 includes a plurality of cavities 307, each having an embedded silicon die 312 attached to the floor of the cavity 307 using a die attach film (DAF) 311.

[0052] The glass substrate 301 also includes glass build-up layers 304 above and below the glass core 302. The glass build-up layers 304 are made of silicon oxide (SiO2). xThe dielectric layer may be made from any suitable glass material, including but not limited to silicon dioxide (SiO2), also known as silica, or fused silica, and spin-on glass (such as silica (SiO2) containing dopants such as boron, phosphorus, titanium, and / or zinc). Therefore, in some embodiments, the glass build-up layer 304 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, and alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 304 (e.g., CTE) may be adjusted to match those of silicon (e.g., for hybrid bonding with silicon chips).

[0053] The substrate 301 also includes conductive traces 306 patterned within the glass core 302 and glass build-up layer 304, including vias within the glass core 302 and glass layer 304 and horizontal traces within the glass layer 304. In some embodiments, the conductive traces 306 may be made of a metal (e.g., copper and / or titanium).

[0054] The conductive trace 306 electrically couples the embedded die 312, the recessed pad 308 at the top of the substrate 301, and the bump 310 at the bottom of the substrate 301. The recessed pad 308 and the bump 310 are conductive contacts used to electrically couple other components to the substrate 301. The recessed pad 308 may be a copper pad recessed slightly below the dielectric glass layer 304, and the bump 310 may be a solder ball, bump, or microbump. The package substrate 301 also includes a layer of solder resist 309 at the bottom of the substrate where the bump 310 is located.

[0055] In some embodiments, for example, one or more additional silicon dies (not shown) may be hybrid-bonded to the recessed pads 308 on the upper side of the substrate 301 (e.g., via a combination of dielectric and copper-copper junctions). Furthermore, the substrate 301 may be bonded to a circuit board (e.g., a motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 310 at the bottom of the substrate 301.

[0056] For simplicity, the embedded die 312 is shown only on the upper side of the core 302. However, in other embodiments, passive components (e.g., trace 306) and the active silicon die 312 may be embedded on both sides of the core 302, or within the glass build-up layer 304 (e.g., using an embedded multi-die interconnect / bridge), or across both the core 302 and the glass build-up layer 304.

[0057] Figures 4A to 4I show the process flow for forming the embedded die package 300 of Figure 3. In particular, the process flow shown is used to embed the active die and passive components (e.g., traces / bridges / interconnects) into the glass substrate. However, this process flow is only one exemplary methodology for manufacturing such a package.

[0058] In Figure 4A, a glass panel (or wafer) of appropriate thickness is used as the substrate core 302 (for example, as in Figure 2A).

[0059] In Figure 4B, a cavity 307 for the silicon die is formed within the core 302 (for example, by using LISE processing).

[0060] In Figure 4C, the silicon die 312 is mounted to the bottom of the cavity 307 using a die attach film (DAF) 311 with precise alignment and chip tilt control. The die 312 includes a top surface pad 314 for interconnection with other components.

[0061] In Figure 4D, silicon oxide film deposition is used to form a glass layer 304 and fill the gap above the die 312, and the glass layer 304 is planarized (for example, by grinding and / or CMP).

[0062] In Figure 4E, through holes 303 are formed in the glass core 302, and via holes 305 leading to pads 314 on the silicon die 312 are formed in the glass layer 304 (for example, using LISE treatment).

[0063] In Figure 4F, metal seeding and plating are performed to form conductive paths 306 that pass through the core 302 to the silicon die 312 and are located above and below the core 302 (for example, above the glass layer 304). For example, through-glass vias (TGVs) 306 are formed in the core 302 by filling through holes 303 with metal, vias 306 are formed in the glass layer 304 by filling via holes 305 with metal, and conductive layers 306 are formed above and below the core 302 by depositing metal below and above the core 302 in the glass layer 304.

[0064] The remaining steps in Figures 4G, 4H, and 4I are the same as those in Figures 2H, 2I, and 2J, respectively.

[0065] Figure 5 shows an embedded die package 500 in a glass substrate using through-silicon vias. For example, the embedded die package 500 is an integrated circuit package in a glass substrate 501 that includes an embedded silicon die 512 having through-silicon vias (TSVs) 513.

[0066] In the embodiment shown, the glass substrate 501 is silicon oxide (SiO xThe glass core 502 may be a glass substrate made from any suitable glass (e.g., amorphous) material, including but not limited to silicon dioxide (SiO2), also known as silica, fused silica, alkali glass, non-alkali glass, borosilicate glass, float borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass. Thus, in various embodiments, the glass core 502 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of those elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0067] The glass core 502 also includes a plurality of cavities 507, each having an embedded silicon die 512 attached to the floor of the cavity 507 using a die attach film (DAF) 511. The embedded silicon die 512 includes through silicon vias (TSVs) 513 for electrically coupling the die 512 to conductive traces 506 above and below the die 512 in the substrate 501.

[0068] The glass substrate 501 also includes glass build-up layers 504 above and below the glass core 502. The glass build-up layers 504 are made of silicon oxide (SiO2). xThe dielectric layer may be made from any suitable glass material, including but not limited to silicon dioxide (SiO2), also known as silica, or fused silica, and spin-on glass (such as silica (SiO2) containing dopants such as boron, phosphorus, titanium, and / or zinc). Therefore, in some embodiments, the glass build-up layer 504 may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, and alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 504 (e.g., CTE) may be adjusted to match those of silicon (e.g., for hybrid bonding with silicon chips).

[0069] The substrate 501 also includes conductive traces 506 patterned within the glass core 502 and glass build-up layer 504, including vias within the glass core 502 and glass layer 504 and horizontal traces within the glass layer 504. In some embodiments, the conductive traces 506 may be made of a metal (e.g., copper and / or titanium).

[0070] The conductive trace 506 electrically couples the embedded die 512, the recessed pad 508 at the top of the substrate 501, and the bump 510 at the bottom of the substrate 501. The recessed pad 508 and the bump 510 are conductive contacts used to electrically couple other components to the substrate 501. The recessed pad 508 may be a copper pad recessed slightly below the dielectric glass layer 504, and the bump 510 may be a solder ball, bump, or microbump. The package substrate 501 also includes a layer of solder resist 509 at the bottom of the substrate where the bump 510 is located.

[0071] In some embodiments, for example, one or more additional silicon dies (not shown) may be hybrid-bonded to the recessed pads 508 on the upper side of the substrate 501 (e.g., via a combination of dielectric and copper-copper junctions). Furthermore, the substrate 501 may be bonded to a circuit board (e.g., a motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 510 at the bottom of the substrate 501.

[0072] For simplicity, the embedded die 512 is shown only on the upper side of the core 502. However, in other embodiments, passive components (e.g., trace 506) and the active silicon die 512 may be embedded on both sides of the core 502, or within the glass build-up layer 504 (e.g., using an embedded multi-die interconnect / bridge), or across both the core 502 and the glass build-up layer 504.

[0073] Figures 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, and 6I show the process flow for forming the embedded die package 500 of Figure 5. This process flow is just one exemplary methodology for manufacturing such a package.

[0074] The processing flow for the embedded die package 500, as shown in Figures 6A to 6I, is the same as the processing flow for the embedded die package 300, as shown in Figures 4A to 4I, except as will be described later.

[0075] In Figure 6C, the die 512 mounted in the cavity 507 includes through-silicon vias (TSVs) 513 connected to pads 514 on the top and bottom of the die 512.

[0076] In Figure 6E, via holes 505 are formed in the glass core 502 up to the die pad 514 on the top of the die 512 within the glass layer 504, and through holes 503 within the glass core 502, as well as within the glass core 502 up to the die pad 514 on the bottom of the embedded die 512. Additionally, the die attach film 511 on the bottom die pad 514 is removed (e.g., by laser) to allow electrical connections between the bottom die pad 514 and the subsequently formed vias.

[0077] Figures 7A to 7C illustrate various embodiments of glass substrates and packages having microbumps. In particular, Figures 7A, 7B, and 7C show embodiments of Figures 1, 3, and 5, respectively, in which the first level interconnects on the top surface for hybrid bonding are formed by microbumps rather than recessed pads. Thus, one or more silicon dies (or other integrated circuit packages / components) can be mounted to the top surface via microbumps.

[0078] For example, Figure 7A shows a glass package substrate 100' having microbumps 108' on its top surface, Figure 7B shows a glass embedded die package 300' having microbumps 308' on its top surface, and Figure 7C shows a glass embedded die package 500' having through-silicon vias 513 in an embedded die 512 and microbumps 508' on its top surface.

[0079] The embodiments in Figures 7A, 7B, and 7C can be manufactured using the same processing flows as those described in Figures 2A to 2J, 4A to 4I, and 6A to 6I, respectively. However, in the final stage of processing, solder resist and bumps are added to both sides of the glass substrate, not just on the bottom. Conventional bumping techniques can be used to form bumps for the first level interconnect (on the top) and the second level interconnect (on the bottom). Thus, conventional bump / microbump bonding is used on all-glass substrates, rather than on organic substrates or glass core-only substrates, to fully utilize the electrical and mechanical benefits of glass.

[0080] In embodiments illustrated and described throughout this disclosure (e.g., substrates / packages 100, 100', 300, 300', 500, 500'), other types of conductive contacts may be used instead of, or in addition to, those illustrated, including, but not limited to, metal pads (e.g., recessed or non-recessed copper pads), metal bumps / microbumps (e.g., C2 / C4 copper bumps), solder balls / bumps, and solder paste, among other examples.

[0081] Furthermore, in various embodiments, the glass substrate described herein may be an "all-glass" substrate or a "generally glass" substrate, meaning that the core is made of glass and all or some of the dielectric build-up layers are made of glass. In some embodiments, for example, the glass core may be made of solid glass rather than glass cloth or fabric (and may be patterned with various integrated circuit features). Furthermore, in some embodiments, all dielectric build-up layers may be glass layers, while in other embodiments, a combination of glass and non-glass build-up layers may exist, where the non-glass build-up layers are made of other dielectric materials, such as organic materials (e.g., ABF, solder resist). Furthermore, the glass core and / or glass / dielectric build-up layers may be patterned with various features, including but not limited to vias / traces, conductive contacts (e.g., pads, bumps), recesses, cavities, and embedded silicon dies.

[0082] Furthermore, the glass substrate described can be used as a substrate in any type of electronic device, including integrated circuit packages and circuit boards (e.g., printed circuit boards).

[0083] Figure 8 shows a flowchart 800 for forming an integrated circuit (IC) package on a substrate having a glass core and a glass build-up layer. In light of this disclosure, it will be understood that flowchart 800 is merely one exemplary methodology for reaching an IC package on a substrate having a glass core and a glass build-up layer.

[0084] The steps in flowchart 800 can be performed using any suitable semiconductor manufacturing technology. For example, patterning and removal, such as interconnect patterning, via opening formation and shaping, can be performed using any suitable technology, such as lithography-based patterning / masking and / or etching. Alternatively, film deposition can be performed, such as layer deposition, filling of layer portions (e.g., removed portions) and via opening filling, using any suitable deposition technology, such as electroless plating, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) and / or physical vapor deposition (PVD).

[0085] The flowchart begins in block 802 with the acceptance of a glass panel (or wafer) to be used as the core of a substrate for an IC package. The glass core can be formed from any type of glass. Thus, in some embodiments, the glass core may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3), and any combination of those elements.

[0086] Next, the flowchart proceeds to block 804 for forming traces inside and above / below the glass core. For example, through holes may be formed within the glass core and filled with a conductive material (e.g., metal) to form through-glass vias through the core. Furthermore, conductive layers may be formed above and below the core and etched into a suitable pattern of conductive traces. In some embodiments, the conductive material used to form the traces may include metals such as copper, titanium, tin, silver, gold, nickel, aluminum, tungsten and / or alloys thereof.

[0087] Next, the flowchart proceeds to block 806 for forming glass layers above and below the glass core. Furthermore, in some embodiments, the properties of the glass layers (e.g., CTE) can be adjusted to match those of the glass core and / or silicon (e.g., for hybrid bonding with a silicon die).

[0088] In some embodiments, for example, the glass layer is made of silicon oxide (SiO2). x The dielectric layer may be made from any suitable glass material, including but not limited to silicon dioxide (SiO2), also known as silica, or fused silica, and spin-on glass (such as silica (SiO2) containing dopants such as boron, phosphorus, titanium, and / or zinc). Therefore, in some embodiments, the glass layer may be made from a material containing elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, and alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0089] Next, the flowchart proceeds to block 808 for forming traces within the glass layers above and below the core, which include vias and horizontal traces.

[0090] Blocks 806 and 808 may be repeated as many times as necessary to form the appropriate number of glass build-up layers patterned using conductive traces above and below the core.

[0091] Next, the flowchart proceeds to block 810 for forming conductive contacts on one or more surfaces of the substrate (e.g., bonded to traces, on the top and / or bottom of the glass layer), among other examples, such as metal pads (e.g., recessed or non-recessed copper pads), metal bumps / microbumps (e.g., C2 / C4 copper bumps), solder balls / bumps and solder paste.

[0092] In some embodiments, for example, recessed pads (e.g., for hybrid bonding) or microbumps may be formed on the upper surface of the glass substrate for first-level interconnection to one or more integrated circuit dies. Furthermore, bumps may be formed on the lower surface of the glass substrate for second-level interconnection to a circuit board (e.g., a motherboard, mainboard, etc.) or another integrated circuit package.

[0093] Thus, the completed package substrate includes a glass core, glass build-up layers above and below the glass core, conductive traces patterned within the glass core and glass build-up layers, and conductive contacts on the surface of the substrate for first and / or second level interconnection.

[0094] Next, the flowchart proceeds to block 812 for mounting one or more integrated circuit (IC) dies to the substrate. In some embodiments, for example, one or more dies may be mounted on top of the glass substrate by, among other examples, hybrid bonding the dies to recessed copper pads on the substrate surface, or by mounting the dies to microbumps on the substrate surface. Alternatively, in some embodiments, one or more cavities may be formed within the glass core and / or glass layer during an earlier stage of processing, and one or more silicon dies may be embedded within the cavities and interconnected with conductive traces patterned within the glass build-up layer.

[0095] An integrated circuit die may include, but is not limited to, any suitable type of circuitry, including processing circuits, communication circuits, and / or memory / storage circuits. In some embodiments, for example, an integrated circuit die may include, among other examples, a central processing unit (CPU), a graphics processing unit (GPU), a visual processing unit (VPU), a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an input / output (I / O) controller, a network interface controller (NIC), memory, and / or solid-state storage.

[0096] The completed IC package may then be mounted on a circuit board, another integrated circuit board or package, or an electronic device (e.g., electronic device 1200), or may be included as part of such a device.

[0097] In some embodiments, for example, an IC package may be included in an electronic device, such as a mobile phone, wearable device, computer, server, camera, video playback device, video game console, display device, vehicle control unit, or appliance, among other examples.

[0098] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may be restarted and / or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart block 802 to form another integrated circuit package having the same or similar design. [Embodimentary Integrated Circuit Embodiment]

[0099] Figure 9 is a top view of a wafer 900 and a die 902 that may be included in any of the embodiments disclosed herein. The wafer 900 may be composed of a semiconductor material and may include one or more dies 902 having an integrated circuit structure formed on the surface of the wafer 900. Each die 902 may be a repeating unit of an integrated circuit product containing any suitable integrated circuit. After the manufacturing of the semiconductor product is complete, the wafer 900 may undergo a unitization process in which the dies 902 are separated from each other to provide individual “chips” of the integrated circuit product. The die 902 may be any of the dies disclosed herein. The die 902 may include one or more transistors (e.g., some of the transistors 1040 in Figure 10, which are discussed below), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors or inductors), and / or any other integrated circuit components that may be manufactured on the wafer. In some embodiments, the wafer 900 or die 902 may include memory devices (e.g., random access memory (RAM) devices, e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, and NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be formed on the same die 902 as a processor unit (e.g., processor unit 1202 in Figure 12) or other logic, configured to store information in the memory devices or to execute instructions stored in the memory array. Various microelectronic assemblies disclosed herein may be manufactured using die-wafer assembly technology, in which several dies are mounted onto a wafer 900 containing other dies, and the wafer 900 is subsequently assembled.

[0100] Figure 10 is a side cross-sectional view of an integrated circuit device 1000 that may be included in any of the embodiments disclosed herein (e.g., any of the dies). One or more of the integrated circuit devices 1000 may be included in one or more dies 902 (Figure 9). The integrated circuit device 1000 may be formed on a die substrate 1002 (e.g., wafer 900 in Figure 9) and may be included in a die (e.g., die 902 in Figure 9). The die substrate 1002 may be a semiconductor substrate composed of a semiconductor material system including, for example, a system of n-type or p-type material (or a combination of both). The die substrate 1002 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials that may or may not be combined with silicon, including, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Groups II to VI, III to V, or IV may also be used to form the die substrate 1002. A few examples of materials on which the die substrate 1002 may be formed are described here, but any material capable of functioning as the basis for the integrated circuit device 1000 may be used. The die substrate 1002 may be a standalone die (e.g., die 902 in Figure 9) or part of a wafer (e.g., wafer 900 in Figure 9).

[0101] The integrated circuit device 1000 may include one or more device layers 1004 disposed on the die substrate 1002. The device layer 1004 may include features of one or more transistors 1040 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The transistor 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling the flow of current between the S / D regions 1020, and one or more S / D contacts 1024 for routing electrical signals to and from the S / D regions 1020. The transistor 1040 may include additional features not shown for clarity, such as device isolation regions and gate contacts. The transistor 1040 is not limited to the type and configuration shown in Figure 10 and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include, for example, FinFET transistors such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon, nanosheet, or nanowire transistors.

[0102] Returning to Figure 10, the transistor 1040 may include a gate 1022 formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of one or more layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high dielectric constant dielectric materials.

[0103] High dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high dielectric materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and zinc lead niobate. In some embodiments, when a high dielectric material is used, the gate dielectric layer may be subjected to annealing to improve its quality.

[0104] The gate electrode may be formed on a gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1040 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Further metal layers, such as barrier layers, may be included for other purposes.

[0105] In the case of PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). In the case of NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0106] In some embodiments, when viewed as a cross-section of the transistor 1040 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1002 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1002 and not including sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0107] In some embodiments, pairs of sidewall spacers may be formed on opposing sides of a gate stack so as to surround the gate stack. These sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Several processes for forming sidewall spacers are known in the art and generally involve deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of a gate stack.

[0108] The S / D region 1020 may be formed within the die substrate 1002 adjacent to the gate 1022 of individual transistors 1040. The S / D region 1020 may be formed, for example, by an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1002 to form the S / D region 1020. An annealing process may follow the ion implantation process to activate the dopants and diffuse them further into the die substrate 1002. In the latter process, the die substrate 1002 may first be etched to form a depression at the location of the S / D region 1020. Then, an epitaxial growth process may be performed to fill the depression with the material used to manufacture the S / D region 1020. In some packaging configurations, the S / D region 1020 may be manufactured using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1020 may be formed using one or more alternating semiconductor materials, such as germanium or materials or alloys of groups III to V. In further embodiments, one or more layers of metals and / or metallic alloys may be used to form the S / D region 1020.

[0109] Electrical signals, such as power and / or information carrier signals (e.g., input / output (I / O) signals), can be routed to and from devices on device layer 1004 (e.g., transistor 1040) through one or more interconnection layers (shown as interconnection layers 1006 to 1010 in Figure 10) located on device layer 1004. For example, conductive features on device layer 1004 (e.g., gate 1022 and S / D contact 1024) can be electrically coupled to the interconnection structure 1028 of interconnection layers 1006 to 1010. One or more interconnection layers 1006 to 1010 can form a metallization stack (also referred to as an "ILD" stack) 1019 of the integrated circuit device 1000.

[0110] The interconnect structure 1028 may be arranged within interconnect layers 1006 to 1010 to route electrical signals according to a wide variety of designs; in particular, such arrangement is not limited to the specific configuration of the interconnect structure 1028 shown in Figure 10. Although a certain number of interconnect layers 1006 to 1010 are shown in Figure 10, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than shown.

[0111] In some embodiments, the interconnection structure 1028 may include traces or lines 1028a and / or vias 1028b filled with a conductive material such as metal. Lines 1028a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1002 on which the device layer 1004 is formed. For example, from the viewpoint of Figure 10, lines 1028a may route electrical signals in the direction inward and outward of the page and / or across the page. Vias 1028b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, vias 1028b may electrically couple lines 1028a from different interconnection layers 1006 to 1010 together.

[0112] As shown in Figure 10, interconnection layers 1006 to 1010 may include dielectric material 1026 disposed between interconnection structures 1028. In some embodiments, the dielectric material 1026 disposed between interconnection structures 1028 in different interconnection layers 1006 to 1010 may have different compositions; in other embodiments, the composition of the dielectric material 1026 between different interconnection layers 1006 to 1010 may be the same. Device layer 1004 may also include dielectric material 1026 disposed between transistor 1040 and the bottom layer of the metallization stack. The dielectric material 1026 contained in device layer 1004 may have a different composition from the dielectric material 1026 contained in interconnection layers 1006 to 1010; in other embodiments, the composition of the dielectric material 1026 in device layer 1004 may be the same as the dielectric material 1026 contained in any one of interconnection layers 1006 to 1010.

[0113] A first interconnection layer 1006 (which may be referred to as metal 1 or "M1" layer) may be formed directly on the device layer 1004. As shown, in some embodiments, the first interconnection layer 1006 may include lines 1028a and / or vias 1028b. Lines 1028a of the first interconnection layer 1006 may be coupled to contacts of the device layer 1004 (e.g., S / D contacts 1024). Vias 1028b of the first interconnection layer 1006 may be coupled to lines 1028a of the second interconnection layer 1008.

[0114] A second interconnection layer 1008 (which may be referred to as metal 2 or the "M2" layer) may be formed directly on the first interconnection layer 1006. In some embodiments, the second interconnection layer 1008 may include vias 1028b for connecting a line 1028 of the second interconnection layer 1008 to a line 1028a of the third interconnection layer 1010. Although the line 1028a and via 1028b are structurally depicted using lines within the individual interconnection layers for clarity, the line 1028a and via 1028b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during dual damascene treatment).

[0115] A third interconnection layer 1010 (which may be referred to as metal 3 or "M3" layer) (and any additional interconnection layers as desired) may be formed in succession on the second interconnection layer 1008 according to similar techniques and configurations described in relation to the second interconnection layer 1008 or the first interconnection layer 1006. In some embodiments, interconnection layers that are "higher" (i.e., further away from device layer 1004) in the metallization stack 1019 within the integrated circuit device 1000 may be thicker than interconnection layers that are lower in the metallization stack 1019, and lines 1028a and vias 1028b in the higher interconnection layers may be thicker than those in the lower interconnection layers.

[0116] The integrated circuit device 1000 may include a solder resist material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on interconnect layers 1006 to 1010. In Figure 10, the conductive contacts 1036 are shown to take the form of bonding pads. The conductive contacts 1036 may be electrically coupled to an interconnect structure 1028 and may be configured to route electrical signals from transistor 1040 to an external device. For example, solder joints may be formed on one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die comprising the integrated circuit device 1000 to another component (e.g., a printed circuit board). The integrated circuit device 1000 may include additional or alternating structures for routing electrical signals from interconnect layers 1006 to 1010; for example, the conductive contacts 1036 may include other similar features (e.g., posts) for routing electrical signals to an external component. The conductive contact 1036 may function as any of the conductive contacts described throughout this disclosure.

[0117] In some embodiments where the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may include another metallization stack (not shown) on the opposite side of the device layer 1004. This metallization stack may include a number of interconnect layers discussed above with reference to interconnect layers 1006 to 1010 to provide conductive paths (including, for example, conductive wires and vias) between the device layer 1004 and additional conductive contacts (not shown) on the opposite side of the conductive contact 1036 of the integrated circuit device 1000. These additional conductive contacts may function as any of the conductive contacts described throughout this disclosure.

[0118] In other embodiments where the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may include one or more through-silicon vias (TSVs) through the die substrate 1002; these TSVs may contact the device layer 1004 and may provide a conductive path between the device layer 1004 and additional conductive contacts (not shown) of the integrated circuit device 1000 on the opposite side of the conductive contact 1036. These additional conductive contacts may function as any of the conductive contacts described throughout this disclosure. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts of the integrated circuit device 1000 on the opposite side of the conductive contact 1036 to the transistor 1040 and any other components integrated into the die 1000, and a metallization stack 1019 may be used to route I / O signals from the conductive contact 1036 to the transistor 1040 and any other components integrated into the die 1000.

[0119] In individual stacked devices, multiple integrated circuit devices 1000 may be stacked using one or more TSVs that provide connections between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on a base integrated circuit die, and TSVs within the HBM die may provide connections between the individual HBM dies and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0120] Figure 11 is a side cross-sectional view of an integrated circuit device assembly 1100, which may include any of the embodiments disclosed herein. For example, any suitable component of the integrated circuit device assembly 1100 may include one or more of the glass substrates / packages 100, 300, 500 disclosed herein. In some embodiments, the integrated circuit device assembly 1100 may be a microelectronic assembly. The integrated circuit device assembly 1100 includes a number of components arranged on a circuit board 1102 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 1100 includes components arranged on a first surface 1140 of the circuit board 1102 and an opposing second surface 1142 of the circuit board 1102; generally, components may be arranged on one or both surfaces 1140 and 1142. Any integrated circuit component discussed below with reference to the integrated circuit device assembly 1100 may take the form of any suitable embodiment of the microelectronic assembly 100 disclosed herein.

[0121] In some embodiments, the circuit board 1102 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnected) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. One or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1102. In other embodiments, the circuit board 1102 may be a non-PCB substrate. The integrated circuit device assembly 1100 shown in Figure 11 includes a package-on-interposer structure 1136 coupled to a first surface 1140 of the circuit board 1102 by a coupling component 1116. The coupling component 1116 may electrically and mechanically couple the package-on-interposer structure 1136 to the circuit board 1102 and may include solder balls (shown in Figure 11), pins (e.g., part of a pin grid array (PGA)), contacts (e.g., part of a land grid array (LGA)), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure. The coupling component 1116 may, as appropriate, function as a coupling component shown or described for any of the board assemblies or board assembly components described herein.

[0122] The package-on-interposer structure 1136 may include an integrated circuit component 1120 coupled to an interposer 1104 by a coupling component 1118. The coupling component 1118 can take any suitable form for the application, such as the form discussed above with reference to the coupling component 1116. Although a single integrated circuit component 1120 is shown in Figure 11, multiple integrated circuit components may be coupled to the interposer 1104; in fact, additional interposers may be coupled to the interposer 1104. The interposer 1104 may provide an intervening substrate used to bridge the circuit board 1102 and the integrated circuit component 1120.

[0123] The integrated circuit component 1120 may be a packaged or unpackaged integrated circuit product comprising one or more integrated circuit dies (e.g., die 902 in Figure 9, integrated circuit device 1000 in Figure 10) and / or one or more other suitable components. The packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, and the integrated circuit dies and package substrate are sealed within a casing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1120, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly mounted to the interposer 1104. The integrated circuit component 1120 may comprise one or more computing system components, such as one or more processor units (e.g., a system-on-a-chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor, an I / O controller, memory, or a network interface controller). In some embodiments, the integrated circuit component 1120 may comprise one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0124] In embodiments where the integrated circuit component 1120 comprises multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). The multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0125] In addition to comprising one or more processor units, the integrated circuit component 1120 may comprise additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor units, or on one or more separate integrated circuit dies from the integrated circuit die comprising the processor units. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments in which the integrated circuit component comprises multiple integrated circuit dies, interconnection between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded within the package substrate (such as Intel® Embedded Multi-Die Interconnection Bridges (EMIBs)), or a combination thereof.

[0126] In general, the interposer 1104 may have wider pitches between connections, or it may reroute connections to different connections. For example, the interposer 1104 may couple an integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of a coupling component 1116 for coupling to a circuit board 1102. In the embodiment shown in Figure 11, the integrated circuit component 1120 and the circuit board 1102 are mounted on opposing sides of the interposer 1104; in other embodiments, the integrated circuit component 1120 and the circuit board 1102 may be mounted on the same side of the interposer 1104. In some embodiments, three or more components may be interconnected by the interposer 1104.

[0127] In some embodiments, the interposer 1104 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, an epoxy resin containing an inorganic filler, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1104 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III to V and IV materials. The interposer 1104 may include metal interconnects 1108 and vias 1110, which include, but are not limited to, through vias 1110-1 (extending from a first surface 1150 of the interposer 1104 to a second surface 1154 of the interposer 1104), blind vias 1110-2 (extending from the first or second surface 1150 or 1154 of the interposer 1104 to an internal metal layer), and embedded vias 1110-3 (connecting internal metal layers).

[0128] In some embodiments, the interposer 1104 may comprise a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections from a first face of the silicon interposer to an opposing second face of the silicon interposer. In some embodiments, the interposer 1104 comprising a silicon interposer may further comprise one or more routing layers for routing connections from the first face of the interposer 1104 to the opposing second face of the interposer 1104.

[0129] The interposer 1104 may further include embedded devices 1114, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. Multiple more complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1104. The package-on-interposer structure 1136 may take any form of package-on-interposer structure known in the art. In embodiments where the interposer is a non-printed circuit board,

[0130] The integrated circuit device assembly 1100 may include an integrated circuit component 1124 coupled to the first surface 1140 of the circuit board 1102 by a coupling component 1122. The coupling component 1122 may take any form of the embodiments discussed above with reference to coupling component 1116, and the integrated circuit component 1124 may take any form of the embodiments discussed above with reference to integrated circuit component 1120.

[0131] The integrated circuit device assembly 1100 shown in Figure 11 includes a package-on-package structure 1134 coupled to a second surface 1142 of a circuit board 1102 by a coupling component 1128. The package-on-package structure 1134 may include integrated circuit components 1126 and 1132, coupled together by a coupling component 1130 such that integrated circuit component 1126 is positioned between the circuit board 1102 and integrated circuit component 1132. The coupling components 1128 and 1130 may take any form of the embodiment of the coupling component 1116 discussed above, and the integrated circuit components 1126 and 1132 may take any form of the embodiment of the integrated circuit component 1120 discussed above. The package-on-package structure 1134 may be configured according to any package-on-package structure known in the art.

[0132] Figure 12 is a block diagram of an exemplary electrical device 1200, which may include one or more embodiments disclosed herein. For example, any suitable components of the electrical device 1200 may include one or more of the glass substrates / packages 100, 100', 300, 300', 500, 500', integrated circuit device assembly 1100, integrated circuit component 1120, integrated circuit device 1000, or integrated circuit die 902 disclosed herein. Although numerous components are shown in Figure 12 as being included in the electrical device 1200, one or more of these components may be omitted or duplicated where appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1200 may be mounted on one or more motherboard mainboards or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die.

[0133] Additionally, in various embodiments, the electrical device 1200 does not have to include one or more of the components shown in Figure 12, but it may include interface circuits for coupling one or more components. For example, the electrical device 1200 does not have to include the display device 1206, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1206 can be coupled. In another set of examples, the electrical device 1200 does not have to include the audio input device 1224 or the audio output device 1208, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1224 or the audio output device 1208 can be coupled.

[0134] The electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit may be referred to as XPU (or xPU).

[0135] The electrical device 1200 may include a memory 1204, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard drives). In some embodiments, the memory 1204 may include a memory located on the same integrated circuit die as the processor unit 1202. This memory may be used as a cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0136] In some embodiments, the electrical device 1200 may comprise one or more processor units 1202 that are heterogeneous or asymmetrical to other processor units 1202 within the electrical device 1200. A variety of differences may exist among the processing units 1202 in the system with respect to a range of value criteria, including architecture, microarchitecture, thermal and power consumption characteristics, etc. These differences can effectively represent themselves as asymmetry and heterogeneity among the processor units 1202 in the electrical device 1200.

[0137] In some embodiments, the electrical device 1200 may include a communication component 1212 (e.g., one or more communication components). For example, the communication component 1212 may manage wireless communication for data transfer to and from the electrical device 1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term “wireless” does not imply that the associated device does not include any wires, although this may not be the case in some embodiments.

[0138] The communication component 1212 may implement any of the numerous wireless standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects, including any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are collectively referred to as WiMAX® networks, an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication component 1212 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1212 may operate in accordance with GSM® Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication component 1212 may operate in accordance with other radio protocols.The electrical device 1200 may include an antenna 1222 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0139] In some embodiments, the communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet® standard). As described above, the communication component 1212 may include multiple communication components. For example, the first communication component 1212 may be dedicated to shorter-range wireless communications, such as Wi-Fi® or Bluetooth®, and the second communication component 1212 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1212 may be dedicated to wireless communications, and the second communication component 1212 may be dedicated to wired communications.

[0140] The electrical device 1200 may include a battery / power supply circuit 1214. The battery / power supply circuit 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power).

[0141] The electrical device 1200 may include a display device 1206 (or the corresponding interface circuit discussed above). The display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0142] The electrical device 1200 may include an audio output device 1208 (or the corresponding interface circuit discussed above). The audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or earphone.

[0143] The electrical device 1200 may include an audio input device 1224 (or a corresponding interface circuit as discussed above). The audio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output). The electrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or a corresponding interface circuit as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1218 may communicate with a satellite-based system and determine the geographic location of the electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0144] The electrical device 1200 may include other output devices 1210 (or corresponding interface circuits as discussed above). Examples of other output devices 1210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0145] The electrical device 1200 may include other input devices 1220 (or corresponding interface circuits as discussed above). Examples of other input devices 1220 may include accelerometers, gyroscopes, compasses, imaging devices (e.g., planar or stereoscopic cameras), cursor control devices such as trackballs, trackpads, touchpads, keyboards, and mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, Quick Response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photopulse wave) sensors, galvanic skin reaction sensors, any other sensors, or radio frequency identification (RFID) readers.

[0146] The electrical device 1200 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, 2-in-1 convertible computer, portable all-in-one computer, notebook computer, ultrabook computer, personal digital assistant (PDA®), ultramobile personal computer, portable gaming console, etc.), desktop electrical device, server, rack-level computing solution (e.g., blade, tray, or thread computing system), workstation or other network computing component, printer, scanner, display device (e.g., monitor, television), set-top box, entertainment control unit, video game console, video playback device, vehicle control unit, digital camera, digital video recorder, wearable electrical device, or embedded computing system (e.g., a vehicle, smart home appliance, consumer electronics product or device, or a computing system that is part of manufacturing equipment). In some embodiments, the electrical device 1200 may be any other electronic device that processes data. In some embodiments, the electrical device 1200 may comprise a plurality of separate physical components. Considering the range of devices that the electrical device 1200 can represent, as in various embodiments, in some embodiments the electrical device 1200 may be referred to as a computing device or computing system. [Example Embodiments]

[0147] Exemplary examples of the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components described in one or more of the figures above may be configured to perform one or more operations, techniques, processes and / or methods described in the following examples.

[0148] Example 1 is a substrate comprising a glass core; a plurality of glass layers on the glass core, some of the glass layers being above the glass core and some of the glass layers being below the glass core; a plurality of conductive traces, the conductive traces being inside the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate.

[0149] Example 2 includes the substrate described in Example 1, wherein the conductive traces have a plurality of vias, wherein the vias are located inside at least some of the glass core and the glass layer; and a plurality of horizontal traces, wherein the horizontal traces are located inside at least some of the glass layer.

[0150] Example 3 includes a substrate according to any one of Examples 1 to 2, wherein at least some of the conductive contacts are electrically coupled to a circuit board or integrated circuit package.

[0151] Example 4 includes a substrate according to any one of Examples 1 to 3, wherein at least some of the conductive contacts are electrically coupled to an integrated circuit die.

[0152] Example 5 includes the substrate described in Example 4, wherein the conductive contact electrically coupled to the integrated circuit die has a plurality of microbumps; or a plurality of pads.

[0153] Example 6 includes the substrate described in Example 5, wherein the pad is recessed relative to the glass layer.

[0154] Example 7 includes a substrate according to any one of Examples 1 to 6, wherein the glass core has a thickness in the range of approximately 100 to 1000 microns.

[0155] Example 8 includes a substrate according to any one of Examples 1 to 7, wherein at least some of the glass layers have a thickness in the range of approximately 10 to 50 microns.

[0156] Example 9 includes a substrate according to any one of Examples 1 to 8, wherein at least some of the glass layers have silicon and oxygen.

[0157] Example 10 includes a substrate according to any one of Examples 1 to 9, wherein the conductive trace has at least one of copper or titanium.

[0158] Example 11 includes an integrated circuit package comprising an integrated circuit die; and a package substrate electrically coupled to the integrated circuit die, wherein the package substrate has a glass core; a plurality of glass layers on the glass core, some of the glass layers being above the glass core and some of the glass layers being below the glass core; a plurality of conductive traces, the conductive traces being inside the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the package substrate.

[0159] Example 12 includes the integrated circuit package described in Example 11, wherein at least some of the conductive contacts are electrically coupled to a circuit board or another integrated circuit package.

[0160] Example 13 includes an integrated circuit package according to any one of Examples 11 to 12, wherein at least some of the conductive contacts are electrically coupled to the integrated circuit die.

[0161] Example 14 includes an integrated circuit package according to any one of Examples 11 to 12, wherein the integrated circuit die is embedded in a cavity of the package substrate.

[0162] Example 15 includes an integrated circuit package according to any one of Examples 11 to 14, wherein the integrated circuit die has a processing circuit, a communication circuit, or a memory circuit.

[0163] Example 16 includes an electronic device comprising a circuit board; and an integrated circuit package electrically coupled to the circuit board, wherein the integrated circuit package has one or more integrated circuit dies; and a package substrate electrically coupled to the one or more integrated circuit dies, the package substrate having a glass core; a plurality of glass layers on the glass core, where some of the glass layers are above the glass core and some of the glass layers are below the glass core; a plurality of conductive traces, where the conductive traces are inside the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the package substrate.

[0164] Example 17 includes the electronic device described in Example 16, wherein the electronic device is a mobile phone, a wearable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit, or an appliance.

[0165] Example 18 includes a method comprising the steps of: receiving a glass core; forming a plurality of glass layers on the glass core, wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core; forming a plurality of conductive traces inside the glass core and at least some of the glass layers; and forming a plurality of conductive contacts on one or more surfaces of the glass layers.

[0166] Example 19 further comprises the method of Example 18, further comprising the step of attaching an integrated circuit die to at least some of the conductive contacts.

[0167] Example 20 includes the method of Example 18, further comprising the steps of forming cavities inside at least some of the glass core and / or glass layers; and embedding an integrated circuit die within the cavities.

[0168] While the concepts of this disclosure are open to various modifications and alternative forms, specific embodiments are shown as examples in the drawings and described in detail herein. However, it should be understood that the concepts of this disclosure are not intended to be limited to any specific forms disclosed, but rather are intended to encompass all modifications, equivalents, and alternatives that are consistent with this disclosure and the appended claims.

[0169] In drawings, certain structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order is not required. Rather, in some embodiments, such features may be arranged in a different manner and / or order than those shown in the exemplary drawings. Additionally, the inclusion of structural or method features in a particular drawing is not intended to suggest that such features are required in all embodiments, and in some embodiments, they may be omitted or combined with other features. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0170] Furthermore, the examples and / or descriptions of various embodiments may be simplified or approximated for ease of understanding and may not necessarily reflect the level of precision or variability that may be presented in actual embodiments. For example, while some figures generally show straight lines, right angles, and smooth surfaces, given real-world limitations on manufacturing processes, actual implementations of the disclosed embodiments may have imperfect straight lines and right angles, and some features may have surface topologies or may not be smooth. Similarly, the examples and / or descriptions of how components are arranged may be simplified or approximated for ease of understanding and may vary due to some tolerances in actual embodiments (e.g., due to manufacturing processes).

[0171] Unless otherwise specified, the use of ordinal numbers such as “first,” “second,” and “third” to describe a common object merely indicates that different examples of similar objects are being referred to, and is not intended to suggest that the objects described in this way must be in a given order, temporally, spatially, in order, or in any other manner.

[0172] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 10% of the target value (unless otherwise specified). Similarly, terms describing spatial relationships, such as "perpendicular," "orthogonal," or "coplanar," may substantially refer to being within the described spatial relationship (e.g., orthogonality within + / - 10).

[0173] Furthermore, certain terms may be used for reference purposes only in the above explanations and are therefore not intended to be restrictive. For example, terms such as “upper,” “lower,” “above,” “below,” “bottom,” and “top” refer to the direction in the drawing being referenced. Terms such as “front,” “back,” “rear,” and “side” describe the orientation and / or position of a part of a component within a consistent but arbitrary reference frame, which becomes clear by referring to the wording describing the component being discussed and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0174] As used herein, the terms “over,” “between,” “adjacent,” “to,” and “on” may refer to the relative position of one layer or component to another layer or component. For example, one layer that is “over” or “on” another layer, “adjacent” to another layer, or “to” another layer may be in direct contact with that other layer, or may have one or more intervening layers. One layer “between” multiple layers may be in direct contact with multiple layers, or may have one or more intervening layers.

[0175] The meanings of "a," "an," and "the" include multiple references. The meaning of "in" includes "inside" and "on."

[0176] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0177] The term "package" generally refers to an internal carrier of one or more dies, where the dies are mounted on a package substrate and may be sealed for protection, along with integrated or wire-bonded interconnections between the dies and leads, pins, or bumps located on the external portion of the package substrate. A package may contain one or more dies that provide a specific function. Packages are typically mounted on a printed circuit board for interconnection with other packaged integrated circuits and individual components to form a larger circuit.

[0178] Here, the term "cored" generally refers to the substrate of an integrated circuit package built on a substrate, card, or wafer containing a rigid, non-flexible material. Typically, a small printed circuit board is used as the core, on which integrated circuit devices and individual passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuits on one side of the core to be directly coupled to circuits on the opposite side. The core can also function as a platform for building layers of conductive and dielectric materials.

[0179] Here, the term "coreless" generally refers to the substrate of an integrated circuit package that does not have a core. Since through-vias have relatively large dimensions and pitches compared to high-density interconnects, the absence of a core allows for a higher density package architecture.

[0180] As used herein, the term “land side” generally refers to the side of the substrate of an integrated circuit package that is closest to the plane on which it is mounted to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side,” which refers to the side of the substrate of an integrated circuit package to which a die or die is mounted.

[0181] The term “dielectric” generally refers to any number of nonconductive materials that constitute the structure of a package substrate. For the purposes of this disclosure, dielectric materials may be incorporated into an integrated circuit package as layers of a multilayer film or as a resin molded onto an integrated circuit die mounted on a substrate.

[0182] Here, the term "metallization" generally refers to a metallic layer formed on and through the dielectric material of a package substrate. The metallic layer is generally patterned to form metallic structures such as traces and bonding pads. The metallization of the package substrate may be limited to a single layer or may occur within multiple layers separated by dielectric layers.

[0183] Here, the term “bonding pad” generally refers to the metallization structure that terminates integrated traces and vias within an integrated circuit package and die. The term “solder pad” sometimes supersedes “bonding pad” and retains the same meaning.

[0184] The term "solder bump" generally refers to the layer of solder that forms on a bonding pad. This solder layer typically has a rounded shape, hence the term "solder bump."

[0185] The term “substrate” generally refers to a flat platform having a dielectric and / or metallization structure. A substrate may encapsulate one or more IC dies with a formable dielectric material and mechanically support and electrically couple one or more IC dies on a single platform. A substrate may include solder bumps (or other conductive contacts) that join interconnections on one or both sides. One side of the substrate is collectively referred to as the “die side” and may include solder bumps for chip or die bonding. The opposite side of the substrate is collectively referred to as the “land side” and may include solder bumps for bonding the package to a printed circuit board.

[0186] The term "assembly" generally refers to the grouping of multiple parts into a single functional unit. These parts may be separate and mechanically assembled into a functional unit, where they may be detachable. In another example, the parts may be permanently joined together. In some examples, the parts are integrated together.

[0187] The terms "coupled" or "connected" refer to direct or indirect connections between multiple connected objects, such as direct electrical, mechanical, magnetic, or fluid connections, or indirect connections through one or more passive or active intermediate devices.

[0188] The terms “circuit” or “module” may refer to one or more passive and / or active components arranged to work together to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. (Other possible items) (Item 1) It is a substrate, Glass core; A plurality of glass layers on the glass core, where some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are located inside at least some of the glass core and the glass layer; and Multiple conductive contacts on one or more surfaces of the aforementioned substrate A substrate comprising the above. (Item 2) The conductive trace is Multiple vias, wherein the vias are located inside at least some of the glass core and the glass layers; and Multiple horizontal traces, where the horizontal traces are located inside at least some of the glass layers. Having, The circuit board described in item 1. (Item 3) A substrate according to any one of items 1 to 2, wherein at least some of the conductive contacts are electrically coupled to a circuit board or integrated circuit package. (Item 4) A substrate according to any one of items 1 to 3, wherein at least some of the conductive contacts are electrically coupled to an integrated circuit die. (Item 5) The conductive contact electrically coupled to the integrated circuit die is Multiple microbumps; or Multiple pads Having, The circuit board described in item 4. (Item 6) The substrate according to item 5, wherein the pad is recessed relative to the glass layer. (Item 7) The glass core is a substrate according to any one of items 1 to 6, having a thickness in the range of approximately 100 to 1000 microns. (Item 8) A substrate according to any one of items 1 to 7, wherein at least some of the glass layers have a thickness in the range of approximately 10 to 50 microns. (Item 9) A substrate according to any one of items 1 to 8, wherein at least some of the glass layers have silicon and oxygen. (Item 10) The conductive trace is a substrate according to any one of items 1 to 9, having at least one of copper or titanium. (Item 11) Integrated circuit dies; and Package substrate electrically coupled to the aforementioned integrated circuit die Equipped with, The aforementioned package substrate is Glass core; A plurality of glass layers on the glass core, where some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are located inside at least some of the glass core and the glass layer; and Multiple conductive contacts on one or more surfaces of the aforementioned package substrate Having, device. (Item 12) The device according to item 11, wherein at least some of the conductive contacts are electrically coupled to the integrated circuit die, and the conductive contacts electrically coupled to the integrated circuit die include microbumps or pads. (Item 13) The device according to item 12, wherein the pad is recessed relative to the glass layer. (Item 14) The integrated circuit die is embedded in a cavity of the package substrate, as described in any one of items 11 to 13. (Item 15) The device according to any one of items 11 to 14, wherein the glass core has a thickness in the range of approximately 100 to 1000 microns. (Item 16) The device according to any one of items 11 to 15, wherein at least some of the glass layers have a thickness in the range of approximately 10 to 50 microns. (Item 17) The device according to any one of items 11 to 16, wherein at least some of the glass layers have silicon and oxygen. (Item 18) The conductive trace is the device according to any one of items 11 to 17, wherein the conductive trace has at least one of copper or titanium. (Item 19) The integrated circuit die is a device according to any one of items 11 to 18, having a processing circuit, a communication circuit, or a memory circuit. (Item 20) The device according to any one of items 11 to 19, further comprising an integrated circuit package, wherein the integrated circuit package comprises the integrated circuit die and the package substrate. (Item 21) The device according to item 20, further comprising a circuit board, wherein the integrated circuit package is electrically coupled to the circuit board. (Item 22) The device is a mobile phone, a wearable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit, or an appliance, as described in item 21. (Item 23) Acceptance phase for the glass core; The step of forming a plurality of glass layers on the glass core, wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core; A step of forming a plurality of conductive traces inside at least some of the glass core and the glass layer; and The step of forming a plurality of conductive contacts on one or more surfaces of the glass layer. A method for providing this. (Item 24) The method according to item 23, further comprising the step of attaching an integrated circuit die to at least some of the aforementioned conductive contacts. (Item 25) The step of forming a cavity inside at least some of the glass core and / or glass layers; and The step of embedding an integrated circuit die in the cavity. The method described in item 23, which further includes the following:

Claims

1. It is a substrate, Glass core; A plurality of glass layers on the glass core, where some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are located inside at least some of the glass core and the glass layer; and Multiple conductive contacts on one or more surfaces of the aforementioned substrate A substrate comprising the above.

2. The conductive trace is Multiple vias, wherein the vias are located inside at least some of the glass core and the glass layers; and Multiple horizontal traces, where the horizontal traces are located inside at least some of the glass layers. Having, The substrate according to claim 1.

3. The substrate according to claim 1, wherein at least some of the conductive contacts are electrically coupled to a circuit board or integrated circuit package.

4. The substrate according to claim 1, wherein at least some of the conductive contacts are electrically coupled to an integrated circuit die.

5. The conductive contact electrically coupled to the integrated circuit die is Multiple microbumps; or Multiple pads Having, The substrate according to claim 4.

6. The substrate according to claim 5, wherein the pad is recessed relative to the glass layer.

7. The substrate according to claim 1, wherein the glass core has a thickness in the range of approximately 100 to 1000 microns.

8. The substrate according to claim 1, wherein at least some of the glass layers have a thickness in the range of approximately 10 to 50 microns.

9. The substrate according to claim 1, wherein at least some of the glass layers have silicon and oxygen.

10. The conductive trace is the substrate according to any one of claims 1 to 9, wherein the conductive trace has at least one of copper or titanium.

11. Integrated circuit dies; and Package substrate electrically coupled to the aforementioned integrated circuit die Equipped with, The aforementioned package substrate is Glass core; A plurality of glass layers on the glass core, where some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are located inside at least some of the glass core and the glass layer; and Multiple conductive contacts on one or more surfaces of the package substrate Having, device.

12. The device according to claim 11, wherein at least some of the conductive contacts are electrically coupled to the integrated circuit die, and the conductive contacts electrically coupled to the integrated circuit die include microbumps or pads.

13. The device according to claim 12, wherein the pad is recessed relative to the glass layer.

14. The device according to claim 11, wherein the integrated circuit die is embedded in a cavity of the package substrate.

15. The device according to claim 11, wherein the glass core has a thickness in the range of approximately 100 to 1000 microns.

16. The device according to claim 11, wherein at least some of the glass layers have a thickness in the range of approximately 10 to 50 microns.

17. The device according to claim 11, wherein at least some of the glass layers have silicon and oxygen.

18. The device according to claim 11, wherein the conductive trace has at least one of copper or titanium.

19. The device according to claim 11, wherein the integrated circuit die has a processing circuit, a communication circuit, or a memory circuit.

20. The device according to any one of claims 11 to 19, further comprising an integrated circuit package, wherein the integrated circuit package comprises the integrated circuit die and the package substrate.

21. The device according to claim 20, further comprising a circuit board, wherein the integrated circuit package is electrically coupled to the circuit board.

22. The device according to claim 21, wherein the device is a mobile phone, a wearable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit, or an appliance.

23. Acceptance phase for the glass core; A step of forming a plurality of glass layers on the glass core, wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core; A step of forming a plurality of conductive traces inside at least some of the glass core and the glass layer; and The step of forming a plurality of conductive contacts on one or more surfaces of the glass layer. A method for providing this.

24. The method according to claim 23, further comprising the step of attaching an integrated circuit die to at least some of the conductive contacts.

25. The step of forming a cavity inside at least some of the glass core and / or glass layers; and The step of embedding an integrated circuit die in the cavity. The method according to claim 23, further comprising:

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