Semiconductor memory

Abstract

To provide a semiconductor memory device that can improve yield. [Solution] A semiconductor memory device according to one embodiment comprises a substrate, a laminate disposed above the substrate in a first direction, a first conductive layer disposed between the substrate and the laminate, a memory pillar including a semiconductor film, extending in the first direction and penetrating the first conductive layer, and a first member disposed spaced apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductive layer. The laminate has a structure in which a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from the substrate side. The first semiconductor layer covers the edge of the semiconductor film in the first direction and the edge of the first member in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatiley, a NAND-type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a semiconductor storage device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 3] A perspective view showing an overview of the bonding structure of a semiconductor memory device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 5] A plan view showing an example of a planar layout of a memory cell array in the memory area of ​​a semiconductor storage device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory cell array in the memory region of a semiconductor storage device according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar included in a semiconductor memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first embodiment. [Figure 9] Figure 8 shows an enlarged cross-sectional view of a portion of the region including the laminate. [Figure 10]Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 11] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 12] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 13] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 14] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 15] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 16] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 17] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 18] Cross-sectional view showing an example of a cross-sectional structure of a semiconductor memory device according to the second embodiment. [Figure 19] Cross-sectional view of a partially enlarged region including the laminate of FIG. 18. [Figure 20] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 21] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 22] Cross-sectional view showing an example of a cross-sectional structure of a semiconductor memory device according to the third embodiment. [Figure 23] Cross-sectional view of a partially enlarged region including the laminate of FIG. 22. [Figure 24] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the third embodiment. [Figure 25] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the third embodiment. [Figure 26] Cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to the third embodiment. [Figure 27] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first modification of the third embodiment. [Figure 28] Cross-sectional view of a partially enlarged region including the laminate of FIG. 27. [Figure 29] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the second modification of the third embodiment. [Figure 30] Cross-sectional view of a partially enlarged region including the laminate of FIG. 29. [Figure 31] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the fourth embodiment. [Figure 32] Cross-sectional view of a partially enlarged region including the laminate of FIG. 31. [Figure 33] Cross-sectional view for explaining an example of a manufacturing method of a semiconductor memory device according to the fourth embodiment. [Figure 34] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the fifth embodiment. [Figure 35] Cross-sectional view of a partially enlarged region including the laminate of FIG. 34. [Figure 36] Cross-sectional view for explaining an example of a manufacturing method of a semiconductor memory device according to the fifth embodiment. [Figure 37] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the sixth embodiment. [Figure 38] Cross-sectional view of a partially enlarged region including the laminate of FIG. 37. [Figure 39] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the seventh embodiment. [Figure 40] Cross-sectional view of a partially enlarged region including the laminate of FIG. 39. [Figure 41] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first modification of the seventh embodiment. [Figure 42] Cross-sectional view of a partially enlarged region including the laminate of FIG. 41. [Figure 43] Cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the second modification of the seventh embodiment. [Figure 44]Figure 43 shows an enlarged cross-sectional view of a portion of the area including the laminate. [Figure 45] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the eighth embodiment. [Figure 46] A magnified cross-sectional view of a portion of the area including the laminate shown in Figure 45. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. The dimensions and proportions in the drawings are not necessarily the same as those of reality. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. When elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Memory System Configuration The configuration of a memory system including a semiconductor memory device according to the first embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the configuration of a memory system. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM These are memory cards, UFS (universal flash storage), or SSDs (solid state drives). As shown in Figure 1, the memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0009] The memory controller 2 is an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from the host device. For example, the memory controller 2 writes data requested by the host device to the semiconductor memory device 3. The memory controller 2 also reads data requested by the host device from the semiconductor memory device 3 and transmits it to the host device.

[0010] The semiconductor memory device 3 is a memory that stores data non-volatilely. For example, the semiconductor memory device 3 is a NAND flash memory. In the following explanation, we will use a NAND flash memory as an example of the semiconductor memory device 3.

[0011] 1.1.2 Configuration of Semiconductor Memory Devices Next, with reference to Figure 1, the configuration of the semiconductor memory device 3 will be described. As shown in Figure 1, the semiconductor memory device 3 includes an array chip 100 and a circuit chip 200.

[0012] The array chip 100 includes, for example, a memory cell array 10.

[0013] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0014] The circuit chip 200 includes, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16. Hereinafter, the command register 11, address register 12, sequencer 13, driver module 14, row decoder module 15, and sense amplifier module 16 will be collectively referred to as "peripheral circuits."

[0015] The command register 11 is a circuit that stores the command CMD received by the semiconductor memory device 3 from the memory controller 2. The command CMD includes, for example, instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0016] The address register 12 is a circuit that stores the address ADD received by the semiconductor memory device 3 from the memory controller 2. The address ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. For example, the block address BAd, the page address PAAd, and the column address CAD are used for selecting the block BLK, the word line, and the bit line, respectively.

[0017] The sequencer 13 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11. For example, the sequencer 13 performs read operations, write operations, erase operations, etc.

[0018] The driver module 14 is a circuit that generates voltages used in read operations, write operations, erase operations, etc. For example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PAd stored in the address register 12.

[0019] The row decoder module 15 is a circuit that selects one block BLK in the corresponding memory cell array 10 based on the block address Bad stored in the address register 12. The row decoder module 15, for example, transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] The sense amplifier module 16 is a circuit that selects a bit line based on the column address CAd stored in the address register 12. For example, during a write operation, the sense amplifier module 16 applies a voltage based on the write data DAT received from the memory controller 2 to the selected bit line. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistor based on the voltage of the selected bit line. The sense amplifier module 16 transfers the determination result as read data DAT to the memory controller 2.

[0021] 1.1.3 Circuit configuration of memory cell array The circuit configuration of the memory cell array 10 will be explained using Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. In Figure 2, one of the multiple block BLKs included in the memory cell array 10 is shown. As shown in Figure 2, the block BLK includes, for example, five string units SU0 to SU4. The string unit SU is a collection of NAND strings NS, which will be described later. For example, in a write or read operation, the NAND strings NS within the string unit SU are selected collectively.

[0022] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer to hold data non-volatile. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0023] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0024] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU4 are connected to selection gate lines SGD0 to SGD4, respectively. The gate of selection transistor ST2 in string units SU0 to SU4 is connected to selection gate line SGS.

[0025] Each bit line BL0 to BLm is assigned a different column address CAd. Each bit line BL is shared among multiple block BLKs by a NAND string NS, which is assigned the same column address CAd. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple block BLKs.

[0026] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0027] The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT, and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0028] 1.1.4 Bonding structure of semiconductor memory devices The general structure of the semiconductor memory device 3 will be explained using Figure 3. Figure 3 is a perspective view showing the general structure of the semiconductor memory device 3.

[0029] As shown in Figure 3, the semiconductor memory device 3 has a structure in which an array chip 100 is bonded to a circuit chip 200. Each of the array chip 100 and the circuit chip 200 includes a plurality of bonding pads BP provided on opposite surfaces. In the bonding structure, the bonding pads BP of the array chip 100 and the bonding pads BP of the circuit chip 200 are bonded together to form a single bonding pad BP. In other words, the electrodes (conductors) constituting the bonding pad BP provided on the array chip 100 and the electrodes (conductors) constituting the bonding pad BP provided on the circuit chip 200 are bonded together to form a bonding pad BP.

[0030] In the following, the surface on which the array chip 100 and the circuit chip 200 are bonded (hereinafter referred to as the "bonding surface") will be the XY plane. The directions that are orthogonal to each other in the XY plane will be the X direction and the Y direction. The direction that is approximately perpendicular to the XY plane and moves from the array chip 100 towards the circuit chip 200 will be the Z1 direction. The direction that is approximately perpendicular to the XY plane and moves from the circuit chip 200 towards the array chip 100 will be the Z2 direction. If neither the Z1 direction nor the Z2 direction is specified, it will be referred to as the Z direction. Furthermore, in the array chip 100, the surface on the bonding surface side of a certain component will be called the "first surface," and the surface opposite the bonding surface of a certain component will be called the "second surface." In the circuit chip 200, the surface on the bonding surface side of a certain component will be called the "first surface," and the surface opposite the bonding surface of a certain component will be called the "second surface."

[0031] 1.1.5 Planar structure of memory cell array The planar structure of the memory cell array 10 will be explained using Figure 4. Figure 4 is a plan view showing an example of the planar layout of the memory cell array 10. In Figure 4, the regions corresponding to the four blocks BLK0 to BLK3 are shown.

[0032] The memory cell array 10 includes a stacked wiring structure and a plurality of components SLT and SHE. The stacked wiring structure includes selected gate lines SGD and SGS and a plurality of word lines WL. The stacked wiring structure is a structure stacked along the Z direction according to the number of stacks of selected gate lines SGD and SGS and the plurality of word lines WL. In the following description, the selected gate lines SGD and SGS and the plurality of word lines WL will be collectively referred to as "stacked wiring". The memory cell array 10 also includes, for example, a memory area MR and an extraction area HR arranged in the X direction. The memory area MR is the area where data is substantially stored. The memory area MR is also the area used to connect the bit line BL to the peripheral circuit. The extraction area HR is the area used to connect the stacked wiring to the peripheral circuit.

[0033] The stacked wiring structure is provided, for example, in the X direction, across the memory area MR and the lead-out area HR.

[0034] Each SLT extends in the X direction. Each SLT traverses the stacked wiring structure in the X direction across the memory area MR and the lead area HR. Each SLT has a structure, for example, with an insulator or plate-shaped conductor embedded inside. Each SLT separates adjacent stacked wiring through it. The area separated by multiple SLTs corresponds to one block BLK.

[0035] Each member SHE extends in the X direction. In this embodiment, a case is described in which four members SHE are provided between adjacent members SLT. Each member SHE traverses the stacked wiring structure in the X direction across the memory area MR. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE, for example, divides adjacent selection gate lines SGD through the member SHE. The area separated by multiple members SLT and SHE each corresponds to one string unit SU.

[0036] In the memory cell array 10, for example, the planar layout shown in Figure 4 is repeatedly arranged in the Y direction.

[0037] Note that the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of members SHE placed between adjacent members SLT can be designed to be any number depending on the number of string units SU.

[0038] 1.1.6 Structure of memory cell array in the memory area The structure of the memory cell array 10 in the memory region MR will be described.

[0039] 1.1.6.1 Planar structure of memory cell array in memory region First, the planar structure of the memory cell array 10 in the memory region MR will be explained using Figure 5. Figure 5 is a plan view showing an example of the planar layout of the memory cell array 10 in the memory region MR.

[0040] As shown in Figure 5, in the memory region MR, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each component SLT includes a conductor LI and a spacer SP.

[0041] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern of, for example, 24 rows in the region between two adjacent members SLT. For example, counting from the top of the paper, one member SHE is placed overlapping the 5th, 10th, 15th, and 20th memory pillar MPs, respectively.

[0042] Each of the multiple bit lines BL extends in the Y direction. Furthermore, the multiple bit lines BL are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example in Figure 5, each bit line BL is positioned to overlap with two memory pillar MPs for each string unit SU. One of the multiple bit lines BL overlapping with a memory pillar MP is electrically connected to that memory pillar MP via a contact CV. No contact is provided between the memory pillar MP overlapping with member SHE and the bit line BL. That is, the memory pillar MP overlapping with member SHE and the bit line BL are not electrically connected.

[0043] The conductor LI is a conductor extended in the X direction. The spacer SP is an insulator provided on the side surface of the conductor LI. The conductor LI is sandwiched between the spacer SP. The conductor LI and the laminated wiring adjacent to it in the Y direction are electrically isolated by the spacer SP. As a result, the conductor LI and the laminated wiring adjacent to it in the Y direction are electrically insulated from each other.

[0044] 1.1.6.2 Cross-sectional structure of memory cell array in the memory region Next, the cross-sectional structure of the memory cell array 10 in the memory region MR will be explained using Figure 6. Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of the memory cell array 10 in the memory region MR. In Figure 6, the upper side of the paper corresponds to the bonding surface.

[0045] As shown in Figure 6, the memory cell array 10 further includes a conductive layer 30, semiconductor layers 31a and 31b, conductive layers 32a, 32b, 33 and 35, multiple conductive layers 34, 36, 37 and 38, insulating layers 40, 41, 43 and 44, and multiple insulating layers 42. In Figure 6, five of the multiple memory pillar MPs are shown. Also in Figure 6, the case in which the multiple conductive layers 34 and multiple insulating layers 42 include eight conductive layers 34 and eight insulating layers 42.

[0046] The conductive layer 30 is provided, for example, in the shape of a plate extending along the XY plane. The conductive layer 30 is composed of a conductive material. This conductive material includes, for example, an N-type semiconductor with impurities added.

[0047] A semiconductor layer 31a is provided on the second surface of the conductive layer 30. The semiconductor layer 31a contains, for example, doped polysilicon with N-type impurities. As described later, the semiconductor layer 31a is deposited on the second surface of the conductive layer 30, the plurality of memory pillars MP, and the plurality of component SLTs. As a result, the second surface of the semiconductor layer 31a has irregularities corresponding to, for example, the plurality of memory pillars MP. That is, the second surface of the semiconductor layer 31a does not have to be flat.

[0048] A semiconductor layer 31b is provided on the second surface of semiconductor layer 31a. Semiconductor layer 31b includes, for example, doped polysilicon with N-type impurities. Semiconductor layer 31b is formed on the second surface of semiconductor layer 31a, as will be described later. As a result, the second surface of semiconductor layer 31b has irregularities, similar to the second surface of semiconductor layer 31a. That is, the second surface of semiconductor layer 31b does not have to be flat, similar to the second surface of semiconductor layer 31a.

[0049] A conductive layer 32a is provided on the second surface of the semiconductor layer 31b. The conductive layer 32a contains, for example, titanium or titanium nitride. The conductive layer 32a functions as a barrier metal for the conductive layer 32b. The conductive layer 32a is formed on the second surface of the semiconductor layer 31b, as will be described later. As a result, the second surface of the conductive layer 32a has irregularities, similar to the second surface of the semiconductor layer 31b. That is, the second surface of the conductive layer 32a does not have to be flat, similar to the second surface of the semiconductor layer 31b.

[0050] A conductive layer 32b is provided on the second surface of the conductive layer 32a. The conductive layer 32b contains, for example, tungsten. The conductive layer 32b is formed on the second surface of the conductive layer 32a, as will be described later. As a result, the second surface of the conductive layer 32b has irregularities, similar to the second surface of the conductive layer 32a. That is, the second surface of the conductive layer 32b does not have to be flat, similar to the second surface of the conductive layer 32a.

[0051] The conductive layer 30, semiconductor layers 31a and 31b, and conductive layers 32a and 32b, provided as described above, function as a source wire SL. The lamination of polysilicon (conductive layer 30, and semiconductor layers 31a and 31b) and metal (conductive layers 32a and 32b) can reduce the resistance of the source wire SL. Hereinafter, the laminated structure provided on the second surface of the conductive layer 30 will be referred to as the "laminated body SB". In this embodiment, the laminated body SB has a structure in which semiconductor layer 31a, semiconductor layer 31b, conductive layer 32a, and conductive layer 32b are laminated in order from the conductive layer 30 side.

[0052] An insulating layer 40 is provided on the first surface of the conductive layer 30. The insulating layer 40 contains, for example, silicon oxide. A conductive layer 33 is provided on the first surface of the insulating layer 40. The conductive layer 33 is provided in the shape of a plate extending along the XY plane, for example. The conductive layer 33 functions as a selectable gate line SGS. The conductive layer 33 contains, for example, tungsten.

[0053] An insulating layer 41 is provided on the first surface of the conductive layer 33. The insulating layer 41 contains, for example, silicon oxide. Eight conductive layers 34 and eight insulating layers 42 are stacked on the first surface of the insulating layer 41 in the order of conductive layer 34, insulating layer 42, ..., conductive layer 34, and insulating layer 42 in the Z1 direction. The conductive layer 34 is provided in the form of a plate extending along the XY plane, for example. The eight conductive layers 34 function as word lines WL0 to WL7 in order along the Z1 direction. The conductive layer 34 contains, for example, tungsten. The insulating layer 42 contains, for example, silicon oxide.

[0054] A conductive layer 35 is provided on the first surface of the uppermost insulating layer 42 in the Z1 direction among the eight insulating layers 42. The conductive layer 35 is provided, for example, in the shape of a plate extending along the XY plane. The conductive layer 35 functions as a selected gate line SGD. The conductive layer 35 is electrically insulated for each string unit SU by, for example, multiple members SHE. The conductive layer 35 contains, for example, tungsten.

[0055] An insulating layer 43 is provided on the first surface of the conductive layer 35. The insulating layer 43 contains, for example, silicon oxide. Multiple conductive layers 36 are provided on the first surface of the insulating layer 43. Each conductive layer 36 is provided extending along the Y direction. Figure 6 shows one of the multiple conductive layers 36. Each conductive layer 36 functions as a bit line BL. The multiple conductive layers 36 are electrically connected to multiple memory pillars MP via multiple conductive layers 37 and 38. The conductive layers 36 contain, for example, copper.

[0056] An insulating layer 44 is provided on the first surface of the conductive layer 36. The insulating layer 44 contains, for example, silicon oxide.

[0057] In the Z1 direction, multiple memory pillars MP are provided below the multiple conductive layers 36, extending along the Z direction. The first surface of each of the multiple memory pillars MP is located, for example, between conductive layer 35 and conductive layer 36. The multiple memory pillars MP penetrate conductive layers 30, 33 and 35, as well as the multiple conductive layers 34.

[0058] Each of the multiple memory pillars MP includes, for example, a core member 50, a semiconductor film 51, and a multilayer film 52. The core member 50 is provided stretched along the Z direction. The semiconductor film 51 covers the periphery of the core member 50. The ends of the semiconductor film 51 in the Z2 direction are in contact with the semiconductor layer 31a. The multilayer film 52 covers the sides of the semiconductor film 51, except for the portion where the semiconductor film 51 and the semiconductor layer 31a are in contact. The core member 50 includes an insulator such as silicon oxide. The semiconductor film 51 includes, for example, silicon. The configuration of the multilayer film 52 will be described later.

[0059] A conductive layer 37 is provided on the first surface of the semiconductor film 51. The conductive layer 37 functions, for example, as a columnar contact. The conductive layer 37 contains, for example, tungsten. A conductive layer 38 is provided on the first surface of the conductive layer 37. The conductive layer 38 functions, for example, as a contact CV. The conductive layer 38 contains, for example, tungsten. With the above configuration, the conductive layers 37 and 38 connect the semiconductor film 51 and the conductive layer 36. One conductive layer 36 is connected to one conductive layer 37 and one conductive layer 38 in each of the spaces separated by members SLT and SHE.

[0060] The component SLT divides, for example, the conductive layers 30, 33, and 35, and the plurality of conductive layers 34. In other words, the component SLT penetrates the conductive layers 30, 33, and 35, and the plurality of conductive layers 34. The conductor LI within the component SLT is provided along the component SLT. The first surface of the conductor LI is located, for example, between conductive layer 35 and conductive layer 36. The second surface of the conductor LI is in contact with semiconductor layer 31a. The conductor LI includes, for example, tungsten. Spacers SP are provided between the conductor LI and conductive layer 30, semiconductor layer 31a, conductive layers 33 and 35, and the plurality of conductive layers 34. In other words, the sides of the conductor LI are covered by spacers SP. The conductor LI is separated from and electrically insulated from conductive layers 33 and 35, and the plurality of conductive layers 34 by spacers SP. The spacer SP includes, for example, silicon oxide. Although not shown in Figure 6, the conductor LI may also include a barrier metal. That is, the conductor LI may have a structure in which the barrier metal covers the second surface and side surfaces of a conductive member containing, for example, a metal such as tungsten. Alternatively, the conductor LI may be formed from a semiconductor member, or the entire member SLT may have a structure in which it is embedded by the insulator of the spacer SP.

[0061] The portion where each of the multiple memory pillars MP intersects with the conductive layer 33 functions as a selection transistor ST2. The portion where each of the multiple memory pillars MP intersects with each of the multiple conductive layers 34 functions as a memory cell transistor MT. The portion where each of the multiple memory pillars MP intersects with the conductive layer 35 functions as a selection transistor ST1.

[0062] Although not shown in Figure 6, this embodiment describes a case in which the space between the memory pillar MP and each of the conductive layers 33, 34, and 35, the first and second surfaces of each of the conductive layers 33, 34, and 35, and the side surface of the spacer SP are covered by the insulator 46.

[0063] 1.1.6.3 Cross-sectional structure of the memory pillar The cross-sectional structure of the memory pillar MP will be explained using Figure 7. Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of the memory pillar MP.

[0064] As shown in Figure 7, the laminated film 52 includes, for example, a tunnel insulating film 53, an insulating film 54, and a block insulating film 55. The tunnel insulating film 53 covers the sides of the semiconductor film 51, except for the portion where the semiconductor film 51 and the semiconductor layer 31a are in contact. The insulating film 54 covers the sides of the tunnel insulating film 53. The block insulating film 55 covers the sides of the insulating film 54. The insulator 46 covers the sides of the block insulating film 55. The insulator 46 functions as a block insulating film of the memory cell transistor MT together with the block insulating film 55. The conductive layer 34 covers the sides of the insulator 46. The tunnel insulating film 53 and the block insulating film 55 include, for example, silicon oxide. The insulating film 54 includes, for example, silicon nitride. The insulator 46 includes, for example, aluminum oxide.

[0065] In the configuration described above, the semiconductor film 51 functions as a channel for each of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 54 has the function of accumulating an amount of charge corresponding to the data stored by the memory cell transistors MT. That is, the insulating film 54 functions as a charge storage layer for the memory cell transistors MT. The semiconductor memory device 3 turns on each of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2, thereby allowing current to flow between the source line SL and the bit line BL through the memory pillar MP and the conductive layers 37 and 38.

[0066] 1.1.7 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3 will be explained using Figure 8. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3. Figure 8 shows the cross-sectional structure of a part of the semiconductor memory device 3 (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0067] 1.1.7.1 Circuit Chips First, let's describe the cross-sectional structure of circuit chip 200.

[0068] As shown in Figure 8, the circuit chip 200 includes, for example, a semiconductor substrate 71, a plurality of conductive layers 201, 202, 203, 204, 205, and 206 that constitute part of the peripheral circuit, and insulating layers 45 and 61. The semiconductor substrate 71 is made of, for example, a P-type semiconductor with impurities added. The plurality of conductive layers 201 to 206 each function, for example, as columnar contacts or wiring. In Figure 8, one conductive layer 203 of the plurality of conductive layers 203, one conductive layer 204 of the plurality of conductive layers 204, one conductive layer 205 of the plurality of conductive layers 205, and one conductive layer 206 of the plurality of conductive layers 206 are shown.

[0069] An insulating layer 45 is provided on the first surface of the semiconductor substrate 71. The insulating layer 45 contains, for example, silicon oxide. Multiple conductive layers 201, 202, 203, 204, and 205 are provided within the insulating layer 45.

[0070] Peripheral circuits are provided on the first surface of the semiconductor substrate 71. In Figure 8, a transistor TR1 is shown as an example of a component included in the peripheral circuit. Transistor TR1 is included, for example, in the sense amplifier module 16. Transistor TR1 includes a gate insulating film, a gate electrode, and a source and drain (not shown) provided on the semiconductor substrate 71.

[0071] A conductive layer 201 is provided on the first surface of each of the gate electrode, source, and drain of the transistor TR1. A corresponding conductive layer 202 is provided on the first surface of each of the multiple conductive layers 201.

[0072] A corresponding conductive layer 203 is provided on the first surface of each of the multiple conductive layers 202.

[0073] A corresponding conductive layer 204 is provided on the first surface of each of the multiple conductive layers 203.

[0074] A corresponding conductive layer 205 is provided on the first surface of each of the multiple conductive layers 204. The first surface of each of the multiple conductive layers 205 is provided so as to be flush with the first surface of the insulating layer 45.

[0075] An insulating layer 61 is provided on the first surface of each of the insulating layer 45 and the plurality of conductive layers 205. The insulating layer 61 contains, for example, silicon oxide.

[0076] Multiple conductive layers 206 are provided on the same layer as the insulating layer 61. Each of the multiple conductive layers 206 is connected to the first surface of the corresponding conductive layer 205. The first surface of each of the multiple conductive layers 206 is provided to be flush with the first surface of the insulating layer 61. The conductive layers 206 include, for example, copper. The multiple conductive layers 206 function as multiple bonding pads BP for electrically connecting the circuit chip 200 and the array chip 100.

[0077] 1.1.7.2 Array Chip Next, the cross-sectional structure of the array chip 100 will be described.

[0078] As shown in Figure 8, the array chip 100 includes, for example, a plurality of conductive layers 101, 102, 103, and 104, and a memory cell array 10. Each of the plurality of conductive layers 101 to 104 functions, for example, as a columnar contact or wiring. In Figure 8, one conductive layer 101 of the plurality of conductive layers 101, one conductive layer 102 of the plurality of conductive layers 102, one conductive layer 103 of the plurality of conductive layers 103, and one conductive layer 104 of the plurality of conductive layers 104 are shown. The memory cell array 10 includes a conductive layer 30, a stacked body SB, conductive layers 33 and 35, a plurality of conductive layers 34, 36, 37, and 38, a plurality of memory pillars MP, and a plurality of components SLT and SHE. The conductive layer 30 is positioned between the conductive layers 33 and 35, the plurality of conductive layers 34, and the laminate SB, and is spaced apart from the conductive layers 33 and 35 and the plurality of conductive layers 34 in the Z2 direction, and is in contact with the semiconductor layer 31a.

[0079] In the array chip 100, an insulating layer 62 is provided on the first surface of the circuit chip 200. The insulating layer 62 contains, for example, silicon oxide.

[0080] Multiple conductive layers 101 are provided on the same layer as the insulating layer 62. Each of the multiple conductive layers 101 is connected to the first surface of the corresponding conductive layer 206. The second surface of each of the multiple conductive layers 101 is provided to be flush with the second surface of the insulating layer 62. The conductive layers 101 include, for example, copper. The multiple conductive layers 101 function as multiple bonding pads BP for electrically connecting the circuit chip 200 and the array chip 100. With this configuration, the circuit chip 200 and the array chip 100 are electrically connected by the multiple conductive layers 206 and 101.

[0081] An insulating layer 44 is provided on the second surface of each of the insulating layer 62 and the plurality of conductive layers 101. A plurality of conductive layers 102 to 104 are provided within the insulating layer 44.

[0082] A corresponding conductive layer 102 is provided on the second surface of each of the multiple conductive layers 101. A corresponding conductive layer 103 is provided on the second surface of each of the multiple conductive layers 102. A corresponding conductive layer 104 is provided on the second surface of each of the multiple conductive layers 103. The second surface of each of the multiple conductive layers 104 is connected to the conductive layer 36. With this configuration, the conductive layer 36 and the transistor TR1 are connected. That is, the bit line BL of the memory cell array 10 and the sense amplifier module 16 are electrically connected.

[0083] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 9 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 8.

[0084] As shown in Figure 9, the insulator 46 is provided between the block insulating film 55 and the conductive layer 33, between the block insulating film 55 and the conductive layer 34, and between the block insulating film 55 and the conductive layer 35 (not shown). The insulator 46 is provided on the first and second surfaces of the conductive layer 33, on the first and second surfaces of the conductive layer 34, and on the first and second surfaces of the conductive layer 35 (not shown). The insulator 46 covers the sides of the spacer SP, except for the parts where the spacer SP and the conductive layer 33 are in contact, the parts where the spacer SP and the conductive layer 34 are in contact, and the parts where the spacer SP and the conductive layer 35 are in contact (not shown). Hereinafter, the structure including the spacer SP that covers the sides of the conductor LI in the Y direction and the insulator 46 that covers the sides of the spacer SP in the Y direction will be referred to as "insulator SW". The insulator SW covers the sides of the conductor LI in the Y direction. Furthermore, a structure including a conductor LI and an insulator SW covering the sides of the conductor LI in the Y direction is also called a "component SLT".

[0085] The ends of the spacer SP and the insulator 46 are machined in the Z2 direction. More specifically, the corner of the end of the spacer SP in the Z2 direction that is not in contact with the conductor LI is machined. That is, the end face of the spacer SP in the Z2 direction has a sloped portion IPa on the side that is not in contact with the conductor LI. The end of the insulator 46 in the Z2 direction is machined down to the first surface of the conductor layer 30. That is, the end face of the insulator 46 in the Z2 direction has a sloped portion IPb along the sloped portion IPa. The sloped portion IPb reaches the first surface of the conductor layer 30. In other words, the end face EF of the insulator SW in the Z2 direction has a sloped portion IP on the side that is not in contact with the conductor LI. The sloped portion IP includes sloped portions IPa and sloped portions IPb. A recessed portion RP exists between the sloped portion IP and the conductor layer 30. The angle of the sloped portion IP with respect to the side surface of the conductor layer 30 is acute. The sloped portion IP is in contact with the semiconductor layer 31a. Furthermore, the inclined portion IP is in contact with the conductive layer 30 at a position below the upper surface of the conductive layer 30 in the Z2 direction.

[0086] In the Z2 direction, a semiconductor layer 31a is provided on each of the following: the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the block insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The semiconductor layer 31a covers the Z2 edges (end face and side surface of the edge) of the semiconductor film 51. The semiconductor layer 31a covers the Z2 edges of the member SLT (the Z2 edges of the conductor LI, the Z2 edges of the spacer SP, and the Z2 edges of the insulator 46). The recessed portion RP is filled by the semiconductor layer 31a.

[0087] The semiconductor layer 31a contains multiple grains (crystal grains). The solid lines within the semiconductor layer 31a in Figure 9 schematically represent grain boundaries GB. The area enclosed by two grain boundaries GB corresponds to a grain.

[0088] In the Z2 direction, a semiconductor layer 31b is provided on top of the semiconductor layer 31a. The semiconductor layer 31b contains multiple grains. The solid lines within the semiconductor layer 31b in Figure 9 schematically represent grain boundaries GB. The area enclosed by two grain boundaries GB corresponds to a grain.

[0089] As shown in Figure 9, the grain boundaries GB of semiconductor layer 31a and semiconductor layer 31b are not connected. In other words, the grain boundaries GB of semiconductor layer 31a and semiconductor layer 31b are discontinuous. Furthermore, the grain size of semiconductor layer 31a is different from that of semiconductor layer 31b. For example, the grain size of semiconductor layer 31a is smaller than that of semiconductor layer 31b. The grain sizes of semiconductor layers 31a and 31b vary depending on, for example, the film deposition method for semiconductor layers 31a and 31b, the amount of impurities injected into semiconductor layers 31a and 31b, the type of impurities injected into semiconductor layers 31a and 31b, and the film thickness of semiconductor layers 31a and 31b. For example, the larger the film thickness, the larger the grain size of semiconductor layers 31a and 31b.

[0090] An oxide film may be provided between the semiconductor layer 31a and the semiconductor layer 31b.

[0091] In the Z2 direction, a conductive layer 32a is provided on the semiconductor layer 31b. In the Z2 direction, a conductive layer 32b is provided on the conductive layer 32a.

[0092] 1.2 Method for Manufacturing Semiconductor Memory Devices The manufacturing method of the semiconductor memory device 3 will be explained using Figures 10 to 17. Figures 10 to 17 are cross-sectional views illustrating an example of the manufacturing method of the semiconductor memory device 3. Figures 10 to 13 show cross-sectional views of the region corresponding to Figure 8. Figures 14 to 17 show cross-sectional views of the region corresponding to Figure 9.

[0093] First, as shown in Figure 10, a transistor TR1 included in the peripheral circuit, a plurality of conductive layers 201 to 206, and insulating layers 45 and 61 are formed on the first surface of the semiconductor substrate 71. In other words, a circuit chip 200 is formed.

[0094] Next, as shown in Figure 11, an insulating layer 47, a semiconductor layer 31, conductive layers 30, 33, and 35, multiple conductive layers 34, 36, 37, 38, and 101-104, insulating layers 40, 41, 43, 44, and 62, multiple insulating layers 42, multiple memory pillars MP, and multiple components SLT and SHE are formed on the first surface of a semiconductor substrate 72 made of impurity-doped P-type semiconductor. In other words, a structure corresponding to an array chip 100 is formed. The semiconductor layer 31 includes, for example, doped polysilicon with N-type impurities. The semiconductor layer 31, as well as the insulating layers 47 and 62, are formed entirely on the first surface of the semiconductor substrate 72.

[0095] Next, as shown in Figure 12, the circuit chip 200 and the structures corresponding to the array chip 100 are bonded together by a bonding process. More specifically, a plurality of conductive layers 206 that function as bonding pads BP in the circuit chip 200 and a plurality of conductive layers 101 that function as bonding pads BP in the array chip 100 are arranged to face each other. The opposing bonding pads BP are then bonded together by heat treatment. After that, the semiconductor substrate 72 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0096] Next, as shown in Figure 13, the insulating layer 47 and semiconductor layer 31 are removed in the portion corresponding to the memory cell array 10. This exposes the Z2 edges of each of the multiple memory pillars MP and component SLT. In the regions other than the portion corresponding to the memory cell array 10, a resist mask is formed, so the insulating layer 47 and semiconductor layer 31 remain and are not removed.

[0097] Next, as shown in Figure 14, the laminated film 52 is removed. The laminated film 52 is removed in the following order, for example, block insulating film 55, insulating film 54, and tunnel insulating film 53.

[0098] First, the block insulating film 55 is removed. For example, the block insulating film 55 is processed by isotropic etching using buffered hydrofluoric acid (BHF) wet etching. This removes the block insulating film 55 above the second surface of the conductive layer 30 at the Z2 direction end of the memory pillar MP. At this time, the Z2 direction ends of the spacer SP and the insulator 46 are also slightly removed.

[0099] Next, the insulating film 54 is removed. For example, the insulating film 54 is processed by isotropic etching using wet etching with phosphoric acid. This removes the insulating film 54 above the second surface of the conductive layer 30 at the end of the memory pillar MP in the Z2 direction.

[0100] Next, the tunnel insulating film 53 is removed. For example, the tunnel insulating film 53 is processed by isotropic etching using CDE (Chemical Dry Etching). This removes the tunnel insulating film 53 above the second surface of the conductive layer 30 at the Z2 edge of the memory pillar MP. At this time, the Z2 edges of the spacer SP and the insulator 46 are also slightly removed.

[0101] The removal of the block insulating film 55, the insulating film 54, and the tunnel insulating film 53 exposes the Z2 edge of the semiconductor film 51 of the memory pillar MP. That is, the channel is exposed. As a result, the second surface of the memory pillar MP has a step. Also, as described above, the Z2 edges of the spacer SP and the insulator 46 are slightly removed. Because the member SLT has a structure in which the side surface of the conductor LI is covered by the spacer SP and the insulator 46, the corner of the Z2 edge of the spacer SP that is not in contact with the conductor LI is beveled, and the Z2 edge of the insulator 46 is beveled along the portion of the spacer SP that has been removed.

[0102] After removing the laminated film 52, isotropic etching is performed by wet etching using diluted hydrofluoric acid (DHF) to eliminate the resistance at the interface of the conductive layer 30. This removes the native oxide film on the second surface of the conductive layer 30. At this time, as shown in Figure 15, the ends of the spacer SP and insulator 46 in the Z2 direction are also shaved off. Since the member SLT has a structure in which the side surface of the conductive LI is covered by the spacer SP and insulator 46, an inclined portion IPa is formed on the side of the end face of the spacer SP in the Z2 direction that is not in contact with the conductive LI. An inclined portion IPb is formed on the end face of the insulator 46 in the Z2 direction, along with the inclined portion IPa. The inclined portion IPb reaches the first surface of the conductive layer 30. In other words, an inclined portion IP is formed on the side of the end face EF of the insulator SW in the Z2 direction that is not in contact with the conductive LI. As a result, a recessed portion RP is formed between the inclined portion IP and the conductive layer 30. The angle of the inclined portion IP with respect to the side surface of the conductive layer 30 becomes acute. In other words, the recessed area RP is sharply angled.

[0103] Next, as shown in Figure 16, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is deposited by LP-CVD (Low Pressure Chemical Vapor Deposition) or PE-CVD (Plasma Enhanced Chemical Vapor Deposition). For example, amorphous silicon is deposited as the semiconductor layer 31a. As a result, the semiconductor layer 31a is deposited on the second surface of each of the conductive layer 30, the multiple memory pillars MP, and the multiple component SLTs. More specifically, in the Z2 direction, the semiconductor layer 31a is deposited on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the block insulating film 55, the conductor LI, the spacer SP, and the insulator 46. By using LP-CVD or PE-CVD, which have relatively high coverage, the sharply recessed portions RP are also filled in by the semiconductor layer 31a.

[0104] Next, as shown in Figure 17, a semiconductor layer 31b is formed. For example, the semiconductor layer 31b is deposited by PVD (Physical Vapor Deposition). For example, amorphous silicon is deposited as the semiconductor layer 31b. As a result, the semiconductor layer 31b is deposited on the second surface of the semiconductor layer 31a. Note that the semiconductor layer 31b may be deposited by a deposition method other than PVD. For example, the semiconductor layer 31b may be deposited by LP-CVD or PE-CVD.

[0105] Next, impurities are introduced into the semiconductor layers 31a and 31b, for example, by ion implantation. The impurities include, for example, phosphorus.

[0106] Next, the semiconductor layers 31a and 31b are subjected to heat treatment, for example, by laser annealing. A laser with a relatively long wavelength is used to instantaneously raise the temperature and activate the impurities. This causes the impurities to diffuse into the semiconductor layers 31a and 31b. In addition, the grains in the deposited semiconductor layers 31a and 31b (amorphous silicon) move and grow due to the heat, and are eventually crystallized and modified into polysilicon.

[0107] If the deposition methods for semiconductor layers 31a and 31b are different, the way amorphous silicon grains grow will differ. Furthermore, if the amount of impurities implanted in semiconductor layers 31a and 31b, the type of impurities implanted, or the film thickness of semiconductor layers 31a and 31b differs, the way amorphous silicon grains grow will also differ. As a result, the grain boundaries between semiconductor layer 31a and semiconductor layer 31b become discontinuous. Also, the grain size of semiconductor layer 31a and semiconductor layer 31b will differ. For example, the larger the film thickness, the larger the grain size of semiconductor layers 31a and 31b. If the film thickness of semiconductor layer 31b is increased compared to semiconductor layer 31a, the grain size of semiconductor layer 31a will be smaller than that of semiconductor layer 31b.

[0108] After heat treatment, for example, isotropic etching is performed by wet etching using DHF to eliminate the resistance at the interface of the semiconductor layer 31b. This removes the native oxide film on the second surface of the semiconductor layer 31b.

[0109] Next, a conductive layer 32a is formed. For example, the conductive layer 32a is deposited by PVD. For example, titanium or titanium nitride is deposited as the conductive layer 32a. As a result, the conductive layer 32a is deposited on the second surface of the semiconductor layer 31b.

[0110] Next, the conductive layer 32b is formed. For example, the conductive layer 32b is deposited by PVD. For example, tungsten is deposited as the conductive layer 32b. As a result, the conductive layer 32b is deposited on the second surface of the conductive layer 32a, and the structure shown in Figure 9 is formed.

[0111] The semiconductor memory device 3 is formed by the manufacturing process described above. However, the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing step, or some steps may be omitted or integrated. A step of forming an oxide film between semiconductor layer 31a and semiconductor layer 31b may be inserted between the step of forming semiconductor layer 31a and the step of forming semiconductor layer 31b. Furthermore, each manufacturing step may be rearranged to the extent possible.

[0112] 1.3 Effects according to this embodiment In a structure where a source wire SL having a laminate of polysilicon, barrier metal, and metal is formed on the uppermost conductive layer after the array chip 100 and circuit chip 200 are bonded together, the laminated film 52 and native oxide film of the memory pillar MP on the conductive layer are removed before the amorphous silicon is deposited. At this time, a part of the insulator SW of the component SLT may be scraped away, potentially forming a sharply angled recess between the component SLT and the conductive layer. If such a recess is formed, when the amorphous silicon is deposited, there may be parts in the recess that are not filled with amorphous silicon. If there are parts in the recess that are not filled, when the native oxide film is removed before the barrier metal and metal are deposited, the etching solution may enter the parts in the recess that are not filled with amorphous silicon by wet etching, potentially dissolving the insulator SW of the component SLT. If there is a melted portion of the insulator SW, when the metal film is deposited, the metal film will be deposited on the melted portion of the insulator SW, potentially causing a short circuit between the source wire SL and the selector gate wire SGS.

[0113] In contrast, in this embodiment, two semiconductor layers are deposited as semiconductor layers covering the semiconductor film 51 (channel) and the component SLT. For example, semiconductor layers 31a and 31b are deposited. Because two semiconductor layers are deposited, the coating performance on sharply recessed portions RP is improved compared to the case where only one semiconductor layer is deposited. As a result, the recessed portions RP are filled by semiconductor layer 31a (amorphous silicon). This makes it possible to suppress the dissolution of the insulator SW by wet etching in the process of removing the native oxide film before depositing the barrier metal and metal, compared to the case where only one semiconductor layer is deposited. As a result, the occurrence of short circuits between the source line SL and the selected gate line SGS can be suppressed. Consequently, the yield can be improved. Note that three or more semiconductor layers may be deposited as semiconductor layers covering the semiconductor film 51, and the same effect can be obtained when three or more semiconductor layers are deposited.

[0114] In this embodiment, for example, the semiconductor layer 31a is formed using LP-CVD or PE-CVD. Because LP-CVD or PE-CVD have relatively high coverage properties, the coverage of sharply recessed portions RP is improved compared to when the semiconductor layer 31a is formed by a deposition method other than LP-CVD or PE-CVD. As a result, the recessed portions RP are filled by the semiconductor layer 31a (amorphous silicon). Therefore, the yield can be improved.

[0115] Furthermore, if the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are connected, when the native oxide film is removed before the formation of the barrier metal and metal films, wet etching may cause the etching solution to travel along the grain boundaries and reach the insulator SW, potentially creating holes in the insulator SW and forming pinholes.

[0116] In contrast, in this embodiment, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are discontinuous. For example, semiconductor layer 31a is deposited using LP-CVD or PE-CVD. Semiconductor layer 31b is deposited using PVD. That is, the deposition methods for semiconductor layers 31a and 31b are different. Because the grain growth differs depending on the deposition method, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b become discontinuous. Also, the grain size of semiconductor layer 31a and semiconductor layer 31b are different in size. Therefore, compared to the case where the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are connected, the formation of pinholes in the insulator SW can be suppressed in the process of removing the native oxide film before deposition of the barrier metal and metal. Consequently, the yield can be improved. Furthermore, the way grains grow differs depending on the amount of impurities implanted in semiconductor layers 31a and 31b, the type of impurities implanted in semiconductor layers 31a and 31b, and the film thickness of semiconductor layers 31a and 31b. Therefore, similar effects can be obtained even when the amount of impurities, the type of impurities, and the film thickness of semiconductor layers 31a and 31b differ.

[0117] 2. Second Embodiment A semiconductor memory device according to the second embodiment will now be described. In the semiconductor memory device 3A according to this embodiment, the structure of the stacked body SB differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0118] 2.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3A will be explained using Figure 18. Figure 18 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3A. Figure 18 shows the cross-sectional structure of a part of the semiconductor memory device 3A (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0119] As shown in Figure 18, the memory cell array 10 further includes an insulating layer 48 in addition to the configuration shown in Figure 8 in the first embodiment. More specifically, the laminate SB has a structure in which an insulating layer 48 is further provided between the semiconductor layer 31a and the semiconductor layer 31b. The cross-sectional structure other than that of the laminate SB is the same as that shown in Figure 8 in the first embodiment.

[0120] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 19 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 18.

[0121] As shown in Figure 19, in the Z2 direction, an insulating layer 48 is provided on the semiconductor layer 31a. The insulating layer 48 includes, for example, silicon oxide or silicon nitride. That is, the insulating layer 48 is, for example, an oxide film or a nitride film. In the Z2 direction, a semiconductor layer 31b is provided on the insulating layer 48.

[0122] As shown in Figure 19, the grain boundaries GB of semiconductor layer 31a and semiconductor layer 31b are separated by the insulating layer 48. As a result, the grain boundaries GB of semiconductor layer 31a and semiconductor layer 31b are not connected. In other words, the grain boundaries GB of semiconductor layer 31a and semiconductor layer 31b are discontinuous. Furthermore, the grain size of semiconductor layer 31a and semiconductor layer 31b are different. For example, the grain size of semiconductor layer 31a is smaller than the grain size of semiconductor layer 31b.

[0123] 2.2 Method for Manufacturing Semiconductor Memory Devices The manufacturing method of the semiconductor memory device 3A will be explained using Figures 20 and 21. Figures 20 and 21 are cross-sectional views illustrating an example of the manufacturing method of the semiconductor memory device 3A. Figures 20 and 21 show cross-sectional views of the region corresponding to Figure 19.

[0124] First, in the same manner as in the first embodiment, the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52.

[0125] Next, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is deposited by PVD. For example, amorphous silicon is deposited as the semiconductor layer 31a. As a result, in the Z2 direction, the semiconductor layer 31a is deposited on each of the conductive layer 30, semiconductor film 51, tunnel insulating film 53, insulating film 54, block insulating film 55, conductor LI, spacer SP, and insulator 46. Note that the semiconductor layer 31a may be deposited by a deposition method other than PVD. For example, the semiconductor layer 31a may be deposited by LP-CVD or PE-CVD.

[0126] Next, the semiconductor layer 31a is subjected to heat treatment, for example, by laser annealing. This causes the grains of the semiconductor layer 31a (amorphous silicon) to move, and the recessed portion RP is filled by the semiconductor layer 31a.

[0127] Next, as shown in Figure 20, an insulating layer 48 is formed on the semiconductor layer 31a in the Z2 direction. For example, the insulating layer 48 is formed when the structure with the semiconductor layer 31a is exposed to the atmosphere in a clean room. The thickness of the insulating layer 48 is, for example, about 1 nm.

[0128] Furthermore, the insulating layer 48 may be formed by radical oxidation in plasma rather than by a native oxide film. Alternatively, the insulating layer 48 may be formed by radical nitridation in plasma.

[0129] Next, as shown in Figure 21, the semiconductor layer 31b is deposited, for example, by PVD. For example, amorphous silicon is deposited as the semiconductor layer 31b. As a result, the semiconductor layer 31b is deposited on the insulating layer 48 in the Z2 direction. Note that the semiconductor layer 31b may be deposited by a deposition method other than PVD. For example, the semiconductor layer 31b may be deposited by LP-CVD or PE-CVD.

[0130] Subsequently, the following steps are carried out in the same manner as in the first embodiment: introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31b, formation of the conductive layer 32a, and formation of the conductive layer 32b. In the heat treatment step, for example, heat treatment is performed by laser annealing, and the grains of the deposited semiconductor layers 31a and 31b (amorphous silicon) move and grow due to the heat. Since there is an insulating layer 48 between the semiconductor layer 31a and the semiconductor layer 31b, the growth of amorphous silicon grains stops at the insulating layer 48. For this reason, the grain size of the semiconductor layer 31a and the grain size of the semiconductor layer 31b are of different sizes.

[0131] 2.3 Effects according to this embodiment In this embodiment, for example, amorphous silicon is deposited as a semiconductor layer 31a using PVD, and then heat treatment is performed by laser annealing. The grains of the amorphous silicon move and grow due to the heat. As a result, the grains of the semiconductor layer 31a (amorphous silicon) move, and the recessed portion RP is filled by the amorphous silicon. This makes it possible to suppress the dissolution of the insulator SW by wet etching in the process of removing the native oxide film before depositing the barrier metal and metal, similar to the first embodiment. Therefore, the yield can be improved.

[0132] Furthermore, in this embodiment, for example, an insulating layer 48 is provided between semiconductor layer 31a and semiconductor layer 31b. As a result, semiconductor layer 31a and semiconductor layer 31b are separated by the insulating layer 48. That is, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b become discontinuous. Also, the growth of grains in semiconductor layers 31a and 31b (amorphous silicon) stops at the insulating layer 48. Therefore, the grain size of semiconductor layer 31a and semiconductor layer 31b become different sizes. As a result, similar to the first embodiment, the formation of pinholes in the insulator SW can be suppressed in the process of removing the native oxide film before the deposition of the barrier metal and metal. Consequently, the yield can be improved.

[0133] 3. Third Embodiment A semiconductor memory device according to the third embodiment will now be described. In the semiconductor memory device 3B according to this embodiment, the structure of the stacked body SB differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0134] 3.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3B will be explained using Figure 22. Figure 22 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3B. Figure 22 shows the cross-sectional structure of a part of the semiconductor memory device 3B (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0135] As shown in Figure 22, the memory cell array 10 has the semiconductor layer 31b removed from the configuration shown in Figure 8 in the first embodiment. More specifically, the laminate SB has a structure in which the semiconductor layer 31a, the conductive layer 32a, and the conductive layer 32b are stacked in that order from the semiconductor substrate 71 side. The cross-sectional structure other than that of the laminate SB is the same as that shown in Figure 8 in the first embodiment.

[0136] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 23 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 22.

[0137] As shown in Figure 23, the ends of the spacer SP and insulator 46 are machined in the Z2 direction. More specifically, the spacer SP and insulator 46 are machined down to a position below the top surface of the conductor LI in the Z2 direction and the top surface of the conductive layer 30 in the Z2 direction. That is, the end faces of the spacer SP and insulator 46 in the Z2 direction are located below the top surface of the conductor LI in the Z2 direction and the top surface of the conductive layer 30 in the Z2 direction. The end face of the insulator 46 in the Z2 direction reaches the first surface of the conductive layer 30. In other words, the end face EF of the insulator SW in the Z2 direction is located below the top surface of the conductor LI in the Z2 direction and the top surface of the conductive layer 30 in the Z2 direction. A recess RP exists between the end face EF of the insulator SW in the Z2 direction and the conductive layer 30. The angle of the end face EF of the insulator SW in the Z2 direction with respect to the side surface of the conductive layer 30 is a relatively large angle (close to 90 degrees). The side surface of the end of the conductor LI in the Z2 direction, and the end face EF of the insulator SW in the Z2 direction, are in contact with the semiconductor layer 31a.

[0138] In the Z2 direction, a semiconductor layer 31a is provided on each of the following: the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the block insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The semiconductor layer 31a contains, for example, doped polysilicon with N-type impurities. The semiconductor layer 31a covers the edges (end face and side surfaces) of the semiconductor film 51 in the Z2 direction. The semiconductor layer 31a also covers the edges (end face and side surfaces) of the conductor LI in the Z2 direction. The recessed portion RP is filled by the semiconductor layer 31a.

[0139] In the Z2 direction, a conductive layer 32a is provided on the semiconductor layer 31a. The conductive layer 32a contains, for example, titanium or titanium nitride. In the Z2 direction, a conductive layer 32b is provided on the conductive layer 32a. The conductive layer 32b contains, for example, tungsten.

[0140] 3.2 Method for Manufacturing Semiconductor Memory Devices The manufacturing method of the semiconductor memory device 3B will be explained using Figures 24 to 26. Figures 24 to 26 are cross-sectional views illustrating an example of the manufacturing method of the semiconductor memory device 3B. Figures 24 to 26 show cross-sectional views of the region corresponding to Figure 23.

[0141] First, in the same manner as in the first embodiment, the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52.

[0142] Next, as shown in Figure 24, an insulating layer 49 is formed. For example, the insulating layer 49 is deposited by PVD. For example, the insulating layer 49 is deposited to a thickness of more than half the height of the recess RP. For example, silicon oxide is deposited as the insulating layer 49. As a result, in the Z2 direction, the insulating layer 49 is deposited on each of the conductive layer 30, semiconductor film 51, tunnel insulating film 53, insulating film 54, block insulating film 55, conductor LI, spacer SP, and insulator 46.

[0143] Next, as shown in Figure 25, isotropic etching is performed by wet etching using, for example, DHF. The etching rate is set relatively high. This removes the insulating layer 49 and erodes the edges of the spacer SP and insulator 46 in the Z2 direction. Because the etching rate is relatively high, the edges of the spacer SP and insulator 46 in the Z2 direction are eroded overall. For example, the edges of the spacer SP and insulator 46 in the Z2 direction are eroded to a position below the top surface of the conductor LI in the Z2 direction and the top surface of the conductive layer 30 in the Z2 direction. The end face of the insulator 46 in the Z2 direction reaches the first surface of the conductive layer 30. In other words, the position of the end face EF of the insulator SW in the Z2 direction is below the top surface of the conductor LI in the Z2 direction and the top surface of the conductive layer 30 in the Z2 direction. A recess RP is formed between the end face EF of the insulator SW in the Z2 direction and the conductive layer 30. The angle between the end face EF of the insulator SW in the Z2 direction and the side surface of the conductive layer 30 is a relatively large angle. In other words, the recessed portion RP is recessed at a relatively large angle.

[0144] Next, as shown in Figure 26, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is deposited by PVD. For example, amorphous silicon is deposited as the semiconductor layer 31a. As a result, the semiconductor layer 31a is deposited on the second surface of each of the conductive layer 30, the multiple memory pillars MP, and the multiple members SLT. More specifically, in the Z2 direction, the semiconductor layer 31a is deposited on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the block insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The recessed portion RP, which is indented at a relatively large angle, is filled by the semiconductor layer 31a. Note that the semiconductor layer 31a may be deposited by a film deposition method other than PVD. For example, the semiconductor layer 31a may be deposited by LP-CVD or PE-CVD.

[0145] Subsequently, the following steps are carried out in the same manner as in the first embodiment: introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b.

[0146] 3.3 Effects according to this embodiment In this embodiment, after the laminated film 52 and native oxide film of the memory pillar MP on the conductive layer 30 are removed, an insulating layer 49 is formed. As a result, the sharply recessed portion RP is filled by the insulating layer 49. Next, etching is performed at a relatively high etching rate. As a result, the insulating SW is completely removed, and a recessed portion RP with a relatively large angle is formed between the insulating SW and the conductive layer 30. Therefore, the coating performance on the recessed portion RP is improved compared to the case where a semiconductor layer 31a (amorphous silicon) is formed on the sharply recessed portion RP. As a result, the recessed portion RP is filled by amorphous silicon. As a result, as in the first embodiment, the dissolution of the insulating SW by wet etching can be suppressed in the process of removing the native oxide film before the formation of the barrier metal and metal. Therefore, the yield can be improved.

[0147] 3.4 First Variation Next, we will describe a semiconductor memory device according to the first modification of the third embodiment. In the semiconductor memory device 3Ba according to this modification, the structure of the stacked body SB differs from that of the third embodiment. The following will focus on the differences from the third embodiment.

[0148] 3.4.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3Ba will be explained using Figure 27. Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Ba. Figure 27 shows the cross-sectional structure of a part of the semiconductor memory device 3Ba (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0149] As shown in Figure 27, the memory cell array 10 further includes a semiconductor layer 31b in addition to the configuration shown in Figure 22 in the third embodiment. More specifically, the laminate SB has a structure in which a semiconductor layer 31b is further provided between the semiconductor layer 31a and the conductive layer 32a. The cross-sectional structure other than that of the laminate SB is the same as that shown in Figure 22 in the third embodiment.

[0150] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 28 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 27.

[0151] As shown in Figure 28, in the Z2 direction, a semiconductor layer 31b is provided on top of the semiconductor layer 31a. The semiconductor layer 31b contains, for example, doped polysilicon with N-type impurities. In the Z2 direction, a conductive layer 32a is provided on top of the semiconductor layer 31b.

[0152] 3.4.2 Method for Manufacturing Semiconductor Memory Devices In the method for manufacturing the semiconductor memory device 3Ba, for example, the semiconductor layer 31b formation step shown in the first embodiment is inserted between the semiconductor layer 31a formation step and the conductive layer 32a formation step in the manufacturing method shown in the third embodiment.

[0153] 3.4.3 Effects of this modified example This modified version provides the same effects as the third embodiment. Furthermore, it provides the same effects as the first embodiment.

[0154] 3.5 Second Variation Next, we will describe a semiconductor memory device according to a second modification of the third embodiment. In the semiconductor memory device 3Bb according to this modification, the structure of the stacked body SB differs from that of the first modification of the third embodiment. The following will focus on the differences from the first modification of the third embodiment.

[0155] 3.5.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3Bb will be explained using Figure 29. Figure 29 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Bb. Figure 29 shows the cross-sectional structure of a part of the semiconductor memory device 3Bb (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0156] As shown in Figure 29, the memory cell array 10 further includes an insulating layer 48 in addition to the configuration shown in Figure 27 in the first modification of the third embodiment. More specifically, the laminate SB has a structure in which an insulating layer 48 is further provided between the semiconductor layer 31a and the semiconductor layer 31b. The cross-sectional structure other than that of the laminate SB is the same as that shown in Figure 27 in the first modification of the third embodiment.

[0157] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 30 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 29.

[0158] As shown in Figure 30, in the Z2 direction, an insulating layer 48 is provided on the semiconductor layer 31b. The insulating layer 48 includes, for example, silicon oxide or silicon nitride. In the Z2 direction, a conductive layer 32a is provided on the insulating layer 48.

[0159] 3.5.2 Method for Manufacturing Semiconductor Memory Devices In the method for manufacturing the semiconductor memory device 3Bb, for example, the process of forming the insulating layer 48 shown in the second embodiment is inserted between the process of forming the semiconductor layer 31a and the process of forming the semiconductor layer 31b in the manufacturing method shown in the first modified example of the third embodiment.

[0160] 3.5.3 Effects of this modified example This modified version achieves the same effects as the third embodiment. Furthermore, it achieves the same effects as the second embodiment.

[0161] 4. Fourth Embodiment A semiconductor memory device according to the fourth embodiment will now be described. In the semiconductor memory device 3C according to this embodiment, the structure of the stacked body SB differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0162] 4.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3C will be explained using Figure 31. Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3C. Figure 31 shows the cross-sectional structure of a part of the semiconductor memory device 3C (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0163] As shown in Figure 31, the memory cell array 10 has the semiconductor layers 31a and 31b removed from the configuration shown in Figure 8 in the first embodiment. The laminated body SB has a structure in which conductive layers 32a and 32b are stacked in order from the semiconductor substrate 71 side. The cross-sectional structure other than that of the laminated body SB is the same as that shown in Figure 8 in the first embodiment.

[0164] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 32 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 31.

[0165] As shown in Figure 32, the ends of the spacer SP and the insulator 46 are machined in the Z2 direction. More specifically, the corner of the end of the spacer SP in the Z2 direction that is not in contact with the conductor LI is machined. That is, the end face of the spacer SP in the Z2 direction has a sloped portion IPa on the side that is not in contact with the conductor LI. The end of the insulator 46 in the Z2 direction is machined down to the first surface of the conductor layer 30. That is, the end face of the insulator 46 in the Z2 direction has a sloped portion IPb along the sloped portion IPb. The sloped portion IPb reaches the first surface of the conductor layer 30. In other words, the end face EF of the insulator SW in the Z2 direction has a sloped portion IP on the side that is not in contact with the conductor LI. The sloped portion IP includes sloped portions IPa and IPb. A recessed portion RP exists between the sloped portion IP and the conductor layer 30. The angle of the sloped portion IP with respect to the side surface of the conductor layer 30 is acute. The sloped portion IP is in contact with the conductor layer 32a. Furthermore, the inclined portion IP is in contact with the conductive layer 30 at a position below the upper surface of the conductive layer 30 in the Z2 direction.

[0166] In the Z2 direction, a conductive layer 32a is provided on each of the conductive layer 30, semiconductor film 51, tunnel insulating film 53, insulating film 54, block insulating film 55, conductor LI, spacer SP, and insulator 46. The conductive layer 32a contains, for example, titanium or titanium nitride. The conductive layer 32a covers the Z2 edges (end face and side surface of the edge) of the semiconductor film 51. The conductive layer 32a covers the Z2 edges of the member SLT (end face of conductor LI in the Z2 direction, end face of spacer SP in the Z2 direction, and end face of insulator 46 in the Z2 direction). The recessed portion RP is filled by the conductive layer 32a. In the Z2 direction, a conductive layer 32b is provided on top of the conductive layer 32a. The conductive layer 32b contains, for example, tungsten.

[0167] 4.2 Method for Manufacturing Semiconductor Memory Devices The manufacturing method of the semiconductor memory device 3C will be explained using Figure 33. Figure 33 is a cross-sectional view illustrating an example of the manufacturing method of the semiconductor memory device 3C. Figure 33 shows a cross-sectional view of the region corresponding to Figure 32.

[0168] First, in the same manner as in the first embodiment, the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52.

[0169] Next, as shown in Figure 33, a conductive layer 32a is formed. For example, the conductive layer 32a is deposited by PVD. For example, titanium or titanium nitride is deposited as the conductive layer 32a. As a result, in the Z2 direction, the conductive layer 32a is deposited on each of the conductive layer 30, semiconductor film 51, tunnel insulating film 53, insulating film 54, block insulating film 55, conductor LI, spacer SP, and insulator 46. By depositing a material with relatively high coverage as the conductive layer 32a, the sharply recessed portion RP is also filled by the conductive layer 32a. Note that the conductive layer 32a may be deposited by a film deposition method other than PVD. For example, the conductive layer 32a may be deposited by LP-CVD or PE-CVD.

[0170] Next, a conductive layer 32b is formed. For example, the conductive layer 32b is deposited by PVD. For example, tungsten is deposited as the conductive layer 32b. As a result, in the Z2 direction, the conductive layer 32b is deposited on the conductive layer 32a, forming the structure shown in Figure 32. Note that the conductive layer 32b may be deposited by a deposition method other than PVD. For example, the conductive layer 32b may be deposited by LP-CVD or PE-CVD.

[0171] 4.3 Effects according to this embodiment In this embodiment, two conductive layers are formed as a laminate SB covering the semiconductor film 51 and the component SLT. For example, conductive layers 32a and 32b are formed. For conductive layer 32a, for example, titanium or titanium nitride is formed. Since these materials have relatively high coverage properties, the coverage of sharply recessed portions RP is improved compared to when a material with relatively low coverage properties is formed. As a result, the recessed portions RP are filled by the conductive layer 32a. This makes it possible to suppress the dissolution of the insulator SW by wet etching in the process of removing the native oxide film before the formation of the barrier metal and metal, similar to the first embodiment. Therefore, the yield can be improved.

[0172] Furthermore, in this embodiment, since the laminated SB does not include a semiconductor layer, it is not necessary to consider the movement of grains in the semiconductor layer (amorphous silicon) due to heat treatment.

[0173] 5. Fifth Embodiment A semiconductor memory device according to the fifth embodiment will now be described. In the semiconductor memory device 3D according to this embodiment, the structure of the stacked body SB and the insulator SW differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0174] 5.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3D will be explained using Figure 34. Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3D. Figure 34 shows the cross-sectional structure of a part of the semiconductor memory device 3D (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0175] As shown in Figure 34, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, in the Z2 direction, the end face of the conductor LI is not in contact with the semiconductor layer 31a. In the Z2 direction, the end face of the spacer SP is in contact with the semiconductor layer 31a. The cross-sectional structure of the laminate SB and the insulator SW, which will be described later, is the same as that shown in Figure 8 in the first embodiment.

[0176] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 35 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 34.

[0177] As shown in Figure 35, the cross-sectional structures of the laminate SB and the insulator SW are the same as those shown in Figure 9 in the first embodiment, except that the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structures of the semiconductor layer 31a, semiconductor layer 31b, conductive layer 32a, conductive layer 32b, and insulator 46 are the same as those shown in Figure 9 in the first embodiment.

[0178] 5.2 Method for Manufacturing Semiconductor Memory Devices A method for manufacturing a semiconductor memory device 3D will be explained using Figure 36. Figure 36 is a cross-sectional view illustrating an example of a semiconductor memory device 3D manufacturing method. Figure 36 shows a cross-sectional view of the region corresponding to Figure 35.

[0179] In forming the component SLT, the process is carried out in the same manner as in the first embodiment, except that not only the sides of the conductive material LI but also the bottom surface of the conductive material LI is covered with spacer SP, up to the step of removing the laminated film 52. This forms the structure shown in Figure 36.

[0180] Subsequently, the following steps are carried out in the same manner as in the first embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the semiconductor layer 31a, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31b, formation of the conductive layer 32a, and formation of the conductive layer 32b. This results in the structure shown in Figure 35.

[0181] 5.3 Effects of this embodiment This embodiment provides the same effects as the first embodiment.

[0182] 6. Sixth Embodiment A semiconductor memory device according to the sixth embodiment will now be described. In the semiconductor memory device 3E according to this embodiment, the structure of the stacked body SB and the insulator SW differs from that of the second embodiment. The following description will focus on the differences from the second embodiment.

[0183] 6.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3E will be explained using Figure 37. Figure 37 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3E. Figure 37 shows the cross-sectional structure of a part of the semiconductor memory device 3E (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0184] As shown in Figure 37, similar to the fifth embodiment, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. The cross-sectional structure of the laminate SB and the insulator SW, which will be described later, is the same as that shown in Figure 18 in the second embodiment.

[0185] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 38 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 37.

[0186] As shown in Figure 38, the cross-sectional structures of the laminate SB and the insulator SW are the same as those shown in Figure 19 in the second embodiment, except that the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structures of the semiconductor layer 31a, the insulator layer 48, the semiconductor layer 31b, the conductor layer 32a, the conductor layer 32b, and the insulator 46 are the same as those shown in Figure 19 in the second embodiment.

[0187] 6.2 Method for Manufacturing Semiconductor Memory Devices A method for manufacturing the semiconductor memory device 3E will be described.

[0188] First, the member SLT is formed in the same manner as in the fifth embodiment, and the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52. As a result, the structure shown in Figure 36 is formed, similar to the fifth embodiment.

[0189] Subsequently, the following steps are carried out in the same manner as in the second embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the semiconductor layer 31a, heat treatment, formation of the insulating layer 48, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31b, formation of the conductive layer 32a, and formation of the conductive layer 32b. This results in the structure shown in Figure 38.

[0190] 6.3 Effects according to this embodiment This embodiment provides the same effects as the second embodiment.

[0191] 7. Seventh Embodiment A semiconductor memory device according to the seventh embodiment will now be described. In the semiconductor memory device 3F according to this embodiment, the structure of the stacked body SB differs from that of the third embodiment. The following description will focus on the differences from the third embodiment.

[0192] 7.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3F will be explained using Figure 39. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3F. Figure 39 shows the cross-sectional structure of a part of the semiconductor memory device 3F (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0193] As shown in Figure 39, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP when the member SLT described later is formed, so the end face of the conductor LI in the Z2 direction is located below the end faces of the core member 50 and the semiconductor film 51 in the Z2 direction. The cross-sectional structure other than the laminate SB is the same as that shown in Figure 22 in the third embodiment.

[0194] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 40 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 39.

[0195] As shown in Figure 40, the cross-sectional structure of the laminate SB is the same as that shown in Figure 23 of the third embodiment, except that in the Z2 direction, the end face of the conductor LI is located below the end faces of the core member 50 and the semiconductor film 51. That is, the cross-sectional structures of the semiconductor layer 31a, the conductor layer 32a, and the conductor layer 32b are the same as those shown in Figure 23 of the third embodiment.

[0196] 7.2 Method for Manufacturing Semiconductor Memory Devices The manufacturing method for semiconductor memory device 3F will be described.

[0197] First, the member SLT is formed in the same manner as in the fifth embodiment, and the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52. As a result, the structure shown in Figure 36 is formed, similar to the fifth embodiment.

[0198] Subsequently, the following steps are carried out in the same manner as in the third embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. This results in the structure shown in Figure 40.

[0199] 7.3 Effects according to this embodiment This embodiment provides the same effects as the third embodiment.

[0200] 7.4 First Variation Next, we will describe a semiconductor memory device according to the first modification of the seventh embodiment. In the semiconductor memory device 3Fa according to this modification, the structure of the stacked body SB differs from that of the first modification of the third embodiment. The following will focus on the differences from the first modification of the third embodiment.

[0201] 7.4.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3Fa will be explained using Figure 41. Figure 41 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Fa. Figure 41 shows the cross-sectional structure of a part of the semiconductor memory device 3Fa (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0202] As shown in Figure 41, in the laminate SB, the end face of the conductor LI in the Z2 direction is located below the end faces of the core member 50 and the semiconductor film 51 in the Z2 direction. The cross-sectional structure other than the laminate SB is the same as that shown in Figure 27 in the first modified example of the third embodiment.

[0203] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 42 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB in Figure 41.

[0204] As shown in Figure 42, the cross-sectional structure of the laminate SB is the same as that shown in Figure 28 in the first modification of the third embodiment, except that in the Z2 direction, the end face of the conductor LI is located below the end faces of the core member 50 and the semiconductor film 51. That is, the cross-sectional structures of the semiconductor layer 31a, semiconductor layer 31b, conductor layer 32a, and conductor layer 32b are the same as those shown in Figure 28 in the first modification of the third embodiment.

[0205] 7.4.2 Method for manufacturing semiconductor memory devices A method for manufacturing the semiconductor memory device 3Fa will be described.

[0206] First, the member SLT is formed in the same manner as in the fifth embodiment, and the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52. As a result, the structure shown in Figure 36 is formed, similar to the fifth embodiment.

[0207] Subsequently, the following steps are carried out in the same manner as in the first modified example of the third embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. As a result, the structure shown in Figure 42 is formed.

[0208] 7.4.3 Effects of this modified example This modified version achieves the same effects as the first modified version of the third embodiment.

[0209] 7.5 Second Variation Next, we will describe a semiconductor memory device according to a second modification of the seventh embodiment. In the semiconductor memory device 3Fb according to this modification, the structure of the stacked body SB differs from that of the second modification of the third embodiment. The following will focus on the differences from the second modification of the third embodiment.

[0210] 7.5.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3Fb will be explained using Figure 43. Figure 43 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Fb. Figure 43 shows the cross-sectional structure of a part of the semiconductor memory device 3Fb (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0211] As shown in Figure 43, in the laminate SB, the end face of the conductor LI in the Z2 direction is located below the end faces of the core member 50 and the semiconductor film 51 in the Z2 direction. The cross-sectional structure other than that of the laminate SB is the same as that shown in Figure 29 in the second modification of the third embodiment.

[0212] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 44 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 43.

[0213] As shown in Figure 44, the cross-sectional structure of the laminate SB is the same as that shown in Figure 30 in the second modification of the third embodiment, except that in the Z2 direction, the end face of the conductor LI is located below the end faces of the core member 50 and the semiconductor film 51. That is, the cross-sectional structures of the semiconductor layer 31a, the insulator layer 48, the semiconductor layer 31b, the conductor layer 32a, and the conductor layer 32b are the same as those shown in Figure 30 in the second modification of the third embodiment.

[0214] 7.5.2 Method for manufacturing semiconductor memory devices This document describes the manufacturing method for the semiconductor memory device 3Fb.

[0215] First, the member SLT is formed in the same manner as in the fifth embodiment, and the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52. As a result, the structure shown in Figure 36 is formed, similar to the fifth embodiment.

[0216] Subsequently, the following steps are carried out in the same manner as in the second modified example of the third embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, heat treatment, formation of the insulating layer 48, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. As a result, the structure shown in Figure 44 is formed.

[0217] 7.5.3 Effects of this modified example This modified example achieves the same effects as the second modified example of the third embodiment.

[0218] 8. Eighth Embodiment A semiconductor memory device according to the eighth embodiment will now be described. In the semiconductor memory device 3G according to this embodiment, the structure of the stacked body SB and the insulator SW differs from that of the fourth embodiment. The following description will focus on the differences from the fourth embodiment.

[0219] 8.1 Overall Cross-sectional Structure of Semiconductor Memory Devices The overall cross-sectional structure of the semiconductor memory device 3G will be explained using Figure 45. Figure 45 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3G. Figure 45 shows the cross-sectional structure of a part of the semiconductor memory device 3G (the area corresponding to the memory area MR of the array chip 100 and the memory area MR of the circuit chip 200).

[0220] As shown in Figure 45, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. The cross-sectional structure of the laminate SB and the insulator SW, which will be described later, is the same as that shown in Figure 31 in the fourth embodiment.

[0221] Next, we will describe the details of the cross-sectional structure of the laminate SB and the area near the laminate SB. Figure 46 is an enlarged cross-sectional view of a portion of the region (region R1) including the laminate SB shown in Figure 45.

[0222] As shown in Figure 46, the cross-sectional structures of the laminate SB and the insulator SW are the same as those shown in Figure 32 in the fourth embodiment, except that the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structures of the conductor layer 32a, the conductor layer 32b, and the insulator 46 are the same as those shown in Figure 32 in the fourth embodiment.

[0223] 8.2 Method for Manufacturing Semiconductor Memory Devices This document describes a method for manufacturing a 3G semiconductor memory device.

[0224] First, the member SLT is formed in the same manner as in the fifth embodiment, and the process is carried out up to the step of removing the native oxide film on the second surface of the conductive layer 30 after the removal of the laminated film 52. As a result, the structure shown in Figure 36 is formed, similar to the fifth embodiment.

[0225] Subsequently, the steps of removing the native oxide film on the second surface of the conductive layer 30, forming the conductive layer 32a, and forming the conductive layer 32b are carried out in the same manner as in the fourth embodiment. This results in the structure shown in Figure 46.

[0226] 8.3 Effects according to this embodiment This embodiment provides the same effects as the fourth embodiment.

[0227] 9. Variations, etc. As described above, the semiconductor memory device (3) according to the embodiment includes a substrate (71), a laminate (SB) disposed above the substrate in a first direction (Z2), a first conductive layer (33 / 34 / 35) disposed between the substrate and the laminate, a memory pillar (MP) including a semiconductor film (51) that is stretched in the first direction and penetrates the first conductive layer, and a first member (SLT) that is spaced apart from the memory pillar in a second direction (Y) intersecting the first direction, stretches in the first direction, and penetrates the first conductive layer. The laminate (SB) has a structure in which a first semiconductor layer (31a), a second semiconductor layer (31b), a second conductive layer (32a), and a third conductive layer (32b) are stacked in order from the substrate (71) side. The first semiconductor layer (31a) covers the edge of the semiconductor film (51) in the first direction (Z2) and the edge of the first member (SLT) in the first direction.

[0228] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0229] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0230] 1...Memory system, 2...Memory controller, 3, 3A, 3B, 3Ba, 3Bb, 3C, 3D, 3E, 3F, 3Fa, 3Fb, 3G...Semiconductor memory device, 10...Memory cell array, 11...Command register, 12...Address register, 13...Programmable logic controller, 14...Driver module, 15...Raw decoder module, 16...Sense amplifier module, 30...Conductive layer, 31, 31a, 31b...Semiconductor layer, 32a, 32b...Conductive layer, 33~3 8...Conductive layer, 40-45...Insulator layer, 46...Insulator, 47, 48...Insulator layer, 50...Core component, 51...Semiconductor film, 52...Laminated film, 53...Tunnel insulating film, 54...Insulating film, 55...Block insulating film, 61, 62...Insulating layer, 71, 72...Semiconductor substrate, 100...Array chip, 101-104...Conductive layer, 200...Circuit chip, 201-206...Conductive layer, MP...Memory pillar, LI...Conductor, SP...Spacer, SB...Laminate, GB...Grain boundary

Claims

1. circuit board and A laminate disposed above the substrate in the first direction, A first conductive layer disposed between the substrate and the laminate, A memory pillar comprising a semiconductor film, stretched in the first direction and penetrating the first conductive layer, A first member is positioned spaced apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer. Equipped with, The laminate has a structure in which a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from the substrate side. The first semiconductor layer covers the edges of the semiconductor film in the first direction and the edges of the first member in the first direction. Semiconductor memory device.

2. The grain boundaries of the first semiconductor layer and the grain boundaries of the second semiconductor layer are discontinuous. The semiconductor memory device according to claim 1.

3. The grain size of the first semiconductor layer is different from the grain size of the second semiconductor layer. The semiconductor memory device according to claim 2.

4. The grain size of the first semiconductor layer is smaller than the grain size of the second semiconductor layer. The semiconductor memory device according to claim 3.

5. The laminate has a structure in which an insulating layer is further provided between the first semiconductor layer and the second semiconductor layer. The semiconductor memory device according to claim 2.

6. The insulating layer is an oxide film or a nitride film. The semiconductor memory device according to claim 5.

7. A fourth conductive layer is disposed between the first conductive layer and the laminate, spaced apart from the first conductive layer in the first direction, and in contact with the first semiconductor layer. Furthermore, The first member includes a conductor, a side surface of the conductor in the second direction, and a first insulator covering the end face of the conductor in the first direction. The end face of the first insulator in the first direction has an inclined portion on the side not in contact with the conductor, The inclined portion is in contact with the first semiconductor layer and is in contact with the fourth conductive layer at a position below the upper surface of the fourth conductive layer in the first direction. The semiconductor memory device according to claim 1.

8. The first insulator includes a second insulator that covers the side surface of the conductor in the second direction and the end face of the conductor in the first direction, and a third insulator that covers the side surface of the second insulator in the second direction. The semiconductor memory device according to claim 7.

9. The first semiconductor layer and the second semiconductor layer include polysilicon. The semiconductor memory device according to claim 1.

10. A first chip including the aforementioned substrate, A second chip comprising the laminate, the first conductive layer, the memory pillar, and the first member. Furthermore, The second chip has a structure in which it is bonded to the first chip. The semiconductor memory device according to claim 1.

11. The aforementioned semiconductor memory device is a NAND flash memory. The semiconductor memory device according to claim 1.

12. circuit board and A laminate disposed above the substrate in the first direction, A first conductive layer disposed between the substrate and the laminate, A memory pillar comprising a semiconductor film, stretched in the first direction and penetrating the first conductive layer, A first member is positioned spaced apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer. Equipped with, The laminate has a structure in which a first semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from the substrate side. The first member includes a conductor and a first insulator covering the side surface of the conductor in the second direction. The first semiconductor layer covers the edges of the semiconductor film in the first direction and the edges of the conductor in the first direction. Semiconductor memory device.

13. A fourth conductive layer is disposed between the first conductive layer and the laminate, spaced apart from the first conductive layer in the first direction, and in contact with the first semiconductor layer. Furthermore, The end face of the first insulator in the first direction is located below the upper surface of the conductor in the first direction and the upper surface of the fourth conductive layer in the first direction. The side surface of the end of the conductor in the first direction and the end face of the first insulator in the first direction are in contact with the first semiconductor layer. The semiconductor memory device according to claim 12.

14. The laminate has a structure in which a second semiconductor layer is further provided between the first semiconductor layer and the second conductive layer. The semiconductor memory device according to claim 13.

15. The laminate has a structure in which an insulating layer is further provided between the first semiconductor layer and the second semiconductor layer. The semiconductor memory device according to claim 14.

16. The first semiconductor layer includes polysilicon, The semiconductor memory device according to claim 12.

17. circuit board and A laminate disposed above the substrate in the first direction, A first conductive layer disposed between the substrate and the laminate, A memory pillar comprising a semiconductor film, stretched in the first direction and penetrating the first conductive layer, A first member is positioned spaced apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer. Equipped with, The laminate has a structure in which a second conductive layer and a third conductive layer are stacked in order from the substrate side. The second conductive layer covers the end of the semiconductor film in the first direction and the end of the first member in the first direction. Semiconductor memory device.

18. A fourth conductive layer is disposed between the first conductive layer and the laminate, spaced apart from the first conductive layer in the first direction, and in contact with the second conductive layer. Furthermore, The first member includes a conductor, a side surface of the conductor in the second direction, and a first insulator covering the end face of the conductor in the first direction. The end face of the first insulator in the first direction has an inclined portion on the side not in contact with the conductor, The inclined portion is in contact with the second conductive layer and is in contact with the fourth conductive layer at a position below the upper surface of the fourth conductive layer in the first direction. The semiconductor memory device according to claim 17.

19. The first insulator includes a second insulator that covers the side surface of the conductor in the second direction and the end face of the conductor in the first direction, and a third insulator that covers the side surface of the second insulator in the second direction. The semiconductor memory device according to claim 18.

20. The second conductive layer comprises titanium or titanium nitride. The third conductive layer contains tungsten, The semiconductor memory device according to claim 17.

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