Core substrates, wiring substrates, and methods for manufacturing them.

Abstract

This technology provides a way to minimize the impact of cracks occurring in a glass core substrate on the entire wiring board, including the core substrate. [Solution] The core substrate of the present disclosure is a glass core substrate having a plurality of through holes and a plurality of through conductors filled therein, wherein the plurality of through holes include a pair of through holes with an interaxial distance of 300 μm or less between adjacent through holes, and a plurality of cracks are formed between the pair of through holes, extending from one through hole toward the other through hole.

Description

Technical Field

[0001] The present disclosure relates to a glass core substrate, a wiring substrate including the same, and methods for manufacturing them.

Background Art

[0002] In recent years, for miniaturization and high integration of wiring substrates, technologies using a glass plate as a core substrate have been provided (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0041] , FIG. 1)

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above-described glass core substrate, points where cracks can occur are different from those in a resin core substrate. In the present application, a technique for suppressing the influence of cracks generated in a glass core substrate on the entire wiring substrate including the core substrate is provided.

Means for Solving the Problems

[0005] One aspect of the invention is a glass core substrate having a plurality of through holes and a plurality of through conductors filled therein, wherein the plurality of through holes include a pair of through holes having an axial distance between adjacent through holes of 300 μm or less, and a plurality of cracks extending from one through hole toward the other through hole are formed between the pair of through holes.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a side cross-sectional view of a wiring substrate according to the first embodiment [Figure 2] FIG. 2 is a plan cross-sectional view of the wiring substrate [Figure 3] Figure 3A is a side cross-sectional view of a densely populated region of through-holes in the core substrate, and Figure 3B is a side cross-sectional view of a sparsely populated region of through-holes in the core substrate. [Figure 4] Figure 4A is a side cross-sectional view of a glass plate with a modified section formed on it, Figure 4B is a side cross-sectional view of a glass plate with a through hole formed on it, Figure 4C is a side cross-sectional view of a glass plate with a metal oxide film formed on it, and Figure 4D is a side cross-sectional view of a glass plate with an electroless plating film formed on it. [Figure 5] Figure 5A is a side cross-sectional view of a glass plate filled with through-hole conductors, Figure 5B is a side cross-sectional view of a core substrate, and Figure 5C is a side cross-sectional view of a core substrate with an insulating layer and a conductive layer laminated on it. [Modes for carrying out the invention]

[0007] [First Embodiment] A wiring board 10 according to one embodiment of the present disclosure will be described with reference to Figures 1 to 5. As shown in Figure 1, the wiring board 10 is a multilayer wiring board in which build-up sections 12 are laminated on both the front and back surfaces of a core substrate 11. The build-up sections 12 include alternately laminated insulating layers 13 and conductive layers 14, and a solder resist layer 15 laminated on the outermost conductive layer 14. The solder resist layer 15 has openings 15H formed therein that correspond to pads 16 included in the outermost conductive layer 14. In addition, adjacent conductive layers 14 separated by the insulating layer 13 are connected by via conductors 17.

[0008] The core substrate 11 is formed by laminating conductive layers 20 on both the front and back surfaces of a glass plate 11K. The glass plate 11K is made from a glass material such as quartz glass, borosilicate glass, aluminosilicate glass, or soda-lime glass, formed into a plate with a thickness of, for example, 800 μm. The conductive layer 20 has a structure in which a metal oxide film 20A, an electroless copper plating film 20B, and an electrolytic copper plating film 20C are layered in that order. In addition, adjacent conductive layers 20 and conductive layers 14 separated by an insulating layer 13 are connected by via conductors 17.

[0009] Multiple through-holes 21 are formed in the glass plate 11K. The through-holes 21 have a shape where the tops of tapered holes are joined together, and their diameter decreases from one side to the other of the glass plate 11K, with the smallest diameter at the center in the thickness direction. The diameter of the opening of the through-holes 21 is, for example, 50 μm to 100 μm, and the diameter of the most tapered part is, for example, 35 μm to 85 μm.

[0010] Then, a through-hole conductor 22 is formed inside the through-hole 21. The through-hole conductor 22 is formed integrally with the conductive layer 20 described above. Specifically, a plating 23, which is integral with the electrolytic copper plating film 20C, is filled inside the metal oxide film 20A and the electroless copper plating film 20B formed along the inner wall of the through-hole 21. These multiple through-hole conductors 22 connect the conductive layers 20 on the front and back sides of the glass plate 11K.

[0011] Figure 2 is a cross-sectional view of AA in Figure 1. As shown therein, the core substrate 11 is provided with a first region R1 in which the multiple through holes 21 described above are densely arranged, and a second region R2 in which the multiple through holes 21 are more sparsely arranged compared to the first region R1. In the first region R1, the interaxial distance L1 between adjacent through holes 21 is 300 μm or less, and in the second region R2, the interaxial distance L2 between adjacent through holes 21 is greater than 300 μm. Specifically, the interaxial distance L1 is, for example, 150 μm to 300 μm, and the interaxial distance L2 is, for example, 350 μm to 500 μm.

[0012] In this embodiment, the interaxial distance between multiple through holes 21 arranged in the first region R1 was 300 μm or less, and the interaxial distance between multiple through holes 21 arranged in the second region R2 was greater than 300 μm. However, this is not limited to this configuration, and adjacent pairs of through holes 21 may be arranged with a mix of those with an interaxial distance of 300 μm or less and those with an interaxial distance greater than 300 μm.

[0013] Multiple cracks 24 are formed between the multiple through holes 21 located in the first region R1 and the second region R2. These multiple cracks 24 are, for example, strip-shaped and extend from one pair of adjacent through holes 21 toward the other. In this embodiment, the direction in which the multiple cracks 24 extend is limited to only one direction (the horizontal direction in Figure 2) among the vertical and horizontal directions in which the multiple through holes 21 are aligned in the first region R1 and the second region R2. Furthermore, none of the cracks 24 are designed to allow the plating solution used in the plating process described later to pass through.

[0014] The size and distribution of the multiple cracks 24 differ between the first region R1 and the second region R2. Specifically, the average width W1 of the multiple cracks 24 in the first region R1 (see Figure 3A; Figure 3A is a cross-sectional view of AA in Figure 2) is 2 to 7 μm, while the average width W2 of the multiple cracks 24 in the second region R2 (see Figure 3B; Figure 3B is a cross-sectional view of BB in Figure 2) is 1 to 5 μm. Thus, the width of the multiple cracks 24 in the first region R1 is wider than that of the multiple cracks 24 in the second region R2. Furthermore, the multiple cracks 24 are irregularly distributed in both the first region R1 and the second region R2, and the distribution density is higher in the first region R1 than in the second region R2. In the following explanation, when distinguishing between crack 24 in the first region R1 and crack 24 in the second region R2, the former will be referred to as "first crack 24" and the latter as "second crack 24".

[0015] In this embodiment, the crack 24 is a band of constant width, but it may gradually narrow or widen as it extends. Furthermore, although the multiple cracks 24 in this embodiment extend in one direction (the horizontal direction in Figure 2), they may also extend in the vertical direction or diagonally. In addition, these multidirectional cracks 24 may be mixed together.

[0016] In addition, although the crack 24 shown in FIGS. 1 and 2 does not connect a pair of adjacent through holes 21, it may connect a pair of adjacent through holes 21. Further, the crack 24 that does not connect adjacent through holes 21 and the crack 24 that connects them may be mixed, or only one of them may be provided.

[0017] The description of the core substrate 11 and the wiring substrate 10 of this embodiment is as above. Hereinafter, the manufacturing method of the core substrate 11 will be described in detail using FIGS. 4 to 5. (1) A glass plate 11K is prepared, and a pulsed laser is irradiated from the plate thickness direction at a predetermined position. As a result, a plurality of modified portions 26 are formed on the glass plate 11K (see FIG. 4A). In this embodiment, a pulsed laser is used, but a near-infrared laser or the like may also be used.

[0018] (2) The glass plate 11K on which the modified portions 26 are formed is subjected to hydrofluoric acid etching to form through holes 21 (see FIG. 4B). The modified portions 26 may be removed by wet etching using hydrofluoric acid as in this embodiment, or the modified portions 26 may be removed by dry etching such as sputter etching or reactive ion etching. In the case of anisotropic etching such as the latter, the diameter of the through hole 21 is substantially constant in the axial direction.

[0019] (3) Next, a metal oxide film 20A is formed on both the front and back surfaces of the glass plate 11K and the inner wall of the through hole 21 by a known method (see FIG. 4C). For the metal oxide film 20A, for example, a tin oxide film, a zinc oxide film, or the like is used.

[0020] (4) Next, electroless plating treatment is performed on the metal oxide film 20A to form an electroless copper plating film 20B (see FIG. 4D).

[0021] (5) Next, using the electroless copper plating film 20B as a seed layer, an electrolytic copper plating film 20C is formed, and the through hole 21 is filled with field plating 23. Then, annealing treatment is performed at 110°C to 150°C. Thereby, the through-hole conductor 22 is obtained (see FIG. 5A).

[0022] In this step (5), due to the shrinkage difference between the glass plate 11K and the electrolytic copper plating film 20C, among the plurality of through holes 21, a plurality of cracks 24 are formed between at least some adjacent pairs of through holes 21. Among the plurality of cracks 24, those arranged in the first region R1 are the relatively wide first cracks 24A, and those arranged in the second region R2 are the second cracks 24B that are narrower than those arranged in the first region R1. These cracks 24 release the stress generated inside the glass plate 11K.

[0023] Note that the crack 24 may be formed in step (5), or may be formed, for example, in the step of forming the modified portion 26 by pulsed laser in step (1).

[0024] (6) Next, an etching resist is formed on the electrolytic plating film 20C on the glass plate 11K, and etching treatment is performed to remove unnecessary portions of the conductor pattern (see FIG. 5B). Thereby, the conductive layer 20 directly above the glass plate 11K is obtained, and the core substrate 11 is completed.

[0025] (7) Next, an insulating resin film is overlaid on the conductive layer 20 and heat-pressed at 180°C to 220°C to form the insulating layer 13. Then, a laser is irradiated at a predetermined position on the insulating layer 13 to form a via hole 17H. After the inside of the via hole 17H is subjected to desmear treatment, electroless plating treatment, plating resist formation, and electrolytic plating treatment are sequentially performed to form the conductive layer 14 and fill the inside of the via hole 17H with the via conductor 17 (see FIG. ५C).

[0026] (8) Next, step (7) is repeated so that multiple insulating layers 13 and multiple conductive layers 14 are alternately stacked, and then a solder resist layer 15 is stacked on the outermost conductive layer 14. Then, an opening 15H is formed at a predetermined position in the solder resist layer 15 by a known method, and the pad 16 is exposed through the opening 15H (see Figure 1). This gives the wiring board 10 of this embodiment.

[0027] Incidentally, in a wiring board 10 using a glass plate 11K as the core substrate 11, there is concern that cracks 24 occurring in the core substrate 11 will affect the entire wiring board 10, including the core substrate 11. Specifically, in the process of forming the build-up section 12, as the insulating layer 13 and the conductive layer 14 are laminated on the core substrate 11, the stress accumulated inside the glass plate 11K also increases. Then, when this stress is suddenly released after the build-up section 12 is formed, parts other than the glass plate 11K, such as the build-up section 12, will be affected by the stress.

[0028] In contrast, in the present invention, by forming cracks 24 in advance to release stress during the stage of forming the conductive layer 20 of the core substrate 11, the stress accumulated inside the glass plate 11K during the stage of forming the build-up portion 12 can be suppressed compared to the conventional method. As a result, even if the stress accumulated in the glass plate 11K is released after the build-up portion 12 is formed, it is possible to reduce the influence that stress has on the wiring board 10. [Other embodiments]

[0029] In the above embodiment, the conductive layer 20 in the form of a glass plate 11K was formed by a subtractive method, but is not limited to this. For example, the metal oxide film 20A, electroless plating film 20B, and electrolytic plating film 20C deposited on both the front and back surfaces of the glass plate 11K are removed by polishing, and then the conductive layer 20 is formed by a known semi-additive method or the like.

[0030] Furthermore, as in the above embodiment, multiple through holes 21 in a row may be arranged in a matrix, or the through holes 21 may be arranged alternately at positions half the pitch of adjacent through holes 21, in a so-called staggered arrangement.

[0031] While this specification and drawings disclose specific examples of the technology included in the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and changes to these examples, as well as parts of the examples taken individually. [Explanation of Symbols]

[0032] 10 Wiring board 11 Core board 11K glass plate 12. Build-up section 13 Insulating layer 14. Conductive layer 16 pads 20 Conductive layer 21 Through hole 26 Modification section R1 First Domain R2 Second Domain

Claims

1. In a glass core substrate having multiple through holes and multiple through conductors filling them, The plurality of through holes include a pair of through holes in which the distance between adjacent through holes is 300 μm or less. Between the pair of through holes, multiple cracks are formed, extending from one through hole toward the other.

2. In the core substrate according to claim 1, The aforementioned multiple cracks do not connect the pairs of through holes.

3. In the core substrate according to claim 1, The maximum width of the crack is 1 to 5 μm.

4. In the core substrate according to claim 1, The inner diameter of the pair of through holes is 50 to 100 μm.

5. In the core substrate according to claim 1, The aforementioned plurality of through holes include another pair of through holes with an interaxial distance of 350 μm to 500 μm between adjacent through holes. Between the other pair of through holes, multiple cracks are formed, extending from one through hole toward the other through hole. The average width of the cracks formed between the other pair of through holes is smaller than the average width of the cracks formed between the pair of through holes.

6. A method for manufacturing a core substrate according to any one of claims 1 to 5, A process in which a laser is irradiated onto a glass plate from the thickness direction to form a modified area, The process involves etching the modified portion to form the through-hole, The process includes forming the through conductor inside the through hole, In the process of forming the through conductor, the glass plate is heated to 110°C or higher, and the crack is formed.

7. A wiring board comprising a core substrate according to any one of claims 1 to 5, Multiple insulating layers and multiple conductive layers are alternately laminated on both the front and back surfaces of the core substrate.

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