Semiconductor equipment

Abstract

To improve the characteristics of semiconductor devices. [Solution] The semiconductor device of the embodiment includes a wiring substrate having through holes, a first conductive layer, an insulating layer on the first conductive layer, a second conductive layer on the insulating layer, a substrate provided in the through holes, a semiconductor chip provided on the substrate within the through holes, and a sealing member covering the substrate and the semiconductor chip within the through holes, wherein the first dimension of the insulating layer along a first direction parallel to the surface of the substrate is greater than the second dimension of the first conductive layer along the first direction and the third dimension of the second conductive layer along the first direction.

Description

Technical Field

[0006] ,

[0004] , , , ,

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[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] The development of semiconductor devices as power modules is being promoted.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the characteristics of semiconductor devices.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a wiring board having a first through hole, a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, and includes a first substrate provided in the first through hole, a first semiconductor chip provided on the first substrate in the first through hole, and a sealing member covering the first substrate and the first semiconductor chip in the first through hole, and a first dimension along a first direction parallel to the surface of the first substrate of the first insulating layer is larger than a second dimension along the first direction of the first conductive layer and a third dimension along the first direction of the second conductive layer.

Brief Description of the Drawings

[0006] <00​​​​​​ [Figure 3] A plan view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 6] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 7] A flowchart illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 8] A plan view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 9] A cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 10] A cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 11] A cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 12] A cross-sectional view showing an example of the structure of a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described with reference to Figures 1 to 12. In the following description, elements having the same function and configuration will be denoted by the same reference numeral. In addition, in each of the following embodiments, if components that are denoted by reference numerals with distinguishing numerals / letters at the end (for example, circuits, wiring, various voltages and signals, etc.) do not need to be distinguished from one another, the reference numerals / letters at the end will be omitted.

[0008] (Embodiment) (1) First Embodiment A semiconductor device of the first embodiment will be described with reference to Figures 1 to 7.

[0009] (a) Configuration example Figure 1 is a bird's-eye view showing a schematic of the semiconductor device 1 of this embodiment.

[0010] As shown in FIG. 1, the semiconductor device 1 of this embodiment includes a wiring substrate 5, a semiconductor chip 2, a substrate 3, and a sealing member 8.

[0011] The wiring substrate 5 is a substrate including wirings (not shown). The wirings are provided on the surface of the wiring substrate 5. The wiring substrate 5 has through holes OP.

[0012] The substrate 3 is a substrate including an insulating layer. The substrate 3 is provided in the through hole OP of the wiring substrate 5. The back surface of the substrate 3 is exposed through the through hole OP.

[0013] The semiconductor chip 2 is a chip including one or more semiconductor elements. The semiconductor chip 2 is provided on the surface of the substrate 3. The semiconductor chip 2 and the substrate 3 are embedded in the through hole OP of the wiring substrate 5 together.

[0014] The sealing member 8 is provided in the through hole OP. The sealing member 8 covers the semiconductor chip 2 and the substrate 3 in the through hole OP.

[0015] Thus, in the semiconductor device 1 of this embodiment, the semiconductor chip 2 and the substrate 3 are built in the wiring substrate 5.

[0016] FIG. 2 is a circuit diagram showing the circuit configuration of the semiconductor device 1 of this embodiment.

[0017] The semiconductor device 1 of this embodiment is a power module. For example, the semiconductor device 1 includes a half-bridge circuit.

[0018] As shown in FIG. 2, the semiconductor device 1 includes transistors TR1, TR2 and terminals P, N, AC, D1-1, D1-2, D2, S1, S2-1, S2-2, G1, G2.

[0019] Each of the terminal P and the terminal N is a power supply terminal of the semiconductor device 1. A positive power supply voltage is applied to the terminal P. A negative power supply voltage (or ground voltage) is applied to the terminal N.

[0020] Terminal AC is the output terminal of semiconductor device 1.

[0021] Terminals G1 and G2 are control terminals of the semiconductor device 1, respectively.

[0022] Transistors TR1 and TR2 are, for example, N-type vertical MOS transistors using silicon or silicon carbide. Although vertical MOS transistors are shown as an example in Figure 3, transistors TR1 and TR2 may also be vertical insulated-gate bipolar transistors (IGBTs) or transistors using gallium nitride.

[0023] Between terminals P and N, the current path of transistor TR1 is connected in series with the current path of transistor TR2.

[0024] The drain of transistor TR1 is connected to terminal P. The source of transistor TR1 is connected to terminal AC. The gate of transistor TR1 is connected to terminal G1.

[0025] The drain of transistor TR2 is connected to terminal AC. The source of transistor TR2 is connected to terminal N. The gate of transistor TR2 is connected to terminal G2.

[0026] For example, each of transistors TR1 and TR2 may be composed of multiple transistors connected in parallel or multiple transistors connected in series.

[0027] Terminals D1-1, D1-2, D2, S1, S2-1, and S2-2 are terminals for monitoring the operation of semiconductor device 1. Terminals D1-1 and D1-2 are connected to the drains of transistor TR1. Terminal S1 is connected to the source of transistor TR1. Terminal D2 is connected to the drain of transistor TR2. Terminals S2-1 and S2-2 are connected to the sources of transistor TR2.

[0028] As shown in the configuration in Figure 2, the semiconductor elements TR1 and TR2 inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1.

[0029] An example of the structure of the semiconductor device 1 of this embodiment will be described with reference to Figures 3 to 6.

[0030] Figure 3 is a plan view showing an example of the structure of the semiconductor device 1 of this embodiment. Figures 4 to 6 are cross-sectional views showing an example of the structure of the semiconductor device 1 of this embodiment. Figure 4 shows a cross-section along line AA in Figure 3. Figure 5 shows a cross-section along line BB in Figure 3. Figure 6 shows a cross-section along line CC in Figure 3.

[0031] As shown in Figures 3 to 6, the semiconductor device 1 of this embodiment includes a wiring board 5, one or more semiconductor chips 2, a substrate 3, and a sealing member 8.

[0032] The wiring board 5 is, for example, a printed circuit board. The wiring board 5 includes a core member 50 and conductive layers 51 and 52.

[0033] The core member (also called the first wall) 50 has a through hole OP. When viewed from a direction perpendicular to the main surface of the wiring board 5, the core member 50 has a rectangular annular structure. The core member 50 is a wall surrounding the space in which the semiconductor chip 2 is provided. The core member 50 is an insulating material. For example, the core member 50 includes a material containing a sealing resin such as epoxy resin. As a specific example, the core member 50 is a mixture of epoxy resin and glass fiber.

[0034] The conductive layers 51 and 52 are provided on the front and back surfaces of the core member 50, respectively. Conductive layer 51 is used as wiring or a terminal for connecting the semiconductor chip 2 to an external device of the semiconductor device 1. Conductive layer 52 is used, for example, as wiring or a heat sink. Conductive layers 51 and 52 are, for example, metal layers containing copper (Cu). Conductive layer 51 may be connected to conductive layer 52 via a plug (not shown) formed within the core member 50.

[0035] The semiconductor chips 2 and substrates 3 are embedded in through-holes OP of the wiring board 5. Six semiconductor chips 2 are provided on one substrate 3. Twelve semiconductor chips 2 and two substrates 3 are provided within the through-holes OP.

[0036] The semiconductor chip 2 includes a semiconductor element 20 and conductive layers 21 and 22. In the semiconductor chip 2, the semiconductor element 20 is sandwiched between the conductive layers 21 and 22. The semiconductor element 20 is, for example, a vertical transistor. The conductive layer 21 is provided on the surface of the semiconductor chip. The conductive layer 22 is provided on the back surface of the semiconductor chip. When the semiconductor element 20 is a vertical transistor, the conductive layer 21 is the source electrode plate of the transistor, and the conductive layer 22 is the drain electrode plate of the transistor.

[0037] The conductive layer 21 is a layer containing copper. The thickness (dimension in the Z direction) of the conductive layer 21 is 10 μm or more. For example, it is desirable that the conductive layer 21 be 20 μm or more thick. When the conductive layer 21 is a copper layer, for example, the conductive layer 21 is formed by a plating process. This improves the transient thermal behavior of the semiconductor elements of the semiconductor chip 2.

[0038] The conductive layer 22 is a layer containing one of the following: gold (Au), silver (Ag), or a gold-silver alloy. The conductive layer 22 may also be a layer containing copper.

[0039] A conductor 29 is provided between the conductive layer 22 and the substrate 3. The conductor 29 includes a sintered material such as pressurized silver or a solder material. When an active sintered material is used for the conductor 29, the oxide film on the surface of the copper layer can be removed.

[0040] The semiconductor chip 2 is connected to the conductive layer (wiring) 31 (31a, 31b) on the substrate 3 via the conductive layer 22 and the conductor 29. This electrically connects multiple semiconductor chips 2 to each other. Alternatively, the semiconductor chips 2 may be connected to the conductive layer 31 by bonding wires.

[0041] The first assembly of six semiconductor chips 2 aligned in the Y direction is connected to a conductive layer 81 via a conductive layer 21 and a plug 82. The conductive layer 81 is connected to a conductive layer 51 of the wiring board 5 via a plug 83. In this way, the semiconductor chips 2 are electrically connected to the wiring board 5.

[0042] Within the through-hole OP of the wiring board 5, the two substrates 3 are aligned in the Y direction. A sealing member 8 is provided between the two substrates 3.

[0043] The substrate 3 includes an insulating layer 30 and conductive layers 31a, 31b, and 32. The conductive layers 31a and 31b are provided on the surface of the insulating layer 30. Conductive layer 31a is separated from conductive layer 31b. Conductive layer 31a is aligned with conductive layer 31b in the X direction. Conductive layer 32 is provided beneath the back surface of the insulating layer 30. The insulating layer 30 is sandwiched between the two conductive layers 31 and 32. The back surface of conductive layer 32 is exposed through a through hole OP.

[0044] The conductive layers 31a and 31b are used as wiring. The conductive layer 32 is used as a heat sink. The conductive layers 31a, 31b, and 32 are, for example, copper layers. For example, the film thickness (dimension in the Z direction) of the conductive layers 31a, 31b, and 32 is 0.3 mm or more. Preferably, the film thickness of the conductive layers 31a, 31b, and 32 is 1.0 mm or more.

[0045] The conductive layer 31a is connected to the conductive layer 84 via a plug 85. The conductive layer 84 is connected to the conductive layer 51 of the wiring board 5 via a plug 86. In this way, the semiconductor chip 2 is electrically connected to the wiring board 5. The conductive layer 84 is also connected to a second assembly of six semiconductor chips 2 arranged in the Y direction via a plug (not shown).

[0046] The conductive layer 31b is connected to the conductive layer 87 via a plug 88. The conductive layer 87 is connected to the conductive layer 51 of the wiring board 5 via a plug 89. In this way, the semiconductor chip 2 is electrically connected to the wiring board 5.

[0047] The insulating layer 30 is, for example, a silicon nitride layer (SiN layer). The insulating layer 30 containing silicon nitride has high fracture toughness and good thermal conductivity. The high fracture toughness of the insulating layer 30 allows for a thicker copper film thickness in the conductive layer (wiring) 31 of the substrate 3. The high thermal conductivity of the insulating layer 30 allows for the dissipation of heat generated from the semiconductor chip 2.

[0048] For example, the thickness of the insulating layer 30 containing silicon nitride is approximately 0.25 mm to 0.5 mm. This prevents dielectric breakdown of the semiconductor chip 2 and the semiconductor device 1 when a high voltage of approximately 1200 V to 3300 V is applied to the semiconductor device 1. For example, the thickness of the insulating layer 30 (dimension in the Z direction) is thicker than the thickness of the conductive layers 31 and 32.

[0049] When the insulating layer 30 containing silicon nitride is sandwiched between conductive layers 31 and 32, the influence of parasitic impedance (e.g., parasitic inductance) of the substrate 3 is reduced. As a result, the substrate 3 has excellent EMI (Electromagnetic Interference) characteristics. For example, the effect of reducing inductance is beneficial in lowering the surge voltage generated in the semiconductor device 1.

[0050] The ends 300 of the insulating layer 30 in the X and Y directions (hereinafter referred to as the side portions or protrusions) protrude in the X and Y directions from the ends of the conductive layers 31 and 32 in the X and Y directions.

[0051] The dimension L0 of the insulating layer 30 in the Y direction is greater than the dimension L1 of the conductive layer 31 in the Y direction and the dimension L2 of the conductive layer 32 in the Y direction. The substrate 3 has a structure in which the side of the insulating layer 30 protrudes from the side of the conductive layers 31 and 32. As a result, the insulating layer 30 divides the electric field lines generated between the conductive layers 31 and 32. Consequently, in the semiconductor device 1 of this embodiment, the insulating layer 30 can prevent leakage between the conductive layers 31 and 32 that bypasses the side of the insulating layer 30.

[0052] The dimensions of the insulating layer 30 in the X direction are greater than the dimensions of the conductive layer 31 in the X direction (however, the sum of the dimensions of the two conductive layers 31a and 31b in the X direction) and the dimensions of the conductive layer 32 in the X direction. However, if the dimensions of the insulating layer 30 are greater than the dimensions of the conductive layers 31 and 32, the dimensions of the insulating layer 30 in the X direction may differ from the dimensions of the insulating layer 30 in the Y direction.

[0053] The area of ​​the insulating layer 30 as viewed from the Z direction is greater than the sum of the area of ​​the conductive layer 31 as viewed from the Z direction and the area of ​​the conductive layer 32 as viewed from the Z direction.

[0054] The sides 300 of the insulating layer 30 are covered with a coating 39. The coating 39 covers the top, sides, and bottom of the sides 300. The coating 39 is a film containing an insulator. The coating 39 functions as an adhesion enhancer between the insulating layer 30 and the sealing member 8. The coating 39 improves the adhesion between the insulating layer 30 and the sealing member 8. The coating 39 suppresses the destruction of the insulating layer 30 by heat and / or high voltage.

[0055] The sealing member 8 is provided on the wiring board 5. The sealing member 8 is embedded in a through hole OP within the wiring board 5. The sealing member 8 is provided between the wiring board 5 and the semiconductor chip 2, between multiple semiconductor chips 2, between two substrates 3, and between the wiring board 5 and the substrate 3. The sealing member 8 is an insulator formed from a resin such as prepreg or epoxy.

[0056] Multiple conductive layers 81, 84, and 87 are provided on the surface side of the wiring board 5. The conductive layers 81, 84, and 87 are embedded within the sealing member 8.

[0057] The conductive layer 81 is connected to the terminal 90 via a conductor 94a, such as solder or sintered material. Terminal 90 is, for example, terminal N to which a negative (or 0V) power supply voltage is applied. For example, terminals S2-1 and S2-2 are connected to the conductive layer 81.

[0058] The conductive layer 84 is connected to the terminal 91 via a conductor 94b, such as solder or sintered material. Terminal 91 is, for example, the output terminal AC of the semiconductor device 1.

[0059] The conductive layer 87 is connected to terminal 92 via a conductor 94c, such as solder or sintered material. Terminal 92 is, for example, terminal P to which a positive power supply voltage is applied.

[0060] The insulating layer 95 covers the conductive layers 81, 84, 87 and the conductors 94a, 94b, 94c. The terminals 90, 91, 92 are embedded in the openings of the insulating layer 95.

[0061] Terminals D2 and S1 are connected to the conductive layer 81. Terminals D1-1 and D1-2 are connected to the conductive layer 81. Terminals G1 and G2 are connected to the gates of the corresponding semiconductor chip 2.

[0062] For example, the dimensions of the semiconductor device 1 in this embodiment in the Z direction are approximately 2 mm.

[0063] For example, the semiconductor device 1 is mounted on a heat dissipation mechanism 98. The heat dissipation mechanism 98 is mounted on the back side of the wiring board 5. In the semiconductor device 1, the conductive layer 32 exposed on the back side of the substrate 3 is joined to the heat dissipation mechanism 98 via an adhesive layer 99 such as a sintered material or solder. The heat dissipation mechanism 98 is a heat sink 98. The heat sink 98 is, for example, a copper plate. The heat dissipation mechanism 98 may also be a cooler.

[0064] For example, components 100A, 100B and other semiconductor devices 200 may be stacked on the semiconductor device 1 by surface mounting. Component 100A and the semiconductor device 200 are provided on an insulating layer 95. Component 100B is provided on the semiconductor device 200. Components 100A and 100B are passive elements such as capacitors. The semiconductor device 200 is, for example, a gate drive circuit. This provides a semiconductor module (e.g., a power module) including the semiconductor device 1 of this embodiment.

[0065] (b) Manufacturing method The method for manufacturing the semiconductor device of this embodiment will be described with reference to Figure 7.

[0066] Figure 7 is a flowchart illustrating the manufacturing method of the semiconductor device 1 according to this embodiment.

[0067] (Step ST1) Semiconductor elements 20, such as transistors, are formed in each chip area of ​​the wafer by known technology.

[0068] (Step ST2) The electrodes are formed on the semiconductor device.

[0069] (Step ST3) A plating process is applied to the wafer. This forms a conductive layer 21 containing copper on the electrodes of the semiconductor device.

[0070] (Step ST4) Dicing is performed on the wafer. This forms multiple semiconductor chips 2 from the wafer. Note that the wafer may be ground to a desired thickness before dicing.

[0071] (Step ST5) The sintered material 29 is formed under the back surface of the semiconductor chip 2 or on the conductive layer 31. The sintered material 29 is conductive.

[0072] (Step ST6) The semiconductor chip 2 is temporarily fixed onto the conductive layer 31 of the substrate 3 via a sintered material 29.

[0073] (Step ST7) A sintering process is performed on the substrate 3 on which the semiconductor chip 2 is placed. This causes the sintering material 29 to be sintered. The sintering of the sintering material 29 bonds (fixes) the semiconductor chip 2 onto the substrate 3. The semiconductor chip 2 is electrically connected to the conductive layer 31 of the substrate 3 via the sintering material (conductor) 29. When the active sintering material 29 is bonded to the conductive layer 31 containing copper, the oxide film on the surface of the conductive layer 31 is removed by the sintering material 29.

[0074] (Step ST8) The through-hole OP is formed within the wiring substrate 5 on which the conductive layers 51 and 52 are formed.

[0075] (Step ST9) A substrate 3 to which semiconductor chips 2 are attached is placed within a through-hole OP of a wiring board 5.

[0076] (Step ST10) The prepreg is embedded in the through-hole OP. The prepreg is hardened by heat treatment and pressure treatment. As a result, the hardened prepreg (sealing member) 8 seals the semiconductor chip 2 and substrate 3 in the through-hole OP into the wiring board 5.

[0077] (Step ST11) Openings or grooves are formed within the prepreg sealing member 8 by laser processing. Subsequently, conductive layers 81, 84, 87 and plugs 82, 83, 85, 86, 88, 89 are formed on the sealing member 8 by plating.

[0078] Subsequently, conductive materials 94a, 94b, 94c such as solder or sintered material and an insulating layer 95 are formed on the wiring board 5 and the conductive layers 81, 84, 87. Terminals 90, 91, 92 are connected to the corresponding conductive layers 81, 84, 87, respectively.

[0079] For example, components 100A, 100B, and other semiconductor devices 200 are mounted on the semiconductor device 1 by surface mounting.

[0080] The semiconductor device 1 of this embodiment is completed through the manufacturing process described above.

[0081] (c) Summary The semiconductor device 1 of this embodiment has a structure in which a plurality of semiconductor chips 2 arranged on an insulating substrate 3 are sealed by a sealing member 8 within through holes OP in a wiring substrate 5.

[0082] In the semiconductor device 1 of this embodiment, the insulating substrate 3 has a structure in which an insulating layer 30 of silicon nitride is sandwiched between two conductive layers (for example, copper layers) 31 and 32.

[0083] In this embodiment, the dimension L0 of the insulating layer 30 in the X direction (or Y direction) is greater than the dimension L1 of the conductive layer 31 in the X direction (or Y direction) and the dimension L2 of the conductive layer 32 in the X direction (or Y direction). In this embodiment, the insulating substrate 3 has a structure in which the side of the insulating layer 30 protrudes from the side of the conductive layers 31 and 32. As a result, the insulating layer 30 can sever the electrical connection between the conductive layers 31 and 32 that bypasses the side of the insulating layer 30. Therefore, the semiconductor device 1 of this embodiment can secure a margin to reach creepage discharge between the conductive layers 31 and 32 on the substrate 3.

[0084] The semiconductor device 1 of this embodiment, with the configuration described above, can achieve weight reduction, high voltage resistance, high output, and high efficiency of the power module.

[0085] As a result, when the semiconductor device 1 of this embodiment is used as a power module in an electric vehicle, the battery voltage (charging output) can be improved. Therefore, the semiconductor device 1 of this embodiment can shorten the charging period of an electric vehicle.

[0086] Furthermore, according to this embodiment, the generation of current during charging using a power module including the semiconductor device 1 of this embodiment is suppressed by making the charging cable thinner, lighter, and using a higher voltage. As a result, the semiconductor device 1 of this embodiment can reduce the amount of heat generated by the power module cable and simplify the cooling mechanism. In this way, the semiconductor device 1 of this embodiment can realize simplification and cost reduction of the system using the semiconductor device 1 of this embodiment.

[0087] The semiconductor device 1 of this embodiment can improve the power performance of electric vehicles by increasing output power and efficiency. The semiconductor device 1 of this embodiment can achieve a higher output power of the drive motor while miniaturizing and reducing the weight of the drive motor by using thinner cables.

[0088] As described above, the semiconductor device of this embodiment can improve the characteristics of the semiconductor device.

[0089] (2) Second embodiment A semiconductor device of the second embodiment will be described with reference to Figures 8 to 11.

[0090] Figure 8 is a plan view showing an example of the structure of the semiconductor device 1 of this embodiment. Figures 9 to 11 are cross-sectional views showing an example of the structure of the semiconductor device 1 of this embodiment. Figure 9 shows a cross-section along line AA in Figure 8. Figure 10 shows a cross-section along line BB in Figure 8. Figure 11 shows a cross-section along line CC in Figure 8.

[0091] The wiring board 5 may include two through holes OP1 and OP2.

[0092] The two through holes OP1 and OP2 are separated by a core member 53. The through holes OP1 and OP2 are aligned in the Y direction, with the core member 53 in between. Hereinafter, the core member 53 between the through holes OP1 and OP2 will be referred to as the separation portion 53 or the wall (second wall) 53.

[0093] The separation section 53 is continuous with the core member 50. The separation section 53 extends in a direction that intersects the direction in which the through holes OP1 and OP2 are aligned (for example, the X direction). The separation section 53 is connected to the portion of the rectangular annular core member 50 that extends in the Y direction. The separation section 53 is a wall that separates the two through holes OP1 and OP2.

[0094] A conductive layer 54 is provided on the surface of the separation section 53. Depending on the wiring layout, the conductive layer 54 may be continuous with the conductive layer 51 or separated from the conductive layer 51.

[0095] A conductive layer 55 is provided beneath the back surface of the separation portion 53. The conductive layer 55 is, for example, continuous with the conductive layer 52. However, the conductive layer 55 may be separated from the conductive layer 52.

[0096] One semiconductor chip 2 and one substrate 3 are placed in one through-hole OP1. The other semiconductor chip 2 and the other substrate 3 are placed in the other through-hole OP2. The separation section 53 is provided between the two substrates 3.

[0097] Conductive layer 81A is connected to one semiconductor chip 2 via plug 82A. Conductive layer 81B is connected to the other semiconductor chip 2 via plug 82B. Conductive layer 81A is connected to conductive layer 81B via conductive layer 71 and plugs 72A, 72B (and conductor 94a).

[0098] The conductive layer 84A is connected to the conductive layer 31a on the substrate 3 via the plug 85A. The conductive layer 84B is connected to the conductive layer 31a on the other substrate 3 via the plug 85B. The conductive layer 84A is connected to the conductive layer 84B via the conductive layer 74 and the plugs 75A, 75B (and the conductor 94b).

[0099] The conductive layer 87A is connected to the conductive layer 31b on one substrate 3 via plug 88A. The conductive layer 87B is connected to the conductive layer 31b on the other substrate 3 via plug 88B. The conductive layer 87A is connected to the conductive layer 87B via conductive layer 77 and plugs 78A, 78B (and conductor 94c).

[0100] The conductive layers 71, 74, 77 and the plugs 72A, 72B, 75A, 75B, 78A, 78B are provided within the insulating layer 95 on the wiring board 5. Each conductive layer 71, 74, 77 extends from one through-hole OP1 side to the other through-hole OP2 side, passing over the separation portion 53. The conductive layers 71, 74, 77 may be exposed from the insulating layer 95.

[0101] Furthermore, three or more through-holes OP may be provided within the wiring board 5 by two or more separation sections 53.

[0102] In this embodiment, when ultrasonic bonding of terminals 90, 91, and 92 to the semiconductor chip 2 and substrate 3 in one through-hole OP1, the separation unit 53 suppresses the propagation of shocks caused by ultrasonic waves to the semiconductor chip 2 and substrate 3 in the other through-hole OP2.

[0103] Furthermore, in this embodiment, the rigidity of the wiring board 5 having the through hole OP is improved by the installation of the separation portion 53.

[0104] As a result, the semiconductor device 1 of this embodiment can prevent the destruction of the semiconductor chip 2 and the peeling of the conductive layers 31 and 32.

[0105] As a result, the semiconductor device 1 of this embodiment can reduce defects in the semiconductor device.

[0106] (3) Third Embodiment Referring to Figure 12, a semiconductor device of the third embodiment will be described.

[0107] Figure 12 is a cross-sectional view showing an example of the structure of the semiconductor device 1 of this embodiment.

[0108] As shown in Figure 12, the semiconductor device 1 of this embodiment may include a semiconductor chip 2 embedded in a wiring board 5 and a semiconductor chip 2 provided in a semiconductor package 9. The semiconductor package 9, including the semiconductor chip 2, is provided together with the wiring board 5 on which the semiconductor chip 2 is embedded on a single heat sink 98.

[0109] In the semiconductor device 1 of this embodiment, the semiconductor chip 2 and the substrate 3 are housed within the through-hole OP of the wiring board 5.

[0110] The substrate 3 containing the silicon nitride layer 30 does not necessarily have to be embedded in the through-hole OP of the wiring board 5.

[0111] The semiconductor package 9 covers the semiconductor chip 2 on the substrate 3. The semiconductor package 9 is an insulating sealing material (e.g., resin). The plug PG is provided inside the semiconductor package 9. On the substrate 3, the side portion 300 of the insulating layer 30 protrudes from the ends of the conductive layers 31 and 32. The dimensions of the insulating layer 30 in the direction parallel to the surface of the wiring substrate 5 are greater than the dimensions of the conductive layer 31 in the direction parallel to the surface of the wiring substrate 5 (the sum of the dimensions along the direction in which the two conductive layers 31 on the same substrate 3 are aligned), and the dimensions of the conductive layer 32 in the direction parallel to the surface of the wiring substrate 5.

[0112] The semiconductor chip 2 inside the semiconductor package 9 is electrically connected to the semiconductor chip 2 inside the wiring board 5 via the plug PG, conductors 62A and 62B, and wiring 63.

[0113] The conductive layer 31 of the substrate 3 inside the semiconductor package 9 is connected to the terminal 60B via the plug PG and the conductor 64.

[0114] In the substrate 3 within the through-hole OP of the wiring board 5, the conductive layer 31 of the substrate 3 is connected to the terminal 60A via the plug PG and conductor 61 in the sealing member 8.

[0115] The semiconductor package 9, which includes the semiconductor chip 2, and the wiring board 5 on which the semiconductor chip 2 is embedded, may be provided inside a case (enclosure) 6. Terminals 60A and 60B are exposed from the case 6.

[0116] Furthermore, the device 999, which includes a semiconductor chip 2 on a substrate 3 sealed by a semiconductor package 9, may be provided as a single semiconductor device 999.

[0117] The semiconductor device 1 of this embodiment can obtain substantially the same effects as the embodiment described above.

[0118] (4) Others In the above-described embodiment, an example is shown in which the semiconductor device 1 of the embodiment is used in a DC-DC converter. However, the semiconductor device 1 of the embodiment may also be applied to other semiconductor circuits such as inverters.

[0119] The semiconductor device 1 of this embodiment can be applied to electric vehicles, railway vehicles, home appliances, and power systems, among others.

[0120] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0121] 1: Semiconductor device, 2: Semiconductor chip, 3: Substrate, 5: Wiring board, 8: Encapsulation material, 9: Semiconductor package, 30: Insulating layer, 31a, 31b, 32: Conductive layer, 98: Heat dissipation mechanism, OP, OP1, OP2: Through hole

Claims

1. A wiring board having a first through hole, A first substrate provided in the first through hole, comprising a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, A first semiconductor chip provided on the first substrate within the first through-hole, A sealing member that covers the first substrate and the first semiconductor chip within the first through hole, It is equipped with, The first dimension of the first insulating layer along a first direction parallel to the surface of the first substrate is greater than the second dimension of the first conductive layer along the first direction, and the third dimension of the second conductive layer along the first direction. Semiconductor equipment.

2. The first insulating layer comprises silicon nitride, The semiconductor device according to claim 1.

3. A first film is provided between the sealing member and the first insulating layer, and covers the side portion of the first insulating layer. The semiconductor device according to claim 1, further comprising the present invention.

4. The second circuit board, A second semiconductor chip provided on the second substrate, Furthermore, it is equipped with, The wiring board further includes a second through hole and a separation portion between the first through hole and the second through hole, The second substrate and the second semiconductor chip are provided within the second through-hole. The semiconductor device according to claim 1.

5. A third conductive layer connects the first semiconductor chip to the second semiconductor chip via the above separation portion, The semiconductor device according to claim 4, further comprising:

6. The aforementioned wiring board is provided in a heat dissipation mechanism, A semiconductor package including a third semiconductor chip is provided on the heat dissipation mechanism, adjacent to the wiring board in a direction parallel to the surface of the heat dissipation mechanism, The semiconductor device according to claim 1, further comprising:

7. The wiring board and the first semiconductor chip are connected, and the fourth conductive layer provided within the sealing member is The semiconductor device according to claim 1, further comprising:

8. A heat dissipation mechanism is bonded to the back surface of the second conductive layer exposed through the first through hole, The semiconductor device according to claim 1, further comprising the present invention.

9. A substrate comprising a first conductive layer, an insulating layer on the first conductive layer, and a second conductive layer on the insulating layer, A semiconductor chip provided on the aforementioned substrate, An insulator provided on the substrate and covering the semiconductor chip, It is equipped with, The first dimension of the insulating layer along a first direction parallel to the surface of the substrate is greater than the second dimension of the first conductive layer along the first direction, and the third dimension of the second conductive layer along the first direction. Semiconductor equipment.

10. The insulating layer contains silicon nitride, The semiconductor device according to claim 9.

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