Test methods, test systems, and tester systems

Abstract

This technology provides a way to reduce the processing load on a tester system that performs tests according to dynamic test patterns based on test results. [Solution] A testing method for a tester system in which a tester tests a device under test, comprising: the tester system collecting test results performed by the tester according to a test pattern; transmitting the collected test results to an analysis system; receiving a test pattern generated or selected by the analysis system based on the test results as the next test pattern; and having the tester perform a test according to the next test pattern.

Description

Technical Field

[0001] The present disclosure relates to a test method, a test system, and a tester system.

Background Art

[0002] In conventional semiconductor testing, a technique called adaptive testing is used. Adaptive testing is a technique for dynamically optimizing test patterns such as test content and test flow using test results. For example, in adaptive testing in semiconductor testing by a tester, dynamic optimization of test patterns may be performed using resources on the tester manufacturer side.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a technique for suppressing the processing load of a tester system that performs testing according to a dynamic test pattern based on test results.

Means for Solving the Problems

[0005] One aspect of the present disclosure is a test method for a tester system in which a tester tests a device under test, the tester system collecting test results obtained by the tester according to a test pattern, transmitting the collected test results to an analysis system, receiving, as a next test pattern, a test pattern generated or selected by the analysis system based on the test results, and causing the tester to perform testing according to the next test pattern.

Effects of the Invention

[0006] This disclosure provides a technology that reduces the processing load on a tester system that performs tests according to dynamic test patterns based on test results. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram illustrating an example of a test system according to this embodiment. [Figure 2] This is a hardware configuration diagram of an example computer. [Figure 3] A functional block diagram showing an example of a tester system and analysis system according to this embodiment. [Figure 4] This is a sequence diagram of an example of the processing of the test system according to this embodiment. [Figure 5] This is a flowchart of an example of the process in step S18. [Figure 6] This is a flowchart of an example of the process in step S22. [Modes for carrying out the invention]

[0008] The following description of this embodiment will be given with reference to the drawings.

[0009] <System Configuration> Figure 1 is a configuration diagram of an example of a test system 1 according to this embodiment. The test system 1 shown in Figure 1 includes a tester 10, an auxiliary computing device 12, and an analysis system 14. The tester 10 and the auxiliary computing device 12 constitute an example of a tester system 2, which is a resource on the tester manufacturer's side. The analysis system 14 is an example of a resource on the semiconductor manufacturer's side. For example, a semiconductor manufacturer is a customer of the tester manufacturer. The tester 10, the auxiliary computing device 12, and the analysis system 14 are connected to each other via networks N1 and N2, such as the Internet or a LAN (Local Area Network).

[0010] Tester 10 is an example of a test device that tests a device under test according to test patterns included in a test program. The test program is provided, for example, by the semiconductor manufacturer. Tester 10 performs tests to verify the logic operation of the device under test. Tester 10 also performs tests to verify characteristics such as voltage, current, or time of the device under test.

[0011] The auxiliary computing device 12 is an example of a resource on the tester manufacturer's side. The auxiliary computing device 12 is a computer such as a PC (Personal Computer). The auxiliary computing device 12 performs general processing, such as the analysis of characteristic data of the test results from the tester 10, between the tester 10 and the analysis system 14.

[0012] Based on the test results obtained when the tester 10 tests the device under test according to the test pattern, the analysis system 14 generates or selects the next test pattern for the tester 10 to perform, as described later. The analysis system 14 also includes the generated or selected next test pattern for the tester 10 in a test program and sends it to the tester 10. The analysis system 14 may be implemented as a cloud service or as one or more server devices.

[0013] The test system 1 shown in Figure 1 is just one example, and it goes without saying that there are various system configurations depending on the application and purpose. The classification of the devices, such as the tester 10, auxiliary calculation device 12, and analysis system 14 in Figure 1, is just one example. For example, the auxiliary calculation device 12 and the analysis system 14 may be in an integrated configuration or they may be in a further separated configuration. The auxiliary calculation device 12 may be installed inside the housing of the tester 10.

[0014] In the test system 1 shown in Figure 1, adaptive testing techniques are used, for example, in semiconductor testing of a semiconductor device, which is an example of a device under test.

[0015] When the process of generating or selecting test patterns required for adaptive testing in semiconductor testing is performed using resources on the tester manufacturer side, it has been difficult to adopt computationally intensive algorithms for generating or selecting test patterns from the perspective of the resources and throughput on the tester manufacturer side. Also, when adopting a computationally intensive algorithm for generating or selecting test patterns, it is necessary to improve the specifications of the resources on the tester manufacturer side.

[0016] In the test system 1 according to the present embodiment, the process of generating or selecting test patterns required for adaptive testing in semiconductor testing is performed using not only resources on the tester manufacturer side but also resources on the semiconductor manufacturer side. The test system 1 according to the present embodiment can adopt a computationally intensive algorithm for generating or selecting test patterns without improving the specifications of the resources on the tester manufacturer side by effectively utilizing not only resources on the tester manufacturer side but also resources on the semiconductor manufacturer side.

[0017] Also, the test system 1 according to the present embodiment arranges an auxiliary arithmetic unit 12 for performing general-purpose processing between the tester 10 and the resources on the semiconductor manufacturer side. The auxiliary arithmetic unit 12 improves the throughput of the test system 2 by performing processing that can be completed by a general-purpose processor, such as analyzing characteristic data of test results obtained according to test patterns, instead of the tester 10.

[0018] Furthermore, the test system 1 according to the present embodiment can reduce the communication volume with the analysis system 14 by completing analysis of characteristic data of test results obtained according to test patterns and the like in the test system 2.

[0019] <Hardware Configuration> The tester 10 shown in FIG. 1 has a PC (tester PC). The tester PC, the auxiliary arithmetic unit 12, and the analysis system 14 may be realized by a computer having a hardware configuration shown in FIG. 2, for example. FIG. 2 is a hardware configuration diagram of an example of a computer 500.

[0020] The computer 500 in FIG. 2 includes an input device 501, an output device 502, an external I / F (interface) 503, a RAM (Random Access Memory) 504, a ROM (Read Only Memory) 505, a CPU (Central Processing Unit) 506, a communication I / F 507, and a HDD (Hard Disk Drive) 508, etc., and they are mutually connected by a bus B. The input device 501 and the output device 502 may be in a form that is connected and used when necessary.

[0021] The input device 501 is a keyboard, a mouse, a touch panel, etc., and is used for an operator or the like to input an operation signal. The output device 502 is a display or the like, and displays the processing result by the computer 500. The communication I / F 507 is an interface for connecting the computer 500 to the networks N1 and N2 shown in FIG. 1. The HDD 508 is an example of a non-volatile storage device that stores programs and data.

[0022] The external I / F 503 is an interface with an external device. The computer 500 can read a recording medium 503a such as an SD (Secure Digital) memory card via the external I / F 503. The external I / F 503 may also be able to write to a recording medium 503a such as an SD memory card via the external I / F 503.

[0023] The ROM 505 is an example of a non-volatile semiconductor memory (storage device) in which programs and data are stored. The RAM 504 is an example of a volatile semiconductor memory (storage device) that temporarily holds programs and data. The CPU 506 is an arithmetic unit that realizes the control and functions of the entire computer 500 by reading programs and data from a storage device such as the ROM 505 or the HDD 508 onto the RAM 504 and executing processing.

[0024] The tester PC, auxiliary computing device 12, and analysis system 14 of the test system 1 shown in Figure 1 perform various functions by executing programs on the computer 500 shown in Figure 2.

[0025] <Functional Configuration> The tester system 2 and analysis system 14 according to this embodiment are implemented using functional blocks as shown in Figure 3. Figure 3 is a functional block diagram showing an example of the tester system 2 and analysis system 14 according to this embodiment. Note that the functional block diagram in Figure 3 omits the illustration of components that are not necessary for the explanation of this embodiment.

[0026] The tester 10 in Figure 3 implements the receiving unit 22 and the test execution unit 24 by executing a program for the tester 10. The auxiliary arithmetic unit 12 implements the data acquisition unit 26, the data processing unit 28, and the transmission unit 30 by executing a program for the auxiliary arithmetic unit 12. The analysis system 14 implements the analysis unit 32 by executing a program for the analysis system 14.

[0027] The receiver 22 of the tester 10 receives a test program containing the next test pattern from the analysis system 14. The test execution unit 24 of the tester 10 tests the device under test 20 according to the test pattern contained in the test program received by the receiver 22 and obtains the test result.

[0028] The acquisition unit 26 of the auxiliary computing unit 12 collects the test results performed by the tester 10 on the device under test 20 according to the test pattern. The data processing unit 28 of the auxiliary computing unit 12 performs general-purpose processing such as saving the test results from the tester 10, analyzing the characteristic data of the test results, and compressing the data. The transmission unit 30 transmits the test results from the tester 10 collected by the acquisition unit 26, the characteristic data of the test results analyzed by the data processing unit 28, or the compressed characteristic data to the analysis system 14.

[0029] The analysis unit 32 of the analysis system 14 generates or selects the next test pattern to be performed by the tester 10 based on the test results received from the tester system 2. The analysis unit 32 can use AI (artificial intelligence) or a rule-based system to generate or select the next test pattern to be performed by the tester 10.

[0030] For example, the analysis unit 32 generates or selects the next test pattern to be performed by the tester 10 by using a machine learning model that studies the relationship between test results and test patterns based on the test results received from the tester system 2. The selection of a test pattern is the process of selecting the next test pattern to be performed by the tester 10 from a plurality of pre-generated test patterns.

[0031] For example, the analysis unit 32 may generate or select the next test pattern to be performed by the tester 10 using a table that associates the test results with the next test pattern to be performed by the tester 10, based on the test results received from the tester system 2.

[0032] The analysis system 14 sends a test program to the tester 10 that includes a test pattern generated or selected based on the test results obtained by the tester 10 when testing the device under test 20, as the next test pattern to be performed by the tester 10.

[0033] Thus, in the test system 1 according to this embodiment, the processing of generating or selecting test patterns necessary for adaptive testing of the device under test 20 is performed by an analysis system 14 external to the tester system 2. This distributes the processing load of the test system 1, allowing for effective utilization of resources not only from the tester manufacturer but also from the semiconductor manufacturer.

[0034] Furthermore, in the test system 1 according to this embodiment, by distributing the processing load of the test system 1, it is possible to employ computationally intensive algorithms for generating or selecting test patterns necessary for adaptive testing of the device under test 20 without improving the resource specifications on the tester manufacturer's side.

[0035] <Processing> The test system 1 according to this embodiment performs adaptive testing of the device under test 20 using the processing procedure shown in Figure 4, for example. Figure 4 is a sequence diagram of an example of the processing of the test system 1 according to this embodiment.

[0036] In step S10, the tester 10 receives a test program, including a test pattern, from the analysis system 14. The test pattern indicates the content of the next test that the tester 10 will perform on the device under test 20. The test pattern may consist of multiple test parts. The tester 10 may also receive the test program via a source other than the analysis system 14, such as a test program server.

[0037] In step S12, the tester 10 tests the device under test 20 according to the test pattern included in the received test program, and obtains the test result in step S14. The test result may be a test result that confirms the logical operation of the device under test 20, or a test result that confirms the characteristics of the device under test 20, such as voltage, current, or time.

[0038] In step S16, the tester 10 transmits the test results, which were obtained according to the test patterns included in the received test program, to the auxiliary arithmetic unit 12.

[0039] In step S18, the auxiliary computing unit 12 collects the test results that the tester 10 performed on the device under test 20 according to the test pattern. The auxiliary computing unit 12 performs general-purpose processing between the tester 10 and the analysis system 14. General-purpose processing performed by the auxiliary computing unit 12 includes, for example, saving the test results from the tester 10, analyzing the characteristic data of the test results, and compressing the data.

[0040] The process in step S18 is carried out, for example, using the procedure shown in Figure 5. Figure 5 is a flowchart of an example of the process in step S18.

[0041] In step S40, the auxiliary arithmetic unit 12 receives the test results from the tester 10 and collects the test results. In step S42, the auxiliary arithmetic unit 12 stores the collected test results in memory. In step S44, the auxiliary arithmetic unit 12 analyzes the collected test results and obtains characteristic data of the test results. In step S46, the auxiliary arithmetic unit 12 compresses the collected test results or characteristic data of the test results.

[0042] Note that the flowchart in Figure 5 is just one example, and the configuration may be such that at least one of steps S44 or S46 is omitted.

[0043] Returning to Figure 4, in step S20, the auxiliary calculation unit 12 transmits the test results collected by the acquisition unit 26 from the tester 10, the characteristic data of the test results analyzed by the data processing unit 28, or the characteristic data compressed by the data processing unit 28 to the analysis system 14.

[0044] In step S22, the analysis system 14 generates or selects a dynamic test pattern for the next test to be performed by the tester 10, based on the test results or characteristic data of the test results received from the tester system 2.

[0045] For example, the analysis system 14 can use AI or a rule-based approach to generate or select a dynamic test pattern for the next test performed by the tester 10, based on the test results or characteristic data of the test results performed on the device under test 20.

[0046] The AI-based analysis system 14 performs the process in step S22, for example, following the procedure shown in Figure 6. Figure 6 is a flowchart of an example of the process in step S22.

[0047] In step S60, the analysis system 14 receives test results or characteristic data of the test results from the tester system 2.

[0048] In step S62, the analysis system 14 uses a machine learning model that studies the relationship between test results and test patterns. The analysis system 14 may also use a machine learning model that studies the relationship between characteristic data of test results and test patterns.

[0049] The machine learning model, which tracks the relationship between test results and test patterns, has its internal parameters adjusted so that when it receives a test result as input, it generates or selects a test pattern that corresponds to that input test result. The test pattern that corresponds to the test result is the test pattern that should be performed in the next test given that test result.

[0050] The machine learning model, which tracks the relationship between test result characteristic data and test patterns, has its internal parameters adjusted so that when received test result characteristic data is input, it generates or selects a test pattern corresponding to the input test result characteristic data. The test pattern corresponding to the test result characteristic data is the test pattern that should be performed in the next test if that test result characteristic data is obtained.

[0051] The analysis system 14 generates or selects test patterns corresponding to the test results or characteristic data of the test results received from the tester system 2 in step S60, using a machine learning model that has studied the relationship between the test results or characteristic data of the test results and the test patterns.

[0052] Returning to Figure 4, the rule-based analysis system 14 uses, for example, a table that associates test results or characteristic data of test results with test patterns. The table associates test results or characteristic data of test results with the test patterns that should be performed in the next test if those test results or characteristic data are obtained. The analysis system 14 generates or selects test patterns that correspond to the test results or characteristic data of test results received from the tester system 2 using the table that associates test results or characteristic data of test results with test patterns.

[0053] In step S24, the analysis system 14 sends a test program to the tester 10 that uses a test pattern generated or selected based on the test results or characteristic data of the test results of the device under test 20 as the next test pattern to be performed. The tester 10 receives the test program containing the next test pattern from the analysis system 14.

[0054] In step S26, the tester 10 tests the device under test 20 according to the next test pattern included in the received test program, and obtains the test result in step S28. After the processing in step S28, the test system 1 repeats the processing in steps S16 to S28 until it reaches the completion state of the adaptive test.

[0055] The test system 1 according to this embodiment effectively utilizes not only the resources of the tester manufacturer but also the resources of the semiconductor manufacturer, allowing for the adoption of computationally intensive algorithms for generating or selecting test patterns without improving the specifications of the tester manufacturer's resources. As a result, the test system 1 according to this embodiment can achieve more effective and efficient adaptive testing.

[0056] Furthermore, since the test system 1 according to this embodiment has an auxiliary computing device 12 as a resource on the tester manufacturer's side, the overall throughput of the test system 1 can be improved by having the auxiliary computing device 12 replace the tester 10 with a general-purpose processor for processing that can be completed by the tester 10.

[0057] Furthermore, since the test system 1 according to this embodiment has an auxiliary computing device 12 as a resource on the tester manufacturer's side, processing such as analysis of characteristic data of test results and data compression can be performed on the tester manufacturer's resources, thereby reducing the amount of data communicated with the semiconductor manufacturer's resources.

[0058] Although preferred embodiments of this embodiment have been described in detail above, this embodiment is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of this embodiment.

[0059] It goes without saying that the test system 1 described herein is not limited to the configuration shown in Figure 1, and there are various system configuration examples depending on the application and purpose. According to this disclosure, it is possible to realize a test method, test system 1, and test system 2 that suppress the processing load of a tester system that performs tests according to a dynamic test pattern based on test results. [Explanation of symbols]

[0060] 1. Test System 10 Tester 12 Auxiliary computing unit 14 Analysis System 20 devices under test 22 Receiving section 24 Test Execution Unit 26 Collection Department 28 Data Processing Unit 30 Transmitter 32 Analysis Department

Claims

1. A test method for a tester system in which a tester tests a device under test, The aforementioned tester system, Collect the test results performed by the tester according to the test pattern, The collected test results are transmitted to the analysis system, The analysis system receives the test pattern it generates or selects based on the test results as the next test pattern to be performed. The tester is made to perform the test according to the test pattern described above, T&C testing method.

2. The tester system comprises the tester and the auxiliary calculation device, The auxiliary computing device analyzes the characteristic data of the test results, The test results or characteristic data are transmitted to the analysis system. The aforementioned tester, The analysis system receives a test pattern generated or selected based on the test results or characteristic data as the next test pattern to be performed. The test is performed according to the test pattern described above. The test method according to claim 1.

3. The auxiliary computing device compresses the test results or characteristic data and then transmits it to the analysis system. The test method according to claim 2.

4. The analysis system generates or selects the test patterns using a machine learning model that has acquired the relationship between the test results and the test patterns, or a table that associates the test results and the test patterns. The test method according to any one of claims 1 to 3.

5. A test system comprising: a tester system in which a tester tests a device under test; and an analysis system for generating or selecting test patterns for the tests performed by the tester, The aforementioned tester system, A collection unit that collects test results performed by the tester according to the aforementioned test pattern, A transmission unit that transmits the collected test results to the analysis system, A receiving unit that receives a test pattern generated or selected by the analysis system based on the test results as the next test pattern to be performed, A test execution unit that causes the tester to perform tests according to the test pattern described above, It has, The aforementioned analysis system, An analysis unit that generates or selects the test pattern based on the test results, Having, Testing system.

6. A tester system that is data-communicatively connected to an analysis system that generates or selects test patterns, and tests a device under test according to the test patterns, A collection unit that collects test results performed by a tester according to the aforementioned test pattern, A transmission unit that transmits the collected test results to the analysis system, A receiving unit that receives a test pattern generated or selected by the analysis system based on the test results as the next test pattern to be performed, A test execution unit that causes the tester to perform tests according to the test pattern described above, Having, Tester system.

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