Packaging substrate and semiconductor package including the same

Abstract

The present invention provides a packaging substrate and a method for connecting the same that improve the adhesion between the electrical conductive layer and the insulating layer without excessively roughening the surface of the electrical conductive layer. [Solution] The packaging substrate 100 includes a core layer 10, a first electrical conductive layer 20 which is an electrical conductive layer disposed in contact with the upper surface of the core layer, and an adhesion-enhancing layer 30 disposed on the core layer and surrounding at least a portion of the upper surface of the first electrical conductive layer. The adhesion-enhancing layer includes one selected from the group consisting of silicon-based compounds, acrylic-based compounds, and combinations thereof. The Ra value, which is the arithmetic mean roughness of the upper surface of the first electrical conductive layer, is 150 nm or less. In this case, the adhesion strength of the insulating layer to the first electrical conductive layer can be effectively improved without excessively roughening the surface of the first electrical conductive layer.

Description

Technical Field

[0001] Embodiments relate to a packaging substrate and a semiconductor package including the same.

Background Art

[0002] In fabricating an electronic component, forming a circuit on a semiconductor wafer is referred to as a front-end (FE) process, and assembling the wafer into a state where it can be used as an actual product is referred to as a back-end (BE) process, and the back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron line widths in nanometer units, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively speaking, there is no technology that can perfectly package this. Therefore, the electrical performance of a semiconductor may sometimes be determined by the packaging technology and the electrical connections thereby rather than the performance of the semiconductor technology itself.

[0004] As materials for a packaging substrate, ceramic or resin is applied. In the case of a ceramic substrate, since the resistance value is high or the dielectric constant is high, it is not easy to mount a high-performance high-frequency semiconductor element. In the case of a resin substrate, relatively speaking, a high-performance high-frequency semiconductor element can be mounted, but there is a limit to reducing the pitch of wiring.

[0005] Recently, research has been conducted on applying silicon or glass to a high-end packaging substrate. By forming through-holes in a silicon or glass substrate and applying a conductive material to these through-holes, the wiring length between an element and a motherboard can be shortened, and excellent electrical characteristics can be achieved.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Korean Published Patent No. 10-2021-0127188 [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of this embodiment is to provide a packaging substrate that improves the adhesion between the electrical conductive layer and the insulating layer without excessively roughening the electrical conductive layer. [Means for solving the problem]

[0008] A packaging substrate according to one embodiment of this specification includes a core layer, a first electrical conductive layer which is an electrical conductive layer disposed in contact with the upper surface of the core layer, and an adhesion-enhancing layer which is disposed on the core layer and surrounds at least a portion of the upper surface of the first electrical conductive layer.

[0009] The adhesion-enhancing layer comprises one selected from the group consisting of silicon-based compounds, acrylic-based compounds, and combinations thereof.

[0010] The Ra value, which is the arithmetic mean roughness of the upper surface of the first electrical conductive layer, is 150 nm or less.

[0011] The aforementioned silicon-based compound may contain a silicon resin.

[0012] The Ry value, which is the maximum height roughness of the upper surface of the first electrical conductive layer, may be 200 nm or less.

[0013] The core layer may be a glass core layer.

[0014] The upper surface of the core layer may include an exposed region in which the first electrical conductive layer is not formed.

[0015] The adhesion-enhancing layer may be positioned in contact with at least a portion of the exposed area.

[0016] The core layer can include a cavity portion which is an area where elements are mounted inside.

[0017] The cavity portion can include an opening disposed on the upper surface side of the core layer, an inner surface of the cavity formed to extend in the thickness direction of the core layer from the opening, and an element mounting space surrounded by the inner surface of the cavity.

[0018] The packaging substrate can include an element disposed in the element mounting space.

[0019] The adhesion strengthening layer can be disposed in contact with at least a part of the upper surface of the element.

[0020] The thickness of the adhesion strengthening layer can be 1 μm to 25 μm.

[0021] The packaging substrate can include an insulating layer disposed in contact with the adhesion strengthening layer.

[0022] The packaging substrate can include a multilayer insulating layer including the adhesion strengthening layer and the insulating layer.

[0023] The adhesive force between the first electrical conduction layer and the multilayer insulating layer can be 300 gf / cm or more.

[0024] A method for manufacturing a packaging substrate according to another embodiment of the present specification includes a preparation step of preparing a preliminary substrate including a core layer and a first electrical conduction layer disposed in contact with the upper surface of the core layer, an adhesion strengthening layer forming step of forming an adhesion strengthening layer surrounding at least a part of the upper surface of the first electrical conduction layer, and a manufacturing step of manufacturing a packaging substrate from the preliminary substrate on which the adhesion strengthening layer is formed.

[0025] The surface roughness Ra value of the upper surface of the first electrical conduction layer is 150 nm or less.

[0026] The adhesion strengthening layer contains any one selected from the group consisting of a silicon-based compound, an acrylic-based compound, and a combination thereof.

[0027] The preparation step can include a surface roughness control process for adjusting the roughness of the upper surface of the first electrical conduction layer.

[0028] The adhesion strengthening layer formation step can include an arrangement process of arranging a composition for manufacturing an adhesion strengthening layer so as to surround at least a part of the upper surface of the first electrical conduction layer, and a heat treatment process of heat-treating the composition for manufacturing an adhesion strengthening layer to form an adhesion strengthening layer.

[0029] The manufacturing step can include an insulating layer formation process of forming an insulating layer disposed in contact with the upper surface of the adhesion strengthening layer.

Advantages of the Invention

[0030] In an embodiment, in a packaging substrate, it is possible to improve the adhesive force between the electrical conduction layer and the insulating layer without excessively roughening the electrical conduction layer.

Brief Description of the Drawings

[0031] [Figure 1] It is a cross-sectional view illustrating a packaging substrate according to an embodiment of the embodiment. [Figure 2] It is a cross-sectional view illustrating a packaging substrate according to another embodiment of the embodiment. [Figure 3] It is a cross-sectional view illustrating a packaging substrate according to still another embodiment of the embodiment.

Best Mode for Carrying Out the Invention

[0032] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. However, the present invention can be realized in various different forms and is not limited to the embodiments described here. The same reference numerals are given to similar parts throughout the specification.

[0033] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0034] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0036] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0037] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0038] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0039] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.

[0040] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.

[0041] In this specification, unless otherwise specified, the physical properties of each component within the packaging substrate are assumed to have been measured at room temperature. Room temperature is defined as 20°C to 25°C.

[0042] The following provides a detailed explanation of specific examples.

[0043] Figure 1 is a cross-sectional view illustrating a packaging substrate according to one embodiment of the actual example. The actual example will be described below with reference to Figure 1.

[0044] The packaging substrate 100 according to the embodiment includes a core layer 10, a first electrical conductive layer 20 which is an electrical conductive layer disposed in contact with the upper surface of the core layer 10, and an adhesion-enhancing layer 30 which is disposed on the core layer 10 and surrounds at least a part of the upper surface of the first electrical conductive layer 20.

[0045] core layer The core layer 10 may have the shape of a substrate. A substrate applicable in the field of packaging substrates may be used as the core layer 10.

[0046] The core layer 10 may include through vias (not shown) that penetrate in the thickness direction of the core layer 10.

[0047] A through via consists of an internal space (not shown) and an inner diameter surface of the via (not shown) surrounding the internal space. The internal space is an empty space, and the inner diameter surface of the via refers to the surface of the core layer 10 formed on the inside of the through via.

[0048] The through vias may have a diameter that varies in the thickness direction of the core layer 10. The through vias may have a substantially uniform diameter in the thickness direction of the core layer 10.

[0049] The surface of the core layer 10 may include an upper surface and a side surface connected to the upper surface and formed in the thickness direction of the core layer 10. The surface of the core layer 10 may also include a lower surface facing the upper surface.

[0050] The statement that the side surface is formed in the thickness direction of the core layer 10 is interpreted to mean not only that the side surface is perpendicular to the upper surface of the core layer 10, but also that at least a portion of the side surface forms an angle (angle of inclination) other than 90° with the upper surface.

[0051] The aforementioned side surface may be flat or curved.

[0052] The core layer 10 may be a glass core layer. The glass core layer may have physical properties suitable for realizing an electrically conductive layer with a fine pitch.

[0053] The glass core layer may have the shape of a glass substrate. The glass core layer may, for example, be alkali borosilicate glass, alkali-free borosilicate glass, alkali-free alkaline earth borosilicate glass, or any glass plate used for electronic components. The glass core layer can be made from glass substrates for electronic devices, and for example, those manufactured by Schott, AGC, Corning, etc., may be used, but are not limited to these.

[0054] The thickness of the core layer 10 may be 100 μm or more. The thickness may be 200 μm or more. The thickness may be 300 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. In such cases, the core layer 10 can have mechanical properties suitable for application to the packaging substrate 100.

[0055] Electrical conductive layer The packaging substrate 100 may include an electrical conductive layer disposed on the core layer 10. The electrical conductive layer may include a first electrical conductive layer 20 disposed in contact with the upper surface of the core layer 10, and a second electrical conductive layer (not shown) disposed on the first electrical conductive layer 20.

[0056] An electrical conductive layer is a conductor that transmits electrical signals. An electrical conductive layer can have a patterned shape.

[0057] The electrical conductive layer may contain an electrical conductive material. The electrical conductive layer may have a structure of one or more layers. The electrical conductive layer may include a seed layer (not shown) and a conductive layer (not shown) formed on the seed layer.

[0058] The seed layer is placed on the upper surface of the core layer 10 or between the insulating layer (not shown) and the conductive layer, and can improve the adhesion of the electrically conductive layer to the upper surface of the core layer 10. The seed layer may include a first seed layer placed in contact with the upper surface of the core layer 10 or the insulating layer, and a second seed layer placed on the first seed layer. The first seed layer may be made of a different material than the material applied to the conductive layer. For example, the first seed layer may include titanium, chromium, nickel, etc. The second seed layer may be made of the same material as the material applied to the conductive layer. For example, the second seed layer may include copper.

[0059] The conductive layer may function as a channel for transmitting signals within the packaging substrate 100. The conductive layer may include at least one of copper, nickel, aluminum, gold, and silver. Copper and the like may be used as the material for the conductive layer.

[0060] The first electrical conductive layer 20 may include an upper surface. The Ra value, which is the arithmetic mean roughness of the upper surface of the first electrical conductive layer 20, may be 40 nm or less.

[0061] To increase the adhesion between the conductive layer and the insulating layer, it may be considered to form the surface of the conductive layer rough. However, when high-frequency power is applied to a conductive layer that has been roughened beyond a certain level, the resistance of the conductive layer may become excessively high due to the skin effect.

[0062] One concrete example is to adjust the surface roughness characteristics of the upper surface of the electrical conductive layer, particularly the first electrical conductive layer 20, to a certain level or lower, and to introduce the adhesion-enhancing layer 30, which will be detailed below. Through this, a sufficient amount of the adhesion-enhancing layer is maintained on the upper surface of the first electrical conductive layer 20, thereby improving the adhesion between the first electrical conductive layer 20 and the insulating layer, and providing a first electrical conductive layer 20 suitable for high-frequency power.

[0063] The Ra value, which is the arithmetic mean roughness of the upper surface of the first electrical conductive layer 20, may be 150 nm or less. The Ra value may be 120 nm or less. The Ra value may be 100 nm or less. The Ra value may be 25 nm or more. The Ra value may be 35 nm or more. The Ra value may be 45 nm or more.

[0064] The Ry value, which is the maximum height roughness of the upper surface of the first electrical conductive layer 20, may be 200 nm or less. The Ry value may be 180 nm or less. The Ry value may be 160 nm or less. The Ry value may be 20 nm or more.

[0065] In such cases, the first electrical conduction layer 20 can smoothly transmit signals even when high-frequency power is applied.

[0066] The Ra and Ry values ​​mentioned above shall be measured in accordance with the provisions of the standard ISO 4287:1997.

[0067] The thickness of the first electrical conductive layer 20 may be 10 μm or more. The thickness may be 15 μm or more. The thickness may be 20 μm or more. The thickness may be 50 μm or less.

[0068] The width of the first electrical conductive layer 20 may be 10 μm or more. The width may be 15 μm or more. The width may be 20 μm or more. The width may be 50 μm or less.

[0069] In such cases, the packaging substrate 100 can be made highly integrated and have stable electrical reliability.

[0070] The packaging substrate 100 may include a second electrical conductive layer disposed on the first electrical conductive layer 20. The second electrical conductive layer may be identical to the first electrical conductive layer 20 in terms of composition, roughness, and layer structure. A description of the composition, roughness, and layer structure of the second electrical conductive layer is omitted as it overlaps with the above description.

[0071] The thickness and / or width of the second electrical conductive layer may be smaller than or the same as that of the first electrical conductive layer 20. In this case, a packaging substrate 100 that can be easily electrically connected to the element can be provided.

[0072] The packaging substrate 100 may further include a third electrical conductive layer, which is an electrical conductive layer located beneath the core layer 10. The composition, roughness, and layer structure of the third electrical conductive layer are omitted as they overlap with the above description.

[0073] The thickness and / or width of the third electrical conductive layer may be greater than or the same as that of the first electrical conductive layer 20. In this case, the packaging substrate 100 can transmit signals smoothly to the motherboard.

[0074] Adhesion-enhancing layer In one concrete example, an adhesion-enhancing layer 30 can be introduced on the upper side of the first electrical conductive layer 20. The adhesion-enhancing layer 30 can be placed between the first electrical conductive layer 20 and the insulating layer. The adhesion-enhancing layer 30 can ensure that the insulating layer has stable adhesion to the first electrical conductive layer 20, even if the first electrical conductive layer 20 has a relatively smooth surface.

[0075] The adhesion-enhancing layer 30 may be placed on the core layer 10. The adhesion-enhancing layer 30 may surround at least a portion of the upper surface of the first electrical conductive layer 20. The adhesion-enhancing layer 30 may surround at least a portion of the side surface of the first electrical conductive layer 20. The adhesion-enhancing layer 30 may surround the side surface of the first electrical conductive layer 20.

[0076] The adhesion-enhancing layer 30 can be in contact with the first electrical conductive layer 20 and surround the first electrical conductive layer 20. The adhesion-enhancing layer 30 can be spaced apart from the first electrical conductive layer 20 and surround the first electrical conductive layer 20.

[0077] An embodiment may further include an adhesion-enhancing layer 30 introduced on the upper surface of the second electrical conductive layer. The adhesion-enhancing layer 30 may be placed between the second electrical conductive layer and the insulating layer. In such a case, the insulating layer can exhibit stable adhesion to the second electrical conductive layer without excessive roughening of the second electrical conductive layer.

[0078] The adhesion-enhancing layer 30 can surround at least a portion of the upper surface of the second electrical conductive layer. The adhesion-enhancing layer 30 can surround at least a portion of the side surface of the second electrical conductive layer. The adhesion-enhancing layer 30 can surround the side surface of the second electrical conductive layer.

[0079] The adhesion-enhancing layer 30 can be in contact with the second electrical conduction layer and surround the second electrical conduction layer. The adhesion-enhancing layer 30 can be spaced apart from the second electrical conduction layer and surround the second electrical conduction layer.

[0080] The adhesion-enhancing layer 30 formed in contact with the second electrical conductive layer may be placed on top of the adhesion-enhancing layer 30 formed in contact with the first electrical conductive layer 20. The adhesion-enhancing layer 30 formed in contact with the second electrical conductive layer may form a separate layer that is isolated from the adhesion-enhancing layer 30 formed in contact with the first electrical conductive layer 20.

[0081] The upper surface of the core layer 10 may include an exposed region EA, which is a region where the first electrical conductive layer 20 is not formed. The adhesion-enhancing layer 30 may be positioned in contact with at least a portion of the exposed region EA.

[0082] The upper surface of the core layer 10 can have low roughness characteristics in order to achieve a precise fine pattern. In this case, a sufficient level of anchoring effect may not occur in the portion formed by the contact between the core layer 10 and the insulating layer, and the insulating layer may not exhibit sufficient adhesion to the upper surface of the core layer 10.

[0083] One concrete example is that by placing the adhesion-enhancing layer 30 in contact with at least a portion of the exposed area EA, it may be helpful in ensuring that the insulating layer can be stably maintained on the exposed area EA.

[0084] The adhesion-enhancing layer 30 may be positioned in contact with at least a portion of the exposed area EA.

[0085] An adhesion-enhancing layer 30 positioned in contact with at least a portion of the exposed region EA can be connected to an adhesion-enhancing layer 30 surrounding at least a portion of the upper surface of the first electrical conductive layer 20 to form a single layer. Alternatively, an adhesion-enhancing layer 30 positioned in contact with at least a portion of the exposed region EA can be formed so as not to be connected to an adhesion-enhancing layer 30 surrounding at least a portion of the upper surface of the first electrical conductive layer 20.

[0086] Figure 2 is a cross-sectional view illustrating a packaging substrate according to another embodiment of the concrete example. The concrete example will be described below with reference to Figure 2.

[0087] The packaging substrate 100 includes a core layer 10, a first electrical conductive layer 20 which is an electrical conductive layer disposed in contact with the upper surface of the core layer 10, and an adhesion-enhancing layer 30 which is disposed on the core layer 10 and surrounds at least a portion of the upper surface of the first electrical conductive layer 20. The components of the packaging substrate 100 are the same as those described in Figure 1 above. The differences will be explained below.

[0088] The core layer 10 may include a cavity portion 11, which is a space in which elements are mounted. The cavity portion 11 may include an opening 111 located on the upper surface side of the core layer 10, an inner cavity surface 112 extending from the opening 111 in the thickness direction of the core layer 10, and an element mounting space 113 surrounded by the inner cavity surface 112.

[0089] The statement that the cavity inner surface 112 is formed in the thickness direction of the core layer 10 is interpreted to mean not only that the cavity inner surface 112 is perpendicular to the upper surface of the core layer 10, but also that at least a portion of the cavity inner surface 112 forms an angle (inclination angle) other than 90° with the upper surface.

[0090] The inner surface 112 of the cavity may be flat or it may be a curved surface.

[0091] The element mounting space 113 may be a space formed when the core layer 10 is observed from the top surface, where a portion of the top surface is recessed in the thickness direction. The element mounting space 113 may have a shape that penetrates the core layer 10 in the thickness direction. The element mounting space 113 may have a shape in which a portion of the core layer 10 is recessed in the thickness direction.

[0092] The element 40 is mounted in the element mounting space 113, and the packaging substrate 100 and the element 40 can be electrically connected. The element 40 may be a semiconductor element such as a CPU, GPU, or memory chip, as well as a capacitor element, transistor element, impedance element, or other module. In other words, any semiconductor element that can be mounted on a semiconductor device can be used as the element without limitation.

[0093] In one concrete example, an adhesion-enhancing layer 30 can be formed on the upper surface of the element 40. Through this, the insulating layer can be stably maintained on the cavity portion 11, contributing to the stable electrical reliability of the packaging substrate 100.

[0094] The adhesion-enhancing layer 30 may be positioned in contact with at least a portion of the upper surface of the element 40. The adhesion-enhancing layer 30 positioned in contact with at least a portion of the upper surface of the element 40 may be connected to the adhesion-enhancing layer 30 surrounding at least a portion of the upper surface of the first electrical conductive layer 20 to form a single layer. The adhesion-enhancing layer 30 positioned in contact with at least a portion of the upper surface of the element 40 may be formed to be separated from the adhesion-enhancing layer 30 surrounding at least a portion of the upper surface of the first electrical conductive layer 20. The adhesion-enhancing layer 30 positioned in contact with at least a portion of the upper surface of the element 40 may be connected to the adhesion-enhancing layer 30 surrounding at least a portion of the exposed region EA to form a single layer. The adhesion-enhancing layer 30 positioned in contact with at least a portion of the upper surface of the element 40 may be formed to be separated from the adhesion-enhancing layer 30 surrounding at least a portion of the exposed region EA.

[0095] The adhesion-enhancing layer 30 may include any one selected from the group consisting of silicon-based compounds, acrylic-based compounds, and combinations thereof. When such a composition is applied to the adhesion-enhancing layer 30, a chemical bond may be formed with the insulating layer when it is placed in contact with the insulating layer in a high-temperature environment. Through this, it can contribute to further improving the adhesion strength of the insulating layer to the electrical conductive layer.

[0096] Silicone compounds may include silicone resins. Silicone compounds may also be silicone resins. Silicone resins may be formed by the curing of silicone adhesives. Silicone resins may also be formed by the curing of silane compounds. Silicone resins may also be formed by the curing of a mixture of silicone adhesive and silane compounds.

[0097] The silicone adhesive may be a peroxide-curing type silicone adhesive. The silicone adhesive may also be an addition-reaction type silicone adhesive. Peroxide-curing type silicone adhesives and addition-reaction type silicone adhesives are not limited as long as they are generally applicable in the field of adhesive or bonding technology. For example, peroxide-curing type silicone adhesives may include Dow's DOWSIL SH 4280 and Shin-Etsu's KR-100. For example, addition-reaction type silicone adhesives may include Dow's DOWSIL 4585 and Shin-Etsu's KR-3700.

[0098] Silicon compounds may include silane compounds. The silane compound may be a silane coupling agent, or a silane coupling agent to which functional groups have been added.

[0099] For example, the silane compound may contain, for example, a methoxy group and / or an ethoxy group at one end. The silane compound may also contain an amino group, a vinyl group, an epoxy group, a methacryloxy group, an acryloxy group, a ureido group, a mercapto group, a sulfide group, or an isocyanate group at the other end.

[0100] Acrylic compounds may include acrylic resins. Acrylic compounds may also be acrylic resins. Acrylic compounds may be formed by curing a compound containing any one selected from the group consisting of acrylic monomers, acrylic prepolymers, acrylic resins, and combinations thereof. Acrylic prepolymers may contain acrylate residues. Acrylic resins may contain acrylate residues. Acrylic monomers may be any one selected from the group consisting of acrylate compounds, methacrylate compounds, alkyl group-containing acrylate compounds, alkyl group-containing methacrylate compounds, hydroxyl group-containing acrylate compounds, hydroxyl group-containing methacrylate compounds, siloxane-modified acrylate compounds, siloxane-modified methacrylate compounds, and combinations thereof. The acrylate residue may be derived from any one selected from the group consisting of acrylate compounds, methacrylate compounds, alkyl group-containing acrylate compounds, alkyl group-containing methacrylate compounds, hydroxyl group-containing acrylate compounds, hydroxyl group-containing methacrylate compounds, siloxane-modified acrylate compounds, siloxane-modified methacrylate compounds, and combinations thereof.

[0101] The thickness of the adhesion-enhancing layer 30 may be 1 μm to 25 μm. The thickness may be 3 μm or more. The thickness may be 5 μm or more. The thickness may be 10 μm or more. The thickness may be 20 μm or less. In such cases, it may be helpful to maintain the adhesion between the insulating layer and the first electrical conductive layer 20, etc., at a certain level or higher.

[0102] insulating layer Figure 3 is a cross-sectional view illustrating a packaging substrate according to yet another embodiment of the concrete example. The concrete example will be described below with reference to Figure 3.

[0103] The packaging substrate 100 includes a core layer 10, a first electrical conductive layer 20 which is an electrical conductive layer disposed in contact with the upper surface of the core layer 10, and an adhesion-enhancing layer 30 which is disposed on the core layer 10 and surrounds at least a portion of the upper surface of the first electrical conductive layer 20. The components of the packaging substrate 100 are as described in Figures 1 and 2 above. The differences will be explained below.

[0104] The packaging substrate 100 may further include an insulating layer 50 disposed on the first conductive layer 20. The insulating layer 50 may be disposed in contact with the adhesion-enhancing layer 30. Through this, the insulating layer 50 can be stably fixed to the first conductive layer 20, which has a relatively smooth surface.

[0105] The insulating layer 50 can surround a portion of the first conductive layer 20. The insulating layer 50 can surround at least a portion of the upper surface of the first conductive layer 20. The insulating layer 50 can surround at least a portion of the side surface of the first conductive layer 20.

[0106] The insulating layer 50 and the first conductive layer 20 may be arranged together on the core layer 10. The first conductive layer 20, which has a patterned shape, may be formed in a form embedded within the insulating layer 50.

[0107] The insulating layer 50 can surround at least a portion of the second electrical conductive layer. The insulating layer 50 can surround at least a portion of the upper surface of the second electrical conductive layer. The insulating layer 50 can surround at least a portion of the side surface of the second electrical conductive layer.

[0108] The second electrical conductive layer may be arranged in combination with the insulating layer 50. The second electrical conductive layer having a patterned shape may be formed in a form embedded within the insulating layer 50.

[0109] The packaging substrate 100 of the embodiment may further include an insulating layer 50 disposed beneath the core layer 10. The insulating layer 50 may surround at least a portion of the third conductive layer. The insulating layer 50 may surround at least a portion of the upper surface of the third conductive layer. The insulating layer 50 may surround at least a portion of the side surface of the third conductive layer.

[0110] The third electrical conductive layer may be arranged in combination with the insulating layer 50. The third electrical conductive layer having a patterned shape may be formed in a form embedded within the insulating layer 50.

[0111] The insulating layer 50 is not limited as long as it is generally applicable in the field of packaging substrates. For example, the insulating layer 50 may be an epoxy resin containing a filler. For example, the insulating layer 50 may be formed from a build-up layer material such as Ajinomoto's ABF (Ajinomoto Build-up Film), an undercoat material, etc., but is not limited thereto.

[0112] The insulating layer 50 may be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0113] The packaging substrate 100 may include a multilayer insulating layer comprising an adhesion-enhancing layer 30 and an insulating layer 50. The packaging substrate 100 may include a multilayer insulating layer comprising an adhesion-enhancing layer 30 and an insulating layer 50. The adhesive strength between the first electrical conductive layer 20 and the multilayer insulating layer may be 300 gf / cm or more. The adhesive strength may be 350 gf / cm or more. The adhesive strength may be 400 gf / cm or more. The adhesive strength may be 450 gf / cm or more. The adhesive strength may be 500 gf / cm or more. The adhesive strength may be 550 gf / cm or more. The adhesive strength may be 600 gf / cm or more. The adhesive strength may be 650 gf / cm or more. The adhesive strength may be 1500 gf / cm or less. In such cases, a packaging substrate 100 with excellent durability and electrical reliability can be provided.

[0114] The adhesive strength between the first electrical conductive layer 20 and the multilayer insulating layer is measured using a bond tester by a 180° peel test. The measurement speed (peel speed) is set to 10 mm / s and the measurement distance (peel distance) is set to 70 mm. For example, the value of the adhesive strength can be measured using a Condor Sigma bond tester from XYZ TEC.

[0115] Other components The packaging substrate 100 may further include through electrodes (not shown) disposed within through vias. The through electrodes can electrically connect the first conductive layer 20 and the third conductive layer. The through electrodes may be made of the same material and have the same layer structure as the conductive layers. The through electrodes may have a shape that completely fills the through via, or they may have a shape that is a thin film in contact with the inner diameter surface of the through via.

[0116] In this embodiment, if necessary, an upper connection electrode (not shown) that electrically connects the element and the second electrical conductive layer can be placed on the upper side of the packaging substrate 100. The upper connection electrode may be directly connected to the element via terminals or the like. The upper connection electrode may also be connected to the element via an element connection part such as a solder ball.

[0117] In one embodiment, if necessary, a bottom connection electrode (not shown) that electrically connects the motherboard and the third electrical conductive layer can be placed on the underside of the packaging substrate 100. The bottom connection electrode may be directly connected to the motherboard via terminals or the like. The bottom connection electrode may also be connected to the motherboard via a connection part such as a bump.

[0118] In the embodiment, if necessary, bumps (not shown) may be arranged in a predetermined form beneath the third electrical conductive layer. The bumps may be placed in a portion of the lower surface of the packaging substrate 100 so that they can come into contact with a motherboard or the like.

[0119] Semiconductor packages A semiconductor package according to yet another embodiment of the embodiment includes a packaging substrate and an element electrically connected to the packaging substrate.

[0120] The packaging board can be mounted on the main board and electrically connected to it.

[0121] The same packaging substrates and components described above may be used. The explanation of the packaging substrates and components will be omitted as it will overlap with the previously mentioned content.

[0122] Manufacturing method for packaging substrates A method for manufacturing a packaging substrate according to yet another embodiment of the embodiment includes a preparation step of preparing a preliminary substrate including a core layer and a first electrical conductive layer disposed in contact with the upper surface of the core layer; an adhesion-enhancing layer formation step of forming an adhesion-enhancing layer surrounding at least a portion of the upper surface of the first electrical conductive layer; and a manufacturing step of manufacturing a packaging substrate from the preliminary substrate on which the adhesion-enhancing layer has been formed.

[0123] The surface roughness Ra value of the upper surface of the first electrical conductive layer is 40 nm or less.

[0124] The aforementioned adhesion-enhancing layer contains a silicon-based compound.

[0125] In the preparation step, a spare substrate with the first electrical conductive layer already formed on it may be prepared, or the spare substrate may be provided by forming the first electrical conductive layer on the core layer.

[0126] The explanation of the core layer and the first electrical conduction layer will be omitted as it will overlap with the content described above.

[0127] The first electrical conductive layer can be provided by forming a first seed layer on the upper surface of the core layer, forming a second seed layer on the first seed layer, and forming a conductive layer on the second seed layer.

[0128] The method for forming the seed layer on the core layer is not limited to methods commonly applied in the field of packaging substrates. For example, the seed layer may be formed by PVD (Physical Vapor Deposition), sputtering, electroless plating, etc.

[0129] The explanations of the first and second seed tiers will be omitted as they overlap with the content described above.

[0130] A conductive layer can be formed on the second seed layer by performing a plating process. The plating process is not limited to methods commonly used in the field of packaging substrates. For example, electroless plating can be applied.

[0131] The explanation of the conductive layer will be omitted as it will overlap with the content mentioned above.

[0132] The seed layer can be patterned before forming the conductive layer. Specifically, after forming a resist film on the seed layer, the resist film can be developed along a pre-designed pattern shape, and the conductive layer can be formed through a plating process. The resist film and the development of the resist film are not limited as long as they are commonly used in the field of packaging substrates.

[0133] Subsequently, the formation of the first conductive layer can be completed by removing the developed resist film and the seed layer present in the region where the conductive layer has not been formed. The seed layer can be removed by etching.

[0134] The preparation step may include a surface roughness control process to adjust the roughness of the upper surface of the first conductive layer. In the surface roughness control process, the upper surface of the first conductive layer can be adjusted to have a roughness within a range predetermined in the embodiment. This contributes to improving the adhesion between the insulating layer and the first conductive layer, and also mitigates the degree of increase in the resistance of the first conductive layer due to the application of high-frequency power.

[0135] In the surface roughness control process, a method of oxidizing and reducing the upper surface of the first electrical conductive layer can be applied. For example, the roughness can be adjusted by oxidizing and reducing the upper surface of the first electrical conductive layer using Atotec's Novabond product.

[0136] During the surface roughness control process, the upper surface of the first electrical conductive layer can be etched. The etching may be performed using wet etching or dry etching.

[0137] The explanation of the surface roughness of the upper surface of the first conductive layer, which is adjusted through the surface roughness control process, will be omitted as it will overlap with the content described above.

[0138] In the adhesion-enhancing layer formation step, the adhesion-enhancing layer can be formed so as to surround at least a portion of the upper surface of the first electrical conductive layer. In addition, in the adhesion-enhancing layer formation step, the adhesion-enhancing layer can be formed so as to be in contact with at least a portion of the exposed area on the upper surface of the core layer. If the packaging substrate includes the cavity portion and the element mounted in the cavity portion, in the adhesion-enhancing layer formation step, the adhesion-enhancing layer can be formed so as to be positioned in contact with at least a portion of the upper surface of the element.

[0139] The explanation of the location, shape, thickness, and composition of the adhesion-enhancing layer will be omitted as it will overlap with the content described above.

[0140] The adhesion-enhancing layer formation step may include a placement step of arranging an adhesion-enhancing layer manufacturing composition that surrounds at least a portion of the upper surface of the first electrical conductive layer, and a heat treatment step of heat-treating the adhesion-enhancing layer manufacturing composition to form an adhesion-enhancing layer.

[0141] During the arrangement process, a multilayer film for manufacturing an adhesion-enhancing layer can be prepared in which the adhesion-enhancing layer manufacturing composition is arranged on a release film. The multilayer film can be laminated on a pre-substrate so that the surface on which the adhesion-enhancing layer manufacturing composition is arranged faces the upper surface of the first electrical conductive layer, thereby arranging the adhesion-enhancing layer manufacturing composition. However, the method of arranging the adhesion-enhancing layer manufacturing composition is not limited to this, and a method in which the adhesion-enhancing layer manufacturing composition is applied to the upper surface of the first electrical conductive layer and then cured to form an adhesion-enhancing layer can also be applied.

[0142] The composition for manufacturing the adhesion-enhancing layer may contain a silicone adhesive. The composition for manufacturing the adhesion-enhancing layer may contain a silane compound. The composition for manufacturing the adhesion-enhancing layer may contain both a silicone adhesive and a silane compound. The explanation of the silicone adhesive and silane compound is omitted as it overlaps with the above.

[0143] The composition for producing the adhesion-enhancing layer may contain an acrylic compound. The acrylic compound may include any one selected from the group consisting of acrylic monomers, acrylic prepolymers, acrylic resins, and combinations thereof. The descriptions of acrylic monomers, acrylic prepolymers, and acrylic resins are omitted as they overlap with the above.

[0144] The composition for producing an adhesion-enhancing layer may further contain additives commonly used in the fields of adhesion and bonding. For example, the composition for producing an adhesion-enhancing layer may further contain curing agents, antioxidants, heat stabilizers, and the like.

[0145] During the heat treatment process, the adhesion-enhancing layer can be further improved by heat-treating a preliminary substrate on which the adhesion-enhancing layer manufacturing composition is placed to form the adhesion-enhancing layer.

[0146] In the heat treatment process, the heat treatment temperature may be 100°C or higher. The heat treatment temperature may be 110°C or higher. The heat treatment temperature may be 120°C or higher. The heat treatment temperature may be 130°C or higher. The heat treatment temperature may be 250°C or lower.

[0147] In the heat treatment process, the heat treatment time may be 10 seconds or more. The heat treatment time may be 15 seconds or more. The heat treatment time may be 20 seconds or more. The heat treatment time may be 30 seconds or more. The heat treatment time may be 30 minutes or less. The heat treatment time may be 20 minutes or less. The heat treatment time may be 10 minutes or less.

[0148] In such cases, the adhesion strength of the bonding reinforcement layer to the insulating layer can be further improved.

[0149] In the manufacturing step, a packaging substrate can be manufactured from a pre-substrate on which an adhesion-enhancing layer has been formed.

[0150] The manufacturing step may include an insulating layer formation process that forms an insulating layer in contact with the upper surface of the adhesion-enhancing layer.

[0151] After heat treatment, an insulating layer-forming film can be laminated onto the adhesion-enhancing layer and then cured to form an insulating layer, or an insulating layer-forming composition can be applied onto the adhesion-enhancing layer and then cured to form an insulating layer.

[0152] The insulating layer-forming film or composition is not limited as long as it is commonly used in the build-up field. Specifically, the insulating layer-forming film or composition may be an epoxy resin-based film or composition.

[0153] The insulating layer may be formed in contact with the upper surface of the adhesion-enhancing layer. The insulating layer may be formed so as to surround the upper surface of the core layer.

[0154] In the embodiment, a second electrical conductive layer may be formed on the insulating layer as needed. The second electrical conductive layer can be formed in the same manner as the first electrical conductive layer, except that a width and thickness of a predetermined size are applied.

[0155] An adhesion-enhancing layer can be formed so as to surround at least a portion of the upper surface of the second electrical conductive layer. The adhesion-enhancing layer can be formed by the same method as the method for forming an adhesion-enhancing layer so as to surround at least a portion of the upper surface of the first electrical conductive layer.

[0156] After forming an adhesion-enhancing layer on the second electrical conductive layer, an insulating layer can be formed in contact with the upper surface of the adhesion-enhancing layer. The insulating layer can be formed by the same method as described above.

[0157] If necessary, a third conductive layer, an adhesion-enhancing layer surrounding at least a portion of the upper surface of the third conductive layer, and an insulating layer surrounding the adhesion-enhancing layer can be formed below the glass core layer. The third conductive layer can be formed in the same manner as the first conductive layer and / or the second conductive layer. However, the third conductive layer may differ from the first or second conductive layer in terms of width and / or thickness.

[0158] The method for manufacturing a packaging substrate may further include steps of forming connection terminals, bumps, cover layers, etc., on the upper and / or lower surfaces of the packaging substrate, or mounting elements onto the substrate.

[0159] The following examples will provide a more detailed explanation of the implementation through specific embodiments. These embodiments are merely illustrative to aid in understanding the implementation, and the scope of implementation is not limited to them.

[0160] Manufacturing example: Formation of packaging substrates Example 1: A first seed layer, which is a titanium layer with a thickness of 150 nm, was formed on a core layer which is a glass substrate by PVD, and a second seed layer, which is a copper layer with a thickness of 150 nm, was formed on the first seed layer by PVD. A conductive layer, which is a copper layer with a thickness of 30 μm, was formed on the seed layer for conductive layer formation by an electroless plating process to form a first electrical conductive layer.

[0161] The upper surface of the first conductive layer was roughened using Atotec's Novabond product, and a spare substrate was prepared. Subsequently, the Ra value of the roughened upper surface of the first conductive layer was measured in accordance with the provisions of standard ISO 4287:1997. Nitto Denko's polyimide tape, PI Carrier Adhesive Tape AS-020PI12 model, was attached to the roughened first conductive layer.

[0162] After the preliminary substrate with the adhesion-enhancing layer formed on it was heat-treated at 150°C for 30 seconds to 5 minutes, the polyimide film, which is the release film, was removed to form the adhesion-enhancing layer.

[0163] After laminating Ajinomoto's build-up layer onto the adhesion-enhancing layer, it was cured at 150°C for 60 minutes to form an insulating layer, completing the packaging substrate.

[0164] Example 2: A packaging substrate was manufactured under the same conditions as in Example 1, except that the upper surface of the first conductive layer was roughened with MAC's CZ8101 model etching solution.

[0165] Example 3: A packaging substrate was manufactured under the same conditions as in Example 1, except that the upper surface of the first electrical conductive layer was not roughened and 3-methacrylateoxypropyltrimethoxysilane, a silane coupling agent, was vacuum-deposited to a thickness of 2 nm to 3 nm.

[0166] Comparative Example 1: A packaging substrate was manufactured under the same conditions as in Example 1, except that no additional roughening or compound surface treatment was performed on the upper surface of the first electrical conductive layer.

[0167] The Ra values ​​measured from the top surface of the first electrical conductive layer for each example and comparative example are shown in Table 1 below.

[0168] Evaluation Example: Evaluation of the adhesive strength between the first electrical conductive layer and the multilayer insulating layer. The adhesive strength between the first conductive layer and the multilayer insulating layer (composed of an adhesion-enhancing layer and an insulating layer) was measured using a 180° peel test with an XYZ TEC Condor Sigma bond tester. The measurement speed (peeling speed) was set to 10 mm / s, and the measurement distance (peeling distance) was set to 70 mm.

[0169] The measured values ​​for each example and comparative example are shown in Table 1 below.

[0170] Evaluation example: Evaluation of long-term durability After leaving the packaging substrates for each example and comparative example at 150°C for 1000 hours, the presence or absence of delamination of the insulating layer on the core layer was evaluated. A rating of P was given if no delamination of the insulating layer occurred, and an F rating was given if delamination occurred.

[0171] The measured values ​​for each example and comparative example are shown in Table 1 below.

[0172] [Table 1]

[0173] In Table 1, Examples 1 to 3 showed an adhesive strength of 400 gf / cm or more and were rated P in the durability evaluation, whereas Comparative Example 1 showed an adhesive strength of 200 gf / cm or less and was rated F in the durability evaluation. This is thought to be because, in the case of Comparative Example 1, the surface of the first conductive layer was not roughened, so a sufficient amount of the adhesion-enhancing layer did not remain on the surface of the first conductive layer, resulting in the insulating layer not being stably adhered to the first conductive layer.

[0174] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of Symbols]

[0175] 100 Packaging substrates 10 core layers 11 Cavity section 111 Aperture 112 Inner surface of the cavity 113 Element mounting space 20 First electrical conduction layer 30 Adhesion-enhancing layer 40 elements 50 Insulating layer EA exposure area

Claims

1. The material includes a core layer, a first electrical conductive layer which is an electrical conductive layer disposed in contact with the upper surface of the core layer, and an adhesion-enhancing layer which is disposed on the core layer and surrounds at least a portion of the upper surface of the first electrical conductive layer. The adhesion-enhancing layer comprises one selected from the group consisting of silicon-based compounds, acrylic-based compounds, and combinations thereof. A packaging substrate having an arithmetic mean roughness Ra value of 150 nm or less on the upper surface of the first electrical conductive layer.

2. The packaging substrate according to claim 1, wherein the silicon-based compound comprises a silicon resin.

3. The packaging substrate according to claim 1, wherein the Ry value, which is the maximum height roughness of the upper surface of the first electrical conductive layer, is 200 nm or less.

4. The aforementioned core layer is a glass core layer, The upper surface of the core layer includes an exposed region in which the first electrical conductive layer is not formed. The packaging substrate according to claim 1, wherein the adhesion-enhancing layer is disposed in contact with at least a portion of the exposed area.

5. The core layer includes a cavity, which is a region in which elements are mounted. The cavity portion includes an opening located on the upper surface side of the core layer, an inner cavity surface formed extending from the opening in the thickness direction of the core layer, and an element mounting space surrounded by the inner cavity surface. Includes elements arranged in the aforementioned element mounting space, The packaging substrate according to claim 1, wherein the adhesion-enhancing layer is disposed in contact with at least a portion of the upper surface of the element.

6. The packaging substrate according to claim 1, wherein the thickness of the adhesion-enhancing layer is 1 μm to 25 μm.

7. The packaging substrate according to claim 1, further comprising an insulating layer disposed in contact with the adhesion-enhancing layer.

8. The multilayer insulating layer includes the aforementioned adhesion-enhancing layer and the aforementioned insulating layer, The packaging substrate according to claim 7, wherein the adhesive strength between the first electrical conductive layer and the multilayer insulating layer is 300 gf / cm or more.

9. The process includes a preparation step of preparing a preliminary substrate including a core layer and a first electrical conductive layer disposed in contact with the upper surface of the core layer; an adhesion-enhancing layer formation step of forming an adhesion-enhancing layer surrounding at least a portion of the upper surface of the first electrical conductive layer; and a manufacturing step of manufacturing a packaging substrate from the preliminary substrate on which the adhesion-enhancing layer has been formed. The surface roughness Ra value of the upper surface of the first electrical conductive layer is 150 nm or less. A method for manufacturing a packaging substrate, wherein the adhesion-enhancing layer comprises one selected from the group consisting of silicon-based compounds, acrylic-based compounds, and combinations thereof.

10. The method for manufacturing a packaging substrate according to claim 9, wherein the preparation step includes a surface roughness control step for adjusting the roughness of the upper surface of the first electrical conductive layer.

11. The method for manufacturing a packaging substrate according to claim 9, wherein the adhesion strengthening layer formation step includes an arrangement step of arranging the adhesion strengthening layer manufacturing composition so as to surround at least a portion of the upper surface of the first electrical conductive layer, and a heat treatment step of heat treating the adhesion strengthening layer manufacturing composition to form an adhesion strengthening layer.

12. The method for manufacturing a packaging substrate according to claim 9, wherein the manufacturing step includes an insulating layer forming step of forming an insulating layer that is disposed in contact with the upper surface of the adhesion-enhancing layer.

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