Memory system

Abstract

We provide a high-performance memory system. [Solution] The memory system comprises a memory controller and NAND flash memory (NAND memory). Each of the multiple memory chips of the NAND memory contains multiple first storage areas. The multiple first memory chips among the multiple memory chips are connected to each of the multiple channels. The memory controller performs a storage operation to store first data in a group of second storage areas, which are one of the multiple first storage areas of each of the multiple first memory chips. In the storage operation, the memory controller generates parity data corresponding to the first data. In addition, partial parity data, which is a part of the parity data, is stored in each of the second storage areas of each of the multiple first memory chips, and the partial parity data and partial first data, which is a part of the first data, are stored in the second storage area of ​​one or more second memory chips.

Description

Technical Field

[0001] This embodiment relates to a memory system.

Background Art

[0002] In a memory system such as an SSD (Solid State Drive), a memory controller is configured to be able to execute data read and write operations on a plurality of memory chips connected to different channels in parallel by controlling the plurality of channels in parallel. Further, the memory controller performs error correction coding on a data block including a plurality of data written in parallel to the plurality of memory chips. Thereby, even if one of the plurality of memory chips in which data is written in parallel becomes inoperable, the data stored in that one memory chip can be restored.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a memory system with high performance.

Means for Solving the Problems

[0005] According to one embodiment, the memory system comprises a plurality of channels, a plurality of memory chips, and a memory controller. The memory controller is electrically connected to the plurality of memory chips via the plurality of channels. Each of the plurality of memory chips contains a plurality of first storage areas. The plurality of first memory chips among the plurality of memory chips are connected to each of the plurality of channels. The number of the plurality of first memory chips is equal to the number of the plurality of channels. The memory controller performs a storage operation to store first data for a first group. The first group is a group of second storage areas, which are one of the plurality of first storage areas of each of the plurality of first memory chips. In the storage operation, the memory controller performs the following operations: The memory controller generates parity data corresponding to the first data by performing error correction coding on the first data. The memory controller stores partial parity data, which is part of the parity data, in any of the second storage areas of each of the plurality of first memory chips. The memory controller stores the partial parity data and partial first data, which is part of the first data, in the second storage area of ​​one or more second memory chips among the plurality of first memory chips. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example configuration of a memory system according to the first embodiment. [Figure 2] A schematic diagram showing an example of the configuration of a memory chip according to the first embodiment. [Figure 3] A diagram showing the circuit configuration of a physical block according to the first embodiment. [Figure 4] A figure showing an example of data coding and threshold voltage distribution according to the first embodiment. [Figure 5] A diagram showing an example of the configuration of a logic block according to the first embodiment. [Figure 6] A diagram illustrating an example of the structure of a logical page according to the first embodiment. [Figure 7] A diagram illustrating an example of data stored in a logical page according to the first embodiment. [Figure 8] A diagram showing an example of a data-out command sequence according to the second embodiment. [Figure 9] A diagram illustrating an example of the arrangement of parity clusters according to the second embodiment. [Figure 10] A diagram illustrating an example of parity cluster arrangement in Modification Example 1. [Figure 11] A diagram illustrating an example of parity cluster arrangement in Modification Example 2. [Modes for carrying out the invention]

[0007] The memory system according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (First embodiment) Figure 1 shows an example of the configuration of a memory system according to the first embodiment.

[0009] Memory system 1 is connectable to host 2 via communication channel 3. Host 2 includes, for example, a CPU (Central Processing Unit), a personal computer, a portable computer, a server, or a mobile communication device. Memory system 1 non-volatilely stores data input from host 2.

[0010] The memory system 1 comprises a memory controller 10, a NAND-type flash memory (NAND memory) 20, and RAM (Random Access Memory) 30. The NAND memory 20 is a non-volatile memory used as storage.

[0011] RAM30 is a volatile memory capable of faster operation than NAND memory 20. RAM30 stores management information used by the memory controller 10 to control NAND memory 20, and buffers data transferred between host 2 and NAND memory 20.

[0012] Note that any type of memory can be applied as the RAM 30. For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof can be applied as the RAM 30. The RAM 30 may be incorporated in the memory controller 10.

[0013] The memory controller 10 includes a CPU (Central Processing Unit) 11, a host interface (host I / F) circuit 12, a RAM controller (RAMC) 13, a NAND controller (NANDC) 14, and an ECC (Error Correction Code) circuit 15. The CPU 11, the host I / F circuit 12, the RAMC 13, the NANDC 14, and the ECC circuit 15 are electrically connected via a bus.

[0014] The memory controller 10 can be configured as a SoC (System-on-a-Chip). The memory controller 10 can also be configured as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). Alternatively, the memory controller 10 can be configured by a plurality of chips.

[0015] The host I / F circuit 12 executes control of signals transferred via the communication path 3. The host I / F circuit 12 receives various commands from the host 2. The host I / F circuit 12 executes, for example, data transfer between the host 2 and the RAM 30. The RAMC 13 controls the RAM 30. The NANDC 14 controls the NAND memory 20. The NANDC 14 executes, for example, data transfer between the RAM 30 and the NAND memory 20.

[0016] The CPU 11 is a processor that executes the control of the entire memory controller 10. The CPU 11 executes the control based on a firmware program.

[0017] Note that part or all of the control executed by the CPU 11 may be executed by a dedicated hardware circuit. The functions of each part of the memory controller 10 may be realized by the CPU 11 executing firmware.

[0018] The ECC circuit 15 performs error correction coding on the data written to the NAND memory 20. The ECC circuit 15 performs decoding on the data read from the NAND memory 20 to detect and correct errors that may be included in the data. An example of error correction coding by the ECC circuit 15 will be described later.

[0019] The NAND memory 20 includes a plurality of memory chips 21. In FIG. 1, to avoid complication of the drawing, the memory chips 21 are simply denoted as chips 21. Each of the plurality of memory chips 21 is electrically connected to any one of the plurality of channels ch. Also, the number of memory chips 21 connected to each of the plurality of channels ch may be common for all channels ch or may be different between channels ch.

[0020] Each channel ch is composed of a group of signal lines conforming to a certain standard. For example, the group of signal lines includes I / O signal lines and a control signal line group. The I / O signal lines are signal lines for transferring data, addresses, and commands. Note that the bit width of the I / O signal lines is not limited to 1 bit. The control signal line group is a group of signal lines for transferring a WE (write enable) signal, a RE (read enable) signal, a CLE (command latch enable) signal, an ALE (address latch enable) signal, a DQS (data strobe) signal, a WP (write protect) signal, etc. Note that the configuration of each channel ch is not limited to this example.

[0021] The memory controller 10 is electrically connected to multiple memory chips 21 via multiple channels ch. The memory controller 10 can control each channel ch individually. By simultaneously and individually controlling multiple channels ch, the memory controller 10 can operate multiple memory chips 21 connected to different channels ch in parallel. In other words, the memory controller 10 can issue access instructions to multiple memory chips 21 connected to different channels ch simultaneously. Access instructions include write instructions, read instructions, and erase instructions. Operating multiple memory chips 21 connected to different channels ch in parallel is referred to as channel parallel operation.

[0022] In the example shown in Figure 1, the memory system 1 has 18 channels (ch.0 to ch.17). Two memory chips 21 are connected to each channel. Therefore, the memory controller 10 can simultaneously control up to 18 memory chips 21 connected to different channels through channel parallel operation.

[0023] Multiple banks 22 are defined for the NAND memory 20. Each bank 22 consists of multiple (18 in this case) memory chips 21 connected to different channels ch. Multiple (2 in this case) memory chips 21 connected to one channel ch each belong to a different bank 22. In other words, the NAND memory 20 has two banks 22 (bank #0 and bank #1).

[0024] The memory controller 10 performs bank interleaving using two banks 22. Bank interleaving is a type of parallel operation. In bank interleaving, while multiple (e.g., 18) memory chips 21 belonging to one bank 22 are accessing data, the memory controller 10 issues access commands to multiple (e.g., 18) memory chips 21 belonging to another bank 22. This reduces the total time required for data transfer between the NAND memory 20 and the memory controller 10. Parallel operation using bank interleaving is referred to as bank parallel operation.

[0025] Multiple memory chips 21 included in the NAND memory 20 share a common configuration. Figure 2 is a schematic diagram showing an example of the configuration of a memory chip 21 according to the first embodiment.

[0026] The memory chip 21 includes a memory cell array 23. The memory cell array 23 is divided into a plurality of sub-arrays 24. Each of the sub-arrays 24 forms a plane P together with one of a plurality of peripheral circuits (not shown) provided in the memory chip 21. Each peripheral circuit includes a row decoder, a column decoder, and a page buffer, etc. In the example shown in Figure 2, the memory chip 21 includes four planes P0 to P3. Each of the four planes P0 to P3 includes one sub-array 24.

[0027] The number of planes P on the memory chip 21 is arbitrary. The memory chip 21 does not need to have multiple planes P. If the memory chip 21 does not have multiple planes P, the memory cell array 23 is not divided into multiple sub-arrays 24.

[0028] The memory chip 21 has independent peripheral circuits for each plane P. Therefore, the memory chip 21 can access the subarrays 24 of each plane P in parallel. Access includes write operations, read operations, and erase operations. The operation of accessing the subarrays 24 of multiple planes P in parallel is referred to as plane parallel operation.

[0029] Each subarray 24 comprises multiple physical blocks 25. A physical block 25 is a unit of erase operation in the memory cell array 23.

[0030] Multiple physical blocks 25 have the same configuration. Figure 3 shows the circuit configuration of a physical block 25 according to the first embodiment.

[0031] The physical block 25 has, for example, four string units SU0 to SU3. Each string unit SU contains multiple NAND strings 26.

[0032] Each of the NAND strings 26 contains, for example, 14 memory cell transistors MT (MT0 to MT13) and selection transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer to non-volatilely retain data. The 14 memory cell transistors MT (MT0 to MT13) are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The memory cell transistors MT may be of the MONOS (Metal Oxide Nitride Oxide Silicon) type with an insulating film in the charge storage layer, or of the FG (Floating Gate) type with a conductive film in the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 26 is not limited to 14.

[0033] The gates of the selection transistor ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistor ST2 in each of the string units SU0 to SU3 are connected in common to, for example, the selection gate line SGS. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 may be connected to different selection gate lines SGS0 to SGS3 (not shown) for each string unit SU. The control gates of the memory cell transistors MT0 to MT13 within the same physical block 25 are connected in common to the word lines WL0 to WL13, respectively.

[0034] The drains of the selection transistor ST1 of each NAND string 26 within the string unit SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number greater than or equal to 2). Furthermore, the bit lines BL connect one NAND string 26 within each string unit SU to multiple physical blocks 25. Additionally, the sources of each selection transistor ST2 are connected to a common source line SL.

[0035] In other words, a string unit SU is a collection of NAND strings 26 connected to different bit lines BL and the same selected gate line SGD. A physical block 25 is a collection of multiple string units SU that share a common word line WL. A subarray 24 is a collection of multiple physical blocks 25 that share a common bit line BL.

[0036] As mentioned above, the data erasure operation on the subarray 24 is performed in units of physical blocks 25.

[0037] Furthermore, write operations to the sub-array 24 (specifically, program operations) and read operations from the sub-array 24 (specifically, sense operations) are performed collectively on the memory cell transistor MT connected to a single word line WL in a single string unit SU. Hereinafter, the group of memory cell transistors MT selected collectively during program and sense operations will be called the memory cell group MCG. The collection of storage areas for 1 bit of data stored in each memory cell transistor MT included in a single memory cell group MCG will be called a physical page.

[0038] Each memory cell transistor (MT) may be configured to store multiple bits of data. For example, if each memory cell transistor (MT) can store n (n≧2) bits of data, the memory cell group (MCG) contains n physical pages of storage space, and the storage capacity per memory cell group (MCG) is equal to the size of n physical pages. Here, as an example, we will describe a configuration in which 3 bits of data are stored in each memory cell transistor (MT). In this configuration, each memory cell group (MCG) holds data equivalent to 3 physical pages.

[0039] Figure 4 shows an example of data coding and threshold voltage distribution according to the first embodiment. The horizontal axis represents the threshold voltage of the memory cell transistor MT. The eight lobes shown in Figure 4 schematically represent the threshold voltage distribution. The eight threshold voltage distributions are each threshold voltage regions, also referred to as states. The eight states correspond to 3-bit data. In the example shown in this figure, the Er state corresponds to the data "111", the A state corresponds to the data "110", the B state corresponds to the data "100", the C state corresponds to the data "000", the D state corresponds to the data "010", the E state corresponds to the data "011", the F state corresponds to the data "001", and the G state corresponds to the data "101". The first digit of each data is defined as the MSB (Most Significant Bit). The last digit of each data is defined as the LSB (Least Significant Bit). Note that the correspondence between states and data is not limited to this.

[0040] The threshold voltage of each memory cell transistor MT is controlled to belong to one of eight states. The threshold voltage of each memory cell transistor MT is set to the Er state by the erase operation and then set to a state from A to G depending on the data by the program operation.

[0041] In sense operation, the state to which the threshold voltage of each memory cell transistor MT belongs is determined by comparing several read levels applied to the control gate via the word line WL with the threshold voltage. Then, data corresponding to the determined state is read out.

[0042] The memory area where the LSB data is stored within the three physical pages of a single memory cell group (MCG) is referred to as the lower page. The memory area where the MSB data is stored within the three physical pages is referred to as the upper page. The memory area where the data between the LSB and MSB is stored within the three physical pages is referred to as the middle page. The classification of lower pages, middle pages, and upper pages is referred to as the page type.

[0043] The data coding applicable to the first embodiment is not limited to the examples described above. Furthermore, the size of the data stored in each memory cell transistor MT is not limited to 3 bits.

[0044] Each physical page contains multiple clusters. A logical address is assigned to each predetermined-sized area (e.g., a sector) in the logical address space provided to host 2. This predetermined-sized area to which a logical address is assigned is referred to as a unit area. A cluster is a storage area in the NAND memory 20 that corresponds to a unit area in the logical address space. The size of the unit area and the size of the cluster may be the same or different.

[0045] Furthermore, each physical page is mapped to a column address space. More specifically, multiple bit lines BL (for example, bit lines BL0 to BL(L-1) in Figure 3) are assigned consecutive column addresses, allowing the position within each physical page to be specified by the column address. The memory controller 10 specifies the position of each cluster within each physical page by the column address. Hereafter, a group of consecutive column addresses assigned to a single physical page will be referred to as the unit column address space. Note that the unit column address space is just one example of a unit space. Also, a memory cell transistor MT connected to a bit line BL specified by a certain column address will be referred to as the memory cell transistor MT of that column address, and the column address specifying a bit line BL connected to a certain memory cell transistor MT will be referred to as the column address of that memory cell transistor MT.

[0046] Hereafter, among the multiple clusters contained in a physical page, the cluster containing the memory cell transistor MT at the first column address of the unit column address space will simply be referred to as the "first cluster." Similarly, among the multiple clusters contained in a physical page, the cluster containing the memory cell transistor MT at the last column address of the unit column address space will simply be referred to as the "last cluster." Furthermore, the cluster containing the memory cell transistor MT at the column address immediately following the largest column address among the multiple memory cell transistors MT contained in the first cluster will simply be referred to as the "second cluster from the beginning." The same applies to the Nth cluster from the beginning (where N is an integer greater than or equal to 3).

[0047] As mentioned above, the memory system 1 is capable of channel-parallel operation, bank-parallel operation, and plane-parallel operation. The memory controller 10 manages a group of physical blocks 25 that can be accessed in parallel by channel-parallel operation, bank-parallel operation, or plane-parallel operation as a single logical block. The memory controller 10 then performs erase operations on a logical block basis. A logical block is also called a superblock.

[0048] Figure 5 shows an example of the configuration of a logic block according to the first embodiment. For example, one physical block 25 is selected for each combination of channel ch to which the memory chip 21 is connected, bank to which the memory chip 21 belongs, and plane P, as shown by the hatched physical blocks 25 in Figure 5. The group of physical blocks 25 selected for each combination of channel ch to which the memory chip 21 is connected, bank 22 to which the memory chip 21 belongs, and plane P is considered to be one logic block. The memory controller 10 can perform erase operations in parallel on the group of physical blocks 25 that constitute the logic block.

[0049] Hereafter, the combination of Channelch to which the memory chip 21 is connected, Bank 22 to which the memory chip 21 belongs, and Plane P will be referred to as the combination of Channelch, Bank 22, and Plane P.

[0050] For a group of physical blocks 25 that constitute a logical block, the memory controller 10 can perform write and read operations in parallel using one of the following methods: channel parallel operation, bank parallel operation, or plane parallel operation. More specifically, a logical page is composed of a group of one or more physical pages 27 collected from each of the physical blocks 25 that constitute a single logical block. The memory controller 10 can then perform write or read operations on a logical page basis. A logical page is also called a superpage.

[0051] Figure 6 is a diagram illustrating an example of the configuration of a logical page according to the first embodiment.

[0052] In the example shown in Figure 6, three physical pages 27 are selected for each combination of channel ch, bank 22, and plane P: a lower page physical page 27, a middle page physical page 27, and an upper page physical page 27. Then, a logical page 40 is formed by the group of physical pages 27 collected for all combinations of channel ch, bank 22, and plane P, using the three physical pages 27 selected for each combination of channel ch, bank 22, and plane P.

[0053] The memory controller 10 performs error correction coding on the data stored in a single logical page 40 using the ECC circuit 15. Specifically, the memory controller 10 performs error correction coding on data blocks containing multiple data stored in multiple memory chips 21, each connected to at least different channels ch of the data stored in a single logical page 40. This type of error correction coding is referred to as cross-channel error correction coding.

[0054] Any algorithm can be used as the cross-channel error correction coding algorithm. For example, the ECC circuit 15 can perform coding using RS coding (Reed-Solomon Coding) as the cross-channel error correction coding.

[0055] The error correction code obtained by cross-channel error correction coding is simply referred to as parity data. The original data to which cross-channel error correction coding is applied, i.e., the data sent from host 2, is simply referred to as user data. Note that the data before cross-channel error correction coding is applied may have been pre-coded with an error correction coding different from that of cross-channel error correction coding, for example, by the ECC circuit 15. That is, the user data in this application may include error correction codes generated by an error correction coding different from that of cross-channel error correction coding. The error correction coding different from that of cross-channel error correction coding may be, for example, an error correction coding in units of 27 physical pages.

[0056] Figure 7 illustrates an example of data stored in a logical page 40 according to the first embodiment. In this figure, the storage areas constituting the logical page 40 are shown in units of clusters. One physical page 27 is assumed to contain four clusters as an example. The order of the four clusters in each physical page 27 corresponds to the order of the column addresses. The number of clusters contained in one physical page 27 is not limited to four.

[0057] In the example shown in Figure 7, one logical page 40, corresponding to a combination of 18 channels (ch), 2 banks, 4 planes (P), 3 physical pages per memory cell group (MCG), and 4 clusters per physical page, contains 18 × 2 × 4 × 3 × 4 = 1728 clusters.

[0058] User data stored in a single cluster is referred to as a cluster data fragment. A cluster where parity data is stored is referred to as a parity cluster.

[0059] Clusters contained in the lower pages of plane P0 or the middle pages of plane P2 are denoted as cluster C0. The group of clusters C0 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all clusters C0 except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in cluster C0.

[0060] Clusters contained in the lower pages of plane P1 or the middle pages of plane P3 are denoted as cluster C1. The group of clusters C1 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all clusters C1 except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in the group of clusters C1.

[0061] Clusters contained in the lower pages of plane P2 or the upper pages of plane P0 are denoted as cluster C2. The group of clusters C2 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all clusters C2 except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in the group of clusters C2.

[0062] Clusters contained in the lower pages of plane P3 or the upper pages of plane P1 are denoted as cluster C3. The group of cluster C3 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all cluster C3 groups except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in the group of cluster C3.

[0063] Clusters contained in the middle pages of plane P0 or the upper pages of plane P2 are denoted as cluster C4. The group of cluster C4 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all cluster C4 groups except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in the group of cluster C4.

[0064] Clusters contained in the middle pages of plane P1 or the upper pages of plane P3 are denoted as cluster C5. The group of cluster C5 contains eight parity clusters. The memory controller 10 performs cross-channel error correction coding on the group of cluster data fragments stored in all cluster C5 groups except for the parity clusters, and generates parity data for eight clusters. The memory controller 10 stores the generated parity data for eight clusters in the eight parity clusters contained in the group of cluster C5.

[0065] Thus, in the example shown in Figure 7, a total of 48 out of 1728 clusters in one logical page 40 are used as parity clusters, and user data is stored in the remaining 1680 clusters.

[0066] The memory controller 10 may perform a read operation on the logical page 40 in response to a read command from the host 2. Such a read operation is referred to as a logical page read operation. In a logical page read operation, the memory controller 10 performs the read of all cluster data fragments stored in the target logical page in parallel on 18 channels ch. To improve the response speed to the host 2, it is desirable to increase the efficiency of the logical page read operation, that is, to reduce the time required for the logical page read operation.

[0067] A technology comparable to the embodiment will be described. A technology comparable to the embodiment will be referred to as a comparative example. According to the comparative example, 24 of the 48 parity clusters contained in one logical page are located on one memory chip connected to one channel, and the remaining 24 parity clusters are located on one memory chip connected to another channel. In other words, the 18 channels include 16 channels in which no parity clusters are located on any of the memory chips connected to them, and 2 channels in which 24 parity clusters are located on one memory chip connected to them.

[0068] The time required to read user data in a single channel increases with the amount of user data written through that channel. In other words, the time required to read user data in a single channel increases as the amount of parity data written through that channel decreases.

[0069] Furthermore, the time required for a logical page read operation depends on the longest time required for reading user data through each of the 18 channels. Therefore, according to the comparative example, the time required for a logical page read operation is equal to the time required for reading user data on a channel in which no parity cluster is located on any of the connected memory chips.

[0070] Hereafter, the placement of parity clusters on memory chips connected to a channel will be referred to as "distribution of parity clusters to the channel."

[0071] In this embodiment, the 48 parity clusters contained in one logical page 40 are arranged so that they are distributed as evenly as possible across the 18 channels ch. As a result, as shown in Figure 7, each of the 18 channels ch is allocated two or three parity clusters.

[0072] The time required to read user data in a channel ch with two parity clusters is longer than the time required to read user data in a channel ch with three parity clusters, but shorter than the time required for user data in a channel with no parity clusters. Therefore, according to this embodiment, the longest time required to read user data among the 18 channels ch is shortened compared to the comparative example. As a result, the efficiency of the logical page read operation is improved compared to the comparative example. In other words, the performance is higher than that of the comparative example.

[0073] In the example shown in Figure 7, for channels ch.0 and ch.1, the first cluster C2 on the upper page of plane P0 of the memory chip 21 belonging to bank #1, and the second cluster C4 from the top of the upper page of plane P2 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0074] For channels ch.2 and ch.3, the cluster C1 at the end of the middle page of plane P3 of the memory chip 21 belonging to bank #1, and the cluster C4 at the beginning of the upper page of plane P2 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0075] For channels ch.4 and ch.5, the third cluster C1 from the top of the middle page of plane P3 of the memory chip 21 belonging to bank #1, and the last cluster C3 of the upper page of plane P1 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0076] For channels ch.6 and ch.7, the second cluster C1 from the top of the middle page of plane P3 of the memory chip 21 belonging to bank #1, the third cluster C3 from the top of the upper page of plane P1 of the memory chip 21 belonging to bank #1, and the last cluster C5 of the upper page of plane P3 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0077] For channels ch.8 and ch.9, the following are set as parity clusters: cluster C1 at the beginning of the middle page of plane P3 of the memory chip 21 belonging to bank #1, cluster C3 second from the beginning of the upper page of plane P1 of the memory chip 21 belonging to bank #1, and cluster C5 third from the beginning of the upper page of plane P3 of the memory chip 21 belonging to bank #1.

[0078] For channels ch.10 and ch.11, the following are set as parity clusters: cluster C0 at the end of the middle page of plane P2 of the memory chip 21 belonging to bank #1, cluster C3 at the beginning of the upper page of plane P1 of the memory chip 21 belonging to bank #1, and cluster C5, the second to last cluster of the upper page of plane P3 of the memory chip 21 belonging to bank #1.

[0079] For channels ch.12 and ch.13, the third cluster from the top of the middle page of plane P2 of the memory chip 21 belonging to bank #1, cluster C2 at the end of the upper page of plane P0 of the memory chip 21 belonging to bank #1, and cluster C5 at the beginning of the upper page of plane P3 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0080] For channels ch.14 and ch.15, the second cluster from the top of the middle page of plane P2 of the memory chip 21 belonging to bank #1, cluster C0 from the top of the upper page of plane P0 of the memory chip 21 belonging to bank #1, and cluster C4 at the end of the upper page of plane P2 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0081] For channels ch.16 and ch.17, the following are set as parity clusters: cluster C0 at the beginning of the middle page of plane P2 of the memory chip 21 belonging to bank #1, cluster C2 at the second-to-last of the upper page of plane P0 of the memory chip 21 belonging to bank #1, and cluster C4 at the third-to-last of the plane P2 of the memory chip 21 belonging to bank #1.

[0082] Therefore, each of channels ch.0 to ch.5 is allocated two parity clusters, and each of channels ch.6 to ch.17 is allocated three parity clusters.

[0083] When the memory controller 10 stores data for the logical page 40 configured as described above, it first prepares the user data for the logical page 40 and the corresponding parity data in the RAM 30. The memory controller 10 generates the parity data by performing cross-channel error correction coding on the user data. Then, the memory controller 10 distributes the user data and parity data across 18 channels (ch) and transfers them to the NAND memory 20, and writes the user data and parity data to the logical page 40.

[0084] The transfer does not necessarily have to begin after all user data and parity data for logical page 40 have been prepared. The memory controller 10 may start the transfer when some of the data to be written, including user data and parity data, has been prepared in RAM 30.

[0085] (Second embodiment) A read operation for a single physical page 27 consists of a sense operation and a data-out operation. The sense operation is, as described above, an operation to read data from a single physical page 27 of a single memory cell group MCG. The data read by the sense operation is stored in a page buffer included in the peripheral circuit. The data-out operation is an operation to transfer some or all of the data from the single physical page 27 stored in the page buffer to the memory controller 10.

[0086] After causing the memory chip 21 to perform a sense operation, the memory controller 10 transfers a data out command sequence to the memory chip 21, thereby causing the memory chip 21 to perform a data out operation.

[0087] Figure 8 shows an example of a data-out command sequence according to the second embodiment.

[0088] The data-out command sequence includes the command identifier CM of the data-out command and the address ADDR. The memory controller 10 transfers a pair of row address and column address as address ADDR to the memory chip 21. The memory controller 10 transfers address ADDR which includes the value of the column address that indicates the starting position of the range to be read from the physical page 27.

[0089] Upon receiving the data-out command sequence, the memory chip 21, through a sense operation, transfers the data DAT from the position specified by the column address included in address ADDR to the memory controller 10, which is part of the data in one physical page 27 stored in the page buffer.

[0090] The size of the data DAT output from the memory chip 21 is determined, in one example, by the number of times the RE signal is toggled by the memory controller 10. When the memory controller 10 toggles the RE signal, the memory chip 21 generates a DQS signal based on the RE signal. The memory chip 21 outputs the data DAT in synchronization with the DQS signal. When the memory controller 10 finishes toggling the RE signal, the memory chip 21 finishes outputting the data DAT and DQS signal in accordance with the end of the RE signal toggle.

[0091] Thus, the memory controller 10 can retrieve data stored in a single range of contiguous column addresses within the physical page 27 by using a data-out command sequence. Therefore, if it is desired to retrieve data from multiple ranges of non-contiguous column addresses within the physical page 27, the memory controller 10 needs to issue a data-out command sequence for each of the multiple ranges.

[0092] In other words, if a cluster that is neither the first nor the last cluster of a physical page 27 is set as the parity cluster, the memory controller 10 needs to issue two data-out command sequences in order to read all user data from that physical page 27 during a logical page read operation. Specifically, the memory controller 10 needs to issue a data-out command sequence to obtain user data stored in one or more consecutive clusters before the parity cluster of the physical page 27, and a data-out command sequence to obtain user data stored in one or more consecutive clusters after the parity cluster of the physical page 27.

[0093] The transfer of data-out command sequences itself requires a certain amount of time. Therefore, even for read operations that retrieve data from the same number of clusters within a single physical page 27, the time required for the read operation increases as the number of data-out command sequences issued increases.

[0094] Therefore, in the second embodiment, one or more consecutive clusters including the first cluster or one or more consecutive clusters including the last cluster within the physical page 27 are set as parity clusters, and a cluster in which user data is stored is set in only one consecutive range that is not set as a parity cluster. In other words, by positioning the parity clusters towards the edge of the physical page 27, it is possible to store user data in only one consecutive range within the physical page 27.

[0095] As mentioned above, the time required for a logical page read operation depends on the longest time required to read user data from among the 18 channels. Furthermore, channels with fewer allocated parity clusters (in other words, channels with less parity data transferred when storing data for logical page 40) take longer to read user data.

[0096] Therefore, for the channel ch with the fewest allocated parity clusters, the parity cluster is positioned towards the edge of the physical page 27. This reduces the time required to read user data in the channel ch that takes the longest time to read user data. As a result, the time required for logical page read operations is reduced, and the efficiency of logical page read operations is improved.

[0097] Figure 9 is a diagram illustrating an example of the arrangement of parity clusters according to the second embodiment.

[0098] Similar to the example shown in Figure 7, each of the clusters C0, C1, C2, C3, C4, and C5 contains eight parity clusters. These 48 parity clusters are then arranged to be distributed as evenly as possible across the 18 channels. As a result, each of the 18 channels is allocated two or three parity clusters.

[0099] In the example shown in Figure 9, three parity clusters are allocated to each of channels ch.0 to ch.11, and two parity clusters are allocated to each of channels ch.12 to ch.17.

[0100] For channels ch.12 to ch.17, which are allocated two parity clusters, the time required to read user data is longer compared to channels ch.0 to ch.11, which are allocated three parity clusters. For channels ch.12 to ch.17, which are allocated two parity clusters, each parity cluster is either the first or last cluster of physical page 27.

[0101] Specifically, for channels ch.0 and ch.1, the second cluster from the top of the upper page of plane P0 of the memory chip 21 belonging to bank #1, cluster C2 from the top of the upper page of plane P2 of the memory chip 21 belonging to bank #1, and cluster C5 at the end of the upper page of plane P3 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0102] On the other hand, for channels ch.12 and ch.13, the cluster C1 at the beginning of the middle page of plane P3 of the memory chip 21 belonging to bank #1, and the cluster C3 at the beginning of the upper page of plane P1 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0103] Therefore, for channels ch.12 to ch.17, when acquiring user data from physical page 27 where a parity cluster is provided, the memory controller 10 can acquire all user data by issuing a data-out command sequence only once. The time required to read user data is reduced in channels ch.12 to ch.17, where two parity clusters are distributed, and as a result, the time required for logical page read operations is reduced. Therefore, the efficiency of logical page read operations is improved.

[0104] (Variation 1) In the first and second embodiments, a maximum of one cluster was configured as a parity cluster within a single physical page 27. The number of clusters configured as parity clusters within a single physical page 27 does not have to be a maximum of one.

[0105] Figure 10 is a diagram illustrating an example of the arrangement of parity clusters according to Modification Example 1.

[0106] Similar to the example shown in Figure 7, each of the clusters C0, C1, C2, C3, C4, and C5 contains eight parity clusters. However, the total of 48 parity clusters are distributed as described below.

[0107] For channels ch.0 and ch.1, all clusters C4 and C5 of the upper pages of planes P2 and P3 of the memory chip 21 belonging to bank #1 are configured as parity clusters. In other words, for each of channels ch.0 and ch.1, four parity clusters are configured for each of the two physical pages 27.

[0108] For channels ch.2 and ch.3, the two clusters C3 in the latter half of the upper page of plane P1 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0109] For channels ch.4 and ch.5, the first two clusters C3 in the first half of the upper page of plane P1 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0110] For channels ch.6 and ch.7, the latter two clusters C2 in the upper page of plane P0 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0111] For channels ch.8 and ch.9, the first two clusters C2 in the first half of the upper page of plane P0 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0112] For channels ch.10 and ch.11, the two clusters C1 in the latter half of the middle page of plane P3 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0113] For channels ch.12 and ch.13, the first two clusters C1 in the first half of the middle page of plane P3 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0114] For channels ch.14 and ch.15, the latter half of the middle pages of plane P2 of memory chip 21 belonging to bank #1, specifically clusters C0, are configured as parity clusters.

[0115] For channels ch.16 and ch.17, the first two clusters C0 in the first half of the middle page of plane P2 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0116] In the example above, eight parity clusters are distributed to each of channels ch.0 to ch.1, and two parity clusters are distributed to each of channels ch.2 to ch.17. Therefore, the time required to read user data is longest in channels ch.2 to ch.17, where two parity clusters are distributed. Furthermore, in channels ch.2 to ch.17, the two parity clusters are positioned towards the beginning or end of the physical page 27. In other words, in channels ch.2 to ch.17, when acquiring user data from the physical page 27 where the parity clusters are provided, the memory controller 10 can acquire all user data by issuing a data-out command sequence only once. The time required to read user data is shortened in channels ch.12 to ch.17, where two parity clusters are distributed. Therefore, similar to the second embodiment, the efficiency of the logical page read operation is improved.

[0117] (Modification 2) In the first embodiment, the second embodiment, and Modification 1, the total number of parity clusters is not equal to a multiple of the number of channels, so it is not possible to arrange the parity clusters so that the number of parity clusters is uniform across all channels. When the total number of parity clusters is equal to a multiple of the number of channels, the parity clusters can be arranged so that the number of parity clusters is uniform across all channels.

[0118] Figure 11 is a diagram illustrating an example of the arrangement of parity clusters according to Modification Example 2.

[0119] The hardware configuration of the memory system 1 according to Modification 2 differs from the first embodiment, the second embodiment, and Modification 1 in that the memory system 1 has a total of 16 channels ch, from channel ch.0 to ch.15.

[0120] Similar to the example shown in Figure 7, each of the clusters C0, C1, C2, C3, C4, and C5 contains eight parity clusters.

[0121] The total number of parity clusters in logical page 40 is 48. In other words, the total number of parity clusters in logical page 40 is three times the total number of channels (ch) in memory system 1. Therefore, three parity clusters are allocated to each channel (ch).

[0122] Specifically, for channels ch.0 and ch.1, the three clusters C5 from the second cluster C5 at the top to the last cluster C5 on the upper page of plane P3 of the memory chip 21 belonging to bank #1 are configured as parity clusters.

[0123] For channels ch.2 and ch.3, the two clusters C4 in the latter half of the upper page of plane P2 of the memory chip 21 belonging to bank #1, and the cluster C5 at the beginning of the upper page of plane P3 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0124] For channels ch.4 and ch.5, the last cluster C3 of the upper page of plane P1 of the memory chip 21 belonging to bank #1, and the first two clusters C4 of the upper page of plane P2 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0125] For channels ch.6 and ch.7, the first three clusters C3 of the upper page of plane P1 of the memory chip 21 belonging to bank #1, from the first cluster C3 to the third cluster C3 from the top, are configured as parity clusters.

[0126] For channels ch.8 and ch.9, the three clusters C2 from the second cluster C2 at the top to the last cluster C2 on the upper page of plane P0 of memory chip 21 belonging to bank #1 are configured as parity clusters.

[0127] For channels ch.10 and ch.11, the two clusters C1 in the latter half of the middle page of plane P3 of the memory chip 21 belonging to bank #1, and the cluster C2 at the beginning of the upper page of plane P0 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0128] For channels ch.12 and ch.13, the last cluster C0 of the middle page of plane P2 of the memory chip 21 belonging to bank #1, and the two clusters C1 in the first half of the middle page of plane P3 of the memory chip 21 belonging to bank #1 are set as parity clusters.

[0129] For channels ch.14 and ch.15, the first three clusters C0 of the middle page of plane P2 of memory chip 21 belonging to bank #1, from the first cluster C0 to the third cluster C0 from the top, are set as parity clusters.

[0130] In this way, three parity clusters are evenly distributed to each channel (ch).

[0131] Furthermore, in all physical pages 27 equipped with parity clusters, one or more parity clusters are positioned towards the beginning or end of the physical page 27. This means that, in all channels ch, when acquiring user data from a physical page 27 equipped with a parity cluster, the memory controller 10 can acquire all user data by issuing a data-out command sequence only once. Therefore, the time required to read user data from a physical page 27 equipped with a parity cluster is reduced, and as a result, the time required for logical page read operations is reduced. Thus, as in the second embodiment, the efficiency of logical page read operations is improved.

[0132] In the first embodiment, the second embodiment, modification 1, and modification 2, three physical pages 27, namely a lower page, a middle page, and an upper page, were selected for each combination of channel ch, bank 22, and plane P. Then, the group of physical pages 27, obtained by collecting the three physical pages 27 selected for each combination of channel ch, bank 22, and plane P, for all possible combinations, was defined as a logical page 40. The configuration of the logical page 40 is not limited to this. At least, as long as the logical page 40 is composed of a group of physical pages 27 selected from each of the multiple memory chips 21 constituting the NAND memory 20, the configuration method is arbitrary.

[0133] As described above, in the first embodiment, the second embodiment, modification 1, and modification 2, when the memory controller 10 stores user data in a logical page 40 composed of a group of physical pages 27 selected from each of the multiple memory chips 21 constituting the NAND memory 20, it generates parity data corresponding to the user data by cross-channel error correction coding of the user data. The logical page 40 is configured such that parity clusters are distributed across all channels ch. That is, the logical page 40 includes a physical page 27 with a parity cluster for each channel ch. Therefore, the memory controller 10 distributes the user data and the parity data across all channels ch and transfers them to the NAND memory 20.

[0134] Because parity clusters are distributed to all channels ch, the memory system 1 of the first embodiment, the second embodiment, modification 1, and modification 2 have the following characteristics. That is, as is clear from, for example, Figures 7, 9, 10, and 11, some or all of the physical pages 27 on which parity clusters are provided include physical pages 27 on which both a portion of the parity data and a portion of the user data are stored.

[0135] In this way, since parity clusters are distributed to all channels (ch), the time required for logical page read operations is reduced compared to the comparative example. In other words, the performance of memory system 1 is higher than that of the comparative example.

[0136] Furthermore, according to the second embodiment, modification 1, and modification 2, for the channel ch with the fewest number of distributed parity clusters among all channels ch, the parity cluster is positioned towards the edge of the physical page 27. In other words, for the physical page 27 where data is stored via the channel ch with the smallest amount of parity data transferred when storing data for the logical page 40, and where both a portion of the parity data and a portion of the user data are stored, a portion of the parity data is stored in a contiguous range at the beginning or end of the physical page 27 (referred to as the first range), and a portion of the user data is stored in only one contiguous range of the physical page 27 that is different from the first range (referred to as the second range).

[0137] Therefore, the time required to read user data is reduced in channel ch, which takes the longest time. As a result, the time required for logical page read operations is reduced, and the efficiency of logical page read operations is improved.

[0138] According to the first embodiment, the second embodiment, modification 1, and modification 2, each physical page 27 comprises multiple clusters. The memory controller 10 distributes the parity data across multiple channels ch in units of clusters and stores it in the group of physical pages 27 provided with parity clusters among the logical pages 40.

[0139] According to the first embodiment, the second embodiment, Modification 1, and Modification 2, the logical page 40 includes three physical pages 27 selected for each plane P. The configuration of the logical page 40 is not limited thereto.

[0140] In the first embodiment, the second embodiment, modification 1, and modification 2, each physical page 27 included in the memory cell array 23 of each memory chip 21 is an example of a first storage area. In other words, each memory chip 21 can be considered to contain multiple first storage areas.

[0141] Furthermore, each memory chip 21 belonging to bank #1 is an example of a first memory chip. Therefore, the number of first memory chips can be considered equal to the number of channels ch.

[0142] Of all the physical pages 27 that make up the logical page 40, the physical page 27 contained in the first memory chip is an example of a second memory area. The group consisting of each second memory area of ​​all the physical pages 27 that make up the logical page 40 is an example of a first group.

[0143] In other words, when the memory controller 10 stores user data for the first group, it stores a portion of the parity data in the second storage area of ​​each first memory chip. The memory controller 10 also stores both a portion of the parity data and a portion of the user data in the second storage area of ​​one or more second memory chips among the multiple first memory chips.

[0144] Physical page 27, which stores both a portion of the parity data and a portion of the user data, is an example of a third memory area.

[0145] A cluster is an example of a fourth memory area. Subarray 24 is an example of a subset.

[0146] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0147] 1 Memory system, 2 Host, 3 Communication channel, 10 Memory controller, 11 CPU, 12 Host I / F circuit, 13 RAMC, 14 NANDC, 15 ECC circuit, 20 NAND memory, 21 Memory chip, 22 Bank, 23 Memory cell array, 24 Subarray, 25 Physical block, 26 NAND string, 27 Physical page, 40 Logical page, MCG Memory cell group, ch Channel.

Claims

1. Multiple channels, Multiple memory chips, A memory controller electrically connected to the plurality of memory chips via the plurality of channels, comprising Each of the aforementioned plurality of memory chips includes a plurality of first storage areas, The plurality of first memory chips among the plurality of memory chips are connected to each of the plurality of channels, and the number of the plurality of first memory chips is equal to the number of the plurality of channels. The aforementioned memory controller A storage operation is performed to store first data in a first group which is a group of second storage areas that are one of the plurality of first storage areas of each of the plurality of first memory chips. In the storage operation, the memory controller By performing error correction coding on the first data, parity data corresponding to the first data is generated. In each of the second storage areas of the plurality of first memory chips, partial parity data, which is a part of the parity data, is stored. The partial parity data and the partial first data, which is a part of the first data, are stored in the second storage area of ​​one or more second memory chips among the plurality of first memory chips. Memory system.

2. Each of the aforementioned plurality of first memory regions is mapped to a unit space consisting of a group of addresses with consecutive values. The aforementioned memory controller In the third storage area, which is the second storage area of ​​one or more second memory chips that stores the smallest amount of partial parity data, the partial parity data is stored in a contiguous first range at the beginning or end of the unit space, and the partial first data is stored in only one contiguous second range of the unit space that is different from the first range. The memory system according to claim 1.

3. The aforementioned memory controller From the first range of the third storage area, read the partial parity data by a single command sequence. The partial first data is read from the second range of the third memory area by another command sequence. The memory system according to claim 2.

4. Each of the aforementioned plurality of first memory regions comprises a plurality of fourth memory regions. The memory controller divides the parity data into partial parity data in units of the fourth storage area, and stores the partial parity data in each of the second storage areas of the plurality of first memory chips. The memory system according to any one of claims 1 to 3.

5. The memory controller stores the partial parity data in all of the multiple fourth storage areas included in the second storage area of ​​one or more third memory chips among the multiple first memory chips. The memory system according to claim 4.

6. Each of the aforementioned plurality of memory chips has a plurality of first storage areas which are divided into a plurality of subsets. The first group includes the first memory area of ​​each of the plurality of subsets as the second memory area. The memory system according to any one of claims 1 to 3.

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