Semiconductor packages

Abstract

To provide semiconductor packages with improved integration and miniaturization. [Solution] The semiconductor package includes a first substrate 100 comprising a core portion 110 made of glass and a wiring layer 120 provided on the upper surface of the core portion, a first semiconductor chip 200 formed on the lower surface of the core portion and having a recess region RS in contact with the side surface of the core portion and disposed on the wiring layer, a second semiconductor chip 300 disposed on the bottom surface of the recess region, the second semiconductor chip having an optical integrated circuit (PIC), a cover portion 400 covering the second semiconductor chip on the bottom surface of the recess region and a second substrate 500 covering the lower surface of the cover portion and the lower surface of the core portion, the lower surface of the core portion being at a lower level than the lower surface of the cover portion, the core portion including an optical waveguide 116 provided on the bottom surface of the recess region, the optical waveguide extending from between the second semiconductor chip and the core portion toward the side surface of the core portion toward one side of the second semiconductor chip, and the second semiconductor chip being optically coupled to the optical waveguide.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including an optical element and a method for manufacturing the same.

Background Art

[0002] With the development of the electronics industry, the requirements for higher functionality, higher speed, and miniaturization of electronic components are increasing. In response to such a trend, recent packaging technologies are progressing in the direction of mounting a plurality of semiconductor chips in one package.

[0003] Recently, the demand for portable devices in the electronics product market has increased rapidly, and as a result, miniaturization and weight reduction of the electronic components mounted on these products have been continuously required. In order to achieve such miniaturization and weight reduction of electronic components, not only technology for reducing the individual size of mounted components but also semiconductor package technology for integrating a large number of individual elements into one package is required. In particular, semiconductor packages in which a large number of elements such as optical elements in addition to electronic elements are integrated require various structural characteristics, electrical characteristics, and optical characteristics according to the characteristics and functions of the elements.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package with improved integration density and miniaturization. Another object of the present invention is to provide a semiconductor package with improved electrical characteristics.

[0006] The problems that this invention aims to solve are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the above objective, a semiconductor package according to one aspect of the present invention includes a first substrate, the first substrate having a first lower surface and a second lower surface located at different vertical levels from the upper surface of the first substrate, a first semiconductor chip mounted on the upper surface of the first substrate, a second semiconductor chip mounted on the first lower surface of the first substrate, the second semiconductor chip having an optical integrated circuit (PIC), and a second substrate disposed on the second lower surface of the first substrate and covering the second semiconductor chip. The first substrate may include a first via that penetrates the first substrate vertically and connects the first semiconductor chip and the second semiconductor chip, a second via that penetrates the first substrate vertically and connects the first semiconductor chip and the second substrate, and an optical waveguide provided on the first lower surface. The first distance from the upper surface to the first lower surface of the first substrate is smaller than the second distance from the upper surface to the second lower surface of the first substrate.

[0008] To achieve the above objectives, a semiconductor package according to another aspect of the present invention may include a first substrate including a core made of glass and a wiring layer provided on the upper surface of the core; a first semiconductor chip disposed on the wiring layer, with the core having a recess region formed on the lower surface of the core and in contact with the side surface of the core; a second semiconductor chip disposed on the bottom surface of the recess region; a cover portion covering the second semiconductor chip on the bottom surface of the recess region, with the second semiconductor chip having an optical integrated circuit (PIC); and a second substrate covering the lower surface of the cover portion and the lower surface of the core. The lower surface of the core may be located at a lower level than the lower surface of the cover portion. The core may include an optical waveguide provided on the bottom surface of the recess region. The optical waveguide may extend from between the second semiconductor chip and the core toward one side of the second semiconductor chip toward the side surface of the core. The second semiconductor chip is characterized by being optically coupled to the optical waveguide.

[0009] A semiconductor package according to yet another aspect of the present invention, made to achieve the above objective, may include a first substrate, a first semiconductor chip mounted on the upper surface of the first substrate, a second semiconductor chip mounted on the lower surface of the first substrate, a second substrate provided on the lower surface of the second semiconductor chip, a vertical connecting portion provided between the second semiconductor chip and electrically connecting the first and second substrates, and a cover portion disposed between the first and second substrates. The first substrate may include an optical waveguide provided on the lower surface of the first substrate. The optical waveguide extends from above the second semiconductor chip to one side of the second semiconductor chip. Each of the cover portions is disposed on the one side of the second semiconductor chip. The cover portion is perpendicularly separated from the optical waveguide. The space between the optical waveguide and the cover portion constitutes a socket. [Effects of the Invention]

[0010] According to the semiconductor package of the present invention, the first substrate can provide both an optical path from the outside to the second semiconductor chip and an electrical path from the second semiconductor chip to the first semiconductor chip, resulting in a semiconductor package that is simple in structure, miniaturized, and has improved integration density.

[0011] By forming a recess region in the first substrate and embedding the second semiconductor chip within the recess region, the distance from the top surface of the first substrate to the bottom surface of the second semiconductor chip, or the distance from the top surface of the first substrate to the second bottom surface of the first substrate, can be reduced. In other words, a miniaturized semiconductor package can be provided. Furthermore, the thickness of the first substrate can be reduced between the second semiconductor chip and the first semiconductor chip, and therefore the vertical height of the first via connecting the second and first semiconductor chips can be reduced. In other words, since the length of the electrical connection between the second and first semiconductor chips is short, a semiconductor package with improved electrical characteristics can be provided.

[0012] The cover portion of the socket secures the second semiconductor chip beneath the first substrate, thereby improving the structural stability of the semiconductor package. Furthermore, because the cover portion is made of a material with high thermal conductivity, heat generated from the second semiconductor chip is easily dissipated to the outside through the cover portion. In other words, a semiconductor package with improved heat dissipation efficiency can be provided. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 2] This is a plan view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. [Figure 5]It is a plan view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 6] It is a plan view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 7] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 8] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 10] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 11] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 12] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 13] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 14] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 15] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 16] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 17] It is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention. [Figure 18] It is a cross-sectional view for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] It is a cross-sectional view for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] It is a cross-sectional view for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21]This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 23] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Modes for carrying out the invention]

[0014] The semiconductor package according to the concept of the present invention will be described below with reference to the drawings.

[0015] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. Figure 2 is a plan view illustrating a semiconductor package according to an embodiment of the present invention, showing a first substrate and a second semiconductor chip mounted on the lower surface of the first substrate, viewed from below. Figure 3 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0016] A first substrate 100 is provided with reference to Figures 1 and 2. The first substrate 100 includes a core portion 110 and a wiring layer 120.

[0017] The first core portion 110 contains an insulating material. For example, the first core portion 110 contains glass fibers. That is, the first substrate 100 is a wiring substrate made of glass.

[0018] The first core portion 110 has an upper surface 110u and a first lower surface 110l1 and a second lower surface 110l2 facing the upper surface 110u. The first lower surface 110l1 and the second lower surface 110l2 are located at different vertical levels from the upper surface 110u. This will be explained in more detail below. The first core portion 110 includes a horizontal portion 112 and a projection 114 located below the horizontal portion 112.

[0019] The horizontal portion 112 has a flat plate shape. The upper surface 110u of the horizontal portion 112 corresponds to the upper surface 110u of the first core portion 110. The protruding portion 114 projects onto the lower surface 110l1 of the horizontal portion 112. The lower surface 110l2 of the protruding portion 114 is located at a lower level than the lower surface 110l1 of the horizontal portion 112. That is, the lower surface 110l2 of the protruding portion 114 is located further from the upper surface 110u of the first core portion 110 than the lower surface 110l1 of the horizontal portion 112. The lower surface 110l2 of the protruding portion 114 corresponds to the first lower surface 110l1 of the first core portion 110. The lower surface 110l1 of the horizontal portion 112 that is exposed and not covered by the protruding portion 114 corresponds to the second lower surface 110l2 of the first core portion 110. The thickness of the first core portion 110 on the first lower surface 110l1 is smaller than the thickness of the first core portion 110 on the second lower surface 110l2. In plan view, the projection 114 is located on the center of the horizontal portion 112. The projection 114 is spaced apart from the side surface of the horizontal portion 112. Therefore, the first core portion 110 has a T-shaped cross-section.

[0020] In other words, the first core portion 110 has a recess area RS formed at the bottom of the first core portion 110. In plan view, the recess area RS extends along the edge of the first core portion 110. The recess area RS is in contact with the side surface of the first core portion 110. The recess area RS surrounds the first lower surface 110l1 of the first core portion 110. That is, the planar shape of the recess area RS is a ring shape that extends along the side surface of the first core portion 110. The recess area RS has a shape that is recessed inward from the second lower surface 110l2 of the first core portion 110 towards the inside of the first core portion 110. That is, the first lower surface 110l1 of the first core portion 110 corresponds to the bottom surface 110l1 of the recess area RS. The bottom surface 110l1 of the recess area RS is connected to the side surface of the first core portion 110.

[0021] The first core section 110 includes a first via TGV1 and a second via TGV2. The first via TGV1 and the second via TGV2 penetrate the first core section 110 vertically.

[0022] The first via TGV1 connects the upper surface 110u and the first lower surface 110l1 of the first core portion 110. The upper surface of the first via TGV1 is exposed on the upper surface 110u of the first core portion 110, and the lower surface of the first via TGV1 is exposed on the first lower surface 110l1 of the first core portion 110. The upper surface of the first via TGV1 forms a substantially flat coplanar surface with the upper surface 110u of the first core portion 110, and the lower surface of the first via TGV1 forms a substantially flat coplanar surface with the first lower surface 110l1 of the first core portion 110.

[0023] The second via TGV2 connects the upper surface 110u and the second lower surface 110l2 of the first core portion 110. The upper surface of the second via TGV2 is exposed on the upper surface 110u of the first core portion 110, and the lower surface of the second via TGV2 is exposed on the second lower surface 110l2 of the first core portion 110. The upper surface of the second via TGV2 forms a substantially flat coplane with the upper surface 110u of the first core portion 110, and the lower surface of the second via TGV2 forms a substantially flat coplane with the second lower surface 110l2 of the first core portion 110.

[0024] Because the second lower surface 110l2 is located at a lower vertical level than the first lower surface 110l1, the vertical length of the second via TGV2 is longer than the vertical length of the first via TGV1. The first via TGV1 and the second via TGV2 contain a conductive material. For example, the first via TGV1 and the second via TGV2 contain a metallic material such as copper (Gu) or tungsten (W).

[0025] The first core section 110 has a waveguide 116 provided at the lower part of the first core section 110. The waveguide 116 is provided at the first lower surface 110l1 of the first core section 110. The waveguide 116 is positioned adjacent to the side surface of the horizontal section 112 of the first core section 110. The waveguide 116 is located between the side surface of the horizontal section 112 of the first core section 110 and the first via TGV1. That is, the waveguide 116 is closer to the side surface of the horizontal section 112 of the first core section 110 than to the first via TGV1. The waveguide 116 has a bar shape. The planar shape of the waveguide 116 has a line shape extending from the projection 114 toward one of the side surfaces of the horizontal section 112. Figure 2 illustrates that three waveguides 116 are provided on each side surface of the horizontal section 112, but the present invention is not limited thereto. The arrangement and number of waveguides 116 are provided in various ways as needed. The lower surface of waveguide 116 is part of the first lower surface 110l1 of the first core portion 110. That is, the lower surface of waveguide 116 is coplanar with the first lower surface 110l1 of the first core portion 110.

[0026] Waveguide 116 is a glass optical waveguide formed on the first lower surface 110l1 of the first core portion 110. For example, waveguide 116 has the same material as the first core portion 110. Waveguide 116 contains glass. More specifically, waveguide 116 contains glass, and some of the components of the glass are substituted with other elements. For example, waveguide 116 is glass in which +1 valent alkali elements in the glass components are substituted with other +1 valent elements.

[0027] The first core portion 110 has a first substrate pad 102 and a second substrate pad 104 provided below the first core portion 110. The first substrate pad 102 is located on the first lower surface 110l1 of the first core portion 110. Each of the first substrate pads 102 is connected to the lower surface of any one of the first vias TGV1. The first substrate pads 102 are electrically connected to the wiring layer 120, which will be described later, through the first vias TGV1. The second substrate pad 104 is a pad to which the second substrate 500, which will be described later, is connected. The second substrate pad 104 is located on the second lower surface 110l2 of the first core portion 110. Each of the second substrate pads 104 is connected to the lower surface of any one of the second vias TGV2. The second substrate pad 104 is electrically connected to the wiring layer 120, which will be described later, through the second vias TGV2. The first substrate pad 102 is a pad to which the second semiconductor chip 300, which will be described later, is connected. The first substrate pad 102 and the second substrate pad 104 contain a metallic substance such as copper (Cu).

[0028] The wiring layer 120 is positioned on the upper surface 110u of the first core portion 110. The wiring layer 120 covers the entire upper surface 110u of the first core portion 110. The sides of the wiring layer 120 are aligned with the sides of the first core portion 110. The wiring layer 120 includes a first insulating film 122 and a first wiring portion 124.

[0029] The upper surface 110u of the first core portion 110 is covered with a first insulating film 122. The first insulating film 122 covers the upper surfaces of the first via TGV1 and the second via TGV2 formed on the first core portion 110. That is, the first via TGV1 and the second via TGV2 are not exposed by the first insulating film 122. The first insulating film 122 contains an insulating material. For example, the first insulating film 122 contains an insulating polymer or a photosensitive polymer (PID). In contrast, the first insulating film 122 may contain at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0030] Within the first insulating film 122, a first wiring section 124 is provided, which is connected to a first via TGV1 and a second via TGV2. The first wiring section 124 includes a wiring pattern embedded within the first insulating film 122. For example, the wiring pattern includes a rewiring pattern for horizontal wiring and a via pattern for vertical connections. The first wiring section 124 is located between the upper and lower surfaces of the first insulating film 122. The first wiring section 124 penetrates the first insulating film 122 vertically and is connected to the first via TGV1 and the second via TGV2. A portion of the first wiring section 124 is exposed on the upper surface of the first insulating film 122, and the exposed portion of the first wiring section 124 serves as a first upper substrate pad of the wiring layer 120. The first wiring section 124 includes, for example, copper (Cu) or tungsten (W).

[0031] A first semiconductor chip 200 is placed on a first substrate 100. The first semiconductor chip 200 includes a first chip base layer 210 and a first chip wiring layer 220.

[0032] The first chip base layer 210 includes a semiconductor substrate. For example, the first chip base layer 210 is a semiconductor substrate such as a semiconductor wafer. A first integrated circuit is provided on the lower surface of the first chip base layer 210. The first integrated circuit includes logic circuits. That is, the first semiconductor chip 200 is a logic chip. For example, the first semiconductor chip 200 is an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an AP (Application Processor). In contrast, the first integrated circuit may include memory circuits. That is, the first semiconductor chip 200 may be a memory chip. For example, it may be one of DRAM (Dynamic Random Access Memory), SRAM (static random access memory), and NAND-FLASH. The lower surface of the first semiconductor chip 200 is the active surface, and the upper surface of the first semiconductor chip 200 is the inactive surface. In other words, the first semiconductor chip 200 is placed on the first substrate 100 in a face-down configuration.

[0033] A first chip wiring layer 220 is positioned on the lower surface of the first chip base layer 210. For example, the first chip wiring layer 220 includes a first chip insulation pattern 222 and a first chip wiring pattern 224 formed on the lower surface of the first chip base layer 210. The first chip wiring layer 220 may further include circuit patterns or protective films as needed.

[0034] The first chip insulating pattern 222 covers the first integrated circuit on the lower surface of the first chip base layer 210. The first chip insulating pattern 222 contains an insulating material. As an example, the first chip insulating pattern 222 contains at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0035] The first chip wiring pattern 224 is provided within the first chip insulation pattern 222. The first chip wiring pattern 224 is electrically connected to the first integrated circuit formed on the lower surface of the first chip insulation pattern 222. The first chip wiring pattern 224 contains a conductive material. For example, the first chip wiring pattern 224 contains a metallic material such as copper (Cu). A portion of the first chip wiring pattern 224 exposed on the lower surface of the first chip wiring layer 220 is the first chip pad of the first semiconductor chip 200.

[0036] The first semiconductor chip 200 is mounted on the first substrate 100. For example, the first semiconductor chip 200 is mounted on the first substrate 100 using a flip-chip method. More specifically, the first semiconductor chip 200 is electrically connected to the first substrate 100 through a first coupling terminal 230. The first coupling terminal 230 is provided between the first chip pad of the first semiconductor chip 200 and the first upper substrate pad of the first substrate 100. The first semiconductor chip 200 is electrically connected to the wiring layer 120 of the first substrate 100 through the first coupling terminal 230.

[0037] An underfill layer 240 is provided between the first substrate 100 and the first semiconductor chip 200. The underfill layer 240 fills the space between the first substrate 100 and the first semiconductor chip 200 and surrounds the first connecting terminal 230.

[0038] At least one second semiconductor chip 300 is placed beneath the first substrate 100. The second semiconductor chip 300 is placed on the first lower surface 110l1 of the first core portion 110 of the first substrate 100. The second semiconductor chip 300 is located on one side of the protruding portion 114 of the first core portion 110. In a plan view, the second semiconductor chip 300 is located between the side surface of the protruding portion 114 of the first core portion 110 and the side surface of the horizontal portion 112 of the first core portion 110. The second semiconductor chip 300 is horizontally separated from the side surface of the protruding portion 114 of the first core portion 110. However, the present invention is not limited thereto, and the second semiconductor chip 300 may be in contact with the side surface of the protruding portion 114 of the first core portion 110. The second semiconductor chip 300 is horizontally separated from the side surface of the horizontal portion 112 of the first core portion 110. At least a portion of the second semiconductor chip 300 is superimposed perpendicularly with the waveguide 116 of the first core portion 110. If multiple second semiconductor chips 300 are provided, each second semiconductor chip 300 is superimposed with one of the waveguides 116. In other words, each waveguide 116 extends from one of the sides of the horizontal portion 112 of the first core portion 110 onto the upper surface of one of the second semiconductor chips 300. Figure 2 illustrates that three second semiconductor chips 300 are provided on each side of the horizontal portion 112, depending on the number and arrangement of waveguides 116, but the present invention is not limited thereto. The arrangement and number of second semiconductor chips 300 are provided in various ways as needed. The lower surface of the second semiconductor chip 300 is located at a higher vertical level than the lower surface of the protrusion 114 of the first core portion 110, i.e., the second lower surface 110l2.

[0039] The configuration of the second semiconductor chip 300 will be described in more detail below, using one second semiconductor chip 300 as a reference. The second semiconductor chip 300 includes a second chip base layer 310 and a second chip wiring layer 320.

[0040] The second chip base layer 310 includes a semiconductor substrate. For example, the second chip base layer 310 is a semiconductor substrate such as a semiconductor wafer. A second integrated circuit is provided on the upper surface of the second chip base layer 310. The second integrated circuit includes a photonic integrated circuit (PIC). That is, the second semiconductor chip 300 is an optoelectronic device. If necessary, the second integrated circuit may further include an electronic integrated circuit (EIC). The upper surface of the second semiconductor chip 300 is the active surface, and the lower surface of the second semiconductor chip 300 is the inactive surface. That is, the second semiconductor chip 300 is arranged in a face-up configuration.

[0041] A second chip wiring layer 320 is placed on the upper surface of the second chip base layer 310. For example, the second chip wiring layer 320 includes a second chip insulating pattern 322 and a second chip wiring pattern 324 formed on the upper surface of the second chip base layer 310. The second chip wiring layer 320 may further include circuit patterns or protective films as needed.

[0042] The second chip insulating pattern 322 covers the second integrated circuit on the upper surface of the second chip base layer 310. The second chip insulating pattern 322 contains an insulating material. As an example, the second chip insulating pattern 322 contains at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0043] The second chip wiring pattern 324 is provided within the second chip insulation pattern 322. The second chip wiring pattern 324 is electrically connected to the second integrated circuit formed on the upper surface of the second chip insulation pattern 322. The second chip wiring pattern 324 contains a conductive material. For example, the second chip wiring pattern 324 contains a metallic material such as copper (Cu). A portion of the second chip wiring pattern 324 exposed on the upper surface of the second chip wiring layer 320 is the second chip pad of the second semiconductor chip 300.

[0044] The second semiconductor chip 300 further includes a sensor portion 350. The sensor portion 350 is formed on the second chip base layer 310. The sensor portion 350 is exposed on the upper surface of the second chip wiring layer 320. The sensor portion 350 is electrically connected to the second integrated circuit formed on the second chip base layer 310. The sensor portion 350 is positioned adjacent to one of the sides of the second semiconductor chip 300. The sensor portion 350 is superimposed perpendicularly with one of the waveguides 116 of the first core portion 110 of the first substrate 100. The sensor portion 350 is optically coupled with one of the waveguides 116. The sensor portion 350 receives light from one of the waveguides 116 and converts it into an electrical signal.

[0045] The second semiconductor chip 300 is mounted on the first substrate 100. For example, the second semiconductor chip 300 is mounted on the first substrate 100 using a flip-chip method. More specifically, the second semiconductor chip 300 is electrically connected to the first substrate 100 through a second coupling terminal 330. The second coupling terminal 330 is provided between the second chip pad of the second semiconductor chip 300 and the first substrate pad 102 of the first substrate 100. The second semiconductor chip 300 is electrically connected to the first via TGV1 of the first substrate 100 through the second coupling terminal 330. The second semiconductor chip 300 is electrically connected to the first semiconductor chip 200 through the first substrate 100.

[0046] According to an embodiment of the present invention, a waveguide 116 through which an optical signal is transmitted from the outside is provided to the first substrate 100. A second semiconductor chip 300 that receives and inputs the optical signal and converts and processes the optical signal into an electrical signal is connected to the first lower surface 110l1 of the first substrate 100. A first semiconductor chip 200 that processes the electrical signal is connected to the upper surface 100u of the first substrate 100. The second semiconductor chip 300 and the first semiconductor chip 200 are connected to each other through a first via TGV1 and a wiring layer 120. That is, the first substrate 100 can provide both an optical path from the outside to the second semiconductor chip 300 and an electrical path from the second semiconductor chip 300 to the first semiconductor chip 200, providing a semiconductor package that is simple in structure, miniaturized, and has improved integration.

[0047] Since a recess region RS is formed in the first substrate 100 and the second semiconductor chip 300 is housed within the recess region RS, the distance from the upper surface of the first substrate 100 to the lower surface of the second semiconductor chip 300 or the distance from the upper surface of the first substrate 100 to the second lower surface 110l2 of the first substrate 100 is small. In other words, a miniaturized semiconductor package is provided.

[0048] Furthermore, the thickness of the first substrate 100 between the second semiconductor chip 300 and the first semiconductor chip 200 is thin, and therefore the vertical height of the first via TGV1 connecting the second semiconductor chip 300 and the first semiconductor chip 200 is small. In other words, the length of the electrical connection between the second semiconductor chip 300 and the first semiconductor chip 200 is short, so a semiconductor package with improved electrical characteristics is provided.

[0049] Referring to Figures 1 and 2, the cover portion 400 is positioned below the first substrate 100. The cover portion 400 is positioned on the first lower surface 110l1 of the first substrate 100. The cover portion 400 covers the second semiconductor chip 300 on the first lower surface 110l1 of the first substrate 100. The cover portion 400 is in contact with the lower surface of the second semiconductor chip 300. Although not shown, the cover portion 400 is bonded to the lower surface of the second semiconductor chip 300 using an adhesive or the like. The cover portion 400 does not cover the second lower surface 110l2 of the first substrate 100. That is, the second lower surface 110l2 of the first substrate 100 is exposed on the lower surface of the cover portion 400. In plan view, the cover portion 400 surrounds the protruding portion 114 of the first core portion 110. The lower surface of the cover portion 400 is located at the same vertical level as the second lower surface 110l2 of the first substrate 100. However, the present invention is not limited thereto. The lower surface of the cover portion 400 may be located at a vertical level higher or lower than the second lower surface 110l2 of the first substrate 100. The cover portion 400 is in contact with the side surface of the protrusion 114 of the first core portion 110 of the first substrate 100. However, the present invention is not limited thereto. The cover portion 400 may be horizontally separated from the side surface of the protrusion 114. The cover portion 400 extends from the lower surface of the second semiconductor chip 300 onto the outer surface of the second semiconductor chip 300. Here, the outer surface of the second semiconductor chip 300 is defined as the side surface of the second semiconductor chip 300 facing the side surface of the first substrate 100, more preferably the side surface of the horizontal portion 112 of the first core portion 110. In other words, the side surface of the second semiconductor chip 300 facing the protrusion 114 of the first core portion 110 is defined as the inner surface of the second semiconductor chip 300, and the outer surface of the second semiconductor chip 300 is the surface facing the inner surface. The sensor portion 350 of the second semiconductor chip 300 is positioned adjacent to the outer surface of the second semiconductor chip 300. The cover portion 400 covers at least a portion of the outer surface of the second semiconductor chip 300. At this time, on one side of the second semiconductor chip 300, more preferably on the outer surface of the second semiconductor chip 300, the cover portion 400 is separated perpendicularly from the waveguide 116 of the first substrate 100. The side surface of the cover portion 400 is aligned perpendicularly to the side surface of the first substrate 100. The cover portion 400 contains a material with high thermal conductivity. As an example, the cover portion 400 contains a metallic material.

[0050] The space between the cover portion 400 and the waveguide 116 is a socket for connecting an external input device. For example, as shown in Figure 3, an external input device 600 or multiple external input devices 600 are connected to the space between the cover portion 400 and the waveguide 116. The external input device 600 is, for example, an optical element, an optical cable, or an optical input device. The external input device 600 is fixed to one side of the second semiconductor chip 300 by the cover portion 400 and the first substrate 100. The external input device 600 transmits an optical signal to the waveguide 116 of the first substrate 100, and the waveguide 116 transmits the optical signal to the second semiconductor chip 300 through the sensor portion 350.

[0051] According to an embodiment of the present invention, the structural stability of the semiconductor package is improved by fixing the second semiconductor chip 300 to the first substrate 100 through the cover portion 400 that constitutes the socket. Furthermore, since the cover portion 400 is made of a material with high thermal conductivity, the heat generated from the second semiconductor chip 300 is easily dissipated to the outside through the cover portion 400. In other words, a semiconductor package with improved heat dissipation efficiency is provided. The following description will be made with reference to Figures 1 and 2.

[0052] A second substrate 500 is provided beneath the first substrate 100. The second substrate 500 is provided beneath the second lower surface 110l2 of the first substrate 100 and the lower surface of the cover portion 400. The second substrate 500 includes a printed circuit board (PCB) having a signal pattern on its upper surface. The second substrate 500 has a third substrate pad 510 positioned on its upper surface. The third substrate pad 510 is located beneath the second lower surface 110l2 of the first substrate 100. More preferably, the third substrate pad 510 is aligned with the second substrate pad 104 of the first substrate 100.

[0053] The first substrate 100 is mounted on the second substrate 500. For example, the first substrate 100 is electrically connected to the second substrate 500 through a third connecting terminal 520. The third connecting terminal 520 connects the second substrate pad 104 of the first substrate 100 to the third substrate pad 510 of the second substrate 500. The second substrate 500 is electrically connected to the first substrate 100, the first semiconductor chip 200, and the second semiconductor chip 300 through the third connecting terminal 520.

[0054] Although not shown, external terminals are located beneath the second substrate 500. The external terminals include solder balls or solder bumps, and depending on the type and arrangement of the external terminals, the semiconductor package is provided in the form of a ball grid array (BGA), a fine ball-grid array (FBGA), or a land grid array (LGA). In other embodiments, external terminals may not be provided.

[0055] In the following embodiments, the same reference numerals are used for the components described in the embodiments of Figures 1 to 3, and for the sake of simplicity, their descriptions will be omitted or briefly explained. In other words, the following embodiments will be described primarily for the differences between the embodiments of Figures 1 to 3 and the following embodiments.

[0056] Figure 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. Figures 5 and 6 are plan views illustrating a semiconductor package according to an embodiment of the present invention.

[0057] Referring to Figures 4 and 5, the protrusion 114 is not located on the center of the horizontal portion 112. For example, the protrusion 114 is located adjacent to the first side surface 110s1 on the side surface of the first core portion 110 of the first substrate 100. In other words, the first lower surface 110l1 and the second lower surface 110l2 of the first core portion 110 are arranged side by side horizontally. The second lower surface 110l2 is located adjacent to the first side surface 110s1 of the first core portion 110, and the first lower surface 110l1 is located adjacent to the second side surface 110s2 which is opposite to the first side surface 110s1 of the first core portion 110. Therefore, the first core portion 110 has an inverted L-shaped cross-section.

[0058] Depending on the arrangement of the protrusions 114, the waveguides 116 of the first core portion 110 are arranged along the second side surface 110s2 of the first core portion 110. The waveguides 116 extend from the second side surface 110s2 of the first core portion 110 toward the first side surface 110s1. The second semiconductor chip 300 is arranged along the second side surface 110s2 of the first core portion 110.

[0059] In contrast, referring to Figures 4 and 6, the projection 114 is not located on the center of the horizontal portion 112. For example, the projection 114 is positioned adjacent to one of the corners 110e1 of the first core portion 110 of the first substrate 100. In other words, the projection 114 is spaced apart from the third side surface 110s3 and the fourth side surface 110s4 of the first core portion 110, which do not touch the corner 110e1 of the first core portion 110. The second lower surface 110l2 of the first core portion 110 is positioned adjacent to the corner 110e1 of the first core portion 110, and the second lower surface 110l2 of the first core portion 110 extends along the third side surface 110s3 and the fourth side surface 110s4.

[0060] Depending on the arrangement of the protrusion 114, the waveguide 116 of the first core portion 110 is arranged along the third side surface 110s3 or the fourth side surface 110s4 of the first core portion 110. The waveguide 116 extends from the third side surface 110s3 or the fourth side surface 110s4 of the first core portion 110 toward the protrusion 114. The second semiconductor chip 300 is arranged along the third side surface 110s3 or the fourth side surface 110s4 of the first core portion 110.

[0061] Figure 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0062] Referring to Figure 7, the first substrate 100 does not have a wiring layer 120 (see Figure 1). That is, the upper surface 110u of the first core portion 110 of the first substrate 100 is the upper surface of the first substrate 100. The upper surfaces of the first via TGV1 and the second via TGV2 are exposed on the upper surface 110u of the first core portion 110.

[0063] The first semiconductor chip 200 is mounted on the first substrate 100. For example, the first semiconductor chip 200 is mounted on the first substrate 100 using a flip-chip method. More specifically, the first semiconductor chip 200 is electrically connected to the first substrate 100 through a first connection terminal 230. The first connection terminal 230 is connected to the first chip pad of the first semiconductor chip 200. The first connection terminal 230 is connected to the upper surface of the first via TGV1 and the upper surface of the second via TGV2, which are exposed on the upper surface 110u of the first core portion 110. The first semiconductor chip 200 is electrically connected to the first via TGV1 and the second via TGV2 through the first connection terminal 230.

[0064] Figure 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0065] Referring to Figure 8, a second connecting terminal 330 (see Figure 1) is not provided between the first substrate 100 and the second semiconductor chip 300.

[0066] The first substrate 100 does not have a first substrate pad 102. The first via TGV1 is exposed on the first lower surface 110l1 of the first core portion 110 of the first substrate 100.

[0067] The second semiconductor chip 300 is mounted on the first substrate 100. More specifically, the second semiconductor chip 300 is positioned on the first lower surface 110l1 of the first core portion 110 of the first substrate 100. The second chip pad of the second chip wiring layer 320 of the second semiconductor chip 300 and the first via TGV1 of the first substrate 100 are aligned vertically. The second semiconductor chip 300 and the first core portion 110 are in contact with each other so that the second chip pad and the first via TGV1 are connected to each other.

[0068] The second semiconductor chip 300 is connected to the first substrate 100. Specifically, the second semiconductor chip 300 and the first core portion 110 are in contact with each other. At the interface between the second semiconductor chip 300 and the first core portion 110, the second chip pad of the second semiconductor chip 300 and the first via TGV1 of the first substrate 100 are bonded. At this time, the second chip pad and the first via TGV1 form an intermetallic hybrid bond. In this specification, hybrid bonding means bonding in which two components containing the same material fuse at their interface. For example, the bonded second chip pad and the first via TGV1 have a continuous structure, and the interface between the second chip pad and the first via TGV1 is not visually visible. For example, the second chip pad and the first via TGV1 are made of the same material, and there is no interface between the second chip pad and the first via TGV1. That is, the second chip pad and the first via TGV1 are provided as a single component. For example, the second chip pad and the first via TGV1 are coupled together to form a single unit.

[0069] Figures 9 to 11 are cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

[0070] Referring to Figure 9, a third substrate 700 is provided below the first substrate 100, which is not the second substrate 500 (see Figure 1). The third substrate 700 includes a redistribution substrate. The third substrate 700 includes a substrate insulation pattern 710 and a substrate wiring pattern 720.

[0071] A substrate insulating pattern 710 is placed on the second lower surface 110l2 of the first substrate 100 and the lower surface of the cover portion 400. The substrate insulating pattern 710 covers the second lower surface 110l2 of the first substrate 100 and the lower surface of the cover portion 400. The substrate insulating pattern 710 is in contact with the second lower surface 110l2 of the first substrate 100 and the lower surface of the cover portion 400. The substrate insulating pattern 710 contains an insulating material. For example, the substrate insulating pattern 710 contains an oxide, a nitride, or an oxynitride. As an example, the substrate insulating pattern 710 contains at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0072] A substrate wiring pattern 720 is provided within the substrate insulation pattern 710, which is connected to the second via TGV2. The substrate wiring pattern 720 includes a wiring pattern embedded within the substrate insulation pattern 710. For example, the substrate wiring pattern includes a rewiring pattern for horizontal wiring and a via pattern for vertical connections. The substrate wiring pattern 720 penetrates the substrate insulation pattern 710 vertically on the second lower surface 110l2 of the first substrate 100 and is connected to the second via TGV2. The substrate wiring pattern 720 is located between the upper and lower surfaces of the substrate insulation pattern 710. The substrate wiring pattern 720 includes, for example, copper (Cu) or tungsten (W).

[0073] A fourth substrate pad 730 is provided on the lower surface of the substrate insulation pattern 710. The fourth substrate pad 730 is exposed on the lower surface of the substrate insulation pattern 710. The fourth substrate pad 730 protrudes from the lower surface of the substrate insulation pattern 710. In contrast, the lower surface of the fourth substrate pad 730 is coplanar with the lower surface of the substrate insulation pattern 710. The fourth substrate pad 730 is connected to the substrate wiring pattern 720. The fourth substrate pad 730 includes, for example, copper (Cu) or tungsten (W).

[0074] External terminals 740 are provided on the lower surface of the third substrate 700. The external terminals 740 are connected to the fourth substrate pad 730. The external terminals 740 include solder balls or solder bumps, and depending on the type and arrangement of the external terminals 740, the semiconductor package is provided in the form of a ball grid array (BGA), a fine ball-grid array (FBGA), or a land grid array (LGA).

[0075] Unlike the embodiment shown in Figure 9, in the embodiment shown in Figure 10, the cover portion 400 does not cover the lower surface of the second semiconductor chip 300. As shown in Figure 10, the cover portion 400 covers the outer surface of the second semiconductor chip 300. The cover portion 400 does not extend onto the lower surface of the second semiconductor chip 300. That is, the lower surface of the second semiconductor chip 300 is exposed on the lower surface of the cover portion 400. The lower surface of the cover portion 400 forms a substantially flat coplanar surface with the lower surface of the second semiconductor chip 300.

[0076] A third substrate 700 is provided beneath the first substrate 100, the second semiconductor chip 300, and the cover portion 400. The third substrate 700 includes a substrate insulation pattern 710 and a substrate wiring pattern 720. The substrate insulation pattern 710 is in contact with the second lower surface 110l2 of the first substrate 100, the lower surface of the second semiconductor chip 300, and the lower surface of the cover portion 400. Within the substrate insulation pattern 710 is a substrate wiring pattern 720 that is connected to the second via TGV2. The substrate wiring pattern 720 penetrates the substrate insulation pattern 710 perpendicularly on the second lower surface 110l2 of the first substrate 100 and is connected to the second via TGV2.

[0077] Unlike the embodiment shown in Figure 10, in the embodiment shown in Figure 11, each of the second semiconductor chips 300 further includes chip vias 360 that penetrate vertically through the second semiconductor chip 300.

[0078] A chip via 360 is a pattern for vertical routing. The chip via 360 penetrates vertically through the second chip base layer 310 and connects to the second chip routing layer 320. The chip via 360 is exposed on the lower surface of the second chip base layer 310. The lower surface of the chip via 360 is coplane with the lower surface of the second chip base layer 310. The chip via 360 contains, for example, tungsten (W).

[0079] A third substrate 700 is provided beneath a first substrate 100, a second semiconductor chip 300, and a cover portion 400. The third substrate 700 includes a substrate insulation pattern 710 and a substrate wiring pattern 720. The substrate insulation pattern 710 is in contact with the second lower surface 110l2 of the first substrate 100, the lower surface of the second semiconductor chip 300, and the lower surface of the cover portion 400. Within the substrate insulation pattern 710, a substrate wiring pattern 720 is provided which is connected to a second via TGV2 and a chip via 360. The substrate wiring pattern 720 penetrates the substrate insulation pattern 710 perpendicularly on the second lower surface 110l2 of the first substrate 100 and is connected to the second via TGV2, and penetrates the substrate insulation pattern 710 perpendicularly on the lower surface of the second semiconductor chip 300 and is connected to the chip via 360.

[0080] Figures 12 to 15 are cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

[0081] Figures 1 to 11 show that only a second semiconductor chip 300 having a photonic integrated circuit (PIC) on the first lower surface 110l1 of the first substrate 100 is provided, but the present invention is not limited thereto.

[0082] Referring to Figure 12, at least one third semiconductor chip 800 is placed beneath the first substrate 100. The third semiconductor chip 800 is placed on the first lower surface 110l1 of the first core portion 110 of the first substrate 100. The third semiconductor chip 800 is located on one side of the protrusion 114 of the first core portion 110. In plan view, the third semiconductor chip 800 is located between the side surface of the protrusion 114 of the first core portion 110 and the second semiconductor chip 300. The third semiconductor chip 800 is horizontally separated from the second semiconductor chip 300. The arrangement and number of the third semiconductor chips 800 are provided in various ways as needed. The lower surface of the third semiconductor chip 800 is located at a vertical level higher than the second lower surface 110l2 of the protrusion 114 of the first core portion 110.

[0083] The configuration of the third semiconductor chip 800 will be described in more detail below, using one third semiconductor chip 800 as a reference. The third semiconductor chip 800 includes a third chip base layer 810 and a third chip wiring layer 820.

[0084] The third chip base layer 810 includes a semiconductor substrate. For example, the third chip base layer 810 is a semiconductor substrate such as a semiconductor wafer. A third integrated circuit is provided on the upper surface of the third chip base layer 810. The third integrated circuit includes an electronic integrated circuit (EIC). As an example, the third semiconductor chip 800 is a chip for driving the second semiconductor chip 300. The upper surface of the third semiconductor chip 800 is the active surface, and the lower surface of the third semiconductor chip 800 is the inactive surface. That is, the third semiconductor chip 800 is arranged in a face-up configuration.

[0085] A third chip wiring layer 820 is positioned on the upper surface of the third chip base layer 810. For example, the third chip wiring layer 820 includes a third chip insulating pattern 822 and a third chip wiring pattern 824 formed on the upper surface of the third chip base layer 810. The third chip wiring layer 820 may further include circuit patterns or protective films as needed.

[0086] The third chip insulating pattern 822 covers the third integrated circuit on the upper surface of the third chip base layer 810. The third chip insulating pattern 822 includes an insulating material such as silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0087] The third chip wiring pattern 824 is provided within the third chip isolation pattern 822. The third chip wiring pattern 824 is electrically connected to the third integrated circuit formed on the upper surface of the third chip isolation pattern 822. The third chip wiring pattern 824 contains a conductive material such as copper (Cu). A portion of the third chip wiring pattern 824 exposed on the upper surface of the third chip wiring layer 820 is the third chip pad of the third semiconductor chip 800.

[0088] A third semiconductor chip 800 is mounted on a first substrate 100. For example, the third semiconductor chip 800 is mounted on the first substrate 100 using a flip-chip method. More specifically, a third coupling terminal 830 is provided on the third chip pad of the third semiconductor chip 800. The third semiconductor chip 800 is electrically connected to the first substrate 100 through the third coupling terminal 830. The third coupling terminal 830 is provided between the third chip pad of the third semiconductor chip 800 and the first substrate pad 102 of the first substrate 100. The third semiconductor chip 800 is electrically connected to the first via TGV1 of the first substrate 100 through the third coupling terminal 830.

[0089] The cover portion 400 is positioned on the first lower surface 110l1 of the first substrate 100. The cover portion 400 covers the second semiconductor chip 300 and the third semiconductor chip 800 on the first lower surface 110l1 of the first substrate 100.

[0090] Unlike the embodiment shown in Figure 12, the third semiconductor chip 800 can be stacked vertically with the second semiconductor chip 300.

[0091] Referring to Figure 13, each of the second semiconductor chips 300 further includes chip vias 360 that penetrate vertically through the second semiconductor chip 300. The chip vias 360 penetrate vertically through the second chip base layer 310 and are connected to the second chip wiring layer 320. The chip vias 360 are exposed on the lower surface of the second chip base layer 310.

[0092] Each of the second semiconductor chips 300 further includes a fourth chip pad 370 provided on the lower surface of the second semiconductor chip 300. The fourth chip pad 370 is connected to a chip via 360 on the lower surface of the second semiconductor chip 300.

[0093] The third semiconductor chip 800 is positioned on the lower surface of the second semiconductor chip 300.

[0094] A third semiconductor chip 800 is mounted on a second semiconductor chip 300. For example, the third semiconductor chip 800 is mounted on the second semiconductor chip 300 using a flip-chip method. More specifically, a third coupling terminal 830 is provided on the third chip pad of the third semiconductor chip 800. The third semiconductor chip 800 is electrically coupled to the second semiconductor chip 300 through the third coupling terminal 830. The third coupling terminal 830 is provided between the third chip pad of the third semiconductor chip 800 and the fourth chip pad 370 of the second semiconductor chip 300. The third semiconductor chip 800 is electrically coupled to a chip via 360 of the second semiconductor chip 300 through the third coupling terminal 830.

[0095] The cover portion 400 is positioned on the first lower surface 110l1 of the first substrate 100. The cover portion 400 covers the third semiconductor chip 800 on the first lower surface 110l1 of the first substrate 100.

[0096] Unlike the embodiment shown in Figure 13, the third semiconductor chip 800 can be directly bonded to the second semiconductor chip 300.

[0097] Referring to Figure 14, the third semiconductor chip 800 is mounted on the second semiconductor chip 300. More specifically, the third chip pad of the third chip wiring layer 820 of the third semiconductor chip 800 and the fourth chip pad 370 of the second semiconductor chip 300 are aligned vertically. The third semiconductor chip 800 and the second semiconductor chip 300 are in contact with each other so that the third chip pad and the fourth chip pad 370 are connected to each other.

[0098] The third semiconductor chip 800 is connected to the second semiconductor chip 300. Specifically, the third chip pad of the third semiconductor chip 800 and the fourth chip pad 370 of the second semiconductor chip 300 are bonded at the interface between the third semiconductor chip 800 and the second semiconductor chip 300. At this time, the third chip pad and the fourth chip pad 370 form an intermetallic hybrid bond. For example, the third chip pad and the fourth chip pad 370 bond to each other to form a single unit.

[0099] Unlike the embodiments shown in Figures 12 to 14, the third semiconductor chip 800 may be provided as a single module.

[0100] Referring to Figure 15, the module is positioned on the lower surface of the second semiconductor chip 300. The module includes a first internal substrate 840, a third semiconductor chip 800, a second internal substrate 850, a molding film 860, and conductive posts 870. The configuration of the module will be described below using one module as a reference.

[0101] A first internal substrate 840 is provided. The first internal substrate 840 includes a printed circuit board (PCB) or a redistribution substrate having a signal pattern on its upper surface.

[0102] A third semiconductor chip 800 is mounted on the upper surface of the first internal substrate 840. The third semiconductor chip 800 is identical or similar to the third semiconductor chip 800 described with reference to Figures 12 to 14. The third semiconductor chip 800 is mounted on the first internal substrate 840 using a flip-chip method. More specifically, the third semiconductor chip 800 is mounted on the first internal substrate 840 using a third connecting terminal 830 on the third chip pad of the third semiconductor chip 800.

[0103] A molding film 860 is placed on the first internal substrate 840. The molding film 860 covers the third semiconductor chip 800 on the first internal substrate 840. The molding film 860 contains an insulating polymer material such as epoxy molding compound (EMC).

[0104] A second internal substrate 850 is placed on the molding film 860. The second internal substrate 850 covers the upper surface of the molding film 860. The second internal substrate 850 includes a redistribution substrate.

[0105] A conductive post 870 is placed within the molding film 860. The conductive post 870 penetrates the molding film 860 perpendicularly, connecting the first internal substrate 840 and the second internal substrate 850. The third semiconductor chip 800 is electrically connected to the second internal substrate 850 through the first internal substrate 840 and the conductive post 870.

[0106] The module is positioned on the lower surface of the second semiconductor chip 300.

[0107] The module is mounted on the second semiconductor chip 300. For example, module terminals 880 are provided on the module's second internal substrate 850. The module is electrically connected to the second semiconductor chip 300 through module terminals 880. Module terminals 880 are provided between the module's second internal substrate 850 and the fourth chip pad 370 of the second semiconductor chip 300. The module is electrically connected to the chip vias 360 of the second semiconductor chip 300 through third connection terminals 830.

[0108] The cover portion 400 is positioned on the first lower surface 110l1 of the first substrate 100. The cover portion 400 covers the module, more specifically the first internal substrate 840 of the module, on the first lower surface 110l1 of the first substrate 100.

[0109] Figure 16 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0110] Referring to Figure 16, the first core portion 110 has a flat plate shape. In other words, unlike the embodiments in Figures 1 to 15, the first core portion 110 has a horizontal portion 112 and does not have a protruding portion 114 (see Figure 1) that protrudes from the horizontal portion 112. The first core portion 110 has one flat lower surface. For example, the first lower surface 110l1 and the second lower surface 110l2 of the first core portion 110 are located at the same vertical level.

[0111] A vertical connecting portion 900 is provided on the first lower surface 110l1 of the first core portion 110. The vertical connecting portion 900 is configured for vertical wiring between the first substrate 100 and the second substrate 500 between the second semiconductor chips 300. In the embodiments shown in Figures 1 to 15, the protrusion 114 of the first core portion 110 (see Figure 1) serves as the vertical connecting portion. The vertical connecting portion 900 is located between the second semiconductor chips 300. The cover portion 400 surrounds the vertical connecting portion 900. The lower surface of the cover portion 400 is located at the same vertical level as the lower surface of the vertical connecting portion 900. The vertical connecting portion 900 has a second core portion 910, a fifth substrate pad 920, a sixth substrate pad 930, and a third via 940.

[0112] The second core portion 910 contains an insulating material. For example, the second core portion 910 contains glass fibers. Alternatively, the second core portion 910 contains an insulating polymer.

[0113] The fifth substrate pad 920 is provided on the upper surface of the second core portion 910. The sixth substrate pad 930 is provided on the lower surface of the second core portion 910. The third via 940 penetrates the second core portion 910 vertically and connects the fifth substrate pad 920 and the sixth substrate pad 930.

[0114] The vertical connector 900 is mounted on the first substrate 100. For example, a fourth connector terminal 950 is provided on the fifth substrate pad 920 of the vertical connector 900. The vertical connector 900 is electrically connected to the first substrate 100 through the fourth connector terminal 950. The fourth connector terminal 950 is provided between the fifth substrate pad 920 of the vertical connector 900 and a second substrate pad 104 provided on the second lower surface 110l2 of the first substrate 100. The vertical connector 900 is electrically connected to the second via TGV2 of the first substrate 100 through the fourth connector terminal 950.

[0115] The vertical connector 900 is mounted on the second substrate 500. For example, the vertical connector 900 is electrically connected to the second substrate 500 through the third connector terminal 520. The third connector terminal 520 connects the sixth substrate pad 930 of the vertical connector 900 to the third substrate pad 510 of the second substrate 500. The second substrate 500 is electrically connected to the first substrate 100, the first semiconductor chip 200, and the second semiconductor chip 300 through the third connector terminal 520, the vertical connector 900, and the fourth connector terminal 950.

[0116] Figure 17 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0117] Referring to Figure 17, the semiconductor package further includes at least one chip stack 1000 mounted on the first substrate 100. The chip stack 1000 is positioned horizontally away from the first semiconductor chip 200.

[0118] The chip stack 1000 includes a base semiconductor chip, semiconductor chips stacked on the base semiconductor chip, and a molding film surrounding the semiconductor chips on the base semiconductor chip. The base semiconductor chip is a memory chip such as DRAM, SRAM, MRAM, or flash memory. Alternatively, the base semiconductor chip is a buffer chip that provides only vertical wiring connectivity without another integrated circuit. The semiconductor chip is a memory chip such as DRAM, SRAM, MRAM, or flash memory. The semiconductor chip is stacked on the base semiconductor chip in a chip-on-wafer (COW) structure. The chip stack 1000 includes a chip stack pad 1010 provided on the lower surface of the base semiconductor chip. The memory chip is electrically connected to the chip stack pad 1010 through the base semiconductor chip.

[0119] The chip stack 1000 is mounted on the first substrate 100. For example, the chip stack 1000 is electrically connected to the first substrate 100 through a fifth connecting terminal 1020. The fifth connecting terminal 1020 is provided between the chip stack pad 1010 of the chip stack 1000 and the first upper substrate pad of the first substrate 100. The chip stack 1000 is electrically connected to the wiring layer 120 of the first substrate 100 through the fifth connecting terminal 1020.

[0120] Figures 18 to 23 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0121] Referring to Figure 18, a first core portion 110 is provided. The first core portion 110 includes glass fibers.

[0122] A recess region RS is formed on the first core portion 110 by performing an etching process. The etching process is performed along the edge of the first core portion 110, and the central part of the first core portion 110 is not etched. After the etching process, the first core portion 110 has a flat horizontal portion 112 and a projection 114 that protrudes from the central region of the horizontal portion 112. The first core portion 110 has an inverted T-shaped cross-section.

[0123] Referring to Figure 19, the first core portion 110 is etched to form the first via hole VH1 and the second via hole VH2. The first via hole VH1 penetrates the horizontal portion 112 vertically on one side of the projection 114. The first via hole VH1 is exposed on the upper and lower surfaces of the horizontal portion 112. The second via hole VH2 penetrates the projection 114 and the horizontal portion 112 vertically. The second via hole VH2 is exposed on the upper surface of the projection 114 and the lower surface of the horizontal portion 112.

[0124] Referring to Figure 20, the first via TGV1 is formed by filling the first via hole VH1 with conductive material, and the second via TGV2 is formed by filling the second via hole VH2 with conductive material. The upper surface of the first via TGV1 is coplane with the upper surface of the horizontal portion 112. The upper surface of the second via TGV2 is coplane with the upper surface of the protruding portion 114. The lower surfaces of the first via TGV1 and the lower surfaces of the second via TGV2 are coplane with the lower surfaces of the horizontal portion 112.

[0125] A first substrate pad 102 and a second substrate pad 104 are formed on the first core portion 110. For example, after forming a conductive layer on the first core portion 110, the conductive layer is patterned to form the first substrate pad 102 and the second substrate pad 104. The first substrate pad 102 is connected to the upper surface of the first via TGV1. The second substrate pad 104 is connected to the upper surface of the second via TGV2.

[0126] Waveguides 116 are formed in the first core portion 110. For example, the waveguide 116 is formed in the first core portion by performing an ion exchange process. More specifically, a solution having ions different from those of the material constituting the first core portion 110 is precipitated or an ion implantation process is performed on the region in the first core portion 110 where the waveguide 116 is formed. Through the above process, some of the components of the glass constituting the waveguide 116 are replaced with other elements. As an example, in the waveguide 116, +1 valent alkali elements in the glass components are replaced with other +1 valent elements.

[0127] Referring to Figure 21, a wiring layer 120 is formed on the first core portion 110. As an example, the first core portion 110 is inverted vertically, with the protruding portion 114 located below the horizontal portion 112. After forming an insulating layer covering the upper surface 110u of the first core portion 110, the insulating layer is patterned to form the first insulating film 122. After forming a conductive layer on the first insulating film 122, the conductive layer is patterned to form the first wiring portion 124. The processes of vapor deposition and patterning of the insulating layer and vapor deposition and patterning of the conductive layer are repeatedly performed to form the first insulating film 122 and the first wiring portion 124.

[0128] Referring to Figure 22, the first core portion 110 is inverted vertically, and the protruding portion 114 is positioned above the horizontal portion 112. The second semiconductor chip 300 is mounted on the first substrate 100. The second semiconductor chip 300 is identical or similar to the second semiconductor chip 300 described with reference to Figures 1 to 17. The second semiconductor chip 300 is mounted on the first substrate 100 using a flip-chip method. More specifically, a second connecting terminal 330 is provided on the second chip pad of the second semiconductor chip 300. The second semiconductor chip 300 is positioned on the first substrate 100 such that the second connecting terminal 330 is aligned with the first substrate pad 102 of the first substrate 100, and the sensor portion 350 is aligned with the waveguide 116. The second connecting terminal 330 is in contact with the first substrate pad 102. Subsequently, a reflow process is performed on the second connecting terminal 330 to connect it with the first substrate pad 102 and the second chip pad.

[0129] A cover portion 400 is placed on the first substrate 100. The cover portion 400 is the same as or similar to the cover portion 400 described with reference to Figures 1 to 17. The cover portion 400 covers the top surface and outer surface of the second semiconductor chip 300. Although not shown, the cover portion 400 is bonded to the top surface of the second semiconductor chip 300 using an adhesive or the like.

[0130] Referring to Figure 23, a second substrate 500 is provided. The second substrate 500 is identical or similar to the second substrate 500 described with reference to Figures 1 to 17. The first substrate 100 is mounted on the second substrate 500. More specifically, a third coupling terminal 520 is provided on the third substrate pad 510 of the second substrate 500. The second substrate 500 is positioned on the first substrate 100 such that the third coupling terminal 520 is aligned with the second substrate pad 104 of the first substrate 100. The third coupling terminal 520 makes contact with the second substrate pad 104. Subsequently, a reflow process is performed on the third coupling terminal 520 to connect it with the second substrate pad 104 and the third substrate pad 510.

[0131] Referring again to Figure 1, the result in Figure 23 is inverted vertically, with the first substrate 100 positioned on top of the second substrate 500.

[0132] A first semiconductor chip 200 is provided. The first semiconductor chip 200 is identical or similar to the first semiconductor chip 200 described with reference to Figures 1 to 17. The first semiconductor chip 200 is mounted on a first substrate 100. More specifically, a first coupling terminal 230 is provided on a first chip pad of the first semiconductor chip 200. The first semiconductor chip 200 is positioned on the first substrate 100 such that the first coupling terminal 230 is aligned with a first upper substrate pad of the first substrate 100. The first coupling terminal 230 makes contact with the first upper substrate pad. Subsequently, a reflow process is performed on the first coupling terminal 230 to connect it with the first chip pad and the first upper substrate pad.

[0133] Although embodiments of the present invention have been described above with reference to the drawings, those with ordinary skill in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of Symbols]

[0134] 100 First board 110 First Core Section 112 Horizontal section 114 Protrusion 116 Waveguides 120 wiring layer 200 First Semiconductor Chip 300 Second Semiconductor Chips 350 Sensor section 400 Cover section 500 Second board 600 External Input Device 800 Third Semiconductor Chips 900 Vertical connection

Claims

1. First substrate and The first substrate has a first lower surface and a second lower surface located at different vertical levels from the upper surface of the first substrate. A first semiconductor chip mounted on the upper surface of the first substrate, A second semiconductor chip mounted on the first lower surface of the first substrate, The second semiconductor chip has an optical integrated circuit (PIC), The first substrate includes a second substrate disposed on the second lower surface of the first substrate and covering the second semiconductor chip, The first substrate is, A first via that penetrates the first substrate vertically and connects the first semiconductor chip and the second semiconductor chip, A second via that penetrates the first substrate vertically and connects the first semiconductor chip and the second substrate, The optical waveguide provided on the first lower surface includes, A semiconductor package characterized in that the first distance from the upper surface to the first lower surface of the first substrate is smaller than the second distance from the upper surface to the second lower surface of the first substrate.

2. At least a portion of the second semiconductor chip overlaps perpendicularly with a portion of the optical waveguide, The semiconductor package according to claim 1, characterized in that the second semiconductor chip is optically coupled to the optical waveguide.

3. In a plan view, the first lower surface surrounds the second lower surface, The semiconductor package according to claim 1, characterized in that the first substrate has a T-shaped cross-section.

4. The second lower surface is horizontally separated from the first lower surface. The semiconductor package according to claim 1, characterized in that the first substrate has an inverted L-shaped cross-section.

5. The semiconductor package according to claim 1, characterized in that a portion of the first substrate protrudes from the first lower surface on one side of the second semiconductor chip, and the lower surface of the portion of the first substrate is the second lower surface.

6. The semiconductor package according to claim 1, characterized in that the second substrate includes a printed circuit board or a redistribution board.

7. The first substrate includes a wiring layer provided on the upper surface of the first substrate, and the first via and the second via are connected to the wiring layer. The semiconductor package according to claim 1, characterized in that the first semiconductor chip is mounted on the wiring layer.

8. The first via is exposed on the first lower surface, The semiconductor package according to claim 1, characterized in that the second via is exposed on the second lower surface.

9. The first lower surface further includes a cover portion that covers the second semiconductor chip, On one side of the second semiconductor chip, the cover portion is separated perpendicularly from the optical waveguide. The semiconductor package according to claim 1, characterized in that the space between the optical waveguide and the cover portion constitutes a socket.

10. The semiconductor package according to claim 1, characterized in that the lower surface of the second semiconductor chip and the second lower surface of the first substrate are in contact with the upper surface of the second substrate.

11. The second semiconductor chip includes a third via that penetrates the second semiconductor chip vertically. The semiconductor package according to claim 10, characterized in that the third via is connected to the second substrate.

12. The semiconductor package according to claim 1, characterized in that the active surface of the second semiconductor chip is in contact with the first lower surface of the first substrate.

13. The active surface of the second semiconductor chip faces the first lower surface of the first substrate. The semiconductor package according to claim 1, characterized in that the second semiconductor chip is mounted on the first substrate using a connecting terminal provided between the second semiconductor chip and the first substrate.

14. The present invention further includes a third semiconductor chip mounted on the first lower surface of the first substrate, The third semiconductor chip is arranged horizontally apart from the second semiconductor chip. The semiconductor package according to claim 1, characterized in that the third semiconductor chip has an electronic integrated circuit (EIC).

15. The present invention further includes a fourth semiconductor chip provided between the second semiconductor chip and the second substrate, The fourth semiconductor chip is mounted on the lower surface of the second semiconductor chip. The second semiconductor chip includes a fourth via that penetrates the second semiconductor chip vertically and connects to the fourth semiconductor chip. The semiconductor package according to claim 1, characterized in that the fourth semiconductor chip has an electronic integrated circuit (EIC).

16. The semiconductor package according to claim 1, characterized in that the first semiconductor chip includes a logic chip.

17. The semiconductor package according to claim 1, characterized in that the first substrate includes glass.

18. A first substrate comprising a core made of glass and a wiring layer provided on the upper surface of the core, The core portion has a recessed area formed on the lower surface of the core portion that is in contact with the side surface of the core portion. A first semiconductor chip arranged on the aforementioned wiring layer, A second semiconductor chip is disposed on the bottom surface of the recess region, The second semiconductor chip has a photon integrated circuit (PIC), A cover portion that covers the second semiconductor chip on the bottom surface of the recess region, It includes a second substrate that covers the lower surface of the cover portion and the lower surface of the core portion, The lower surface of the core portion is located at a lower level than the lower surface of the cover portion. The core portion includes an optical waveguide provided at the bottom surface of the recess region, The optical waveguide extends from between the second semiconductor chip and the core portion toward the side surface of the core portion toward one side of the second semiconductor chip. A semiconductor package characterized in that the second semiconductor chip is optically coupled to the optical waveguide.

19. The first substrate is, A first via that vertically penetrates the core portion and is exposed on the upper surface of the core portion and the bottom surface of the recess region, and is connected to the wiring layer, The semiconductor package according to claim 18, further comprising: a second via that penetrates the core portion vertically and is exposed on the upper surface and the lower surface of the core portion, and is connected to the wiring layer.

20. First substrate and A first semiconductor chip mounted on the upper surface of the first substrate, A second semiconductor chip mounted on the lower surface of the first substrate, A second substrate provided on the lower surface of the second semiconductor chip, A vertical connecting portion provided between the second semiconductor chips to electrically connect the first substrate and the second substrate, The system includes a cover portion disposed between the first substrate and the second substrate, The first substrate includes an optical waveguide provided on the lower surface of the first substrate. The optical waveguide extends from above the second semiconductor chip to one side of the second semiconductor chip. Each of the cover portions is positioned on one side of the second semiconductor chip. The cover portion is separated perpendicularly from the optical waveguide, A semiconductor package characterized in that the space between the optical waveguide and the cover portion constitutes a socket.

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