Multilayer ceramic capacitor

Abstract

This invention provides a bottom-electrode type multilayer ceramic capacitor that can increase capacitance even in confined spaces. [Solution] The multilayer ceramic capacitor 10 comprises first and second surfaces 12a and b opposite to the stacking direction x, third and fourth surfaces 12c and d and fifth and sixth surfaces 12e and f opposite to first and second directions y and z, respectively, which are perpendicular to the stacking direction, and has first to third external electrodes 30a to 30c extending in the stacking direction of the fifth surface, a first internal electrode layer 16a connected to the first external electrode, and a second internal electrode layer 16b connected to the second and third external electrodes. The first external electrode includes a first folded portion extending from the fifth surface to a part of the first and second surfaces, the second external electrode includes a second folded portion extending from the fifth surface to a part of the first and second surfaces and a third folded portion extending to a part of the third surface, and the third external electrode includes a fourth folded portion extending from the fifth surface to a part of the first and second surfaces and a fifth folded portion extending to a part of the fourth surface.

Description

[Technical Field]

[0001] This invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] As a capacitor with a lower ESL than conventional 3-terminal multilayer ceramic capacitors, there is a bottom-electrode type 3-terminal capacitor that shortens the high-frequency current path by bringing the signal internal electrode and GND internal electrode leads to the mounting surface. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-35630 [Overview of the project] [Problems that the invention aims to solve]

[0004] In recent years, multilayer ceramic capacitors have played a crucial role in modern electronic devices where mounting in confined spaces is required. In this context, while electronics advancements have led to miniaturization of components, there is a growing demand for higher capacitance. A bottom-electrode type three-terminal multilayer ceramic capacitor capable of achieving high capacitance while being mounted in a limited area has been sought.

[0005] Therefore, the main objective of this invention is to provide a bottom-electrode type multilayer ceramic capacitor that can increase capacitance even in a confined space. [Means for solving the problem]

[0006] The multilayer ceramic capacitor according to this invention comprises a laminate having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode extending in the lamination direction at the center of the fifth surface in the first direction, a second external electrode extending in the lamination direction at one end of the fifth surface in the first direction, and a third external electrode extending in the lamination direction at the other end of the fifth surface in the first direction; the laminate having a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers comprising a first internal electrode layer connected to the first external electrode and a second external electrode A multilayer ceramic capacitor comprising a second internal electrode layer connected to a third external electrode, wherein the first external electrode includes a first folded portion provided from the fifth surface to a portion of each of the first and second surfaces, the second external electrode includes a second folded portion provided from the fifth surface to a portion of each of the first and second surfaces, and a third folded portion provided over a portion of the third surface, and the third external electrode includes a fourth folded portion provided from the fifth surface to a portion of each of the first and second surfaces, and a fifth folded portion provided over a portion of the fourth surface, and the length of the laminate in the second direction is greater than the length in the stacking direction.

[0007] In the multilayer ceramic capacitor according to this invention, the length of the laminate in the second direction is greater than the length in the lamination direction, so the capacitance of the multilayer ceramic capacitor can be increased without increasing the mounting area. [Effects of the Invention]

[0008] This invention provides a bottom-electrode type multilayer ceramic capacitor that can increase capacitance even in a confined space.

[0009] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

Brief Description of the Drawings

[0010] [Figure 1] It is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 2] It is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] It is a right side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] It is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 5] It is a schematic cross-sectional view taken along line V-V in FIG. 2. [Figure 6] It is a schematic cross-sectional view taken along line VI-VI in FIG. 2. [Figure 7] (a) is a schematic cross-sectional view taken along line VIIA-VIIA in FIG. 3, and (b) is a schematic cross-sectional view taken along line VIIB-VIIB in FIG. 3. [Figure 8] It is a perspective view showing the arrangement state of the internal electrode layers inside the laminate of a multilayer ceramic capacitor according to an embodiment of the present invention. <x [Figure 9] (a) is a schematic cross-sectional view showing a modification example of the first internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention, and (b) is a schematic cross-sectional view showing a modification example of the second internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 10A] (a) to (d) are schematic cross-sectional views showing other modification examples of the first internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 10B] (a) to (d) are schematic cross-sectional views showing other modification examples of the second internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] 1. Multilayer Ceramic Capacitor Next, an example of the multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1 is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a front view showing an example of the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a right side view showing an example of the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a bottom view showing an example of the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7(a) is a schematic cross-sectional view taken along line VIIA-VIIA in FIG. 3, and FIG. 7(b) is a schematic cross-sectional view taken along line VIIB-VIIB in FIG. 3. FIG. 8 is a perspective view showing the arrangement state of the internal electrode layers inside the laminate of the multilayer ceramic capacitor according to an embodiment of the present invention.

[0013] As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 10 includes, for example, a laminate 12 and external electrodes 30.

[0014] The laminate 12 has a plurality of dielectric layers 14 laminated thereon and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0015] The laminate 12 has a first surface 12a and a second surface 12b opposite to each other in the lamination direction x, a third surface 12c and a fourth surface 12d opposite to each other in a first direction y orthogonal to the lamination direction x, and a fifth surface 12e and a sixth surface 12f opposite to each other in a second direction z orthogonal to the lamination direction x and the first direction y.

[0016] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f may have irregularities or other features formed on them.

[0017] Here, let the dimension of the laminate 12 in the first direction y be dimension l, the dimension of the laminate 12 in the second direction z be dimension t, and the dimension of the laminate 12 in the stacking direction x be dimension w. Dimension t is larger than dimension w of the laminate 12.

[0018] The laminate 12 includes a volume-forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x.

[0019] In the capacitance forming section 18, a first internal electrode layer 16a and a second internal electrode layer 16b are alternately stacked via a dielectric layer 14.

[0020] The first outer layer 20a is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer 20b is located on the second surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the capacitance forming portion 18.

[0021] As shown in Figure 6, the laminate 12 has an upper region 24a located between the volume-forming portion 18 and the sixth surface 12f, and a lower region 24b located between the volume-forming portion 18 and the fifth surface 12e, which includes the first extraction portion 28a of the first internal electrode layer 16a, and the second extraction portion 28b and third extraction portion 28c of the second internal electrode layer 16b.

[0022] Furthermore, as shown in Figure 5, the laminate 12 has end regions 22a and 22b located between the volume-forming portion 18 and the third surface 12c, and between the volume-forming portion 18 and the fourth surface 12d.

[0023] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0024] The thickness of the dielectric layer 14 is preferably 0.40 μm or more and 0.75 μm or less. Furthermore, the number of dielectric layers 14 to be stacked is preferably 320 or more and 1020 or less. Note that this number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the capacitance forming section 18 and the number of dielectric layers 14 in the first outer layer section 20a and the second outer layer section 20b.

[0025] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b.

[0026] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14. The first internal electrode layer 16a is also drawn out to a fifth surface 12e.

[0027] More specifically, as shown in Figure 7(a), the first internal electrode layer 16a has a first main portion 26a facing the second internal electrode layer 16b, and a first lead portion 28a extending from the first main portion 26a and leading out to the fifth surface 12e. The first main portion 26a is located in the central part of the dielectric layer 14. The first lead portion 28a is exposed to the fifth surface 12e of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the third surface 12c, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The shape of the first main portion 26a and the shape of the first lead portion 28a are not particularly limited, but are preferably rectangular. However, the corners of the first main portion 26a may be rounded.

[0028] As shown in Figure 7(b), the second internal electrode layer 16b has a second main portion 26b facing the first internal electrode layer 16a, and a second lead portion 28b and a third lead portion 28c extending from the second main portion 26b and leading out to the fifth surface 12e. The second main portion 26b is located in the central part of the dielectric layer 14. The second lead portion 28b is exposed to the fifth surface 12e on the third surface 12c side. The third lead portion 28c is exposed to the fifth surface 12e on the fourth surface 12d side. Therefore, the second internal electrode layer 16b is not exposed to the third surface 12c, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The shape of the second main portion 26b and the shape of the first lead portion 28a are not particularly limited, but a rectangular shape is preferred. However, the corners of the second main section 26b may be rounded.

[0029] The first main portion 26a of the first internal electrode layer 16a and the second main portion 26b of the second internal electrode layer 16b face each other. In this embodiment, the first main portion 26a of the first internal electrode layer 16a and the second main portion 26b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0030] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 150 to 500. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 150 to 500. Therefore, the combined number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 300 to 1000.

[0031] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.60 μm or less. Similarly, the thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.60 μm or less.

[0032] The thickness of the first drawer section 28a is greater than the thickness of the first main section 26a. Furthermore, it is preferable that the thickness of the second drawer section 28b is greater than the thickness of the second main section 26b, and the thickness of the third drawer section 28c is greater than the thickness of the second main section 26b.

[0033] Furthermore, as shown in Figure 9(a), it is preferable that the thickness of the region located in the first lower main portion 26a1, which occupies the lower half of the first drawer portion 28a and the first main portion 26a, is greater than the thickness of the first upper main portion 26a2, which occupies the upper half of the first main portion 26a.

[0034] Similarly, as shown in Figure 9(b), the thickness of the region located in the second lower main portion 26b1, which occupies the lower half of the second main portion 26b, is preferably greater than the thickness of the second upper main portion 26b2, which occupies the upper half of the second main portion 26b.

[0035] Furthermore, the coverage of the dielectric layer 14 in the region of the first extraction portion 28a of the first internal electrode layer 16a may be greater than the coverage of the dielectric layer 14 in the region of the first main portion 26a of the first internal electrode layer 16a. Also, the coverage of the dielectric layer 14 in the region of the second extraction portion 28b and the third extraction portion 28c of the second internal electrode layer 16b, in the region equivalent to that region, may be greater than the coverage of the dielectric layer 14 in the region of the second main portion 26b of the second internal electrode layer 16b.

[0036] Furthermore, the coverage of the region located in the first lower main portion 26a1, which occupies the lower half of the first main portion 26a of the first internal electrode layer 16a, with respect to the dielectric layer 14 in that region may be greater than the coverage of the region in the first upper main portion 26a2, which represents the upper half of the first main portion 26a of the first internal electrode layer 16a, with respect to the dielectric layer 14 in that region.

[0037] Furthermore, the coverage of the dielectric layer 14 in the region located in the second lower main portion 26b1, which occupies the second lead portion 28b, the third lead portion 28c, and the lower half of the second main portion 26b of the second internal electrode layer 16b, may be greater than the coverage of the dielectric layer 14 in the region of the second upper main portion 26b2, which represents the upper half of the second main portion 26b of the second internal electrode layer 16b.

[0038] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0039] Furthermore, by including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0040] (external electrode) The external electrode 30 has a first external electrode 30a, a second external electrode 30b, and a third external electrode 30c.

[0041] The first external electrode 30a is positioned on the fifth surface 12e. The first external electrode 30a is also connected to the first lead portion 28a of the first internal electrode layer 16a. Furthermore, the first external electrode 30a has a first covering portion 30a1 that covers the first lead portion 28a of the first internal electrode layer 16a that is exposed on the fifth surface 12e, a first folded portion 30a2 formed on the first surface 12a parallel to the first internal electrode layer 16a, and a second folded portion 30a3 formed on the second surface 12b parallel to the first internal electrode layer 16a.

[0042] The second external electrode 30b is positioned on the fifth surface 12e. The second external electrode 30b is also connected to the second lead portion 28b of the second internal electrode layer 16b. Furthermore, the second external electrode 30b has a second covering portion 30b1 that covers the second lead portion 28b of the second internal electrode layer 16b that is exposed on the fifth surface 12e, a third folded portion 30b2 formed on the first surface 12a parallel to the second internal electrode layer 16b, and a fourth folded portion 30b3 formed on the second surface 12b parallel to the second internal electrode layer 16b. The second external electrode 30b also has a fifth folded portion 30b4 that extends over a portion of the third surface 12c.

[0043] The third external electrode 30c is positioned on the fifth surface 12e. The third external electrode 30c is also connected to the third lead portion 28c of the second internal electrode layer 16b. Furthermore, the third external electrode 30c has a third covering portion 30c1 that covers the second lead portion 28b of the second internal electrode layer 16b that is exposed on the fifth surface 12e, a sixth folded portion 30c2 formed on the first surface 12a parallel to the second internal electrode layer 16b, and a seventh folded portion 30c3 formed on the second surface 12b parallel to the second internal electrode layer 16b. The third external electrode 30c also has an eighth folded portion 30c4 that extends over a portion of the fourth surface 12d.

[0044] Preferably, the length h1 of the first folded portion 30a2 of the first external electrode 30a in the second direction z is greater than d1 / 2, which is half the length d1 of the first folded portion 30a2 in the first direction y. Similarly, preferably, the length of the second folded portion 30a3 of the first external electrode 30a in the second direction z is greater than half the length of the second folded portion 30a3 in the first direction y.

[0045] Furthermore, it is preferable that the length h1 of the first folded portion 30a2 of the first external electrode 30a in the second direction z is 1 / 5 or more and 1 / 2 or less of the length t (dimension t) of the laminate 12 in the second direction z. Similarly, it is preferable that the length of the second folded portion 30a3 of the first external electrode 30a in the second direction z is 1 / 5 or more and 1 / 2 or less of the length t (dimension t) of the laminate 12 in the second direction z.

[0046] Preferably, the length h2 of the third folded portion 30b2 of the second external electrode 30b in the second direction z is greater than the length d2 of the third folded portion 30b2 in the first direction y. Similarly, preferably, the length of the fourth folded portion 30b3 of the second external electrode 30b in the second direction z is greater than the length of the fourth folded portion 30b3 in the first direction y. Furthermore, preferably, the maximum length h4 of the fifth folded portion 30b4 of the second external electrode 30b in the second direction z is greater than the length d2 of the third folded portion 30b2 in the first direction y.

[0047] Furthermore, the length h2 of the third folded portion 30b2 of the second external electrode 30b in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t (dimension t) of the laminate 12 in the second direction z. Similarly, the length of the fourth folded portion 30b3 of the second external electrode 30b in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t of the laminate 12 in the second direction z. Moreover, the maximum length h4 of the fifth folded portion 30b4 of the second external electrode 30b in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t of the laminate 12 in the second direction z.

[0048] Preferably, the length h3 of the sixth folded portion 30c2 of the third external electrode 30c in the second direction z is greater than the length d3 of the sixth folded portion 30c2 in the first direction y. Similarly, preferably, the length of the seventh folded portion 30c3 of the third external electrode 30c in the second direction z is greater than the length of the seventh folded portion 30c3 in the first direction y. Furthermore, preferably, the maximum length of the eighth folded portion 30c4 of the third external electrode 30c in the second direction z is greater than the length d3 of the sixth folded portion 30c2 in the first direction y.

[0049] Furthermore, the length h3 of the sixth folded portion 30c2 of the third external electrode 30c in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t (dimension t) of the laminate 12 in the second direction z. Similarly, the length of the seventh folded portion 30c3 of the third external electrode 30c in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t of the laminate 12 in the second direction z. Moreover, the maximum length of the eighth folded portion 30c4 of the third external electrode 30c in the second direction z is preferably 1 / 5 or more and 1 / 2 of the length t of the laminate 12 in the second direction z.

[0050] The length l1 in the first direction y of the first covering portion 30a1 of the first external electrode 30a, located on the fifth surface 12e, is longer than the length l2 in the first direction y of the second covering portion 30b1 of the second external electrode 30b, and longer than the length l3 in the first direction y of the third covering portion 30c1 of the third external electrode 30c.

[0051] As described above, the configuration of each external electrode 30 with its respective folded portion allows for a taller multilayer ceramic capacitor 10 with the external electrodes 30 on the bottom side, thereby increasing the volume of the external electrodes 30 and lowering the center of gravity, thus stabilizing the mountability of the multilayer ceramic capacitor 10. Furthermore, by increasing the length of the second direction (height direction) z of each folded portion of the external electrodes 30 located on the bottom side, the contact area between the solder and the external electrodes 30 can be increased during solder mounting, thereby improving the bonding strength between the mounting substrate and the multilayer ceramic capacitor 10.

[0052] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0053] The base electrode layer 32 has a first base electrode layer 32a, a second base electrode layer 32b, and a third base electrode layer 32c.

[0054] The plating layer 34 has a first plating layer 34a, a second plating layer 34b, and a third plating layer 34c.

[0055] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c.

[0056] The first underlay electrode layer 32a is positioned on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover a portion of the first surface 12a and the second surface 12b, respectively. The second base electrode layer 32b is positioned on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover a portion of each of the first surface 12a, the second surface 12b, and the third surface 12c. The third underlay electrode layer 32c is positioned on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover a portion of the first surface 12a, the second surface 12b, and the fourth surface 12d, respectively.

[0057] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0058] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0059] In the first base electrode layer 32a located on the fifth surface 12e and extending in the lamination direction x at the center of the first direction y connecting the third surface 12c and the fourth surface 12d, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f is preferably 10 μm or more and 30 μm or less. In the second base electrode layer 32b located on the fifth surface 12e and extending in the lamination direction x at one end of the first direction y connecting the third surface 12c and the fourth surface 12d, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f is preferably 10 μm or more and 30 μm or less. In the third base electrode layer 32c located on the fifth surface 12e and extending in the lamination direction x at the other end of the first direction y connecting the third surface 12c and the fourth surface 12d, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f is preferably 10 μm or more and 30 μm or less.

[0060] Furthermore, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a of the first folded portion 30a2 located in part of the first surface 12a and the second folded portion 30a3 located in part of the second surface 12b is preferably, for example, 3 μm or more and 10 μm or less. The thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b of the third folded portion 30b2 located in part of the first surface 12a and the second base electrode layer 32b of the fourth folded portion 30b3 located in part of the second surface 12b is preferably, for example, 3 μm or more and 10 μm or less. The thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the third base electrode layer 32c of the sixth folded portion 30c2 located in part of the first surface 12a and the third base electrode layer 32c of the seventh folded portion 30c3 located in part of the second surface 12b is preferably, for example, 3 μm or more and 10 μm or less.

[0061] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0062] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0063] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0064] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0065] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0066] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0067] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0068] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0069] The thickest part of the conductive resin layer is preferably, for example, 20 μm to 40 μm.

[0070] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0071] The plating layer 34 is positioned to cover the underlying electrode layer 32.

[0072] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0073] The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0074] Alternatively, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. Although not shown in the diagrams below, a structure in which a plating layer is provided without a base electrode layer 32 will be described.

[0075] The first external electrode 30a, the second external electrode 30b, and the third external electrode 30c, or each of them, may have a plating layer directly formed on the surface of the laminate 12 without providing an underlayment electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0076] Furthermore, if the plating layer is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be converted into a lower profile, i.e., a thinner design, or into the thickness of the laminate 12, i.e., the thickness of the capacitance forming section 18, thereby improving the design flexibility of the thin chip.

[0077] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability.

[0078] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 30a, the second external electrode 30b, and the third external electrode 30c may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode.

[0079] In this case, when the external electrode 30 is formed using only the plating layer without providing the underlayer electrode layer 32, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 32 is 1 μm or more and 15 μm or less.

[0080] Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0081] The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, in the first direction y is defined as dimension L. Dimension L is preferably 0.60 mm or more and 1.30 mm or less. The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, in the second direction z is defined as dimension T. Dimension T is preferably 0.50 mm or more and 1.20 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, including the laminated body 12 and the external electrodes 30, is defined as the W dimension. The W dimension is preferably 0.30 mm or more and 0.95 mm or less.

[0082] In the multilayer ceramic capacitor 10 shown in Figure 1, the t dimension of the laminate 12 is larger than the w dimension, so the capacitance of the multilayer ceramic capacitor can be increased without increasing the mounting area.

[0083] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the length h1 of the first folded portion 30a2 of the first external electrode 30a in the second direction z is greater than d1 / 2, which is half the length d1 of the first folded portion 30a2 in the first direction y, and the length of the second folded portion 30a3 of the first external electrode 30a in the second direction z is greater than half the length of the second folded portion 30a3 in the first direction y, the center of gravity of the multilayer ceramic capacitor 10 can be lowered, thereby stabilizing its mountability on the mounting substrate.

[0084] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of this multilayer ceramic capacitor. The manufacturing method of the multilayer ceramic capacitor 10 will be described below.

[0085] First, prepare the dielectric sheet and the conductive paste for the internal electrodes. The ceramic green sheet and the conductive paste for the internal electrodes contain a binder (e.g., a known organic binder) and a solvent (e.g., an organic solvent).

[0086] Next, a conductive paste for internal electrodes is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer formed on it and a dielectric sheet with the pattern of the second internal electrode layer formed on it.

[0087] More specifically, a gravure printing plate is prepared for printing the first internal electrode layer and the second internal electrode layer, and each internal electrode layer of the present invention can be printed. In the design of the internal electrode shape of the gravure printing plate, by adjusting thickness control factors such as the depth of the plate, the thickness of the main part of each internal electrode layer can be made thinner, and the thickness of the leading part can be made thicker than the main part. Accordingly, the coverage of the main part can be made smaller, and the coverage of the leading part can be made larger than the coverage of the main part.

[0088] Here, a portion that will form a capacitance-forming area is formed by alternately stacking dielectric sheets on which a first internal electrode layer and a second internal electrode layer are printed, in order to obtain the desired structure.

[0089] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second outer layer portion 20b on the second surface 12b side. Subsequently, the portion that will become the capacitance forming portion 18, formed by the above process, is stacked on top of the portion that will become the second outer layer portion 20b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the capacitance forming portion 18 to form the first outer layer portion 20a on the first surface 12a side. This completes the production of the laminated sheet.

[0090] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0091] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0092] The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0093] (base electrode layer) Next, the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, and the third base electrode layer 32c of the third external electrode 30c are formed on the fifth surface 12e of the laminate 12 obtained by firing.

[0094] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0095] Here, various methods can be used for forming the baked layer. For example, a method can be used in which the orientation of the laminate 12 is aligned using a camera or magnet so that the fifth surface 12e is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the first base electrode layer 32a to the third base electrode layer 32c can be formed not only on the fifth surface 12e, but also on a part of the first surface 12a and a part of the second surface 12b. Furthermore, for the second and third external electrodes, by adjusting the position and size of the slits or holes through which the conductive paste is extruded, the base electrode layer 32 can be formed on a part of the third surface 12c and a part of the fourth surface 12d.

[0096] Furthermore, the layer can also be formed using a roller transfer method. When forming the base electrode layer 32 of the first external electrode not only on the fifth surface 12e but also on a portion of the first surface 12a and a portion of the second surface 12b using the roller transfer method, it is possible to form the base electrode layer 32 on a portion of the first surface 12a and a portion of the second surface 12b by increasing the pressing pressure during roller transfer. In addition, for the second and third external electrodes, the base electrode layer 32 can be formed on a portion of the third surface 12c and a portion of the fourth surface 12d by adjusting the position and size of the roller grooves for transferring the conductive paste.

[0097] (Conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0098] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0099] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, such as a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0100] (thin film layer) Furthermore, when forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0101] (Plating layer) Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. In that case, it can be formed by the following method.

[0102] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0103] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0104] 3. Other variations of each internal electrode Figures 10A(a) to (d) show modified examples of the first internal electrode layer 16a provided in the multilayer ceramic capacitor 10 according to the present invention. The first internal electrode layer 16a1 shown in Figure 10A(a) has inclined portions 27a1 and 27a2 at both corners of the first main portion 26a on the sixth surface 12f side, such that the length of the first main portion 26a in the first direction y decreases as it moves from the fifth surface 12e toward the sixth surface 12f. Therefore, the length of the side of the first main portion 26a in the first direction y on the sixth surface 12f side of the first internal electrode layer 16a1 is l 12 The length of the side in the first direction y of the first main part 26a on the fifth surface 12e side is l 11 That one is longer. The first internal electrode layer 16a2 shown in Figure 10A(b) has rounded edges 27a3 and 27a4 at both corners of the first main portion 26a on the sixth surface 12f side, such that the length of the first main portion 26a in the first direction y decreases as it moves from the fifth surface 12e towards the sixth surface 12f. Therefore, the length of the side of the first main portion 26a in the first direction y on the sixth surface 12f side of the first internal electrode layer 16a2 is l 12 The length of the side in the first direction y of the first main part 26a on the fifth surface 12e side is l 11 That one is longer. The first internal electrode layer 16a3 shown in FIG. 10A(c) is provided with corner notch portions 27a5 and 27a6 at both corners of the first main portion 26a on the sixth surface 12f side. Therefore, the length l of the side in the first direction y of the first main portion 26a on the sixth surface 12f side of the first internal electrode layer 16a3 12 is longer than the length l of the side in the first direction y of the first main portion 26a on the fifth surface 12e side 11 . The first internal electrode layer 16a4 shown in FIG. 10A(d) is provided with a notch portion 27a7 in the middle of the first main portion 26a on the sixth surface 12f side. By providing the notch portion 27a7, the side in the first direction y of the first main portion 26a on the sixth surface 12f side is divided. Therefore, the length l of the side in the first direction y of the first main portion 26a on the sixth surface 12f side of the first internal electrode layer 16a4 13 and the length l 14 is longer than the length l of the side in the first direction y of the first main portion 26a on the fifth surface 12e side 11 in total length. With the structure of the first internal electrode layers 16a1 to 16a4 as shown in FIGS. 10A(a) to (d), even if the multilayer ceramic capacitor 10 provided with an electrode on the bottom surface side as in the present invention is made taller, its center of gravity can be lowered, so that the mounting property of the multilayer ceramic capacitor 10 can be stabilized.

[0105] Also, FIGS. 10B(a) to (d) show modified examples of the second internal electrode layer 16b included in the multilayer ceramic capacitor 10 according to the present invention. The second internal electrode layer 16b1 shown in FIG. 10B(a) is provided with inclined portions 27b1 and 27b2 at both corners of the second main portion 26b on the sixth surface 12f side, such that the length of the second main portion 26b in the first direction y decreases as it goes from the fifth surface 12e to the sixth surface 12f. Therefore, the length l of the side in the first direction y of the second main portion 26b on the sixth surface 12f side of the second internal electrode layer 16b1 22 is longer than the length l of the side in the first direction y of the second main portion 26b on the fifth surface 12e side 21 . As shown in Figure 10B(b), the second internal electrode layer 16b2 has rounded edges 27b3 and 27b4 at both corners of the second main portion 26b on the sixth surface 12f side, such that the length of the second main portion 26b in the first direction y decreases as it moves from the fifth surface 12e towards the sixth surface 12f. Therefore, the length of the side of the second main portion 26b in the first direction y on the sixth surface 12f side of the second internal electrode layer 16b2 is l 22 The length of the side in the first direction y of the second main part 26b on the fifth face 12e side is l 21 That one is longer. The second internal electrode layer 16b3 shown in Figure 10B(c) has corner notches 27b5 and 27b6 at both corners of the second main portion 26b on the sixth surface 12f side. Therefore, the length of the side in the first direction y of the second main portion 26b on the sixth surface 12f side of the second internal electrode layer 16b3 is l 22 The length of the side in the first direction y of the second main part 26b on the fifth face 12e side is l 21 That one is longer. As shown in Figure 10B(d), the second internal electrode layer 16b4 has a notch 27b7 in the middle of the second main part 26b on the sixth surface 12f side. The notch 27b7 divides the side of the second main part 26b on the sixth surface 12f side in the first direction y. Therefore, the length of the side of the second main part 26b on the sixth surface 12f side in the first direction y is l. 23 and length l 24 The length of the side in the first direction y of the second main part 26b on the fifth face 12e side is greater than the total length of the sides l 21 That one is longer. With the structure of the second internal electrode layers 16b1 to 16b4 as shown in Figures 10B(a) to (d), even if the multilayer ceramic capacitor 10, which has electrodes on the bottom side as in the present invention, is made taller, its center of gravity can be lowered, thereby stabilizing the mountability of the multilayer ceramic capacitor 10.

[0106] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, and these modifications are included in the present invention.

[0107] <1> A laminate comprising: a first surface and a second surface facing each other in the stacking direction; a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction; and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; In the central portion of the fifth surface in the first direction, a first external electrode extending in the stacking direction, A second external electrode extending in the stacking direction at one end of the fifth surface in the first direction, A third external electrode extending in the stacking direction at the other end of the fifth surface in the first direction, Equipped with, The laminated body is Multiple dielectric layers, multiple internal electrode layers, It has, The plurality of internal electrode layers are A first internal electrode layer connected to the first external electrode, A second internal electrode layer connected to the second external electrode and the third external electrode, It has, The first external electrode has a first folded portion that extends from the fifth surface to a portion of each of the first and second surfaces, Includes, The second external electrode has a second folded portion extending from the fifth surface to a portion of each of the first and second surfaces, and a third folded portion extending to a portion of the third surface. Includes, The third external electrode has a fourth folded portion extending from the fifth surface to a portion of each of the first and second surfaces, and a fifth folded portion extending to a portion of the fourth surface. Includes, A multilayer ceramic capacitor in which the length of the laminate in the second direction is greater than the length in the lamination direction.

[0108] <2> The length of the first folded portion in the second direction is greater than half the length of the first folded portion in the first direction. <1> The multilayer ceramic capacitor described above.

[0109] <3> The length of the second folded portion in the second direction is greater than the length of the second folded portion in the first direction. The length of the third folded portion in the second direction is greater than the length of the third folded portion in the first direction. <1> or <2> The multilayer ceramic capacitor described above.

[0110] <4> The length of the first folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. <1> or <3> A multilayer ceramic capacitor as described in any of the following.

[0111] <5> The length of the second folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. The length of the third folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. <1> or <4> A multilayer ceramic capacitor as described in any of the following.

[0112] <6> The length of the first external electrode located on the fifth surface in the first direction is longer than the length of the second external electrode and the third external electrode located on the fifth surface in the first direction. <1> or <5> A multilayer ceramic capacitor as described in any of the following. [Explanation of symbols]

[0113] 10 Multilayer ceramic capacitors 12-layer structure 12a First face 12b Second face 12c Third side 12d Fourth face 12e Fifth side 12f Sixth face 14 Dielectric layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacity forming part 20a First outer layer 20b Second outer layer 22a, 22b L gap 24a, 24b W gap 25a First main part 25b Second Main Part 28a First drawer 28b Second drawer section 28c Third drawer 30 External electrode 30a First external electrode 30a1 First covering portion 30a2 First folded section 30a3 Second folded section 30b Second external electrode 30b1 Second covering portion 30b2 Third fold 30b3 Fourth fold 30b4 Fifth fold 30c Third external electrode 30c1 Third covering part 30c2 Sixth fold 30c3 Seventh fold 30c4 Eighth fold 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 32c Third Underlay Electrode Layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer x stacking direction y First direction z Second direction

Claims

1. A laminate comprising: a first surface and a second surface facing each other in the stacking direction; a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction; and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; In the central portion of the fifth surface in the first direction, a first external electrode extending in the stacking direction, A second external electrode extending in the stacking direction at one end of the fifth surface in the first direction, A third external electrode extending in the stacking direction at the other end of the fifth surface in the first direction, Equipped with, The laminated body is Multiple dielectric layers, multiple internal electrode layers, It has, The plurality of internal electrode layers are A first internal electrode layer connected to the first external electrode, A second internal electrode layer connected to the second external electrode and the third external electrode, It has, The first external electrode has a first folded portion that extends from the fifth surface to a portion of each of the first and second surfaces, Includes, The second external electrode has a second folded portion extending from the fifth surface to a portion of each of the first and second surfaces, and a third folded portion extending to a portion of the third surface. Includes, The third external electrode has a fourth folded portion extending from the fifth surface to a portion of each of the first and second surfaces, and a fifth folded portion extending to a portion of the fourth surface. Includes, A multilayer ceramic capacitor in which the length in the second direction is greater than the length in the stacking direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the length of the first folded portion in the second direction is greater than half the length of the first folded portion in the first direction.

3. The length of the second folded portion in the second direction is greater than the length of the second folded portion in the first direction. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the length of the third folded portion in the second direction is greater than the length of the third folded portion in the first direction.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the length of the first folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction.

5. The multilayer ceramic capacitor according to claim 3, wherein the length of the first folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction.

6. The length of the second folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the length of the third folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction.

7. The length of the second folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. The multilayer ceramic capacitor according to claim 3, wherein the length of the third folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction.

8. The length of the second folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction. The multilayer ceramic capacitor according to claim 5, wherein the length of the third folded portion in the second direction is 1 / 5 or more and 1 / 2 or less of the length of the laminate in the second direction.

9. The multilayer ceramic capacitor according to claim 1, wherein the length of the first external electrode located on the fifth surface in the first direction is longer than the lengths of the second external electrode and the third external electrode located on the fifth surface in the first direction.

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