Semiconductor device and method for manufacturing the same

Abstract

This makes it easier to manage the positional accuracy of the terminals. [Solution] The semiconductor device 10 comprises a semiconductor chip having a plurality of main electrodes and gate electrodes, a first substrate on which the semiconductor chip is mounted, a second substrate provided on the first substrate and having conductive plates 30a1 to 30a4 electrically connected to the semiconductor chip on its front surface, and a case 11. The case 11 has openings 11a to 11d on its upper surface that expose at least a portion of the conductive plates 30a1 to 30a4 to the outside, and houses the semiconductor chip, the first substrate, and the second substrate.

Description

Technical Field

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[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a sealing resin of a semiconductor device, a semiconductor device has been proposed in which an opening for exposing a conductor portion provided on a substrate on which a semiconductor chip is mounted is provided, and a terminal or an electronic component is connected to the exposed conductor portion (see, for example, Patent Documents 1-8).

Prior Art Documents

Patent Documents

[0006] The device may further include terminals connected to the conductive plate exposed through the opening.

[0007] The area of ​​the portion of the conductive plate exposed from the opening may be larger than the area of ​​the connection portion of the terminal connected to the conductive plate.

[0008] The second substrate is a printed circuit board in which multiple insulating layers and conductive layers are laminated, and the conductive plate may be included in the uppermost conductive layer of the printed circuit board.

[0009] The thickness of the conductive plate may be 50 μm or more and 2000 μm or less.

[0010] The opening may have a tapered shape, with the opening area narrowing from the top surface to the bottom surface of the case.

[0011] The conductive plate includes a first conductive plate and a second conductive plate having different potentials, and at least a portion of the first conductive plate and at least a portion of the second conductive plate may be exposed to the outside through a common opening or different openings.

[0012] The first conductive plate may be electrically connected to the gate electrode, and the second conductive plate may be electrically connected to one of the plurality of main electrodes.

[0013] Also, according to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: mounting a semiconductor chip having a plurality of main electrodes and a gate electrode on a first substrate; disposing a second substrate having a conductive plate on a front surface on the first substrate, and electrically connecting the semiconductor chip and the conductive plate; and forming a case that houses the semiconductor chip, the first substrate, and the second substrate, and has an opening on an upper surface that exposes at least a part of the conductive plate to the outside.

[0014] The method may further include a step of laser welding a terminal to the conductive plate exposed from the opening.

[0015] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Effects of the Invention

[0016] On one side, it becomes easier to manage the positional accuracy of the terminals.

Brief Description of the Drawings

[0017] [Figure 1] It is a top view of an example of a semiconductor device according to the first embodiment. [Figure 2] It is a view showing a part of a side surface as seen from the +X direction of FIG. 1 (excluding the sealing resin). [Figure 3] It is a cross - sectional view showing a part of a cross - section along line III - III of FIG. 1. [Figure 4] It is a top view of an example of a first substrate on which a semiconductor chip is mounted. [Figure 5] It is a top view of an example of a second substrate. [Figure 6] It is a view showing an example of a circuit configuration of a semiconductor device. [Figure 7] It is a cross - sectional view showing an example of connection of a terminal. [Figure 8] It is a view showing the relationship between the area of an exposed portion of a conductive plate and the area of a connection portion of a terminal. [Figure 9]This figure shows an example of a semiconductor device manufacturing method according to the first embodiment. [Figure 10] This is a top view of an example of a semiconductor device according to the second embodiment. [Figure 11] Figure 10 is a cross-sectional view showing a portion of the cross-section along the line XI-XI. [Figure 12] This is a top view of an example of a second substrate in a semiconductor device according to a second embodiment. [Modes for carrying out the invention]

[0018] The embodiments for carrying out the invention will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the XY plane facing upwards (+Z direction) in the semiconductor device shown in the drawing. Similarly, "up" refers to the direction upwards (+Z direction) in the semiconductor device shown in the drawing. "Back surface" and "bottom surface" refer to the XY plane facing downwards (-Z direction) in the semiconductor device shown in the drawing. Similarly, "down" refers to the direction downwards (-Z direction) in the semiconductor device shown in the drawing. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," "down," and "side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions "up" and "down" are not limited to the direction of gravity.

[0019] (First Embodiment) Figure 1 is a top view of an example of a semiconductor device according to the first embodiment. Figure 2 is a view of a part of the side of Figure 1 as seen from the +X direction (excluding the sealing resin). Figure 3 is a cross-sectional view showing a part of the cross-section along line III-III in Figure 1. Figure 4 is a top view of an example of a first substrate on which a semiconductor chip is mounted. Figure 5 is a top view of an example of a second substrate.

[0020] The semiconductor device 10 has semiconductor chips 21a1 to 21a8 and 21b1 to 21b8, as shown in Figure 4. The semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 are mounted on the first substrate 20.

[0021] In this embodiment, the semiconductor device 10 has a module configuration of a half-bridge circuit including an upper arm portion A and a lower arm portion B. The upper arm portion A includes semiconductor chips 21a1 to 21a8. The lower arm portion B of the semiconductor device 10 includes semiconductor chips 21b1 to 21b8.

[0022] The semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 have multiple main electrodes (sometimes called input electrodes or output electrodes) and gate electrodes (sometimes called control electrodes). For example, as shown in Figure 4, semiconductor chip 21a1 has a main electrode 21s and a gate electrode 21g on its upper surface. Although not shown in the figure, other main electrodes are also provided on the back surface of semiconductor chip 21a1. The other semiconductor chips 21a2 to 21a8 and 21b1 to 21b8 have an electrode configuration similar to that of semiconductor chip 21a1.

[0023] The semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 may be semiconductor chips composed mainly of silicon carbide. Such semiconductor chips are, for example, power MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). In this case, the semiconductor chip has a drain electrode, which is one of the main electrodes, on its bottom surface, and a gate electrode and a source electrode, which is one of the main electrodes, on its top surface.

[0024] Furthermore, the semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 may be semiconductor chips composed primarily of silicon. Such semiconductor chips may include RC (Reverse-Conducting)-IGBTs that combine the functions of IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheeling Diodes). This semiconductor chip has a collector electrode, which is one of the main electrodes, on its lower surface, and a gate electrode and an emitter electrode, which is one of the main electrodes, on its upper surface. In this embodiment, the case where the semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 are power MOSFETs is used as an example for explanation, but the embodiment is not limited to this form.

[0025] The first substrate 20 on which semiconductor chips 21a1 to 21a8 and 21b1 to 21b8 are mounted includes conductive plates 20a1 to 20a4, a resin layer 20b, and a metal plate 20c, as shown in Figures 2 to 4. The conductive plates 20a1 to 20a4 are formed on the front surface of the resin layer 20b, and the metal plate 20c is formed on the back surface of the resin layer 20b.

[0026] Conductive plates 20a1 and 20a2 are formed on the upper arm portion A, and conductive plate 20a3 is formed on the lower arm portion B. Conductive plate 20a4 has a configuration that extends from the center of the first substrate 20 toward the outer edge and is formed in the central part of the region of the upper arm portion A on the resin layer 20b.

[0027] The conductive plates 20a1 to 20a4 are formed from a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these. Plating may be performed to improve the corrosion resistance of the conductive plates 20a1 to 20a4. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0028] The resin layer 20b is rectangular in shape when viewed from above. The corners of the resin layer 20b may be rounded (R-chamfered) or chamfered (C-chamfered). The resin layer 20b is formed from a resin material. As the resin material, an epoxy resin can be used which has insulating properties and a filler with better thermal conductivity than the resin material has been added.

[0029] The metal plate 20c is formed primarily from a metal with excellent thermal conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. To improve the corrosion resistance of the metal plate, plating may be performed. In this case, the plating material used may be, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0030] In the example shown in Figure 4, semiconductor chips 21a1 to 21a4 and external terminal 12a are mounted on conductive plate 20a1, semiconductor chips 21a5 to 21a8 and external terminal 12b are mounted on conductive plate 20a2, semiconductor chips 21b1 to 21b8 and external terminal 12d are mounted on conductive plate 20a3, and external terminal 12c is mounted on conductive plate 20a4.

[0031] As shown in Figure 2, semiconductor chips 21a1 and 21a2 are electrically connected to the conductive plate 20a1 by bonding materials 22a1 and 22a2. One end of several post electrodes (sometimes called wiring pins, etc.) 23s1 and 23s2 are connected to the source electrode of each semiconductor chip 21a1 and 21a2 by bonding materials 22b1 and 22b2. The other ends of the post electrodes 23s1 and 23s2 are connected to the second substrate 30. Furthermore, one end of post electrodes 23g1 and 23g2 are connected to the gate electrodes of each semiconductor chip 21a1 and 21a2 by bonding materials 22b1 and 22b2. The other ends of the post electrodes 23s1, 23s2, 23g1, and 23g2 are connected to the second substrate 30. Although not shown in the diagram, the other semiconductor chips 21a3 to 21a8 and 21b1 to 21b8 are similarly connected to one of the conductive plates 20a1 to 20a3 and also to the second substrate 30.

[0032] Although not shown in Figure 2, external terminal 12a is connected to conductive plate 20a1 by a bonding material, and external terminal 12b is connected to conductive plate 20a2 by a bonding material. External terminal 12c is connected to conductive plate 20a4 by a bonding material, and external terminal 12d is connected to conductive plate 20a3 by a bonding material. External terminals 12a to 12d may also be connected to each conductive plate of the first substrate 20 by laser welding or ultrasonic welding.

[0033] External terminals 12a and 12b are P terminals, which are the positive terminals in the half-bridge circuit, and external terminal 12c is N terminal, which is the negative terminal in the half-bridge circuit. External terminal 12d is the output terminal of the half-bridge circuit. As shown in Figure 4, bosses p1, p2, p3, and p4 are formed on the parts where the bonding material of external terminals 12a to 12d contacts, protruding toward the first substrate 20. Bosses p1, p2, p3, and p4 may be created by press working when manufacturing external terminals 12a to 12d. The thickness of the bonding material can be ensured by the height of the bosses.

[0034] As the joining material described above (for example, joining materials 22a1, 22a2, 22b1, 22b2, etc.), solder is used. Lead-free solder is used. Lead-free solder mainly consists of at least one of the following alloys: a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, or a tin-silver-indium-bismuth alloy. A metal sintered body may be used instead of solder. The material of the metal sintered body is silver, gold, nickel, copper, or an alloy containing at least one of these.

[0035] Furthermore, in the example of the first substrate 20 shown in Figure 4, conductive pin terminals 25a1 are provided on conductive plate 20a1, conductive pin terminals 25a2 are provided on conductive plate 20a2, and conductive pin terminals 25a3 to 25a6 are provided on conductive plate 20a3. One end of conductive pin terminals 25a1 to 25a6 is connected to one of the conductive plates 20a1 to 20a3, and the other end is connected to the second substrate 30.

[0036] Furthermore, in the example of the first substrate 20 shown in Figure 4, a conductive member 25b1 is provided on the conductive plate 20a4, and conductive members 25b2 and 25b3 are provided on the conductive plate 20a3. One end of conductive member 25b1 is connected to the conductive plate 20a4, and the other end of conductive member 25b1 is connected to the second substrate 30. One end of conductive members 25b2 and 25b3 is connected to the conductive plate 20a3, and the other ends of conductive members 25b2 and 25b3 are connected to the second substrate 30.

[0037] The conductive members 25b1 to 25b3 are configured, for example, with multiple conductive pins provided on the upper surface of a block-shaped base portion. One end of each conductive pin is connected to the base portion, and the other end of each conductive pin is connected to the second substrate 30. However, the conductive members 25b1 to 25b3 are not limited to this shape.

[0038] In the semiconductor device 10, the first substrate 20 and the second substrate 30 are electrically connected via post electrodes, conductive pin terminals, and conductive members as described above, and a three-dimensional wiring structure is provided on the semiconductor chips 21a1 to 21a8 and 21b1 to 21b8. With this configuration, the second substrate 30 is supported above the first substrate 20 with a predetermined space left, and the semiconductor chips 21a1 to 21a8 of the upper arm A and the semiconductor chips 21b1 to 21b8 of the lower arm B are electrically connected through a conductive layer formed on the second substrate 30.

[0039] As shown in Figures 2 and 3, the second substrate 30 is positioned above the first substrate 20, facing the front surface of the first substrate 20. In the example shown in Figure 3, the second substrate 30 has a multilayer structure in which multiple conductive layers and insulating layers are stacked in the order of conductive layer 30e, insulating layer 30d, conductive layer 30c, insulating layer 30b, and conductive layer 30a from bottom to top. Note that the number of conductive layers is not limited to this example. The conductive layers 30a, 30c, and 30e may be electrically connected by the aforementioned post electrodes, conductive pin terminals, conductive members, or vias. Such a second substrate 30 can also be called a printed circuit board.

[0040] Figure 5 shows examples of conductive plates 30a1, 30a2, 30a3, 30a4, 30a5, 30a6, and 30a7 on the front surface of the second substrate 30. Conductive plates 30a1 to 30a7 are conductive plates included in the uppermost conductive layer 30a.

[0041] The conductive plate 30a1 is electrically connected to the gate electrodes of the semiconductor chips 21a1 to 21a8 on the upper arm portion A. The conductive plate 30a1 is provided with eight holes (for example, holes 31a and 31b in Figure 5) into which post electrodes connected to the gate electrodes are inserted. Each hole penetrates the second substrate 30. For example, the post electrode 23g1 shown in Figure 2 is inserted into hole 31a, and the conductive plate 30a1 is electrically connected to the gate electrode 21g of the semiconductor chip 21a1 via the post electrode 23g1. Also, the post electrode 23g2 shown in Figure 2 is inserted into hole 31b, and the conductive plate 30a1 is electrically connected to the gate electrode of the semiconductor chip 21a2 via the post electrode 23g2.

[0042] Furthermore, the conductive plate 30a1 has an exposed portion 32 that is exposed to the outside of the semiconductor device 10 through an opening 11a formed on the upper surface of the case 11, which will be described later. Terminals, which will be described later, are connected to the exposed portion 32. These terminals are used as control terminals (also called gate terminals). In addition, in order to equalize the gate wiring length from each gate electrode of the semiconductor chips 21a1 to 21a8 to the terminals connected to the exposed portion 32, a plurality of slits 33a, 33b, 33c, and 33d are formed in the conductive plate 30a1.

[0043] The conductive plate 30a2 is electrically connected to the source electrodes of the semiconductor chips 21a1 to 21a8 of the upper arm portion A. The conductive plate 30a2 has regions (for example, regions 35a and 35b in Figure 5) with multiple holes into which multiple post electrodes connected to each source electrode are inserted, provided for each of the semiconductor chips 21a1 to 21a8. Each hole penetrates the second substrate 30.

[0044] For example, post electrodes 23s1, shown in Figure 2, are inserted into multiple holes in region 35a, and the conductive plate 30a2 and the main electrode 21s (source electrode) of the semiconductor chip 21a1 are electrically connected via the post electrodes 23s1. In addition, post electrodes 23s2, shown in Figure 2, are inserted into multiple holes in region 35a, and the conductive plate 30a2 and the source electrode of the semiconductor chip 21a2 are electrically connected via the post electrodes 23s2.

[0045] Furthermore, the conductive plate 30a2 has an exposed portion 36 that is exposed to the outside of the semiconductor device 10 through an opening 11b formed on the upper surface of the case 11, which will be described later. Terminals, which will be described later, are connected to the exposed portion 36. These terminals are used as auxiliary source terminals. By using the conductive plate 30a2 which is electrically connected to the source electrodes of the semiconductor chips 21a1 to 21a8, and by making the auxiliary source terminals for the semiconductor chips 21a1 to 21a8 common, oscillation can be suppressed.

[0046] Conductive plate 30a3 is electrically connected to the gate electrodes of semiconductor chips 21b1 to 21b8 in the lower arm B, and conductive plate 30a4 is electrically connected to the source electrodes of semiconductor chips 21b1 to 21b8 in the lower arm B. Conductive plate 30a3 has the same configuration as conductive plate 30a1 described above, and conductive plate 30a4 has the same configuration as conductive plate 30a2 described above.

[0047] Conductive plate 30a5 is connected to conductive member 25b2 provided on the first substrate 20, conductive plate 30a6 is connected to conductive member 25b3 provided on the first substrate 20, and conductive plate 30a7 is connected to conductive member 25b1 provided on the first substrate 20.

[0048] Furthermore, the second substrate 30 is provided with holes 37a, 37b, 37c, 37d, 37e, and 37f through which the aforementioned conductive pin terminals 25a1 to 25a6 pass. The conductive pin terminals 25a1 to 25a6 are electrically connected to either the conductive layer 30c or 30e contained in the second substrate 30.

[0049] An insulating resin can be used as the insulating material for the insulating layers 30b and 30d of the second substrate 30, and as the insulating material between the conductive plates of the conductive layers 30a, 30c, and 30e. Examples of insulating resins that can be used include phenolic resin, epoxy resin, polyimide resin, and glass epoxy resin. Furthermore, the conductive plates included in the conductive layers 30a, 30c, and 30e of the second substrate 30 are formed from a metal with excellent conductivity.

[0050] Such metals are, for example, copper, aluminum, or alloys containing at least one of these. The surface of the conductive plate may be plated to improve its corrosion resistance. The plating material used in this case may be, for example, aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or alloys containing at least one of these.

[0051] Furthermore, if the thickness of the second substrate 30 is 1 mm to 5 mm, the thickness of the conductive plates 30a1 to 30a7 of the uppermost conductive layer 30a (thickness d in Figure 3) is preferably 50 μm to 2000 μm, considering that terminals are laser-welded to the conductive plates 30a1 to 30a4. This is to prevent the laser from passing through the conductive plates 30a1 to 30a4, damaging the insulating layer 30b, and causing dielectric breakdown. The thickness of the conductive plates 30a1 to 30a7 is formed to an appropriate thickness within the range of 50 μm to 2000 μm, depending on the laser welding conditions. The thickness of the conductive plates of conductive layers 30c and 30e other than the uppermost layer may be the same as that of conductive layer 30a, or it may be thinner.

[0052] Although not shown in the illustration, the first substrate 20 and the second substrate 30 may be provided with multiple holes at the same positions in a plan view, into which position-fixing pins are fitted, in order to fix their relative positions on the XY plane.

[0053] Next, we will describe case 11 of the semiconductor device 10 according to the first embodiment. Case 11 houses semiconductor chips 21a1-21a8, 21b1-21b8, a first substrate 20, and a second substrate 30. As shown in Figures 1 and 3, case 11 has openings 11a, 11b, 11d, and 11c on its top surface that expose at least a portion of the conductive plates 30a1-30a4 of the second substrate 30 shown in Figure 5 to the outside. For example, as mentioned above, the exposed portion 32 in Figure 5 of conductive plate 30a1 is exposed by opening 11a, and the exposed portion 36 in Figure 5 of conductive plate 30a2 is exposed by opening 11b.

[0054] As shown in Figure 1, the openings 11a to 11d are positioned at half the length of the rectangular case 11 in the short side direction (X direction), and are also arranged in the long side direction (Y direction) of the case 11.

[0055] In this way, openings 11a to 11d are provided on the top surface of the case 11, exposing at least a portion of the conductive plates 30a1 to 30a4 on the front surface of the second substrate 30 to the outside, allowing terminals to be connected to this exposed portion later. By determining the size (opening area) of the openings 11a to 11d according to the area of ​​the connection portion of the terminal used to the conductive plates 30a1 to 30a4, a sufficiently large exposed portion can be secured to ensure the positional accuracy of the terminal.

[0056] In the example shown in Figure 1, conductive plates 30a1 and 30a2 with different potentials are exposed to the outside by different openings 11a and 11b. The potential of conductive plate 30a1 is the gate potential, and the potential of conductive plate 30a2 is the source potential. Also, conductive plates 30a3 and 30a4 with different potentials are exposed to the outside by different openings 11c and 11d. The potential of conductive plate 30a3 is the gate potential, and the potential of conductive plate 30a4 is the source potential.

[0057] Thus, the conductive plate on the front surface of the second substrate 30 includes a first conductive plate (conductive plates 30a1 and 30a3 in the example of Figure 1) and a second conductive plate (conductive plates 30a2 and 30a4 in the example of Figure 1) having different potentials. At least a portion of the first conductive plate and at least a portion of the second conductive plate are exposed to the outside through different openings. This allows terminals with different potentials to be attached to the exposed portions of the first and second conductive plates later.

[0058] As shown in Figures 1 and 3, each of the openings 11a to 11d has a tapered shape, with the opening area narrowing from the top surface to the bottom surface of the case 11. This shape facilitates laser welding of terminals to the conductive plates 30a1 to 30a4.

[0059] In Figure 1, the openings 11a to 11d form a square shape in plan view, but this is not the only possible shape. For example, the openings 11a to 11d may be circular in plan view.

[0060] For the sealing resin used to manufacture case 11, an insulating resin such as a thermosetting resin can be used. Examples of thermosetting resins include epoxy resin, phenolic resin, maleimide resin, and polyester resin. Epoxy resin is preferred. Alternatively, an underfill material may be used as the sealing resin. The underfill material may, for example, have an epoxy resin as its main component, a curing temperature of approximately 180 degrees Celsius, and contain a filler material composed of inorganic materials. As the filler material, inorganic materials with high thermal conductivity, such as boron nitride, aluminum nitride, and silicon nitride, can be used.

[0061] Figure 6 shows an example of the circuit configuration of a semiconductor device. In Figure 6, the semiconductor chips 21a1 to 21a8 in the upper arm A are collectively referred to as semiconductor chip 21a, and the semiconductor chips 21b1 to 21b8 in the lower arm B are collectively referred to as semiconductor chip 21b. The switching element of semiconductor chip 21a consists of MOSFET 21-1 and the parasitic diode D1 of MOSFET 21-1. The switching element of semiconductor chip 21b consists of MOSFET 21-2 and the parasitic diode D2 of MOSFET 21-2.

[0062] The drain electrode of MOSFET21-1 is connected to the P terminal and the cathode of parasitic diode D1. The gate electrode of MOSFET21-1 is connected to the gate terminal G1. The source electrode of MOSFET21-1 is connected to the anode of parasitic diode D1, the auxiliary source terminal S1, the output terminal OUT, the drain electrode of MOSFET21-1, and the cathode of parasitic diode D2. The gate electrode of MOSFET21-2 is connected to the gate terminal G2. The source electrode of MOSFET21-2 is connected to the anode of parasitic diode D2, the auxiliary source terminal S2, and the N terminal.

[0063] Figure 7 is a cross-sectional view showing an example of terminal connections. As shown in Figure 7, terminal 40 (corresponding to gate terminal G1 in Figure 6) is connected to the exposed portion (exposed portion 32) of the conductive plate 30a1. Terminal 41 (corresponding to auxiliary source terminal S1 in Figure 6) is connected to the exposed portion (exposed portion 36) of the conductive plate 30a2.

[0064] It is preferable to connect the conductive plates 30a1 and 30a2 to the terminals 40 and 41 by laser welding. Soldering would require heating, and ultrasonic bonding could damage the semiconductor chip. Laser welding is also preferable because it can be performed relatively easily.

[0065] Figure 8 shows the relationship between the area of ​​the exposed portion of the conductive plate and the area of ​​the terminal connection portion. As shown in Figure 8, the area of ​​the portion of the conductive plate 30a1 exposed from the opening 11a (exposed portion 32) is larger than the area of ​​the connection portion (connection portion 40a) of the terminal 40 connected to the conductive plate 30a1. This provides a margin for positional accuracy of the terminal 40. It also facilitates laser welding. Although not shown in the figure, the same relationship applies to the area of ​​the exposed portion of the other conductive plates 30a2 to 30a4 and the area of ​​the connection portion of the terminals connected to the exposed portion.

[0066] Incidentally, there are semiconductor devices in which a printed circuit board is set in a frame with integrated control terminals such as press-fit pins, an insulated circuit board on which a semiconductor chip is mounted, and a printed circuit board positioned above it are electrically connected and sealed with sealing resin. In such semiconductor devices, during subsequent burn-in tests and other testing processes, the semiconductor device is heated, and the positional accuracy of the control terminals may become unstable. In this case, for example, misalignment may prevent the control terminals of the semiconductor device from being properly connected to the user's device. Therefore, it is difficult to manage the positional accuracy of the control terminals, which may require repeated modification of the frame mold.

[0067] In contrast, the semiconductor device 10 of this embodiment does not have terminals pre-installed on the case 11. The semiconductor device 10 exposes at least a portion of the conductive plates 30a1 to 30a4 on the front surface of the second substrate 30 to the outside through openings 11a to 11d in the case 11, allowing terminals to be connected to the exposed portion later. This makes it easier to manage the positional accuracy of the terminals. In other words, the strict positional accuracy requirements for the terminals are greatly relaxed.

[0068] Furthermore, the semiconductor chips 21a1-21a8 and 21b1-21b8 can be electrically connected to the second substrate 30 directly above them, and gate terminals can be provided on the exposed portions of the conductive plates 20a1-20a3 that are close to the top. This allows for a shorter gate wiring length compared to providing control terminals (gate terminals) on the frame, thereby reducing gate inductance and preventing malfunctions in the switching operation of the semiconductor chips 21a1-21a8 and 21b1-21b8 due to noise and other factors.

[0069] Figure 9 shows an example of a method for manufacturing a semiconductor device according to the first embodiment. [Step S1] A preparation step is performed to prepare the components of the semiconductor device 10. The components prepared here include, for example, a first substrate 20, a second substrate 30, semiconductor chips 21a1 to 21a8, 21b1 to 21b8, and external terminals 12a to 12d. Furthermore, the components include post electrodes (for example, post electrodes 23g1, 23g2, 23s1, 23s2 in Figure 2), conductive pin terminals 25a1 to 25a6, conductive members 25b1 to 25b3, etc. In the preparation step, other components applicable to the semiconductor device 10 (for example, a cooler) that are not listed here may also be prepared. In addition, manufacturing equipment used to manufacture the semiconductor device 10 may be prepared. Examples of manufacturing equipment include a soldering device, a molding device, and a laser welding device.

[0070] [Step S2] An assembly process is carried out to assemble the semiconductor device 10. The assembly process includes, for example, the following steps S2a to S2d. (Step S2a) Semiconductor chips 21a1-21a8 and 21b1-21b8 are mounted on the first substrate 20. The semiconductor chips 21a1-21a8 and 21b1-21b8 are placed on bonding materials (for example, bonding materials 22a1 and 22a2 shown in Figure 2) provided on conductive plates 20a1-20a3 on the front surface of the first substrate 20. Conductive pin terminals 25a1-25a6 and conductive members 25b1-25b3 are also placed on bonding materials provided on conductive plates 20a1-20a3. External terminals 12a-12d are placed on bonding materials provided on conductive plates 20a1-20a4.

[0071] Note that the arrangement of conductive pin terminals 25a1 to 25a6 may be carried out in a later step. In that case, a bonding material will be provided at the locations where the conductive pin terminals 25a1 to 25a6 are connected.

[0072] (Step S2b) Post electrodes (for example, post electrodes 23g1, 23g2, 23s1, 23s2 in Figure 2) are inserted into multiple holes in the second substrate 30 (for example, holes 31a, 31b in Figure 5, or multiple holes in regions 35a, 35b).

[0073] If the conductive pin terminals 25a1 to 25a6 are not placed in step S2a, then in step S2b, the conductive pin terminals 25a1 to 25a6 are inserted into the holes 37a to 37f of the second substrate 30.

[0074] The process in step S2b may be performed before or after step S2a. Alternatively, the process in step S2b may be performed in parallel with the process in step S2a.

[0075] (Step S2c) The second substrate 30 is placed on the first substrate 20. The second substrate 30, which has conductive plates 30a1 to 30a7 on its front surface, is placed with its back surface facing the front surface of the first substrate 20. At this time, one end of the post electrode inserted into the hole of the second substrate 30 is positioned to contact the bonding material (for example, bonding materials 22b1 and 22b2 in Figure 2) provided on the gate electrodes and source electrodes on the upper surface of the semiconductor chips 21a1 to 21a8 and 21b1 to 21b8. In addition, the conductive members 25b1 to 25b3 provided on the first substrate 20 are connected to the second substrate 30. If conductive pin terminals 25a1 to 25a6 are provided on the first substrate 20, the conductive pin terminals 25a1 to 25a6 are connected to the second substrate 30.

[0076] In step S2c, reflow is performed with the first substrate 20 and the second substrate 30 arranged as described above. This establishes electrical connections between the semiconductor chips 21a1-21a8, 21b1-21b8 and the conductive plates 30a1-30a7, etc.

[0077] (Step S2d) The sealing process is performed. In the sealing process, for example, a case 11 is formed which has openings 11a to 11d on its upper surface as shown in Figure 1, and which houses semiconductor chips 21a1 to 21a8, 21b1 to 21b8, a first substrate 20, and a second substrate 30.

[0078] In this process, the first substrate 20 with the second substrate 30 attached is set into the cavity of a mold in a predetermined molding apparatus. The mold is shaped to form openings 11a to 11c as shown in Figures 1 and 3. In the molding apparatus, the molten sealing material in the pod is pressurized by a plunger and fed from the pod to the runner, where it is injected into the cavity. The sealing material then hardens. This seals the semiconductor chips 21a1 to 21a8, 21b1 to 21b8, the first substrate 20, and the second substrate 30, forming a case 11 with openings 11a to 11c that expose at least a portion of the conductive plates 30a1 to 30a4 to the outside.

[0079] In addition, during the assembly process, the cooler may be bonded to the lower surface of the semiconductor device 10 via a bonding material.

[0080] (Step S3) Subsequently, the terminals (gate terminals or auxiliary source terminals) are laser-welded to the conductive plates 30a1 to 30a4 exposed through the openings 11a to 11c (see Figure 7). Laser welding may be performed by the user of the semiconductor device 10.

[0081] The semiconductor device 10 of the first embodiment can be manufactured using the manufacturing method described above. In the semiconductor device 10 described above, terminals with different potentials can be later attached to the exposed portions of both the first conductive plate (conductive plates 30a1, 30a3 in the example of Figure 1) and the second conductive plate (conductive plates 30a2, 30a4 in the example of Figure 1), but the device is not limited to this. If a terminal with one potential (for example, an auxiliary source terminal) is not used, an opening that exposes at least a portion of the second conductive plate does not need to be provided.

[0082] (Second Embodiment) Figure 10 is a top view of an example of a semiconductor device according to the second embodiment. Figure 11 is a cross-sectional view showing a part of the cross-section along line XI-XI in Figure 10. Figure 12 is a top view of an example of a second substrate in the semiconductor device according to the second embodiment. In Figures 10 to 12, the same reference numerals are used for elements that are the same as those shown in Figures 1, 3, and 5.

[0083] In the semiconductor device 50 of the second embodiment, the case 51 and the second substrate 60 are different from the case 11 and the second substrate 30 of the semiconductor device 10 of the first embodiment.

[0084] The conductive plates on the front surface of the second substrate 60 include a first conductive plate (conductive plates 30a1 and 30a3 in the example of Figure 12) and a second conductive plate (conductive plates 61a and 61b in the example of Figure 12), both having different potentials. At least a portion of the first conductive plate and at least a portion of the second conductive plate are exposed to the outside through common openings 51a and 51b of the case 51, as shown in Figure 10.

[0085] In the example shown in Figure 10, a portion of the conductive plates 30a1 and 61a is exposed through the opening 51a, and a portion of the conductive plates 30a3 and 61b is exposed through the opening 51b. Figure 12 shows the exposed portion 62 of conductive plate 30a1 and the exposed portion 63 of conductive plate 61a. When conductive plates 30a1 and 61a with different potentials are exposed through a common opening 51a, it is desirable to ensure a sufficient creepage distance between the conductive plates 30a1 and 61a from the viewpoint of preventing short circuits during laser welding of the terminals. For this reason, the distance between the exposed portions 62 and 63 (distance in the Y direction) is longer than the distance between the exposed portions 32 and 36 of the second substrate 30 shown in Figure 5.

[0086] In the semiconductor device 50 of the second embodiment described above, the same effects as those of the semiconductor device 10 of the first embodiment can be obtained. Furthermore, by exposing at least a portion of the first conductive plate and at least a portion of the second conductive plate to the outside through a common opening, the number of openings can be reduced compared to the case where the first conductive plate and the second conductive plate are exposed through different openings.

[0087] Furthermore, the semiconductor device 50 can be manufactured using the same process as shown in Figure 9.

[0088] Although embodiments have been illustrated above, the configurations of each part shown in the embodiments can be replaced with others having similar functions. Furthermore, other arbitrary components or processes may be added. Moreover, any two or more configurations (features) from the embodiments described above may be combined. [Explanation of Symbols]

[0089] 10, 50 Semiconductor Equipment 11, 51 cases 11a~11d, 51a, 51b opening 12a~12d External terminal 20 First board 20a1~20a4, 30a1~30a7, 61a, 61b conductive plate 20b Resin layer 20c metal plate 21a1~21a8, 21b1~21b8, 21a, 21b semiconductor chips 21-1, 21-2 MOSFET 21s main electrode 21g gate electrode 22a1, 22a2, 22b1, 22b2 Bonding material 23s1, 23s2, 23g1, 23g2 Post-electrode 25a1~25a6 Conductive pin terminals 25b1~25b3 Conductive material 30, 60 Second board 30a, 30c, 30e conductive layer 30b, 30d insulating layer 31a, 31b, 37a~37f holes 32, 36, 62, 63 Exposed part 33a~33d Slit 35a, 35b area Terminals 40 and 41 40a connection A Upper arm section B Lower arm section D1, D2 Parasitic Diodes G1, G2 gate terminals S1, S2 Auxiliary Source Terminals OUT output terminal p1~p4 Boss

Claims

1. A semiconductor chip having multiple main electrodes and gate electrodes, A first substrate on which the aforementioned semiconductor chip is mounted, A second substrate having a conductive plate on its front surface that is provided on the first substrate and electrically connected to the semiconductor chip, The upper surface has an opening that exposes at least a portion of the conductive plate to the outside, and the case houses the semiconductor chip, the first substrate, and the second substrate. A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, further comprising a terminal connected to the conductive plate exposed from the opening.

3. The semiconductor device according to claim 2, wherein the area of ​​the portion of the conductive plate exposed from the opening is larger than the area of ​​the connection portion of the terminal connected to the conductive plate.

4. The second substrate is a printed circuit board in which multiple insulating layers and conductive layers are laminated together. The conductive plate is included in the uppermost conductive layer of the printed circuit board. The semiconductor device according to claim 1.

5. The semiconductor device according to claim 1, wherein the thickness of the conductive plate is 50 μm or more and 2000 μm or less.

6. The semiconductor device according to claim 1, wherein the opening has a tapered shape, with the opening area narrowing from the top surface to the bottom surface of the case.

7. The conductive plate includes a first conductive plate and a second conductive plate, each having a different potential. The semiconductor device according to claim 1, wherein at least a portion of the first conductive plate and at least a portion of the second conductive plate are exposed to the outside through a common opening or through different openings.

8. The first conductive plate is electrically connected to the gate electrode, The second conductive plate is electrically connected to one of the plurality of main electrodes. The semiconductor device according to claim 7.

9. A process of mounting a semiconductor chip having multiple main electrodes and gate electrodes onto a first substrate, A step of placing a second substrate having a conductive plate on its front surface on the first substrate, and electrically connecting the semiconductor chip and the conductive plate, The process of forming a case having an opening on the upper surface that exposes at least a portion of the conductive plate to the outside, and which houses the semiconductor chip, the first substrate, and the second substrate, A method for manufacturing a semiconductor device having [a certain feature].

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of laser welding terminals to the conductive plate exposed through the opening.

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