Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a plurality of memory layers arranged in a first direction, via wiring extending in the first direction, a first wiring provided on one side of the plurality of memory layers in the first direction and extending in a second direction, and an insulating layer provided on the other side of the plurality of memory layers in the first direction and covering the ends of the via wiring. Each of the plurality of memory layers comprises a semiconductor layer connected to the via wiring, a gate electrode facing the semiconductor layer, a second wiring extending in a third direction and connected to the gate electrode, and a memory portion provided on the side opposite to the second wiring in the second direction relative to the semiconductor layer and connected to the semiconductor layer. The via wiring comprises a conductive member extending in the first direction and an internal region extending in the first direction, the outer surface of which is surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer or is continuous with the insulating layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] With the increasing integration of semiconductor memory devices, research on the three-dimensionalization of semiconductor memory devices has been underway.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device that operates suitably.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment comprises a plurality of memory layers arranged in a first direction, via wiring extending in the first direction, a first wiring provided on one side of the plurality of memory layers in the first direction and extending in a second direction intersecting the first direction, and an insulating layer provided on the other side of the plurality of memory layers in the first direction and covering the ends of the via wiring. Each of the plurality of memory layers comprises a semiconductor layer electrically connected to the via wiring, a gate electrode facing the semiconductor layer, a second wiring extending in a third direction intersecting the first and second directions and electrically connected to the gate electrode, and a memory portion provided on the side of the semiconductor layer in the second direction opposite to the second wiring and electrically connected to the semiconductor layer. The via wiring comprises a conductive member extending in the first direction and an internal region extending in the first direction, the outer surface of which is surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer or is continuous with the insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic circuit diagram showing the configuration of the semiconductor memory device. [Figure 3] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 4] This is a schematic perspective view showing a part of the configuration of the semiconductor memory device. [Figure 5] This is a schematic cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 6] This is a schematic cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 7] Figure 6 is a cross-sectional view taken along the line A1-A1' of the structure shown, viewed in the direction of the arrow. [Figure 8] This is a schematic cross-sectional view showing a portion of the structure of the transistor layer TL. [Figure 9] Figure 8 is a cross-sectional view taken along the line B1-B1' of the structure shown, viewed in the direction of the arrow. [Figure 10] This is a schematic cross-sectional view showing a portion of the configuration of bit line BL. [Figure 11] Figure 10 is a cross-sectional view taken along the line C1-C1' of the structure shown, viewed in the direction of the arrow. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 27] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 28]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 34] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 35] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 37] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 39] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 41] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 43] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 44] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 45] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 46] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 47] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 48] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 49] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 50] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 51] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 52] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 53] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 54] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 55] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 56] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 57] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 58] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 59] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to Modification 1 of the First Embodiment. [Figure 60] Figure 59 is a cross-sectional view taken along the line D1-D1' of the structure shown, viewed in the direction of the arrow. [Figure 61] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to a modified example 2 of the first embodiment. [Figure 62] This is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the second embodiment. [Figure 63] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 64] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 65] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. [Figure 66] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 67] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 68] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 69] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 70] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 71] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 72] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 73] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 74] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 75] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 76] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 77] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 78] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 79] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 80] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 81A] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to a modified example of the second embodiment. [Figure 81B] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. [Figure 82]This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 83] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 84] Figure 83 is a cross-sectional view taken along the line A3-A3' of the structure shown, viewed in the direction of the arrow. [Figure 85] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. [Figure 86] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 87] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 88] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 89] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 90] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 91] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 92] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 93] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 94] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 95] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 96] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 97] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 98] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 99] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 100]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 101] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 102] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 103] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 104] This is a schematic cross-sectional view illustrating the manufacturing method. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] In this specification, the direction intersecting the surface of the substrate may be referred to as the first direction. The direction along a predetermined plane intersecting the first direction may be referred to as the second direction, and the direction along this plane intersecting the second direction may be referred to as the third direction. The first direction may or may not coincide with the Z direction. The second and third directions may or may not correspond to either the X direction or the Y direction.

[0014] Furthermore, in this specification, when we refer to the "center position" of a certain configuration, it may mean, for example, the center of the circumscribed circle of the configuration, or it may mean the centroid of the configuration on the image.

[0015] [First Embodiment] [Memory die MD structure] Figure 1 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 1, the memory die MD is located on chip C M And, Chip C P It is equipped with chip C. M It features a memory cell array (MCA). Chip C PIt includes a peripheral circuit or the like connected to the memory cell array MCA.

[0016] Chip C M On one surface of it, a plurality of external pad electrodes P X are provided. Also, on the other surface of chip C M a plurality of first bonding electrodes P I1 are provided. Also, on one surface of chip C P a plurality of second bonding electrodes P I2 are provided. Hereinafter, for chip C M the surface on which the plurality of first bonding electrodes P I1 are provided is called the front surface, and the surface on which the plurality of external pad electrodes P X are provided is called the back surface. Also, for chip C P the surface on which the plurality of second bonding electrodes P I2 are provided is called the front surface, and the surface opposite to the front surface is called the back surface.

[0017] Chip C M and chip C P are arranged such that the front surface of chip C M faces the front surface of chip C P . The plurality of first bonding electrodes P I1 are provided corresponding to the plurality of second bonding electrodes P I2 respectively, and are arranged at positions where they can be bonded to the plurality of second bonding electrodes P I2 . The first bonding electrode P I1 and the second bonding electrode P I2 function as bonding electrodes for bonding chip C M and chip C P ] and making them electrically conductive.

[0018] In addition, in the example of FIG. 1, the corner portions a1, a2, a3, a4 of chip C M correspond to the corner portions b1, b2, b3, b4 of chip C P respectively.

[0019] [Circuit Configuration] Figure 2 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. The memory cell array MCA comprises a plurality of memory layers ML, a transistor layer TL, a plurality of bit lines BL connected to the plurality of memory layers ML and the transistor layer TL, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL via the plurality of transistor layers TL, and plate lines PL connected to the plurality of memory layers ML.

[0020] Each memory layer ML comprises multiple word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and multiple memory cells MC connected to these multiple word lines WL0 to WL2. Each memory cell MC comprises a transistor TrC and a capacitor CpC. One electrode of transistor TrC is connected to the bit line BL. The other electrode of transistor TrC is connected to the capacitor CpC. Note that one and the other electrode of transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to transistor TrC. The gate electrode of transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of capacitor CpC is connected to the other electrode of transistor TrC. The other electrode of capacitor CpC is connected to the plate line PL.

[0021] Furthermore, each bit line BL is connected to multiple memory cells MC corresponding to multiple memory layers ML.

[0022] Furthermore, the memory layer ML comprises multiple transistors TrLa and TrLb (hereinafter sometimes referred to as "transistor TrL"), each corresponding to one of the multiple word lines WL0 to WL2. One electrode of transistor TrL is connected to one of the word lines WL0 to WL2. The other electrode of transistor TrL is connected to the word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter sometimes referred to as "word line selection lines LW"). Note that one and the other electrode of transistor TrL function as either a source electrode or a drain electrode depending on the voltage supplied to transistor TrL. The gate electrodes of transistor TrL are connected to the layer selection lines LLa and LLb (hereinafter sometimes referred to as "layer selection lines LL").

[0023] Furthermore, the word line selection line LW is connected to multiple transistors TrL corresponding to multiple memory layers ML. Similarly, the layer selection line LLa is commonly connected to all transistors TrLa corresponding to multiple memory layers ML. Likewise, the layer selection line LLb is commonly connected to all transistors TrLb corresponding to multiple memory layers ML.

[0024] The transistor layer TL comprises multiple bit line selection lines LB0 to LB2 (hereinafter sometimes referred to as "bit line selection lines LB") and multiple transistors TrB connected to the multiple bit line selection lines LB0 to LB2. One electrode of transistor TrB is connected to the global bit line GBL via electrode Cn1. The other electrode of transistor TrB is connected to the bit line BL. Note that one and the other electrode of transistor TrB function as either a source electrode or a drain electrode depending on the voltage supplied to transistor TrB. The gate electrode of transistor TrB is connected to one of the bit line selection lines LB0 to LB2.

[0025] Multiple bit line selection lines LB0 to LB2 are, for example, the first bonding electrode P. I1 and second laminated electrode P I2 (Figure 1) via chip CP It is connected to a drive circuit or the like.

[0026] [Chip C P [Structure] Figure 3 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. Figure 3 shows chip C M and chip C P This shows part of the structure.

[0027] Chip C P Figure 3 shows that multiple transistors Tr, wiring, etc. are provided on a substrate Sub2, such as silicon (Si). These multiple transistors Tr, wiring, etc. constitute a control circuit, drive circuit, etc. for controlling the memory cell array MCA. For example, the control circuit includes a sense amplifier circuit. The sense amplifier circuit is connected to the second bonded electrode P I2 , first laminated electrode P I1 , via the global bit line GBL, chip C M It is electrically connected to the bit line BL provided therein. The sense amplifier circuit can read data stored in the selected memory cell MC by detecting voltage fluctuations or current changes in the bit line BL during read operation.

[0028] [Chip C M [Structure] Chip C M (Figure 3) shows region R MCA And, region R PC It includes the following: Region R MCA and region R PC Below it are a wiring layer M0 including the global bit line GBL and wiring m0, a wiring layer M1 including wiring m1, and the first bonding electrode P. I1 A region R is provided. MCA and region R PC An insulating layer 210 made of silicon nitride (SiN) or the like, and insulating layers 211, 212, and 213 made of silicon oxide (SiO2) or the like are provided on the upper part.

[0029] [Area R MCA [Structure] area RMCA The device includes a memory cell array MCA and a conductive layer MA10, etc., above the memory cell array MCA.

[0030] Figure 4 is a schematic perspective view showing a part of the configuration of the semiconductor memory device according to this embodiment. Figure 4 shows chip C M This shows a portion of the structure of the memory cell array (MCA) located at [location].

[0031] In the following description of the memory cell array (MCA), terms such as "up" and "down" are based on the global bit line (GBL). For example, the direction away from the global bit line (GBL) along the Z-direction is called "up," and the direction approaching the global bit line (GBL) along the Z-direction is called "down." Furthermore, when referring to the top surface or upper end of a configuration, it means the surface or end opposite to the global bit line (GBL) side of that configuration, and when referring to the bottom surface or lower end, it means the surface or end on the global bit line (GBL) side of that configuration. Also, surfaces that intersect with the X-direction or Y-direction are called sides, etc.

[0032] The memory cell array MCA comprises, for example, multiple memory layers ML stacked in the Z direction, a transistor layer TL provided between the memory layers ML and the global bit line GBL, and a conductive layer PM10 provided on the side opposite to the global bit line GBL relative to the multiple memory layers ML. The Z-direction lengths of the memory layers ML and the Z-direction lengths of the transistor layer TL are approximately the same.

[0033] An insulating layer 103 made of silicon oxide (SiO2) or the like is provided between each of the multiple memory layers ML. Furthermore, an insulating layer 203 made of silicon oxide (SiO2) or the like is provided between the bottommost memory layer ML and the transistor layer TL. The length of the insulating layer 203 in the Z direction is greater than the length of the insulating layer 103 in the Z direction.

[0034] [Structure of the memory layer (ML) and the transistor layer (TL)] Next, the structure of the memory layer ML and the transistor layer TL will be described with reference to Figures 3 and 4, as well as Figures 5 to 11.

[0035] Figure 5 is a schematic cross-sectional view showing a portion of the memory layer ML. Figure 6 is a schematic cross-sectional view showing a portion of the memory layer ML, enlarged from a portion of Figure 5. Figure 7 shows a cross-section of the structure shown in Figure 6, cut along the line A1-A1', and viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view showing a portion of the transistor layer TL. Figure 9 shows a cross-section of the structure shown in Figure 8, cut along the line B1-B1', and viewed in the direction of the arrow. Figure 10 is a schematic cross-sectional view showing a portion of the bit line BL. Figure 11 shows a cross-section of the structure shown in Figure 10, cut along the line C1-C1', and viewed in the direction of the arrow.

[0036] As shown in Figure 5, the memory layer ML is provided with a plurality of insulating layers 101 aligned in the X direction and a conductive layer 102 provided between two adjacent insulating layers 101 in the X direction. The insulating layers 101 and conductive layers 102 extend in the Y and Z directions, dividing the plurality of memory layers ML in the X direction.

[0037] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0038] The conductive layer 102 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). Alternatively, the conductive layer 102 may include, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe), or a laminated structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 102 functions, for example, as a plate wire PL (Figure 2).

[0039] Multiple via connections 104 (Figure 5) are provided in the region between the insulating layer 101 and the conductive layer 102. The multiple via connections 104 are aligned in the Y direction and extend in the Z direction, penetrating the transistor layer TL and multiple memory layers ML, as shown in Figure 4, for example.

[0040] As shown in Figures 7 and 9, the via wiring 104 comprises, for example, a conductive oxide film 104a extending in the Z direction and an internal region CAV, which will be described later. The via wiring 104 functions, for example, as a bit line BL (Figure 2). Multiple bit lines BL are provided, for example, as shown in Figures 3 to 5, corresponding to multiple transistors TrC included in the memory layer ML and transistors TrB included in the transistor layer TL.

[0041] The conductive oxide film 104a has a substantially cylindrical shape that is stretched in the Z direction. The conductive oxide film 104a functions, for example, as a conductive member of the via wiring 104. The conductive oxide film 104a contains, for example, indium tin oxide (ITO).

[0042] The memory layer ML and the transistor layer TL each comprise a plurality of transistor structures 110 corresponding to a plurality of via wirings 104, and a conductive layer 120 provided on the side opposite to the conductive layer 102 relative to the plurality of transistor structures 110. The memory layer ML also comprises a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102. The transistor layer TL (Figure 9) also comprises an electrode structure 130c provided between the plurality of transistor structures 110 and a plurality of contact GBLC1.

[0043] The transistor structure 110 includes, for example, as shown in Figures 6 to 9, a semiconductor layer 111 connected to the outer surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the insulating layer 112.

[0044] In the XY cross-sections illustrated in Figures 6 and 8, the side surface of the semiconductor layer 111 on one side in the X direction (the conductive layer 120 side) may be formed along a circle centered on the center position of the via wiring 104. The other side surface of the semiconductor layer 111, insulating layer 112, and conductive layer 113 on the other side in the X direction (the conductive layer 102 side) may be formed linearly along the side surface of the conductive layer 102. Furthermore, both sides of the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the Y direction may be formed linearly along the side surface of the insulating layer 115.

[0045] The semiconductor layer 111 functions, for example, as the channel region of transistors TrC and TrB (Figure 2). The semiconductor layer 111 may be a semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be another oxide semiconductor. Multiple semiconductor layers 111 aligned in the Z direction are commonly connected to via wiring 104 extending in the Z direction.

[0046] The insulating layer 112 functions, for example, as a gate insulating film of transistors TrC and TrB (Figure 2). The insulating layer 112 includes, for example, silicon oxide (SiO2).

[0047] The conductive layer 113 functions, for example, as the gate electrode of transistors TrC and TrB (Figure 2). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 extending in the Y direction (see Figures 4 and 5). The conductive layer 113 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112. In this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0048] An insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two adjacent semiconductor layers 111 in the Y direction. The insulating layer 115 extends in the Z direction, penetrating the transistor layer TL and multiple memory layers ML.

[0049] The conductive layer 120 functions, for example, as a word line WL in the memory layer ML and as a bit line selection line LB in the transistor layer TL (Figure 2). The conductive layer 120 extends in the Y direction and is connected to a plurality of conductive layers 113 aligned in the Y direction. As shown, for example, in Figures 6 and 8, the conductive layer 120 is connected to the conductive layer 113 on one side in the X direction and in contact with the insulating layer 101 on the other side. The conductive layer 120 comprises, for example, a barrier conductive film 121 made of titanium nitride (TiN) and a conductive film 122 made of tungsten (W). The barrier conductive film 121 is provided on the upper surface, lower surface, and one side in the X direction (transistor structure 110 side) of the conductive film 122.

[0050] The capacitor structure 130 includes, for example, a conductive layer 131, an insulating layer 132 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110) of the conductive layer 131, and a conductive layer 133 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110) of the insulating layer 132.

[0051] The conductive layer 131 functions as one electrode of the capacitor CpC (Figure 2). The conductive layer 131 includes, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe). Alternatively, the conductive layer 131 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), or a laminated structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). One side of the conductive layer 131 in the X direction is in contact with the conductive layer 102.

[0052] The insulating layer 132 functions as an insulating layer for the capacitor CpC (Figure 2). The insulating layer 132 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxides. Alternatively, the insulating layer 132 may be, for example, a multilayer film of multiple insulating metal oxides (e.g., a multilayer film of zirconia and alumina).

[0053] The conductive layer 133 functions, for example, as the other electrode of a capacitor CpC (Figure 2). The conductive layer 133 contains, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to the X-direction side of the semiconductor layer 111. The conductive layer 133 is insulated from the conductive layer 102 via the insulating layer 132.

[0054] The electrode structure 130c comprises, for example, a conductive layer 131c, an insulating layer 132c provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (transistor structure 110 side) of the conductive layer 131c, and a conductive layer 133c provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (transistor structure 110 side) of the insulating layer 132c.

[0055] The conductive layer 131c contains the same material as the conductive layer 131. One side of the conductive layer 131c in the X direction (the side with the conductive layer 102) is in contact with the insulating layer 106, such as silicon oxide (SiO2).

[0056] The insulating layer 132c contains the same material as the insulating layer 132. One side of the insulating layer 132c in the X direction (the side facing the conductive layer 102) is in contact with the insulating layer 106.

[0057] The conductive layer 133c functions, for example, as a conductive component of electrode Cn1 (Figure 2). The conductive layer 133c contains the same material as the conductive layer 133. One side of the conductive layer 133c in the X direction (towards the transistor structure 110) is connected to the side of the semiconductor layer 111 in the X direction. The other side of the conductive layer 133c in the X direction (towards the insulating layer 106) is in contact with the insulating layer 106.

[0058] A contact GBLC1 is provided below the electrode structure 130c (Figures 3, 4, and 9). The contact GBLC1 comprises a conductive film 206 such as indium tin oxide (ITO) and an insulating film 207 such as silicon oxide (SiO2), as shown in Figure 9, for example. The upper surface of the contact GBLC1 is connected to the lower surface of the conductive layer 133c included in the electrode structure 130c. The lower surface of the contact GBLC1 is connected to the global bit line GBL (Figure 3). The contact GBLC1 functions as an electrode that connects, for example, transistor TrB to the global bit line GBL via electrode Cn1.

[0059] The global bit line GBL extends in the X direction, as shown in Figure 3, for example, and multiple GBLs are arranged in the Y direction. The global bit line GBLs may be arranged in the Y direction at a pitch equivalent to the pitch of the transistor structure 110 arranged in the Y direction (Figure 5). The global bit line GBL comprises, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive film of tungsten (W).

[0060] The conductive layer PM10 (Figure 3) includes a portion PM10a (Figure 3) that connects to the plate wire PL (conductive layer 102). The conductive layer PM10 functions, for example, as wiring connecting multiple plate wires PL (Figure 5) aligned in the X direction. The conductive layer PM10 (Figure 3) includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

[0061] Furthermore, the conductive layer PM10 (Figure 3) includes a portion PM10b (Figure 3) at a position that overlaps with the via wiring 104 when viewed from the Z direction. The conductive layer PM10 functions, for example, in the manufacturing process described later, as a layer that prevents hydrogen (H) from diffusing into multiple memory layers ML and transistor layers TL.

[0062] The conductive layer MA10 is provided above the conductive layer PM10 via insulating layers 212 and 213. The conductive layer MA10 includes, for example, a laminated structure of titanium nitride (TiN) and aluminum (Al).

[0063] [Area R PC [Structure] area R PC The device includes a contact CC, a conductive layer PM20 connected to the upper end of the contact CC, and a conductive layer MA20 connected to the upper surface of the conductive layer PM20.

[0064] The contact CC (Figure 3) extends in the Z direction. Below, the contact CC is connected to the wiring m0 included in the wiring layer M0, and the first bonding electrode P is connected via wiring m0, m1, etc. I1 It is electrically connected to the contact CC, which includes, for example, a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0065] The conductive layer PM20 includes a portion PM20a (Figure 3) that connects to the contact CC. The conductive layer PM20 functions, for example, as wiring connecting the contact CC to the conductive layer MA20. The conductive layer PM20 (Figure 3) contains, for example, the same material as the conductive layer PM10.

[0066] The portion of conductive layer MA20 that connects to conductive layer PM20 is, for example, the external pad electrode P X It functions as shown in Figure 1. The conductive layer MA20 (Figure 3) contains, for example, the same material as the conductive layer MA10.

[0067] [Details of Internal Region CAV] Next, the details of the internal region CAV will be described with reference to Figures 10 and 11. Figures 10 and 11 are schematic cross-sectional views showing the configuration of the end of the bit line BL. Figure 11 shows a cross-section of the structure shown in Figure 10, cut along the line C1-C1' and viewed in the direction of the arrow. Hereinafter, the end of the internal region CAV opposite the global bit line GBL in the Z direction relative to the memory layer ML may be referred to as the upper end PT10 of the internal region CAV.

[0068] The internal region CAV has a substantially cylindrical shape extending in the Z direction, as shown in Figures 10 and 11, for example. The outer surface of the internal region CAV is surrounded by, for example, a conductive oxide film 104a.

[0069] The upper end portion PT10 of the internal region CAV (Figures 10 and 11) is not covered by the conductive oxide film 104a. The upper end portion PT10 of the internal region CAV is covered by, for example, an insulating layer 211.

[0070] The upper end portion PT10 of the internal region CAV may be in contact with the insulating layer 211, as shown in Figure 10.

[0071] Furthermore, a portion of the insulating layer 211 may be formed so as to extend into the interior of the cylindrical conductive oxide film 104a. In such a case, the upper end of the internal region CAV is continuous with the insulating layer 211.

[0072] The internal region CAV may be, for example, a cavity. A cavity refers to a space surrounded by solid material, and the cavity itself does not contain any solid material. The cavity may contain, for example, air, which is a mixture of multiple gases such as nitrogen, oxygen, and noble gases. The cavity may be degassed to contain no gases.

[0073] The internal CAV region may include an insulating layer such as silicon oxide (SiO2) or silicon nitride (SiN).

[0074] The internal region CAV may extend in the Z direction from the transistor layer TL located closest to the global bit line GBL to the memory layer ML located furthest from the global bit line GBL, as shown in Figure 3, for example. Alternatively, the internal region CAV may extend in the Z direction from the memory layer ML located closest to the global bit line GBL to the memory layer ML located furthest from the global bit line GBL.

[0075] [Manufacturing method] Figures 12 to 58 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0076] Figures 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, and 40 show the XY cross-sections corresponding to Figure 6.

[0077] Figures 42, 44, 46, and 48 show the XY cross-sections corresponding to Figure 8.

[0078] Figures 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, and 49 show the XZ cross-section corresponding to a portion of the memory layer ML and the transistor layer TL.

[0079] Figures 50-53 and 55-58 show cross-sections corresponding to Figure 3. Figure 54 shows an enlarged cross-section of the end of the bit line.

[0080] Furthermore, chip C M In Figures 12 to 49, which illustrate the manufacturing process, the upward direction is represented as the positive Z-direction, and the downward direction is represented as the negative Z-direction. For example, in Figures 12 to 49, chip C M The front surface is referred to as the upper side (positive Z direction), and the back surface as the lower side (negative Z direction). In Figures 50 to 58, the chip C M The front and back surfaces are reversed, and chip C M The front surface is referred to as the bottom side (negative Z direction), and the back surface as the top side (positive Z direction). In Figures 12 to 49, the positive and negative directions of the Z direction are different from the configuration described with reference to Figures 3 to 11. In Figures 50 to 58, the positive and negative directions of the Z direction are the same as the configuration described with reference to Figures 3 to 11.

[0081] In this manufacturing method, an insulating layer 221 made of silicon oxide (SiO2) or the like and a semiconductor layer 220 are formed on a substrate Sub (see Figure 50). The substrate Sub may be a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B), or it may be a substrate containing other impurities or materials. The semiconductor layer 220 may be, for example, polysilicon (p-Si).

[0082] Next, as shown in Figures 12 and 13, for example, multiple insulating layers 103 and 203, and multiple sacrificial layers MLA are alternately formed above the semiconductor layer 220. The sacrificial layers MLA include, for example, silicon nitride (SiN). This process is carried out by, for example, CVD (Chemical Vapor Deposition).

[0083] Next, an insulating layer 115 is formed, for example, as shown in Figure 12. In this step, an opening is formed at a position corresponding to the insulating layer 115. This opening extends in the Z direction, penetrating multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction, exposing the semiconductor layer 220. This step is performed, for example, by RIE (Reactive Ion Etching). After the opening is formed, an insulating layer 115 is formed within the opening. This step is performed, for example, by CVD.

[0084] Next, as shown in Figures 14 and 15, for example, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction, as shown in Figures 14 and 15, penetrating multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction, and exposing the semiconductor layer 220. This process is carried out, for example, by RIE.

[0085] Next, an opening 111A is formed, for example, as shown in Figures 16 and 17. The opening 111A exposes a portion of the upper and lower surfaces of the insulating layers 103 and 203, as well as a portion of the X-direction side surface of the sacrificial layer MLA. In this step, a portion of the sacrificial layer MLA is selectively removed through, for example, the opening 104A. This step is performed, for example, by wet etching.

[0086] Next, as shown in Figures 18 and 19, for example, a conductive layer 113' is formed inside the opening 111A, and a sacrificial layer 104Sc' is formed inside the openings 104A and 111A. In this step, for example, a conductive film such as titanium nitride (TiN) is formed inside the openings 104A and 111A. Next, inside the opening 104A, a portion of the conductive film (the portion formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive film is divided in the Z direction to form a conductive layer 113'. Next, silicon (Si) or the like is embedded in the openings 104A and 111A to form a sacrificial layer 104Sc'. This step is performed by, for example, CVD and RIE.

[0087] Next, as shown in Figures 20 and 21, for example, openings 101A and 120A are formed at positions corresponding to the insulating layer 101 and the conductive layer 120. The opening 120A exposes a portion of the upper and lower surfaces of the insulating layers 103 and 203, as well as the X-direction side surface of the conductive layer 113'. In this step, for example, after forming opening 101A, a portion of the sacrificial layer MLA is selectively removed through opening 101A. This step is performed, for example, by RIE and wet etching.

[0088] Next, as shown in Figures 22 and 23, for example, a conductive layer 120 and an insulating layer 101 are formed inside the openings 120A and 101A. In this step, for example, a conductive film containing the same material as the conductive layer 120 is formed inside the openings 120A and 101A. Next, inside the opening 101A, a portion of the conductive film (the portion formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive film is divided in the Z direction to form the conductive layer 120. Next, the insulating layer 101 is embedded in the opening 101A. This step is performed by methods such as CVD and RIE.

[0089] Next, as shown in Figures 24 and 25, for example, an opening 102A is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A extends in the Z direction, penetrating the multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction, and exposing the semiconductor layer 220. This process is carried out, for example, by RIE.

[0090] Furthermore, as shown in Figures 24 and 25, for example, an opening 130A is formed. Parts of the upper and lower surfaces of the insulating layers 103 and 203, as well as a part of the X-direction side surface of the conductive layer 113', are exposed in the opening 130A. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A. This step is performed, for example, by wet etching.

[0091] Next, as shown in Figures 26 and 27, for example, a portion of the upper and lower surfaces of the insulating layers 103 and 203, as well as a portion of the X-direction side surface of the conductive layer 113', which are exposed in the opening 130A, are removed. This process increases the width of the opening 130A in the Z-direction. This process is carried out, for example, by wet etching.

[0092] Furthermore, as shown in Figures 26 and 27, for example, the sacrificial layer 104Sc' is removed to form openings 104A and 111A. This process connects openings 102A, 104A, 111A, and 130A. This process is carried out, for example, by wet etching.

[0093] Next, as shown in Figures 28 and 29, for example, an insulating layer 112 is formed inside the openings 102A, 104A, 111A, and 130A. This process is carried out, for example, by CVD.

[0094] Next, as shown in Figures 30 and 31, for example, a sacrificial layer 111Sc' of silicon nitride (SiN) or titanium nitride (TiN) is formed inside openings 102A, 104A, 111A, and 130A via openings 102A and 104A. In this step, opening 111A is filled by the sacrificial layer 111Sc', while openings 102A, 104A, and 130A are not filled by the sacrificial layer 111Sc'. This step is performed, for example, by CVD.

[0095] Next, as shown in Figures 32 and 33, for example, a portion of the sacrificial layer 111Sc' is removed through openings 102A and 104A, and the sacrificial layer 111Sc' is divided in the Z direction to form a sacrificial layer 111Sc of silicon nitride (SiN) or titanium nitride (TiN). This process is carried out, for example, by wet etching.

[0096] Next, as shown in Figures 34 and 35, for example, silicon (Si) or the like is embedded in the opening 104A to form a sacrificial layer 104Sc. In this step, for example, silicon (Si) or the like is embedded in the openings 102A and 104A, and then the silicon (Si) or the like embedded in the opening 102A is removed. This step is performed by, for example, CVD, wet etching, etc.

[0097] Next, as shown in Figures 36 and 37, for example, conductive layers 133 and 133c are formed inside the opening 130A. In this step, for example, a conductive oxide layer, such as indium tin oxide (ITO), is formed inside the openings 102A and 130A. Next, inside the opening 102A, a portion of the conductive oxide layer (the portion formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive oxide layer is divided in the Z direction to form conductive layers 133 and 133c. This step is performed by, for example, CVD and RIE.

[0098] Next, as shown in Figures 38 and 39, for example, an insulating layer 132' containing the same material as the insulating layer 132 is formed inside the openings 102A and 130A, and on the upper surface of the structure shown in Figure 37. This process is carried out, for example, by CVD.

[0099] Next, as shown in Figures 40 and 41, for example, a conductive layer 131' containing the same material as conductive layer 131 is formed inside openings 102A and 130A, and then a conductive layer 102' containing the same material as conductive layer 102 is formed inside opening 102A. In this step, opening 130A is filled by conductive layer 131', while opening 102A is not filled by conductive layer 131'. This step is performed, for example, by CVD.

[0100] Next, as shown in Figures 42 and 43, for example, a portion of the conductive layer 102', conductive layer 131', and insulating layer 132' is removed to form conductive layers 131, 131c, insulating layers 132, 132c, conductive layer 102, and opening 205A. This process is carried out, for example, by RIE.

[0101] Next, an insulating layer 106 is formed inside the opening 205A and on the upper surface of the structure shown in Figure 43, for example, as shown in Figures 44 and 45. Then, the portion of the insulating layer 106 located above the sacrificial layer 104Sc is removed to form an opening 106A, and the sacrificial layers 104Sc and 111Sc are removed through the opening 106A to form openings 104A and 111A. This process is carried out by methods such as CVD, RIE, or wet etching.

[0102] Next, as shown in Figures 46 and 47, for example, a semiconductor layer 111 is formed inside the openings 104A and 111A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. This process is carried out, for example, by ALD (Atomic Layer Deposition).

[0103] Furthermore, as shown in Figures 46 and 47, for example, a conductive oxide film 104a' containing the same material as the conductive oxide film 104a is formed inside the opening 104A. In this step, the opening 104A is not filled by the conductive oxide film 104a'. This step is performed, for example, by a method such as CVD.

[0104] Next, as shown in Figures 48 and 49, for example, an insulating layer 107 made of silicon oxide (SiO2) or the like is formed on the upper surface of the structure shown in Figure 47, and an internal region CAV' is formed inside the via wiring 104. In addition, the portion corresponding to the contact GBLC1 is removed from the insulating layer 106, insulating layer 107, etc. to form an opening, and a conductive film 206 and insulating film 207 are formed inside the opening. This process is carried out by, for example, RIE or CVD.

[0105] Next, on the upper surface of the structure shown in Figure 49, there is a global bit line GBL, a wiring layer M0 including multiple wirings m0, a wiring layer M1 including multiple wirings m1, and multiple first bonding electrodes P. I1 It forms.

[0106] Next, as shown in Figures 50 and 51, a chip C in which the memory cell array MCA has been formed in the above process is shown. M The wafer containing the chip C is inverted so that the substrate Sub is at the top and the global bit line GBL is at the bottom. M The surface of the wafer containing and chip C P The surface of the wafer containing the first bonding electrode P is placed facing the wafer (Figure 50), I1 and second laminated electrode P I2 The electrodes are bonded via a barrier (Figure 51). Note that hydrogen (H) and other gases may be generated during the formation process (Figure 49) and bonding process (Figures 50 and 51) of these bonded electrodes.

[0107] Next, as shown in Figure 51, the substrate Sub and the insulating layer 221 are removed. This process is carried out, for example, by grinding, CMP (Chemical Mechanical Polishing), wet etching, etc.

[0108] Next, as shown in Figure 52, the semiconductor layer 220 is removed, and an insulating layer 210' containing the same material as the insulating layer 210 is formed on the upper surface of the structure. This process is carried out, for example, by CVD.

[0109] Next, as shown in Figure 53, a portion of the insulating layer 210' above the bit line BL and the upper end of the bit line BL are removed, opening up the upper part of the internal region CAV'. This process is carried out, for example, by RIE.

[0110] Next, as shown in Figures 53 and 54, annealing is performed in an oxygen (O2) atmosphere. In this process, a relatively large amount of oxygen (O2) diffuses into the internal region CAV' through the opening at the top of the internal region CAV'. As a result, oxygen (O2) diffuses into the multiple semiconductor layers 111 aligned in the Z direction via the conductive oxide film 104a containing the oxide material, and excess oxygen vacancies present in the multiple semiconductor layers 111 are repaired. In this process, as shown in Figure 53, the plate wire PL and contact CC are covered by the insulating layer 210', so their oxidation does not proceed.

[0111] Next, as shown in Figure 55, an insulating layer 211' containing the same material as the insulating layer 211 is formed. This step is carried out, for example, by CVD.

[0112] Next, as shown in Figure 56, a portion of the insulating layer 211' and insulating layer 210' is removed to form insulating layer 210, insulating layer 211, opening PM10aA, and opening PM20aA. The upper end of the plate wire PL is exposed in opening PM10aA. The upper end of the contact CC is exposed in opening PM20aA. This process is carried out, for example, by RIE.

[0113] Next, as shown in Figure 57, the same materials as the conductive layers PM10 and PM20, and the same material as the insulating layer 212 are formed on the upper surface of the structure shown in Figure 56. Patterning is then performed using photolithography or the like to form the conductive layers PM10 and PM20 and the insulating layer 212. This process is carried out by, for example, CVD, wet etching, or the like.

[0114] Next, as shown in Figure 58, a material similar to the insulating layer 213 is formed on the upper surface of the structure shown in Figure 57, and the external pad electrode P X Remove the corresponding portion, leaving the insulating layer 213 and the opening P. X Forms A. Opening P X In area A, a portion of the upper surface of the conductive layer PM20 is exposed. This process is carried out by, for example, CVD, RIE, etc.

[0115] Next, the same material as conductive layers MA10 and MA20 is formed on the upper surface of the structure shown in Figure 58, and patterning is performed by photolithography or the like to form conductive layers MA10 and MA20. This process is carried out by, for example, CVD, wet etching, or the like.

[0116] This results in the structure described with reference to Figures 1 to 11.

[0117] [effect] In transistors using oxide semiconductors as channels, the oxygen vacancies in the oxide semiconductor (semiconductor layer 111) may increase due to hydrogen (H) and other elements generated during the manufacturing process after transistor formation, which can degrade the characteristics of the transistor.

[0118] In the semiconductor memory device according to this embodiment, after the formation of transistors TrC and TrB, the amount of oxygen vacancies in the oxide semiconductor (semiconductor layer 111) containing transistors TrC and TrB may increase due to hydrogen (H) generated during processes such as the formation of bonded electrodes (Figure 49) and the bonding process (Figures 50 and 51).

[0119] However, the semiconductor memory device according to this embodiment includes an internal cavity (CAV). As shown in Figures 53 and 54, after the bonding process, it becomes possible to perform oxygen annealing, which uniformly supplies oxygen to all of the stacked semiconductor layers 111 over a distance of several μm, from the upper end position (oxygen introduction section) of the via wiring 104 (bit line BL) to the lower position, for example, through the internal cavity (CAV). As a result, the semiconductor memory device according to this embodiment can achieve good and uniform characteristics for the stacked transistors TrC and TrB.

[0120] Furthermore, the semiconductor memory device according to this embodiment includes a conductive layer PM10 that covers the upper end of the via wiring 104 (bit line BL) (Figure 3). The conductive layer PM10 prevents the diffusion of hydrogen (H) and other elements from above the conductive layer PM10 to the transistors TrC and TrB after its formation (Figure 57 onwards). Therefore, degradation of the characteristics of transistors TrC and TrB can be suppressed.

[0121] [Modification 1 of the First Embodiment] Next, a modified example 1 of the semiconductor memory device according to the first embodiment will be described with reference to Figures 59 and 60. Figures 59 and 60 are schematic cross-sectional views showing a part of the configuration of the semiconductor memory device according to this modified example. Figure 60 shows a cross-section of the structure shown in Figure 59, cut along the line D1-D1', and viewed along the direction of the arrow.

[0122] The semiconductor memory device according to this modified example (Figures 59 and 60) is basically configured the same as the semiconductor memory device according to the first embodiment (Figures 6 and 7). However, the semiconductor memory device according to this modified example does not have via wiring 104, but instead has via wiring 104_2.

[0123] Via wiring 104_2 is basically constructed in the same way as via wiring 104 (Figures 6 and 7). However, via wiring 104_2 includes, for example, a conductive layer 104b between the conductive oxide film 104a and the internal region CAV.

[0124] The conductive layer 104b has a substantially cylindrical shape, for example, stretched in the Z direction. The outer surface of the conductive layer 104b is in contact with the inner surface of the conductive oxide film 104a. The conductive layer 104b contains a conductive oxide with lower resistance than the conductive oxide film 104a, such as ruthenium oxide (RuO2).

[0125] This structure further reduces the resistance of the bit line BL, making it possible to provide a faster semiconductor memory device.

[0126] [Modification 2 of the First Embodiment] Next, a modified example 2 of the semiconductor memory device according to the first embodiment will be described with reference to Figure 61. Figure 61 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this modified example.

[0127] The semiconductor memory device according to this modified example (Figure 61) is basically configured in the same way as the semiconductor memory device according to the first embodiment (Figure 7). However, the semiconductor memory device according to this modified example (Figure 61) does not have a semiconductor layer 111, and instead has a semiconductor layer 111_2.

[0128] The semiconductor layer 111_2 is basically constructed in the same way as the semiconductor layer 111 (Figure 7). However, the semiconductor layer 111_2 is formed by dividing it in the Z direction for each memory layer ML.

[0129] [Second Embodiment] Figure 62 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the second embodiment. Figures 63 and 64 are schematic cross-sectional views showing a part of the configuration of the semiconductor memory device according to this embodiment. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0130] The semiconductor memory device according to the second embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a plurality of transistor layers TL (Figures 62 to 64). In addition, the semiconductor memory device according to the second embodiment includes a contact GBLC2 and a plug 150 (Figure 64) instead of a contact GBLC1 (Figure 9), and an electrode structure 130c2 (Figure 64) instead of an electrode structure 130c (Figure 9) to realize the electrode Cn1.

[0131] For example, as shown in Figure 62, among the multiple transistors TrB, one electrode is connected to the same bit line BL, while the other electrode is connected to the same global bit line GBL via electrode Cn1. These multiple transistors TrB are connected in parallel between the bit line BL and the global bit line GBL.

[0132] The contact GBLC2 (Figure 64) extends in the Z direction. The upper part of the contact GBLC2 is connected to a plurality of electrode structures 130c2 aligned in the Z direction. The contact GBLC2 is connected to the plug 150 on its lower surface. The contact GBLC2 functions, for example, as an electrode connecting a plurality of transistors TrB to a global bit line GBL via electrode Cn1.

[0133] The electrode structure 130c2 and the contact GBLC2 include an integrally formed conductive layer 131d, an insulating layer 132d, and a conductive layer 133d.

[0134] The conductive layer 131d is integrally provided inside the electrode structure 130c2 and inside the contact GBLC2. The conductive layer 131d contains the same material as the conductive layer 131c.

[0135] The insulating layer 132d is integrally provided inside the electrode structure 130c2 and inside the contact GBLC2. The insulating layer 132d covers the outer surface of the conductive layer 131d. The insulating layer 132d contains the same material as the insulating layer 132c.

[0136] The conductive layer 133d is integrally provided inside the electrode structure 130c2 and inside the contact GBLC2. The conductive layer 133d covers the outer surface of the insulating layer 132d. In the electrode structure 130c2 of each transistor layer TL, the conductive layer 133d is connected to the X-direction side of the semiconductor layer 111 of each transistor layer TL. The conductive layer 133d is connected to the plug 150 on the lower surface portion of the contact GBLC2. The conductive layer 133d contains the same material as the conductive layer 133c.

[0137] The plug 150 extends in the Z direction, penetrating an insulating layer 141, such as silicon nitride (SiN), and an insulating layer 143, such as silicon oxide (SiO2), and is connected to the global bit line GBL on its lower surface. The plug 150 may also include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

[0138] [Manufacturing method] Figures 65 to 80 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0139] Figures 65, 67, 69, 71, and 73 show the XY cross-sections corresponding to the memory layer ML and the transistor layer TL.

[0140] Figures 66, 68, 70, 72, and 74-80 show XZ cross-sections corresponding to parts of the memory layer ML and the transistor layer TL.

[0141] Furthermore, chip C M In Figures 65 to 80, which illustrate the manufacturing process, the upward direction is represented as the positive Z-direction, and the downward direction is represented as the negative Z-direction. For example, in Figures 65 to 80, chip C M The front surface is referred to as the upper side (positive Z direction), and the back surface as the lower side (negative Z direction). In the process described with reference to Figure 50 and beyond, the chip C M The front and back surfaces are reversed, and chip C M The front surface is referred to as the bottom side (negative Z direction), and the back surface as the top side (positive Z direction). In Figures 65 to 80, the positive and negative directions of the Z direction are different from the configuration described with reference to Figures 63 and 64.

[0142] In this manufacturing method, the same steps as those shown in Figures 12 to 21 are performed. However, unlike in Figures 12 to 21, multiple sacrificial layers MLA are formed above the insulating layer 203.

[0143] Next, a conductive layer 120 is formed inside the opening 120A, for example, as shown in Figures 65 and 66. This step is carried out in the same manner as the steps shown in Figures 22 and 23. In addition, an insulating layer 101_2, such as silicon oxide (SiO2), is formed inside the opening 101A and on the upper surface of the structure shown in Figure 21. This step is carried out by a method such as CVD.

[0144] Next, as shown in Figures 67 and 68, for example, an opening 102A_2 is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A_2 extends in the Z direction and penetrates the insulating layer 101_2, multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction. This process is carried out, for example, by RIE.

[0145] Next, as shown in Figures 67 and 68, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A_2, similar to the process shown in Figures 24 and 25, to form the opening 130A. This process is carried out, for example, by wet etching.

[0146] Next, as shown in Figures 69 and 70, for example, a portion of the upper and lower surfaces of the insulating layers 103 and 203, as well as a portion of the X-direction side surface of the conductive layer 113', which are exposed in the opening 130A, are removed. This process increases the width of the opening 130A in the Z direction. This process is carried out, for example, by wet etching. Furthermore, the sacrificial layer 104Sc' is removed through the openings 102A_2 and 130A to form the openings 104A and 111A. This process connects the openings 102A_2, 104A, 111A, and 130A. This process is carried out, for example, by wet etching.

[0147] Next, as shown in Figures 71 and 72, for example, an insulating layer 112 is formed inside the openings 102A_2, 104A, 111A, and 130A through the opening 102A_2. This process is carried out, for example, by CVD.

[0148] Next, as shown in Figures 73 and 74, for example, a sacrificial layer of silicon nitride (SiN) or titanium nitride (TiN) is formed inside openings 102A_2, 104A, 111A, and 130A through opening 102A_2. A portion of the sacrificial layer formed in openings 102A_2 and 130A is then removed through opening 102A_2 to form sacrificial layer 111Sc2. In this process, opening 111A is filled by sacrificial layer 111Sc2, while openings 102A_2, 104A, and 130A are not filled by sacrificial layer 111Sc2. This process is carried out, for example, by CVD.

[0149] Next, as shown in Figure 75, for example, an opening GBLC2A is formed at a position corresponding to the contact GBLC2. The opening GBLC2A extends in the Z direction and penetrates the insulating layer 101_2 and the multiple insulating layers 103 above the insulating layer 203. This process connects the opening GBLC2A and the opening 130A above the insulating layer 203. This process is carried out, for example, by RIE.

[0150] Next, as shown in Figure 76, for example, a sacrificial layer 102_2Sc' of silicon (Si) or the like is formed inside the openings 102A_2, GBLC2A, and 130A. This process is carried out, for example, by CVD.

[0151] Next, as shown in Figure 77, for example, a film of the same material as insulating layer 141 and insulating layer 142 is deposited on the upper surfaces of insulating layer 101_2 and sacrificial layer 102_2Sc', and the portion corresponding to the upper part of conductive layer 102 is removed to form insulating layers 141 and 142. Also, the sacrificial layer 102_2Sc' is removed to form openings 102A_2, GBLC2A, and 130A. This process is carried out by methods such as CVD, RIE, or wet etching.

[0152] Next, as shown in Figure 78, for example, conductive layers 133 and 133d are formed inside the opening 130A and GBLC2A. In this step, for example, a conductive oxide layer such as indium tin oxide (ITO) is formed inside the openings 102A_2, 130A, and GBLC2A. Next, inside the opening 102A_2, a portion of the conductive oxide layer (the portion formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive oxide layer is divided in the Z direction to form conductive layers 133 and 133d. This step is performed by, for example, CVD and RIE.

[0153] Next, as shown in Figure 79, for example, insulating layers 132, 132d and conductive layers 131, 131d are formed inside the openings 102A_2, 130A, and GBLC2A. A material similar to conductive layer 102 is formed inside opening 102A_2, and unnecessary parts are removed to form the capacitor structure 130, electrode structure 130c2, contact GBLC2, and conductive layer 102(PL). This process is carried out by, for example, CVD, RIE, etc.

[0154] Next, as shown in Figure 80, for example, an insulating layer 106 is formed in the opening 102A_2. Then, the portions of insulating layer 101_2 and insulating layer 141 above the opening 104A are removed, and after removing the sacrificial layer 111Sc2 through the opening 104A, a semiconductor layer 111 is formed. Furthermore, a conductive oxide film 104a' containing the same material as the conductive oxide film 104a and an internal region CAV' are formed inside the opening 104A. In this step, the opening 104A is not filled by the conductive oxide film 104a'. This step is performed by methods such as CVD or CMP.

[0155] Next, an insulating layer 143 (Figure 64) is formed on the upper surface of the structure shown in Figure 80, and the portions of insulating layer 141 and insulating layer 143 above the contact GBLC2 are removed, and a plug 150 is formed in the removed portion. Above the insulating layer 143 and plug 150, a wiring layer M0 including a global bit wire GBL and multiple wirings m0, a wiring layer M1 including multiple wirings m1, and multiple first bonding electrodes P are formed. I1 It forms.

[0156] Next, a process similar to the one described with reference to Figures 50 to 58 is performed to form the structure described with reference to Figures 63 and 64.

[0157] [effect] In this embodiment, by integrating the contact GBLC2 and the multiple electrode structures 130c2 into a single film structure, the manufacturing of the contact GBLC2 and the electrode structures 130c2 can be carried out efficiently, contributing to a reduction in the manufacturing cost of semiconductor memory devices. Furthermore, by connecting the contact GBLC2 and the multiple electrode structures 130c2 with low resistance, a high-speed semiconductor memory device can be provided.

[0158] [Modified version of the second embodiment] Next, a modified example of the semiconductor memory device according to the second embodiment will be described with reference to Figure 81A. Figure 81A is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this modified example.

[0159] The semiconductor memory device according to this modified example (Figure 81A) is basically configured the same as the semiconductor memory device according to the second embodiment (Figure 64). However, the semiconductor memory device according to this modified example is equipped with a contact GBLC3 instead of a contact GBLC2, and the plug 150 is not provided. Furthermore, in the semiconductor memory device according to this modified example, the portion of the semiconductor layer 111 and the conductive oxide film 104a on the global bit line GBL side of the transistor layer TL is removed, and an insulating layer 101_3 made of silicon oxide (SiO2) or the like is provided in the removed portion.

[0160] Contact GBLC3 (Figure 81A) is basically constructed in the same way as contact GBLC2 (Figure 64). However, the conductive layer 133d included in contact GBLC3 is directly connected to the global bit line GBL on its lower surface.

[0161] [Manufacturing method] Figure 81B is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to this modified example.

[0162] The semiconductor memory device according to this modified example (Figure 81A) is basically manufactured in the same manner as the semiconductor memory device according to the second embodiment. However, in the manufacturing of the semiconductor memory device according to this modified example, after the process corresponding to Figure 80, the portion of the semiconductor layer 111 and the conductive oxide film 104a' that is on the global bit line GBL side of the transistor layer TL is removed, as shown in Figure 81B. This process is performed, for example, by RIE.

[0163] Next, an insulating layer 101_3 is formed in the area removed in the process shown in Figure 81B by CVD or the like. Furthermore, the insulating layer 141 and a portion of the insulating layers 101_3 and 106 on the upper surface of the structure shown in Figure 81B are removed to expose the conductive layer 133d contained in the contact GBLC3. Then, the global bit wire GBL, the wiring layer M0 containing multiple wirings m0, the wiring layer M1 containing multiple wirings m1, and the multiple first bonding electrodes P are formed. I1 It forms.

[0164] Next, a process similar to the one described with reference to Figures 50 to 58 is performed to form the structure described with reference to Figure 81A.

[0165] [Third Embodiment] Figures 82 to 84 are schematic cross-sectional views showing a portion of the configuration of a semiconductor memory device according to the third embodiment. Figure 82 is a schematic cross-sectional view showing a portion of the configuration of the memory layer ML. Figure 83 is a schematic cross-sectional view showing a portion of the configuration of the memory layer ML, and is an enlarged view of a portion of Figure 82. Figure 84 shows a cross-section of the structure shown in Figure 83, cut along the line A3-A3', and viewed in the direction of the arrow. In the following description, the same reference numerals are used for parts that are the same as in the first embodiment, and their descriptions are omitted.

[0166] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment does not have a conductive layer 120 and an insulating layer 101 (Figure 5), and instead has a conductive layer 120_3 (Figure 82).

[0167] The conductive layer 120_3 (Figures 83 and 84) is basically constructed in the same way as the conductive layer 120 (Figures 6 and 7). However, as shown in Figure 83, for example, in the memory layer ML, the conductive layer 120_3 functions as a word line WL (Figure 2) corresponding to transistors TrC provided on both sides in the X direction relative to the conductive layer 120_3. For example, in the transistor layer TL, the conductive layer 120_3 functions as a bit line selection line LB (Figure 2) corresponding to transistors TrB provided on both sides in the X direction relative to the conductive layer 120_3. The conductive layer 120_3 is connected to the conductive layers 113 provided on both sides in the X direction on its sides in the X direction. The conductive layer 120_3 comprises, for example, a barrier conductive film 121_3 made of titanium nitride (TiN) and a conductive film 122_3 made of tungsten (W).

[0168] The barrier conductive film 121_3 (Figure 84) is basically constructed in the same way as the barrier conductive film 121 (Figure 7). However, unlike the barrier conductive film 121, the barrier conductive film 121_3 is not provided on one side of the conductive layer 113 in the X direction (the side facing the conductive layer 120_3).

[0169] [Manufacturing method] Figures 85 to 104 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0170] Figures 85, 87, 89, 91, 93, 95, 97, 99, 101, and 103 show the XY cross-sections corresponding to Figure 83.

[0171] Figures 86, 88, 90, 92, 94, 96, 98, 100, 102, and 104 show XZ cross-sections corresponding to parts of the memory layer ML and the transistor layer TL.

[0172] In Figures 85 to 104, the upward direction during the manufacturing process is represented as the positive Z-direction, and the downward direction is represented as the negative Z-direction.

[0173] In this manufacturing method, for example, as shown in Figures 85 and 86, multiple insulating layers 103 and 203, and multiple sacrificial layers MLA are alternately formed on top of a substrate Sub (not shown). This process is carried out by, for example, CVD.

[0174] Next, an insulating layer 115 is formed, for example, as shown in Figures 85 and 86. In this step, for example, an opening is formed at a position corresponding to the insulating layer 115. This opening extends in the Z direction and penetrates multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction. This step is performed, for example, by RIE. After the opening is formed, the insulating layer 115 is formed. This step is performed, for example, by CVD.

[0175] Next, as shown in Figures 87 and 88, for example, an opening 102A_3 is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A_3 extends in the Z direction and penetrates multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction. This process is carried out, for example, by RIE.

[0176] Next, as shown in Figures 89 and 90, for example, an opening 130A_3 is formed through the opening 102A_3. Parts of the upper and lower surfaces of the insulating layers 103 and 203 are exposed through the opening 130A_3. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A_3. This step is performed, for example, by wet etching.

[0177] Next, as shown in Figures 91 and 92, for example, silicon (Si) or the like is embedded inside the openings 102A_3 and 130A_3 to form a sacrificial layer 102Sc'_3. This process is carried out by, for example, CVD.

[0178] Next, an opening 104A_3 is formed, for example, as shown in Figures 91 and 92. The opening 104A_3 extends in the Z direction and penetrates multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked in the Z direction. This process is carried out, for example, by RIE.

[0179] Next, as shown in Figures 93 and 94, for example, the sacrificial layer MLA is selectively removed through the opening 104A_3 to form the opening 111A_3. This step is performed, for example, by wet etching.

[0180] Next, as shown in Figures 95 and 96, for example, a barrier conductive film 121_3' containing the same material as the barrier conductive film 121_3 and a conductive film 122_3' containing the same material as the conductive film 122_3 are formed inside the openings 111A_3 and 104A_3 through the opening 104A_3. In this step, the opening 111A_3 is filled by the barrier conductive film 121_3' and the conductive film 122_3', while the opening 104A_3 is not filled by the barrier conductive film 121_3' and the conductive film 122_3'. This step is performed, for example, by CVD.

[0181] Next, as shown in Figures 97 and 98, for example, a portion of the barrier conductive film 121_3' and the conductive film 122_3' is removed through the opening 104A_3, and the barrier conductive film 121_3 and the conductive film 122_3 are formed in a portion of the interior of the opening 111A_3. This process is carried out by, for example, CVD.

[0182] Next, as shown in Figures 99 and 100, for example, a conductive layer 113' is formed inside the opening 111A_3. In this step, for example, a conductive film such as titanium nitride (TiN) is formed inside the openings 104A_3 and 111A_3. Next, inside the opening 104A_3, a portion of the conductive film (the portion formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive film is divided in the Z direction to form the conductive layer 113'. This step is performed by, for example, CVD and RIE.

[0183] Next, as shown in Figures 101 and 102, for example, the sacrificial layer 102Sc'_3 is removed to form openings 102A_3 and 130A_3. Furthermore, a portion of the upper and lower surfaces of the insulating layers 103 and 203, as well as a portion of the X-direction side of the conductive layer 113', exposed in opening 130A_3, are removed to form the conductive layer 113. This process increases the width of opening 130A_3 in the Z-direction. This process is carried out, for example, by wet etching.

[0184] Next, as shown in Figures 103 and 104, for example, an insulating layer 112 is formed inside the openings 102A_3, 104A_3, 111A_3, and 130A_3. This process is carried out, for example, by CVD.

[0185] Next, in the same process as shown in Figures 30 to 49, a capacitor structure 130 or an electrode structure 130c is formed inside the opening 130A_3, a conductive layer 102(PL) etc. is formed inside the opening 102A_3, a transistor structure 110 is formed inside the opening 111A_3, via wiring 104 etc. is formed inside the opening 104A_3, and a contact GBLC1 etc. is formed to connect to the electrode structure 130c.

[0186] Next, a process similar to that shown in Figures 50 to 58 is performed, thereby forming the structure described with reference to Figures 82 to 84.

[0187] [effect] The semiconductor memory device of this embodiment (Figure 82) does not require an insulating layer 101 compared to the semiconductor memory device of the first embodiment (Figure 5). Therefore, it is possible to increase the density of the semiconductor memory device. In addition, by eliminating the process of forming the insulating layer 101, the number of process steps can be reduced, which can contribute to reducing the manufacturing cost of the semiconductor memory device.

[0188] [Other embodiments] The semiconductor memory devices according to the first to third embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations can be adjusted as appropriate.

[0189] For example, in the semiconductor memory devices according to the second and third embodiments, an example in which the via wiring 104 (BL) includes an internal region CAV was shown. However, in the second and third embodiments, the via wiring 104 (BL) may include a conductive member instead of the internal region CAV. The conductive member may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or the like.

[0190] For example, in the semiconductor memory device according to the second embodiment, two transistor layers TL arranged in the Z direction were exemplified. However, three or more transistor layers TL may be arranged in the Z direction. Three or more transistors TrB provided in these three or more transistor layers TL may be connected in parallel between the via wiring 104 (BL) and the global bit line GBL.

[0191] In addition, in the above description, an example in which the capacitor CpC is adopted as the memory unit connected to the transistor structure 110 was described. However, the memory unit does not have to be the capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other materials, and record data by utilizing the characteristics of these materials. For example, in any of the structures described above, any of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[0192] In addition, the manufacturing methods of the semiconductor memory devices according to the first to third embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps may be interchanged, or any two of the above-described steps may be executed simultaneously.

[0193] [Others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0194] 102...conductive layer, 104...via wiring, 111...semiconductor layer, 113...conductive layer, 120...conductive layer, 130...capacitor structure, 130c...electrode structure, BL...bit wire, Cn1...electrode, CpC...capacitor, GBL...global bit wire, GBLC1...contact, PL...plate wire, WL...word wire.

Claims

1. Multiple memory layers arranged in the first direction, via wiring extending in the first direction, A first wiring is provided on one side of the plurality of memory layers in the first direction and extends in a second direction intersecting the first direction, An insulating layer is provided on the other side of the plurality of memory layers in the first direction, covering the end of the via wiring. Equipped with, Each of the aforementioned memory layers is: A semiconductor layer electrically connected to the via wiring, A gate electrode facing the semiconductor layer, A second wiring extends in a third direction intersecting the first and second directions and is electrically connected to the gate electrode, A memory portion is provided on the semiconductor layer opposite to the second wiring in the second direction and electrically connected to the semiconductor layer. Equipped with, The via wiring comprises a conductive member extending in the first direction and an internal region extending in the first direction, the outer surface of which is surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer, or is continuous with the insulating layer. Semiconductor memory device.

2. The aforementioned internal region is in contact with the insulating layer. The semiconductor memory device according to claim 1.

3. The aforementioned internal region includes a cavity. The semiconductor memory device according to claim 1.

4. The aforementioned internal region includes silicon oxide or silicon nitride. The semiconductor memory device according to claim 1.

5. The conductive member includes a first oxide conductive layer extending in the first direction and a second oxide conductive layer extending in the first direction. The second oxide conductive layer is provided between the first oxide conductive layer and the internal region. The semiconductor memory device according to claim 1.

6. The aforementioned multiple memory layers are In the first direction, a first memory layer is provided at the position closest to the first wiring, In the first direction, the second memory layer is located at the position furthest from the first wiring and Includes, The internal region extends in the first direction from the first memory layer to the second memory layer. The semiconductor memory device according to claim 1.

7. A plate wiring extending in the first direction and electrically connected in common to a plurality of the memory units, A conductive layer is provided on the insulating layer side in the first direction for the plurality of memory layers, and is provided at a position that overlaps with the via wiring when viewed from the first direction. Equipped with, The plate wiring and the conductive layer are electrically connected. The semiconductor memory device according to claim 1.

8. It comprises a first chip and a second chip that are connected to each other, The first chip is The plurality of memory layers, The via wiring and, The first wiring mentioned above, A plurality of first bonding electrodes, at least one of which is electrically connected to the first wiring, Equipped with, The second chip is circuit board and Multiple transistors provided on the surface of the substrate, Multiple second adhesive electrodes electrically connected to the plurality of transistors and Equipped with, The plurality of first bonding electrodes are connected to the plurality of second bonding electrodes. The semiconductor memory device according to claim 1.

9. The gate electrode faces one and the other side of the semiconductor layer in the first direction, and one and the other side of the semiconductor layer in the third direction. The semiconductor memory device according to claim 1.

10. The semiconductor layer comprises at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 1.

11. Multiple memory layers arranged in the first direction, A first wiring is provided on one side of the plurality of memory layers in the first direction and extends in a second direction intersecting the first direction, A plurality of select transistor layers are provided between the plurality of memory layers and the first wiring, and are arranged in the first direction, Via wiring extending in the first direction within the range of the first direction corresponding to the plurality of memory layers and the plurality of selected transistor layers, A contact electrode extending in the first direction within a range of the first direction corresponding to the plurality of selected transistor layers Equipped with, Each of the aforementioned memory layers is: A first semiconductor layer electrically connected to the via wiring, A first gate electrode facing the first semiconductor layer, A second wiring extends in a third direction intersecting the first and second directions and is electrically connected to the first gate electrode, A memory portion is provided on the side opposite to the second wiring in the second direction with respect to the first semiconductor layer, and is electrically connected to the first semiconductor layer. Equipped with, Each of the aforementioned multiple selection transistor layers is, A second semiconductor layer electrically connected to the via wiring, A second gate electrode facing the second semiconductor layer, A third wiring extending in the third direction and electrically connected to the second gate electrode, A connecting electrode is provided with respect to the second semiconductor layer on the side opposite to the third wiring in the second direction, and is electrically connected to the second semiconductor layer and the first wiring. Equipped with, The contact electrode is continuous with the plurality of connecting electrodes included in the plurality of selected transistor layers, The contact electrode and the plurality of connecting electrodes include an integrally formed oxide conductive layer. Semiconductor memory device.

12. A portion of the oxide conductive layer contained in the contact electrode is in contact with the first wiring, A portion of the oxide conductive layer included in the connecting electrode is in contact with the second semiconductor layer. The semiconductor memory device according to claim 11.

13. The via wiring has a first surface on the side closer to the first wiring in the first direction, The contact electrode has a second surface on the side closer to the first wiring in the first direction, The position of the second surface in the first direction is closer to the first wiring than the position of the first surface in the first direction. The semiconductor memory device according to claim 11.

14. The via wiring has a first surface on the side closer to the first wiring in the first direction, The contact electrode has a second surface on the side closer to the first wiring in the first direction, The position of the second surface in the first direction is further from the first wiring than the position of the first surface in the first direction. The semiconductor memory device according to claim 11.

15. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 11.

16. Multiple memory layers arranged in the first direction, A first via wiring extending in the first direction, The position of the first via wiring and the second via wiring that intersects the first direction are different, and the second via wiring extends in the first direction. Equipped with, Each of the aforementioned memory layers is: A wiring provided between the first via wiring and the second via wiring, extending in a third direction that intersects the first and second directions, A first semiconductor layer electrically connected to the first via wiring, A first gate electrode facing the first semiconductor layer and electrically connected to the wiring, A first memory portion is provided on the side opposite to the wiring in the second direction with respect to the first semiconductor layer, and is electrically connected to the first semiconductor layer. A second semiconductor layer electrically connected to the second via wiring, A second gate electrode facing the second semiconductor layer and electrically connected to the wiring, A second memory portion is provided on the side opposite to the wiring in the second direction with respect to the second semiconductor layer and is electrically connected to the second semiconductor layer. Equipped with, The aforementioned wiring does not have through holes extending in the first direction. Semiconductor memory device.

17. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 16.

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