Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can prevent sudden malfunctions even if a switching element fails, thereby improving reliability. [Solution] The semiconductor device comprises an upper arm 101 and a lower arm 102, each having a plurality of switching elements 10a to 10h. Multiple units (10a, 10b), (10c, 10d) are formed by connecting multiple switching elements 10a to 10d of the upper arm 101 in series between the high-potential terminal P and the neutral point 15 of the upper arm 101 and the lower arm 102, and these units are connected in parallel between the high-potential terminal P and the neutral point 15. Multiple units (10e, 10f), (10g, 10h) are formed by connecting multiple switching elements 10e to 10h of the lower arm 102 in series between the low-potential terminal N and the neutral point 15, and these units are connected in parallel between the low-potential terminal N and the neutral point 15.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses an inverter module including a plurality of pairs of switching elements connected in series, and a plurality of pairs of switching elements connected in parallel. Patent Document 2 discloses an intelligent power module (IPM). Patent Document 3 discloses a circuit in which a pressure-contact type switching element is connected in parallel to a module type switching element in a circuit in which switching elements of each arm are constituted by a plurality of serially connected module type switching elements. Patent Document 4 discloses a circuit for redundantizing part or all of a power conversion system.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor power module, when a switching element fails due to an accidental failure caused by cosmic rays or the like, the function may suddenly stop, and there is a problem of low reliability.

[0005] In view of the above issues, this disclosure aims to provide a semiconductor device that can prevent sudden malfunctions even when a switching element fails, thereby improving reliability. [Means for solving the problem]

[0006] One aspect of the present disclosure is a semiconductor device comprising a high-potential terminal, a low-potential terminal, an upper arm and a lower arm connected between the high-potential terminal and the low-potential terminal and each having a switching element, and a gate drive circuit for driving the switching element, wherein the switching elements of the upper arm are connected in series in multiple quantities between the high-potential terminal and the neutral point of the upper arm and the lower arm to constitute a first unit, and the first unit is connected in parallel in multiple quantities between the high-potential terminal and the neutral point, and the switching elements of the lower arm are connected in series in multiple quantities between the low-potential terminal and the neutral point to constitute a second unit, and the second unit is connected in parallel in multiple quantities between the low-potential terminal and the neutral point. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a semiconductor device that can prevent sudden malfunctions even if a switching element fails, thereby improving reliability. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram showing an example of a semiconductor device according to the first embodiment. [Figure 2] This is a circuit diagram showing an example of a half-bridge circuit according to the first embodiment. [Figure 3] This is a circuit diagram showing an example of a level shift / control circuit according to the first embodiment. [Figure 4] This is a circuit diagram showing an example of a fault detection circuit according to the first embodiment. [Figure 5] This table shows the input-output relationship of the fault detection circuit according to the first embodiment. [Figure 6] This is a circuit diagram showing an example of a level-down circuit according to the first embodiment. [Figure 7] This is a circuit diagram showing an example of a level-up circuit according to the first embodiment. [Figure 8] This is a circuit diagram showing an example of a gate drive circuit according to the first embodiment. [Figure 9] This is a circuit diagram showing an example of a control circuit according to the first embodiment. [Figure 10] This is a circuit diagram showing a semiconductor device according to a comparative example. [Figure 11] This is a circuit diagram showing an example of a half-bridge circuit according to the second embodiment. [Figure 12] This is a circuit diagram showing an example of a half-bridge circuit according to the third embodiment. [Figure 13] This is a cross-sectional view of a switching element according to a comparative example. [Figure 14] This is a cross-sectional view of a switching element according to the third embodiment. [Figure 15] This is a circuit diagram showing an example of a half-bridge circuit according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the first to fourth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different between the drawings. Further, the first to fourth embodiments shown below are examples of devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as the following.

[0010] Also, in this specification, the definitions of directions such as up and down are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, which is of course.

[0011] (First Embodiment) <Overall Configuration> The semiconductor device (semiconductor power module) according to the first embodiment is applicable to an intelligent power module (IPM) used in an air conditioner, an industrial inverter, etc., an electronic speed controller (ESC) used for driving a motor of a drone, etc. As shown in FIG. 1, the semiconductor device according to the first embodiment includes three-phase half-bridge circuits (redundant half-bridge circuits) 1u, 1v, 1w for the U-phase, V-phase, and W-phase, and level shift / control circuits 2u, 2v, 2w respectively connected to the half-bridge circuits 1u, 1v, 1w and controlling the operations of the half-bridge circuits 1u, 1v, 1w.

[0012] The semiconductor device according to the first embodiment includes a high-potential side terminal (positive terminal) P, a low-potential side terminal (negative terminal) N, output terminals U, V, W, and input terminals LIN(U), HIN(U), LIN(V), HIN(V), LIN(W), HIN(W).

[0013] The high-potential side terminal P is a power supply terminal that supplies a power supply voltage (power) to the half-bridge circuits 1u, 1v, 1w. The high-potential side terminal P is connected to the half-bridge circuits 1u, 1v, 1w. The low-potential side terminal N is a terminal to which a voltage lower than the power supply voltage is applied. The low-potential side terminal N is connected to the half-bridge circuits 1u, 1v, 1w.

[0014] The output terminals U, V, W are terminals that can be respectively connected to the U-phase, V-phase, and W-phase of a load (not shown) such as a motor. The output terminal U is connected to the half-bridge circuit 1u. The output terminal V is connected to the half-bridge circuit 1v. The output terminal W is connected to the half-bridge circuit 1w.

[0015] The input terminals LIN(U), HIN(U), LIN(V), HIN(V), LIN(W), and HIN(W) are terminals that can be connected to an external microcontroller (not shown). Note that the semiconductor device according to the first embodiment may include a microcontroller (not shown). Input terminals LIN(U) and HIN(U) are connected to the level shift / control circuit 2u. Input terminals LIN(V) and HIN(V) are connected to the level shift / control circuit 2v. Input terminals LIN(W) and HIN(W) are connected to the level shift / control circuit 2w.

[0016] <Half-bridge circuit configuration> Figure 2 shows details of the U-phase herb bridge circuit 1u shown in Figure 1. As shown in Figure 2, the U-phase herb bridge circuit 1u comprises a high-potential upper arm 101 connected to the high-potential terminal P and a low-potential lower arm 102 connected to the low-potential terminal N. The neutral point 15, which is the connection point between the upper arm 101 and the lower arm 102, is connected to the output terminal U.

[0017] The upper arm 101 is equipped with a plurality (four) power switching elements (switching elements) 10a to 10d. A plurality (two) of switching elements 10a and 10b are connected in series between the high-potential terminal P and the neutral point 15 to form a unit (10a, 10b). A plurality (two) of switching elements 10c and 10d are connected in series between the high-potential terminal P and the neutral point 15 to form a unit (10c, 10d). The plurality (two) units (10a, 10b) and (10c, 10d) are connected in parallel between the high-potential terminal P and the neutral point 15.

[0018] The lower arm 102 is equipped with multiple (four) power switching elements (switching elements) 10e to 10h. Multiple (two) switching elements 10e and 10f are connected in series between the low-potential terminal N and the neutral point 15 to form a unit (10e, 10f). Multiple (two) switching elements 10g and 10h are connected in series between the low-potential terminal N and the neutral point 15 to form a unit (10g, 10h). Multiple (two) units (10e, 10f) and (10g, 10h) are connected in parallel between the low-potential terminal N and the neutral point 15.

[0019] In the semiconductor device according to the first embodiment, an example is given where the switching elements 10a to 10h are composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). Note that the switching elements 10a to 10h may be composed of other power switching elements such as insulated-gate bipolar transistors (IGBTs). The switching elements 10a to 10h may be composed of elements with the same specifications. Freewheeling diodes (FWDs) 11a to 11h are connected in antiparallel to the switching elements 10a to 10d.

[0020] In the upper arm 101, the drain of the upper (high potential side) switching element 10a is connected to the high potential side terminal P. The source of the switching element 10a is connected to the drain of the lower (low potential side) switching element 10b. The source of the switching element 10b is connected to the neutral point 15. The drain of the upper (high potential side) switching element 10c is connected to the high potential side terminal P. The source of the switching element 10c is connected to the drain of the lower (low potential side) switching element 10d. The source of the switching element 10d is connected to the neutral point 15.

[0021] In the lower arm 102, the drain of the upper (high potential side) switching element 10e is connected to the neutral point 15. The source of the switching element 10e is connected to the drain of the lower (low potential side) switching element 10f. The source of the switching element 10f is connected to the low potential side terminal N. The drain of the upper (high potential side) switching element 10g is connected to the neutral point 15. The source of the switching element 10g is connected to the drain of the lower (low potential side) switching element 10h. The source of the switching element 10h is connected to the low potential side terminal N.

[0022] Gate drive circuits 12a to 12h are connected to the gates of switching elements 10a to 10h, respectively. The gate drive circuits 12a to 12h drive the switching elements 10a to 10h, respectively, and control the on / off operation of the switching elements 10a to 10h.

[0023] A fault detection circuit 13a is connected to the midpoint 14a, which is the connection point between switching elements 10a and 10b. The fault detection circuit 13a monitors the midpoint voltage SENSE, which is the potential at midpoint 14a, and detects faults (abnormalities) in switching elements 10a and 10b. A fault detection circuit 13b is connected to the midpoint 14b, which is the connection point between switching elements 10c and 10d. The fault detection circuit 13b monitors the midpoint voltage SENSE, which is the potential at midpoint 14b, and detects faults (abnormalities) in switching elements 10c and 10d.

[0024] A fault detection circuit 13c is connected to the midpoint 14c, which is the connection point between switching elements 10e and 10f. The fault detection circuit 13c monitors the midpoint voltage SENSE, which is the potential at midpoint 14c, and detects faults (abnormalities) in switching elements 10e and 10f. A fault detection circuit 13d is connected to the midpoint 14d, which is the connection point between switching elements 10g and 10h. The fault detection circuit 13d monitors the midpoint voltage SENSE, which is the potential at midpoint 14d, and detects faults (abnormalities) in switching elements 10g and 10h.

[0025] The details of the configurations of the V-phase herb bridge circuit 1v and the W-phase half-bridge circuit 1w shown in Figure 1 are substantially the same as the details of the configuration of the U-phase herb bridge circuit 1u shown in Figure 2, so redundant explanations will be omitted.

[0026] <Level shift / control circuit configuration> Figure 3 shows an example of the details of the U-phase level shift / control circuit 2u shown in Figure 1. As shown in Figure 3, the level shift / control circuit 2u comprises control circuits 21a to 21d, level-down circuits 22a and 22b that convert the voltage level of the ALM signal from the fault detection circuits 13a to 13d to a lower level, inverter circuits 22c and 22d, and level-up circuits 23a to 23f that convert the voltage level of the OUT signal from the control circuits 21a to 21d to a higher level.

[0027] The control circuit 21a is connected to the input terminal HIN(U). The control circuit 21a outputs a signal OUT that controls the gate drive circuits 12a and 12b in response to the input signal IN from the input terminal HIN(U).

[0028] The level-down circuit 22a is connected to the control circuit 21a and the fault detection circuit 13a shown in Figure 2. The level-down circuit 22a converts the voltage level of the ALM signal from the fault detection circuit 13a shown in Figure 2 to a lower level and outputs the ALM' signal to the control circuit 21a. The level-up circuits 23a and 23b are connected to the control circuit 21a and the gate drive circuits 12a and 12b shown in Figure 2. The level-up circuits 23a and 23b convert the voltage level of the OUT signal from the control circuit 21a to a higher level and output the gate drive signal GDRV to the gate drive circuits 12a and 12b shown in Figure 2.

[0029] The control circuit 21b is connected to the input terminal HIN(U). The control circuit 21b outputs a signal OUT that controls the gate drive circuits 12c and 12d in response to the input signal IN from the input terminal HIN(U).

[0030] The level-down circuit 22b is connected to the control circuit 21b and the fault detection circuit 13b shown in Figure 2. The level-down circuit 22b converts the voltage level of the ALM signal from the fault detection circuit 13b shown in Figure 2 to a lower level and outputs the ALM' signal to the control circuit 21b. The level-up circuits 23c and 23d are connected to the control circuit 21b and the gate drive circuits 12c and 12d shown in Figure 2. The level-up circuits 23c and 23d convert the voltage level of the OUT signal from the control circuit 21b to a higher level and output the gate drive signal GDRV to the gate drive circuits 12c and 12d shown in Figure 2.

[0031] The control circuit 21c is connected to the input terminal LIN(U). The control circuit 21c outputs a signal OUT that controls the gate drive circuits 12e and 12f in response to the input signal IN from the input terminal LIN(U).

[0032] The inverter circuit 22c is connected to the control circuit 21c and the fault detection circuit 13c shown in Figure 2. The inverter circuit 22c inverts the ALM signal from the fault detection circuit 13c shown in Figure 2 and outputs the ALM' signal to the control circuit 21c. The level-up circuit 23e is connected to the control circuit 21c and the gate drive circuit 12e shown in Figure 2. The level-up circuit 23e converts the voltage level of the signal OUT from the control circuit 21c to a higher level and outputs the gate drive signal GDRV to the gate drive circuit 12e shown in Figure 2. The control circuit 21c is connected to the gate drive circuit 12f shown in Figure 2. The signal OUT from the control circuit 21c is transmitted to the gate drive circuit 12f shown in Figure 2 as the gate drive signal GDRV without converting the voltage level.

[0033] The control circuit 21d is connected to the input terminal LIN(U). The control circuit 21d outputs a signal OUT that controls the gate drive circuits 12g and 12h in response to the input signal IN from the input terminal LIN(U). The inverter circuit 22d is connected to the control circuit 21d and the fault detection circuit 13d shown in Figure 2. The level-down circuit 22d inverts the signal ALM from the fault detection circuit 13d shown in Figure 2 and outputs the signal ALM' to the control circuit 21d. The level-up circuit 23f is connected to the control circuit 21d and the gate drive circuit 12g shown in Figure 2. The level-up circuit 23f converts the voltage level of the signal OUT from the control circuit 21d to a higher level and outputs the gate drive signal GDRV to the gate drive circuit 12g shown in Figure 2. The control circuit 21d is connected to the gate drive circuit 12h shown in Figure 2. The signal OUT from the control circuit 21d is transmitted to the gate drive circuit 12h shown in Figure 2 as the gate drive signal GDRV without converting the voltage level.

[0034] The details of the configurations of the V-phase level shift / control circuit 2v and the W-phase level shift / control circuit 2w shown in Figure 1 are substantially the same as the details of the configuration of the U-phase level shift / control circuit 2u shown in Figure 3, so redundant explanations will be omitted.

[0035] <Configuration of fault detection circuit> Figure 4 shows an example of the details of the fault detection circuit 13a shown in Figure 2. As shown in Figure 4, the fault detection circuit 13a comprises resistors 31-34, operational amplifiers 35 and 36, and an XOR circuit 37. One end of resistors 31 and 33 is connected to the high-potential terminal P. The other ends of resistors 31 and 33 are connected to one end of resistors 32 and 34, respectively. The other ends of resistors 32 and 34 are connected to the output terminal U.

[0036] One input side of the operational amplifier 35 is connected to the midpoint 14a of the switching elements 10a and 10b shown in Figure 2, and the midpoint voltage SENSE is input. The other input side of the operational amplifier 35 is connected to the connection point of resistors 31 and 32, and a predetermined threshold voltage (reference voltage) Vref_low, which is the voltage at the connection point of resistors 31 and 32, is input. The predetermined threshold voltage Vref_low is the lower limit voltage of the normal range (lower threshold voltage) and can be set as appropriate.

[0037] One input side of the operational amplifier 36 is connected to the midpoint 14a of the switching elements 10a and 10b shown in Figure 2, and the midpoint voltage SENSE is input. The other input side of the operational amplifier 35 is connected to the connection point of resistors 33 and 34, and a predetermined threshold voltage (reference voltage) Vref_high, which is the voltage at the connection point of resistors 33 and 34, is input. The predetermined threshold voltage Vref_high is the upper limit voltage of the normal range (upper threshold voltage) and can be set as appropriate.

[0038] One input side of the XOR circuit 37 is connected to the output side of the operational amplifier 35. The other input side of the XOR circuit 37 is connected to the output side of the operational amplifier 36. The level-down circuit 22a shown in Figure 3 is connected to the output side of the XOR circuit 37. The XOR circuit 37 outputs the ALM signal to the level-down circuit 22a.

[0039] Figure 5 shows the input-output relationship of the fault detection circuit 13a. As shown in the middle of Figure 5, if the midpoint voltage SENSE input to the fault detection circuit 13a is within the normal range of a predetermined threshold voltage Vref_low or higher and a predetermined threshold voltage Vref_high or lower, the fault detection circuit 13a does not detect a fault and outputs a signal ALM of "1" indicating normal operation.

[0040] Furthermore, as shown in the upper part of Figure 5, if the midpoint voltage SENSE input to the fault detection circuit 13a is less than a predetermined threshold voltage Vref_low, the fault detection circuit 13a detects a fault and outputs "0" as the ALM signal to indicate an abnormality.

[0041] Furthermore, as shown in the lower part of Figure 5, if the midpoint voltage SENSE input to the fault detection circuit 13a exceeds a predetermined threshold voltage Vref_high, the fault detection circuit 13a detects a fault and outputs "0" as the ALM signal to indicate an abnormality.

[0042] The detailed configurations of fault detection circuits 13b to 13d shown in Figure 2, and the input / output relationships of fault detection circuits 13b to 13d, are substantially the same as the detailed configurations of fault detection circuit 13a shown in Figure 4, and the input / output relationships of fault detection circuit 13a shown in Figure 5. Therefore, redundant explanations are omitted.

[0043] <Configuration of the level-down circuit> Figure 6 shows a detailed example of the level-down circuit 22a shown in Figure 3. As shown in Figure 6, the level-down circuit 22a comprises a MOS transistor 51 and a resistor 52. The gate of the MOS transistor 51 is connected to the fault detection circuit 13a shown in Figure 2, and the ALM signal from the fault detection circuit 13a shown in Figure 2 is input to it.

[0044] The source of the MOS transistor 51 is supplied with the sum of the voltage Vout at the output terminal U (neutral point 15) of the switching elements 10a and 10b and the power supply voltage VDD (Vout + VDD). The power supply voltage VDD is, for example, between 10V and 15V, but is not particularly limited. The drain of the MOS transistor 51 is connected to one end of the resistor 52. The other end of the resistor 52 is connected to the low-potential terminal N. The connection point between the MOS transistor 51 and the resistor 52 is connected to the control circuit 21a shown in Figure 3. The voltage at the connection point between the MOS transistor 51 and the resistor 52 is output as the signal ALM' to the control circuit 21a shown in Figure 3.

[0045] The details of the configuration of the level-down circuit 22b shown in Figure 3 are substantially the same as those of the level-down circuit 22a shown in Figure 6, so redundant explanations will be omitted.

[0046] <Configuration of the Level-Up Circuit> Figure 7 shows an example of the details of the level-up circuit 23a shown in Figure 3. As shown in Figure 7, the level-up circuit 23a comprises a pulse generator 61, MOS transistors 62 and 63, inverters 66 and 67, and an RS flip-flop 68. The pulse generator 61 is connected to the control circuit 21a shown in Figure 3. The pulse generator 61 outputs a set signal SET and a reset signal RESET in response to the signal OUT.

[0047] A pulse generator 61 is connected to the gate of MOS transistor 62, and a set signal SET is input to it. The low-potential terminal N is connected to the source of MOS transistor 62. One end of resistor 64 is connected to the drain of MOS transistor 62. The other end of resistor 64 is applied with the sum of the midpoint voltage Vm of switching elements 10a and 10b and the power supply voltage VDD (Vm + VDD).

[0048] A pulse generator 61 is connected to the gate of MOS transistor 63, and a reset signal RESET is applied to it. The low-potential terminal N is connected to the source of MOS transistor 63. One end of resistor 65 is connected to the drain of MOS transistor 63. The other end of resistor 65 is connected to the sum of the midpoint voltage Vm of switching elements 10a and 10b and the power supply voltage VDD (Vm + VDD).

[0049] The input side of inverter 66 is connected to the connection point between MOS transistor 62 and resistor 64. The input side of inverter 67 is connected to the connection point between MOS transistor 63 and resistor 65. The input side of RS flip-flop 68 is connected to the output sides of inverters 66 and 67. The output side of RS flip-flop 68 is connected to the gate drive circuit 12a shown in Figure 2. RS flip-flop 68 outputs the gate drive signal GDRV to the gate drive circuit 12a shown in Figure 2.

[0050] The details of the configuration of the level-up circuits 23b to 23f shown in Figure 3 are substantially the same as the details of the configuration of the level-up circuit 23a shown in Figure 7, so redundant explanations will be omitted. However, the differences between level-up circuits 23b and 23d and level-up circuit 23a will be explained below. In level-up circuits 23b and 23d, the sum of the voltage Vout at the output terminal U (neutral point 15) and the power supply voltage VDD (Vout + VDD) is applied to the other end of resistors 64 and 65. Furthermore, the low-potential side of the power supply of the RS flip-flop 68 is voltage Vout, not the midpoint voltage Vm.

[0051] <Configuration of the gate drive circuit> Figure 8 shows an example of the details of the gate drive circuit 12a shown in Figure 2. As shown in Figure 8, the gate drive circuit 12a comprises an inverter 71 and MOS transistors 72 and 73. The level-up circuit 23a shown in Figure 3 is connected to the input side of the inverter 71, and the gate drive signal GDRV from the level-up circuit 23a is input. The output side of the inverter 71 is connected to the gates of the MOS transistors 72 and 73.

[0052] The source of MOS transistor 72 is the sum of the midpoint voltage Vm of switching elements 10a and 10b and the power supply voltage VDD (Vm + VDD). The drain of MOS transistor 72 is connected to the source of MOS transistor 73. The midpoint voltage Vm of switching elements 10a and 10b is applied to the drain of MOS transistor 73. The voltage at the connection point of MOS transistor 72 and MOS transistor 73 is output as a control signal HO to the gate of switching element 10a.

[0053] The details of the configuration of gate drive circuits 12b to 12h shown in Figure 2 are substantially the same as the details of the configuration of gate drive circuit 12a shown in Figure 8, so redundant explanations will be omitted. However, the differences between gate drive circuits 12b, 12d, 12f, and 12h and gate drive circuit 23a will be explained below. In gate drive circuits 12b and 12d, the sum of the voltage Vout at the output terminal U and the power supply voltage VDD (Vout + VDD) is applied to the source of MOS transistor 72. Furthermore, the voltage Vout at the output terminal U (neutral point 15) is applied to the drain of MOS transistor 73. In gate drive circuits 12f and 12h, the sum of the voltage Vn at the low-potential side terminal (negative terminal) N and the power supply voltage VDD (Vn + VDD) is applied to the source of MOS transistor 72. Furthermore, the voltage Vn at the low-potential side terminal (negative terminal) N is applied to the drain of MOS transistor 73.

[0054] <Control circuit configuration> Figure 9 shows an example of the details of the control circuit 21a shown in Figure 3. The control circuit 21a operates at a power supply voltage VCC that is different from the power supply voltage VDD of the gate drive circuit 12a. As shown in Figure 9, the control circuit 21a comprises a filter 80, an AND gate 84, and an inverter 85. The filter 80 comprises a Schmitt trigger circuit 81, a resistor 82, and a capacitor 83. The input terminal HIN(U) is connected to the input side of the Schmitt trigger circuit 81, and the input signal IN from the input terminal HIN(U) is input. One end of the resistor 82 is connected to the output side of the Schmitt trigger circuit 81. One end of the capacitor 83 is connected to the other end of the resistor 82. The low-potential terminal N is connected to the other end of the capacitor 83 and the low-potential side of the power supply for the control circuit 21a.

[0055] The level-down circuit 22a shown in Figure 3 is connected to the input side of the inverter 85, and the signal ALM' from the level-down circuit 22a is input. The connection point of the resistor 82 and the capacitor 83 is connected to one side of the input side of the AND circuit 84. The output side of the inverter 85 is connected to the other side of the input side of the AND circuit 84. The level-up circuits 23a and 23b shown in Figure 3 are connected to the output side of the AND circuit 84. The AND circuit 84 outputs the signal OUT to the level-up circuits 23a and 23b.

[0056] The details of the configurations of control circuits 21b to 21d shown in Figure 3 are substantially the same as the details of the configuration of control circuit 21a shown in Figure 9, so redundant explanations will be omitted.

[0057] <Fault detection method> In the following, with reference to Figure 2, we will consider the case where the switching elements 10a to 10d of the upper arm 101 are functioning normally, and the case where an abnormality occurs in the switching elements 10a to 10d of the upper arm 101 due to cosmic rays or the like.

[0058] First, if all of the switching elements 10a to 10d of the upper arm 101 are functioning correctly, the voltage applied to the upper arm 101 is divided almost equally among the switching elements 10a, 10b and 10c, 10d that constitute each unit (10a, 10b) and (10c, 10d). Therefore, the midpoint voltage SENSE of the switching elements 10a, 10b and 10c, 10d is approximately half the voltage applied to each unit (10a, 10b) and (10c, 10d). For this reason, the predetermined threshold voltages Vref_low and Vref_high shown in Figure 5 may be set based on half the value of the voltage applied to each unit (10a, 10b) and (10c, 10d).

[0059] The fault detection circuit 13a compares the midpoint voltage SENSE at the midpoint of the switching elements 10a and 10b with a predetermined threshold voltage Vref_low and a predetermined threshold voltage Vref_high. If the midpoint voltage SENSE is within the range of Vref_low or higher and Vref_high or lower, the fault detection circuit 13a determines that the switching elements 10a and 10b are not faulty and are functioning normally. In this case, the fault detection circuit 13a outputs a signal ALM of "1" indicating normal operation.

[0060] The fault detection circuit 13b compares the midpoint voltage SENSE at the midpoint of the switching elements 10c and 10d with a predetermined threshold voltage Vref_low and a predetermined threshold voltage Vref_high. If the midpoint voltage SENSE is within the range of Vref_low or higher and Vref_high or lower, the fault detection circuit 13b determines that the switching elements 10c and 10d are not faulty and are functioning normally. In this case, the fault detection circuit 13b outputs a signal ALM of "1" indicating normal operation.

[0061] Next, let's consider the case where switching element 10c, one of the units (10c, 10d) of the upper arm 101 shown in Figure 2, short-circuits. When switching element 10c short-circuits, the voltage applied to the upper arm 101 is not evenly divided during the period when switching element 10d, which constitutes the same unit (10c, 10d) as switching element 10c, is turned off (off state), and the midpoint voltage SENSE rises above normal. When the midpoint voltage SENSE exceeds a predetermined threshold voltage Vref_high, the fault detection circuit 13b determines that switching element 10c has short-circuited. In other words, the fault detection circuit 13b detects that switching element 10c has short-circuited. In this case, the fault detection circuit 13b outputs an alarm to the outside by outputting a signal ALM of "0" indicating an abnormality.

[0062] The control circuit 21b and the gate drive circuit 12d may, in response to an alarm from the fault detection circuit 13b, stop driving the switching element 10d, keeping the switching element 10d permanently off and interrupting the current flowing to the switching element 10c. This prevents abnormal heat generation and ignition caused by current flowing through a faulty switching element 10c. On the other hand, the output current from the output terminal U to the load is supplied from other units (10a, 10b) within the upper arm 101. Therefore, the semiconductor device according to the first embodiment can maintain its function as a power conversion circuit without suddenly ceasing to function.

[0063] Next, let's consider the case where switching element 10d in the unit (10c, 10d) of the upper arm 101 shown in Figure 2 short-circuits. When switching element 10d short-circuits, the midpoint voltage SENSE of the unit (10c, 10d) drops below normal levels during the period when switching element 10c, which constitutes the same unit (10c, 10d) as switching element 10d, is turned off (off state). When the midpoint voltage SENSE falls below a predetermined threshold voltage Vref_low, the fault detection circuit 13b detects that switching element 10d has short-circuited. In this case, the fault detection circuit 13b outputs an alarm to the outside by outputting "0" as the signal ALM.

[0064] The control circuit 21b and the gate drive circuit 12c may, in response to an alarm from the fault detection circuit 13b, stop driving the switching element 10c, keeping the switching element 10c permanently off and interrupting the current flowing to the switching element 10d. This prevents abnormal heat generation and ignition caused by current flowing through a faulty switching element 10d. Meanwhile, the output current to the load is supplied from other units (10a, 10b) within the same upper arm 101. Therefore, the semiconductor device according to the first embodiment can maintain its function as a power conversion circuit.

[0065] Next, let's consider the case where switching element 10c, one of the units (10c, 10d) of the upper arm 101 shown in Figure 2, has an open fault. When switching element 10c has an open fault, the voltage applied to the upper arm 101 is not evenly divided during the period when switching element 10d, which constitutes the same unit (10c, 10d) as switching element 10c, is turned on (on time), and the midpoint voltage SENSE drops below the normal level. When the midpoint voltage SENSE falls below a predetermined threshold voltage Vref_low, the fault detection circuit 13b detects that switching element 10c has an open fault. In this case, the fault detection circuit 13b outputs an alarm to the outside by outputting "0" as the signal ALM.

[0066] The control circuit 21b and the gate drive circuit 12d may, in response to an alarm from the fault detection circuit 13b, stop driving the switching element 10d, keeping the switching element 10d in a permanently off state and interrupting the voltage applied to the switching element 10d. This prevents the progression of a fault caused by the application of a high voltage to the switching element 10c. Meanwhile, the output current to the load is supplied from other units (10a, 10b) within the upper arm 101. Therefore, the semiconductor device according to the first embodiment can maintain its function as a power conversion circuit.

[0067] Next, let's consider the case where switching element 10d, one of the units (10c, 10d) of the upper arm 101 shown in Figure 2, has an open fault. When switching element 10d has an open fault, the voltage applied to the upper arm 101 is not evenly divided during the period when switching element 10c, which constitutes the same unit (10c, 10d) as switching element 10d, is turned on (on time), and the midpoint voltage SENSE rises above normal. When the midpoint voltage SENSE exceeds a predetermined threshold voltage Vref_high, the fault detection circuit 13b detects that switching element 10d has an open fault. In this case, the fault detection circuit 13b outputs an alarm by outputting "0" as the signal ALM.

[0068] The control circuit 21b and the gate drive circuit 12c may, in response to an alarm from the fault detection circuit 13b, stop driving the switching element 10c, keeping the switching element 10c permanently off and interrupting the voltage applied to the switching element 10d. This prevents the progression of a fault caused by the application of high voltage to the switching element 10d. Meanwhile, the output current to the load is supplied from other units (10a, 10b) within the upper arm 101. Therefore, the semiconductor device according to the first embodiment can maintain its function as a power conversion circuit.

[0069] The operation when the switching elements 10a and 10b of the upper arm 101 and the switching elements 10e to 10h of the lower arm 102 shown in Figure 2 fail is substantially the same as the operation when the switching elements 10c and 10d of the upper arm 101 fail, as described above, so redundant explanations are omitted.

[0070] <Comparative Example> Next, a semiconductor device relating to a comparative example will be described with reference to Figure 10. In the U-phase herb bridge circuit of the semiconductor device relating to the comparative example, the upper arm is composed of one switching element 211, and the lower arm is composed of one switching element 212. FWD221 and 222 are connected in antiparallel to the switching elements. A gate drive / protection circuit 201 is connected to the switching elements 211 and 212 to drive and protect the switching elements 211 and 212.

[0071] In the V-phase herb bridge circuit, the upper arm is composed of one switching element 213, and the lower arm is composed of one switching element 214. FWD223 and 224 are connected in antiparallel to the switching elements. A gate drive / protection circuit 202 is connected to the switching elements 213 and 214 to drive and protect them.

[0072] In a W-phase herb bridge circuit, the upper arm is composed of one switching element 215, and the lower arm is composed of one switching element 216. FWD225 and 226 are connected in antiparallel to the switching elements. A gate drive / protection circuit 203 is connected to the switching elements 215 and 216 to drive and protect them.

[0073] In the comparative example semiconductor device shown in Figure 10, the upper and lower arms are composed of a single switching element 211-216. Therefore, if any of the switching elements 211-216 fail due to accidental failure caused by cosmic rays or other factors, the device will suddenly cease to function without warning. For example, if the comparative example semiconductor device is applied to electric aircraft such as drones, a sudden failure could lead to serious accidents such as crashes. Similarly, if the comparative example semiconductor device is applied to air conditioners or industrial inverters, it may not be usable when needed. For these reasons, the comparative example semiconductor device shown in Figure 10 has poor reliability in high-altitude airspace with strong cosmic ray intensity or in outer space.

[0074] In contrast, according to the semiconductor device of the first embodiment, as shown in Figure 2, the upper arm 101 comprises a plurality of switching elements 10a to 10d. The plurality of switching elements 10a to 10d are connected in series between the high-potential terminal P and the neutral point 15 to form units (10a, 10b) and (10c, 10d), and the plurality of units (10a, 10b) and (10c, 10d) are connected in parallel between the high-potential terminal P and the neutral point 15, thereby making the upper arm 101 redundant. The lower arm 102 comprises a plurality of switching elements 10e to 10h. Furthermore, multiple switching elements 10e to 10h are connected in series between the low-potential terminal N and the neutral point 15 to form units (10e, 10f) and (10g, 10h), and multiple units (10e, 10f) and (10g, 10h) are connected in parallel between the low-potential terminal N and the neutral point 15, thereby making the lower arm 102 redundant.

[0075] As a result, even if one of the multiple switching elements 10a to 10d in the upper arm 101, for example switching element 10a, fails, the normal switching elements 10c and 10d connected in parallel with the failed switching element 10a will operate, maintaining the function of the power conversion circuit and preventing sudden failure. Therefore, reliability can be easily improved at a relatively low cost without significantly changing the design of the power conversion system.

[0076] Furthermore, according to the semiconductor device of the first embodiment, as shown in Figure 2, it is equipped with fault detection circuits 13a to 13d for detecting failures of switching elements 10a to 10h. This allows for the detection of failures of switching elements 10a to 10h when they occur. Therefore, the faulty switching element 10a can be isolated from the circuit by stopping the drive of the switching element 10b which is connected in series with the faulty switching element 10a. In addition, an alarm can be output externally to notify the outside of the abnormality, allowing various countermeasures to be taken before the device completely stops functioning.

[0077] (Second Embodiment) The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figure 2, in that, as shown in Figure 11, voltage divider resistors (hereinafter referred to as "voltage divider resistors") 17a to 17h are connected in parallel to the switching elements 10a to 10h of the upper arm 101 and the lower arm 102.

[0078] The voltage divider resistors 17a to 17h may be, for example, polysilicon resistors formed on the same chip as the switching elements 10a to 10h, or they may be resistors formed on different chips than the switching elements 10a to 10h. The voltage divider resistors 17a to 17h have resistance values ​​smaller than the resistance of the switching elements 10a to 10h when they are off. The voltage divider resistors 17a to 17h may have the same resistance values ​​or different resistance values. The voltage division ratio by the voltage divider resistors 17a to 17h may be, for example, 1 / 2, but is not particularly limited.

[0079] The voltage divider resistors 17a to 17h suppress variations in the voltage applied to units (10a, 10b), (10c, 10d), (10e, 10f), and (10g, 10h) when the switching elements 10a to 10h are functioning correctly. For example, if the voltage division ratio by the voltage divider resistors 17a to 17h is 1 / 2, the voltage applied to units (10a, 10b), (10c, 10d), (10e, 10f), and (10g, 10h) can be brought close to and fixed at 1 / 2. The other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0080] Because the resistance values ​​of switching elements 10a to 10h are very large when they are in the off state, if the voltage divider resistors 17a to 17h are not connected in parallel, it is expected that the resistance values ​​will vary between the two switching elements 10a, 10b, switching elements 10c, 10d, switching elements 10e, 10f, and switching elements 10g, 10h that make up the units (10a, 10b), (10c, 10d), (10e, 10f), and (10g, 10h). If the resistance values ​​vary, it will be necessary to pre-correct the predetermined threshold values ​​Vref_low and Vref_high for the midpoint voltage used by the fault detection circuits 13a to 13d to determine whether the system is normal or faulty. In addition, there is a significant risk that the midpoint voltage will fluctuate due to long-term use.

[0081] In contrast, according to the semiconductor device of the second embodiment, as shown in Figure 11, by connecting voltage divider resistors 17a to 17h in parallel to the switching elements 10a to 10h, the midpoint voltage of the switching elements 10a to 10h is determined (fixed) by the voltage divider resistors 17a to 17h. Therefore, stable fault detection is possible without being affected by resistance variations of the switching elements 10a to 10h or fluctuations due to long-term use.

[0082] (Third embodiment) As shown in Figure 12, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that, in the units (10a, 10b), (10c, 10d), (10e, 10f), (10g, 10h) of the upper arm 101 and the lower arm 102, the resistances of the multiple (two) switching elements 10a, 10b, switching elements 10c, 10d, switching elements 10e, 10f, and switching elements 10g, 10h connected in series are different when they are off.

[0083] In the units (10a, 10b), (10c, 10d), (10e, 10f), and (10g, 10h) of the upper arm 101 and lower arm 102, resistors 16a to 16d are connected in parallel to the lower (low potential side) switching elements 10b, 10d, 10f, and 10h of the multiple (two) switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h connected in series, respectively.

[0084] Alternatively, instead of connecting resistors 16a to 16d in parallel to the lower (low potential) switching elements 10b, 10d, 10f, and 10h, a configuration may be used in which resistors are connected in parallel to the upper (high potential) switching elements 10a, 10c, 10e, and 10g.

[0085] The resistors 16a to 16d shown in Figure 12 may be polysilicon resistors formed on the same chip as the switching elements 10b, 10d, 10f, and 10h, or they may be external resistors formed on a different chip from the switching elements 10b, 10d, 10f, and 10h. The resistance values ​​of resistors 16a to 16d are, for example, about 10 MΩ, but are not particularly limited. The other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0086] Figure 13 is a graph comparing the voltages applied to the upper and lower switching elements (MOSFETs) of a single unit when the arm is off, in the case of an embodiment of the semiconductor device according to the third embodiment and the case where a resistor is not provided in parallel with the switching element as shown in Figure 2 (the example in Figure 2). In the embodiment, a resistor is connected in parallel with the lower MOSFET. In the example in Figure 2, no resistors are connected in parallel with either the upper or lower MOSFET.

[0087] As shown on the left side of Figure 13, in the example of Figure 2, the voltages applied to the upper and lower MOSFETs are equal. On the other hand, as shown on the right side of Figure 13, the voltage applied to the lower MOSFET is smaller than the voltage applied to the upper MOSFET. For example, if the resistance values ​​of the upper and lower MOSFETs in the off state are 1000 MΩ, and the resistance value of the resistor connected in parallel to the lower MOSFET is 10 MΩ, then the ratio of the voltages applied to the upper and lower MOSFETs is approximately 100:1.

[0088] Figure 14 shows schematic cross-sections of the upper and lower switching elements 10a and 10b of the semiconductor device according to the example in Figure 2, as well as the extent of the depletion layers d1 and d2 when the switching elements 10a and 10b are in the off state, and the carriers 9a and 9b generated when cosmic rays R are simultaneously incident on the upper and lower switching elements 10a and 10b.

[0089] The semiconductor device shown in the example in Figure 2 has a configuration in which no resistors are connected in parallel to either the upper or lower switching elements 10a and 10b. The upper switching element 10a is n - A drift layer 3a of type p, a p-type base region 4a provided on the upper side of the drift layer 3a, and an n-type base region 4a provided on the upper side of the base region 4a + A source region 5a of type n provided on the lower surface side of the drift layer 3a + It has a drain region 8a of a certain type. Above the base region 4a, which is sandwiched between the source region 5a and the drift layer 3a, a gate electrode 7a is provided via a gate insulating layer (not shown). Source electrodes 6a are provided on the upper surfaces of the source region 5a and the base region 4a.

[0090] The lower switching element 10b is n - A drift layer 3b of type p, a p-shaped base region 4b provided on the upper side of the drift layer 3b, and an n-shaped base region 4b provided on the upper side of the base region 4b + The source region 5b of type n is provided on the lower side of the drift layer 3b + It has a drain region 8b of a certain type. Above the base region 4b, which is sandwiched between the source region 5b and the drift layer 3b, a gate electrode 7b is provided via a gate insulating layer (not shown). Source electrodes 6b are provided on the upper surfaces of the source region 5b and the base region 4b. The source electrode 6a of the switching element 10a is electrically connected to the drain region 8b.

[0091] In the semiconductor device shown in the example in Figure 2, depletion layers d1 and d2 extend in both the upper and lower switching elements 10a and 10b. When cosmic rays R pass through the depletion layers d1 and d2, carriers 9a and 9b are excited. Excited carriers 9a and 9b themselves become current sources, and can also induce parasitic bipolar operation and avalanche breakdown by disrupting the electric field balance. In the semiconductor device shown in the example in Figure 2, a relatively large number of carriers 9a and 9b are generated in both the upper and lower switching elements 10a and 10b upon incidence of cosmic rays R. As a result, the current I1 passing through the upper and lower switching elements 10a and 10b is large, making failures due to Joule heating more likely.

[0092] In high-altitude airspace and outer space where cosmic ray intensity is high, the possibility of cosmic rays entering both the upper and lower switching elements 10a and 10b almost simultaneously cannot be ignored. Therefore, if the cosmic ray tolerance of the switching elements 10a and 10b is low, there is a risk that the switching elements 10a and 10b will fail simultaneously, resulting in a loss of function as a power conversion circuit.

[0093] On the other hand, Figure 15 shows schematic cross-sections of the upper and lower switching elements 10a and 10b of the semiconductor device according to the third embodiment, as well as the extent of the depletion layers d1 and d2 when the switching elements 10a and 10b are in the off state, and the carriers 9a and 9b generated when cosmic rays R are simultaneously incident on the upper and lower switching elements 10a and 10b.

[0094] The semiconductor device according to the third embodiment has a configuration in which a resistor 16a (see Figure 12) is connected in parallel to the lower switching element 10b. The configuration of the switching elements 10a and 10b themselves is the same as that of the semiconductor device according to the example in Figure 2 shown in Figure 14.

[0095] In the semiconductor device according to the third embodiment, due to the difference in voltage applied to the upper and lower switching elements 10a and 10b, the depletion layer d1 of the upper switching element 10a is wider than that of the semiconductor device according to the example in Figure 2 shown in Figure 14, but the depletion layer d2 of the lower switching element 10b is narrower than that of the semiconductor device according to the example in Figure 2 shown in Figure 14. Therefore, when cosmic rays R are incident on the upper and lower switching elements 10a and 10b simultaneously, the carriers 9a generated in the upper switching element 10a are larger than those of the semiconductor device according to the example in Figure 2 shown in Figure 14, but the carriers 9b generated in the lower switching element 10b are narrower than those of the semiconductor device according to the example in Figure 2 shown in Figure 14. Therefore, the current I2 passing through the upper and lower switching elements 10a and 10b is rate-limited by the amount of carriers generated in the lower switching element 10b, and is narrower than that of the semiconductor device according to the example in Figure 2 shown in Figure 14. Thus, failure of the switching elements 10a and 10b due to cosmic rays is less likely to occur.

[0096] According to the semiconductor device of the third embodiment, in the units (10a, 10b), (10c, 10d), (10e, 10f), (10g, 10h) of the upper arm 101 and the lower arm 102, the resistance of multiple (two) switching elements 10a, 10b, switching elements 10c, 10d, switching elements 10e, 10f, and switching elements 10g, 10h connected in series is made different from each other when they are off, thereby improving the cosmic ray withstand capability.

[0097] (Fourth Embodiment) The semiconductor device according to the fourth embodiment is similar to the semiconductor device according to the third embodiment shown in Figure 12 in that the resistances of the multiple (two) switching elements 10a, 10b, switching elements 10c, 10d, switching elements 10e, 10f, and switching elements 10g, 10h, which are connected in series within the upper arm 101 and lower arm 102, are different when they are off. However, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the third embodiment in that it does not have resistors 16a to 16d connected in parallel with the switching elements 10b, 10d, 10f, and 10h of the semiconductor device according to the third embodiment shown in Figure 12, and has the same configuration as the semiconductor device according to the first embodiment shown in Figure 2.

[0098] In other words, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the third embodiment in that the channel widths of the switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h, which are connected in series in the upper arm 101 and the lower arm 102, are made different from each other.

[0099] For example, the channel widths of the lower switching elements 10b, 10d, 10f, and 10h are made larger than the channel widths of the upper switching elements 10a, 10c, 10e, and 10g. Alternatively, the channel widths of the upper switching elements 10a, 10c, 10e, and 10g may be made larger than the channel widths of the lower switching elements 10b, 10d, 10f, and 10h. The other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the third embodiment, so redundant explanations are omitted.

[0100] According to the semiconductor device of the fourth embodiment, by making the channel width of one of the series-connected switching elements 10a, 10b, switching elements 10c, 10d, switching elements 10e, 10f, and switching elements 10g, 10h larger than that of the other element, the resistance value of one element when it is off can be made smaller than that of the other element. As a result, when the upper arm 101 and the lower arm 102 are off, the voltage applied to the element with a relatively large channel width can be made smaller than the voltage applied to the element with a relatively small channel width, thereby improving cosmic ray withstand capability.

[0101] As a method for making the resistances of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h different when they are off, instead of making their channel widths different, the on-resistances of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h may be made different.

[0102] Furthermore, as a method for making the resistances of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h different when they are off, the drift resistances can be made different by making the impurity concentrations of the drift layers 3a, 3b of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h different.

[0103] Furthermore, as a method for making the resistances of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h different when they are off, the drift resistances can be made different by making the thicknesses of the drift layers 3a, 3b of the series-connected switching elements 10a, 10b, 10c, 10d, 10e, 10f, and 10g, 10h different.

[0104] (Other embodiments) As described above, this disclosure is based on the First to Fourth Embodiments, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0105] For example, in the semiconductor device according to the first to fourth embodiments, the upper arm 101 units (10a, 10b) and (10c, 10d) are illustrated as being configured by connecting two switching elements 10a, 10b and two switching elements 10c, 10d in series, but they may also be configured by connecting three or more switching elements in series. Similarly, the lower arm 102 units (10e, 10f) and (10g, 10h) are illustrated as being configured by connecting two switching elements 10e, 10f and two switching elements 10g, 10h in series, but they may also be configured by connecting three or more switching elements in series. By increasing the number of series connections of switching elements in the upper arm 101 and lower arm 102 units, redundancy can be increased and reliability can be improved.

[0106] In the semiconductor device according to the first to fourth embodiments, when the upper arm 101 and lower arm 102 units are configured by connecting three or more switching elements in series, a fault detection circuit may be connected to each of the midpoints of adjacent switching elements. Alternatively, in each unit, one fault detection circuit may be connected to any of the midpoints of multiple switching elements. Furthermore, in the semiconductor device according to the third and fourth embodiments, when the upper arm 101 and lower arm 102 units are configured by connecting three or more switching elements in series, the resistance value of at least one of the three or more switching elements when it is in the off state may be made different from that of the other switching elements.

[0107] Furthermore, in the semiconductor device according to the first to fourth embodiments, the upper arm 101 is shown as an example where two units (10a, 10b) and (10c, 10d) are connected in parallel, but it may also be configured with three or more units connected in parallel. Similarly, the lower arm 102 is shown as an example where two units (10e, 10f) and (10g, 10h) are connected in parallel, but it may also be configured with three or more units connected in parallel. By increasing the number of units connected in parallel in the upper arm 101 and the lower arm 102, redundancy can be increased and reliability can be improved.

[0108] Furthermore, the semiconductor devices according to the first to fourth embodiments may further include other elements such as protection circuits to protect the switching elements 10a to 10h from overcurrent and high temperatures.

[0109] Furthermore, the configurations disclosed in the first to fourth embodiments can be combined as appropriate, within a non-contradictory scope. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0110] 1u, 1v, 1w... Herb bridge circuit 2u, 2v, 2w... Level shift / control circuit 3a, 3b... Drift layers 4a, 4b... Base region 5a, 5b... Source area 6a, 6b... Source electrodes 7a, 7b… Gate gate 8a, 8b... Drain region 9a, 9b… Career 10a~10h... Switching element 12a~12h...Gate drive circuit 13a~13d...Fault detection circuit 14a~14d...Midpoints that are connection points 15…Connection point (neutral point) 16a~16d,17a~17h...Resistance 21a~21d...Control circuits 22a, 22b... Level-down circuits 22c, 22d... Inverter circuits 23a~23f...Level-up circuit 31-34... Resistance 35, 36… Operational amplifiers 37...XOR circuit 51…MOS transistor 52... Resistance 61... Pulse Generator 62, 63…MOS transistors 64, 65… Resistance 66, 67… Inverter 68...RS flip-flop 71…Inverter 72, 73…MOS transistors 80... Filter 81...Schmitt trigger circuit 82... Resistance 83…Capacity 84... AND gate 85... Inverter 101... Upper Arm 102... Lower arm 201-203...Gate drive / protection circuits 211~216... Switching elements HIN(U), HIN(V), HIN(W)... Input terminals I1,I2…Current LIN(U), LIN(V), LIN(W)... Input terminals N…Low potential side terminal (negative terminal) P... High-potential terminal (positive terminal) U, V, W… Output terminals d1,d2…depletion layer

Claims

1. High-potential side terminal, Low-voltage side terminal and An upper arm and a lower arm, each having a switching element, are connected between the high-potential terminal and the low-potential terminal. A gate drive circuit for driving the switching element, Equipped with, Multiple switching elements of the upper arm are connected in series between the high-potential terminal and the neutral point between the upper arm and the lower arm to form a first unit, and multiple first units are connected in parallel between the high-potential terminal and the neutral point. Multiple switching elements of the lower arm are connected in series between the low-potential terminal and the neutral point to form a second unit, and multiple second units are connected in parallel between the low-potential terminal and the neutral point. Semiconductor equipment.

2. Each of the upper and lower arms further comprises a fault detection circuit connected to the connection point of the adjacent series-connected switching elements. The semiconductor device according to claim 1.

3. The fault detection circuit detects that the higher-potential switching element among the adjacent switching elements has failed when the voltage at the connection point exceeds a predetermined threshold while the adjacent switching elements are turned off. The semiconductor device according to claim 2.

4. The fault detection circuit detects that the lower-potential switching element among the adjacent switching elements has failed when the voltage at the connection point is below a predetermined threshold when the adjacent switching elements are turned off. The semiconductor device according to claim 2.

5. The fault detection circuit detects that the lower-potential switching element among the adjacent switching elements has failed when the voltage at the connection point exceeds a predetermined threshold while the adjacent switching elements are turned on. The semiconductor device according to claim 2.

6. The fault detection circuit detects that the higher-potential switching element among the adjacent switching elements has failed when the voltage at the connection point is below a predetermined threshold while the adjacent switching elements are turned on. The semiconductor device according to claim 2.

7. If the fault detection circuit detects that any of the adjacent switching elements has failed, it will output an alarm. The semiconductor device according to claim 2.

8. The gate drive circuit, in response to the alarm, stops driving the switching element that is connected in series with the switching element that has been detected to be faulty. The semiconductor device according to claim 7.

9. The switching element further comprises a resistor connected in parallel with the switching element. The semiconductor device according to claim 1 or 2.

10. In each of the upper and lower arms, at least two of the series-connected switching elements have different resistance values ​​when turned off. The semiconductor device according to claim 1 or 2.

11. A resistor is connected in parallel to at least one of at least two of the series-connected switching elements. The semiconductor device according to claim 10.

12. At least two of the series-connected switching elements have different channel widths. The semiconductor device according to claim 10.

13. At least two of the series-connected switching elements have drift layers with different impurity concentrations. The semiconductor device according to claim 10.

14. At least two of the series-connected switching elements have drift layers of different thicknesses. The semiconductor device according to claim 10.

Images