Semiconductor equipment

Abstract

The objective is to provide a semiconductor device. [Solution] According to the embodiment, the semiconductor substrate comprises a first diffusion layer region and a second diffusion layer region, a first gate insulating film having at least a portion facing the region between the first diffusion layer region and the second diffusion layer region, a first gate electrode, a first silicide layer and a second silicide layer, a second transistor having a third diffusion layer region and a fourth diffusion layer region, a second gate insulating film, a second gate electrode, a third silicide layer and a fourth silicide layer, and an element isolation portion embedded in the semiconductor substrate to separate the first transistor and the second transistor from their surrounding region, wherein at least one of the first transistor and the second transistor is formed in a recess having a bottom surface at a position lower than the interface position between the element isolation portion formed in the semiconductor substrate and the semiconductor substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices including a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate are known. Further, semiconductor devices including two types of transistors, a high-voltage transistor that operates at a relatively high voltage and a low-voltage transistor that operates at a relatively low voltage, are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device capable of improving the on-current of a low-voltage transistor and suppressing the junction leakage current of a high-voltage transistor.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment has a semiconductor substrate. The semiconductor device has a first diffusion layer region and a second diffusion layer region provided on the semiconductor substrate. The semiconductor device has a first gate insulating film provided on the semiconductor substrate and at least a part of which faces the region between the first diffusion layer region and the second diffusion layer region. The semiconductor device has a first gate electrode located on the opposite side of the semiconductor substrate with respect to the first gate insulating film. The semiconductor device has a first silicide layer embedded on the upper surface of the first diffusion layer region and a second silicide layer embedded on the upper surface of the second diffusion layer region. The first transistor has the first diffusion layer region, the second diffusion layer region, the first gate insulating film, the first gate electrode, the first silicide layer, and the second silicide layer. The semiconductor device has a third diffusion layer region and a fourth diffusion layer region provided on the semiconductor substrate. The semiconductor device has a second gate insulating film provided on the semiconductor substrate, at least a portion of which faces the region between the third diffusion layer region and the fourth diffusion layer region. The semiconductor device has a second gate electrode located on the opposite side of the semiconductor substrate from the second gate insulating film. The semiconductor device has a third silicide layer embedded on the upper surface of the third diffusion layer region and a fourth silicide layer embedded on the upper surface of the fourth diffusion layer region. The second transistor has the third diffusion layer region and the fourth diffusion layer region, the second gate insulating film, the second gate electrode, the third silicide layer and the fourth silicide layer. The semiconductor device has an element isolation portion embedded in the semiconductor substrate that separates the first transistor and the second transistor from their surrounding region. At least one of the first transistor and the second transistor is formed in a recess having a bottom surface located at a position lower than the interface between the element isolation portion formed in the semiconductor substrate and the semiconductor substrate. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view showing an example configuration of a semiconductor substrate and low-voltage transistors and high-voltage transistors applied to the semiconductor device of the first embodiment. [Figure 3] Figure 3 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a low-voltage transistor according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing an example configuration of a semiconductor substrate and a low-voltage transistor according to the first embodiment. [Figure 5] Figure 5 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a high-voltage transistor according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view showing an example configuration of a semiconductor substrate and a high-voltage transistor according to the first embodiment. [Figure 7]Figure 7 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a low-voltage transistor according to Comparative Example 1. [Figure 8] Figure 8 is a cross-sectional view showing an example configuration of a semiconductor substrate and a low-voltage transistor according to Comparative Example 1. [Figure 9] Figure 9 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a high-voltage transistor according to Comparative Example 1. [Figure 10] Figure 10 is a cross-sectional view showing an example configuration of a semiconductor substrate and a high-voltage transistor related to Comparative Example 1. [Figure 11] Figure 11 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a low-voltage transistor according to Comparative Example 2. [Figure 12] Figure 12 is a cross-sectional view showing an example configuration of a semiconductor substrate and a low-voltage transistor according to Comparative Example 2. [Figure 13] Figure 13 is a plan view showing the positional relationship between the source region, drain region, and silicide layer of a high-voltage transistor related to Comparative Example 2. [Figure 14] Figure 14 is a cross-sectional view showing an example configuration of a semiconductor substrate and a high-voltage transistor related to Comparative Example 2. [Figure 15] Figure 15 is a cross-sectional view showing a conventional transistor structure. [Figure 16] Figure 16 is a cross-sectional view illustrating the problems encountered when manufacturing a conventional transistor structure. [Figure 17] Figure 17 is a cross-sectional view showing an example configuration of a semiconductor substrate and low-voltage transistors and high-voltage transistors according to the second embodiment. [Figure 18] Figure 18 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] Figure 19 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 20] Figure 20 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 21] Figure 21 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 22] FIG. 22 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 23] FIG. 23 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment. MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. And redundant descriptions of these components may be omitted. "Parallel", "orthogonal", or "the same" may include cases where they are "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection and may include electrical connection. That is, "connection" is not limited to the case where a plurality of elements are directly connected, and may include the case where a plurality of elements are connected with another element interposed therebetween. "Facing" means that two members overlap when viewed in a certain direction, and may include the case where another member exists between the two members.

[0008] First, the X direction, Y direction, and Z direction are defined. The X direction and Y direction are directions along the surface of the semiconductor substrate 2 described later (see FIG. 1). The X direction is the direction from the first source region 11 to the first drain region 12 in the first transistor 5 described later (see FIG. 2), and is the direction from the second source region 21 to the second drain region 22 in the second transistor 6 described later (see FIG. 2). The Y direction intersects (for example, is orthogonal to) the X direction. The Z direction intersects (for example, is orthogonal to) the X direction and Y direction. The Z direction is the thickness direction of the semiconductor substrate 2 (see FIG. 2). In the following description, the side where the transistor Tr is located with respect to the semiconductor substrate 2 may be referred to as "upper", and the opposite side may be referred to as "lower". However, these expressions are for convenience and do not define the direction of gravity.

[0009] (First Embodiment) <1. Configuration Example of Semiconductor Device> Figure 1 is a cross-sectional view showing an example configuration of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is a semiconductor memory device such as a NAND flash memory. The semiconductor device 1 includes, for example, an array chip AC and a circuit chip CC.

[0010] The array chip AC is a chip capable of storing information. The array chip AC includes, for example, a stack LB, multiple memory pillars MP, multiple source lines SL, and multiple bit lines BL. The stack LB includes multiple word lines WL and multiple insulating layers IL. The multiple word lines WL and the multiple insulating layers IL are stacked alternately one layer at a time in the Z direction.

[0011] Multiple memory pillars MP extend in the Z direction, penetrating the stack LB. Each memory pillar MP includes an insulating layer, a channel layer, a tunnel insulating film, a charge storage layer, and a block insulating film, extending from the center outward. One end of each memory pillar MP is connected to the source line SL. The other end of each memory pillar MP is connected to the bit line BL. Memory cell transistors MC are formed at the intersections of each memory pillar MP and each word line WL. The memory cell transistors MC are memory elements capable of storing information by accumulating charge.

[0012] Circuit chip CC is a control circuit that controls the operation of array chip AC. Circuit chip CC comprises, for example, a semiconductor substrate 2, a plurality of transistors Tr, and a plurality of wiring L. The plurality of transistors Tr are provided on the semiconductor substrate 2. The wiring L connects the transistors Tr to array chip AC.

[0013] <2. Semiconductor Substrate and Transistor Configuration> Next, we will describe in detail the configuration of the semiconductor substrate 2 and the transistor Tr. <2.1 Semiconductor Substrates> Figure 2 is a cross-sectional view showing an example configuration of the semiconductor substrate 2 and the first transistor 5 and second transistor 6, which will be described later. The semiconductor substrate 2 is, for example, a silicon substrate containing single-crystal silicon. One or more element isolation insulating regions 3 (hereinafter referred to as "element isolation regions 3") made of an insulator such as silicon oxide are provided in a part of the upper layer of the semiconductor substrate 2. The element isolation regions 3 are provided along the X direction, at positions that sandwich the first transistor 5 and the second transistor 6, which will be described later. The semiconductor substrate 2 has a first substrate portion 7 and a second substrate portion 8 separated in the X direction via two adjacent element isolation regions 3. The first transistor 5 is formed on the first substrate portion 7, and the second transistor 6 is formed on the second substrate portion 8. Note that the cross-section shown in Figure 2 only shows the upper layer region near the surface of the semiconductor substrate 2, and the element isolation section 3 is formed in a slightly tapering manner from the surface of the semiconductor substrate 2 in the depth direction (-Z direction) down to a predetermined depth of the semiconductor substrate 2. In Figure 2, the bottom side of the element isolation section 3 is omitted, and only the upper side of the element isolation section 3 and the formation regions of the first transistor 5 and the second transistor 6 formed between them are shown. Also, in Figure 1, the element isolation section 3 is omitted, and in Figure 1, the first transistor 5 and the second transistor 6 are not distinguished and are simply referred to as transistor Tr, showing only an overview of the positional relationship of each transistor Tr.

[0014] In the semiconductor device 1 shown in Figure 1, as shown in detail in Figure 2, a structure may be adopted in which a first transistor 5 and a second transistor 6 are arranged adjacent to each other in the X direction on the surface portion of the semiconductor substrate 2 via an element isolation portion 3. In this embodiment, two element isolation sections 3 are formed between the first transistor 5 and the second transistor 6, spaced apart in the X direction. The element isolation sections 3 provided on both sides of the first transistor 5 in the X direction insulate and isolate the region in which the first transistor 5 is formed from its surrounding region. The element isolation sections 3 provided on both sides of the second transistor 6 in the X direction insulate and isolate the region in which the second transistor 6 is formed from its surrounding region. A third substrate portion 9 is formed between two element isolation portions 3 spaced apart along the X direction between the first transistor 5 and the second transistor 6, and a diffusion layer 9A is formed on the upper part of the third substrate portion 9. The diffusion layer 9A is formed from impurities such as As, P, and B, and is provided for use as a resistive element.

[0015] The first substrate section 7 and the second substrate section 8 are the base portions on which the transistor Tr is installed. The first substrate section 7 and the second substrate section 8 have well regions with different polarity (different conductivity types) than the source region and drain region of the transistor Tr, which will be described later, in at least a portion of the region where the transistor Tr is installed. The element isolation unit 3 is an isolation unit that electrically isolates a plurality of transistors Tr provided on the semiconductor substrate 2. On the semiconductor substrate 2, the element isolation unit 3 is provided so as to surround the activation region of each transistor Tr.

[0016] <2.2 Transistors> The multiple transistors Tr include a first transistor 5 (see Figure 2) and a second transistor 6 (see Figure 2). Each of the first transistor 5 and the second transistor 6 is a field-effect transistor, such as a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor).

[0017] The second transistor 6 is a high-voltage transistor that outputs a relatively high voltage (e.g., a voltage of 20V or more) in the semiconductor device 1, and the first transistor 5 is a low-voltage transistor that outputs a relatively low voltage (e.g., 10V or less). As explained earlier, the transistors Tr shown in Figure 1 are simply referred to as transistors Tr without distinguishing between the first transistor 5 and the second transistor 6, and only a general overview is depicted. Among the multiple transistors Tr, some transistors Tr are the first transistor (low voltage transistor) 5, and some transistors Tr are the second transistor (high voltage transistor) 6. Figure 2 shows the structure when the first transistor 5 and the second transistor 6 are placed adjacent to each other along the X direction on the semiconductor substrate 2.

[0018] <First Transistor> The first transistor 5 includes, for example, a first gate electrode 10, a first source region 11, a first drain region 12, a first gate insulating film 13, a first diffusion layer-side silicide layer (hereinafter abbreviated as the first silicide layer) 15, a second diffusion layer-side silicide layer (hereinafter abbreviated as the second silicide layer) 16, a work function metal layer 17, a ferroelectric layer 18, and an insulating sidewall 19. The first source region 11 is an example of the "first diffusion layer region". The first drain region 12 is an example of the "second diffusion layer region". However, the first drain region 12 may correspond to an example of the "first diffusion layer region", and the first source region 11 may correspond to an example of the "second diffusion layer region".

[0019] The first transistor 5 is provided between element isolation sections 3, 3 formed on both sides of the first transistor 5 in the X direction. Between two adjacent element isolation sections 3 in the X direction, a recess (first recess) 7A is formed on the upper surface of the first substrate section 7. The bottom surface 7a of the recess 7A is formed to be one step lower than the upper surface of the element isolation section 3. In the recess 7A, a sloping section 7B is formed in the portion close to the element isolation section 3, which gradually reduces the depth of the recess 7A. The top of the sloping section 7B is at approximately the same height as the upper surface of the element isolation section 3, and the top of the sloping section 7B is continuous with the upper surface of the element isolation section 3. The portion where the top of the sloping section 7B contacts the upper surface of the element isolation section 3 is the interface position B1 between the surface of the semiconductor substrate 2 and the element isolation section 3. Here, the recess 7A can be described as a recess having a bottom surface 7a that is lower in the Z direction than the interface position B1.

[0020] As shown in Figure 2, a first gate insulating film 13 of a predetermined width in the X direction is arranged on the central side of the bottom surface (surface of the first substrate portion 7) 7a of the recess 7A. A first silicide layer 15 and a second silicide layer 16 are arranged on both sides of these along the X direction. A first contact electrode 35 is provided connected to the first silicide layer 15, and a second contact electrode 36 is provided connected to the second silicide layer 16.

[0021] The first gate electrode 10 is provided on the side opposite to the semiconductor substrate 2 relative to the first gate insulating film 13, which will be described later. The first gate electrode 10 is located above the bottom surface 7a of the recess 7A in the first substrate portion 7. In the X direction, the first gate electrode 10 is located between the first source region 11 and the first drain region 12. The first gate electrode 10 is made of a metal such as tungsten as an example, but it may also be a semiconductor layer such as polysilicon or a laminated structure of a semiconductor layer and a metal layer.

[0022] The first source region 11 and the first drain region 12 are formed to a predetermined depth as part of the bottom surface 7a of the recess 7A in the first substrate portion 7. For example, the first source region 11 and the first drain region 12 are formed by doping impurities onto the upper part of the first substrate portion 7 (the bottom surface 7a and the inclined portion 7B of the recess 7A). The first source region 11 and the first drain region 12 are separated from each other in the X direction. Between the first source region 11 and the first drain region 12, which are separated in the X direction, the first gate insulating film 13 is provided on the bottom surface 7a of the recess 7A of the first substrate portion 7. In this embodiment, each of the first source region 11 and the first drain region 12 is n + p-type semiconductor or p-type semiconductor (e.g., p + Includes (type semiconductor).

[0023] The depth of the recess 7A (depth along the Z direction) is approximately 1 / 10 to 2 / 10 of the maximum depth (maximum depth along the Z direction) of the first source region 11 or the first drain region 12. For example, if the maximum depth of the first source region 11 is approximately 100 nm, the depth of the recess 7A can be approximately 10 to 20 nm.

[0024] The first gate insulating film 13 is formed on the bottom surface 7a of the recess 7A in the first substrate portion 7. At least a portion of the first gate insulating film 13 is located between the first gate electrode 10 and the bottom surface 7a of the recess 7A. The first gate insulating film 13 is formed of, for example, a silicon oxide film. In this embodiment, the thickness of the first gate insulating film 13 in the Z direction is smaller than the thickness of the second gate insulating film 23 in the Z direction, which will be described later. The maximum voltage of the current flowing through the first transistor 5 is smaller than the maximum voltage of the current flowing through the second transistor 6. For this reason, the first transistor 5 can be called a low-voltage transistor and the second transistor 6 can be called a high-voltage transistor.

[0025] The first silicide layer 15 is formed on the surface side of the first source region 11 and is thinner than the first source region 11. The first silicide layer 15 includes, for example, a nickel-platinum silicide layer (NiPtSi layer). The first silicide layer 15 is formed, for example, by supplying metallic elements such as nickel (Ni) and platinum (Pt) to the first source region 11 and thermally diffusing these metallic elements.

[0026] The second silicide layer 16 is formed on the surface side of the first drain region 12, and is thinner than the first drain region 12. The second silicide layer 16 includes, for example, a nickel-platinum silicide layer (NiPtSi layer). The second silicide layer 16 is formed, for example, by supplying metallic elements such as nickel (Ni) and platinum (Pt) to the first drain region 12 and thermally diffusing these metallic elements. The first silicide layer 15 and the second silicide layer 16 are separated from each other in the X direction. Between the first silicide layer 15 and the second silicide layer 16, which are separated in the X direction, the first gate insulating film 13 is provided on the bottom surface 7a of the recess 7A.

[0027] The insulating sidewall 19 is formed of, for example, a silicon nitride film or a silicon oxide film. The insulating sidewall 19 is in close contact with the ferroelectric layer 18 on the outside of the ferroelectric layer 18 as viewed from the center of the first transistor 5 (center of the first gate electrode 10), and covers the side of the first gate electrode 10. The bottom of the insulating sidewall 19 covers the bottom side of the ferroelectric layer 18, a part of the first source region 11, and a part of the first drain region 12. There are no particular restrictions on the height of the insulating sidewall 19 in the Z direction. The insulating sidewall 19 may be formed to a height that covers a part or all of the side surface of the first gate electrode 10.

[0028] In this embodiment, the -X-direction end of the first source region 11 reaches one side surface of the element isolation portion 3 near that end, and the +X-direction end of the first source region 11 is in contact with the -X-direction end of the first gate insulating film 13. The -X-direction end of the first drain region 12 is in contact with the +X-direction end of the first gate insulating film 13, and the +X-direction end of the first drain region 12 reaches one side surface of the element isolation portion 3 near that end.

[0029] <Second transistor> The second transistor 6 includes, for example, a second gate electrode 20, a second source region 21, a second drain region 22, a second gate insulating film 23, a third diffusion layer side silicide layer (hereinafter referred to as the third silicide layer) 25, a fourth diffusion layer side silicide layer (hereinafter referred to as the fourth silicide layer) 26, a work function metal layer 27, a ferroelectric layer 28, and an insulating sidewall 29. The second source region 21 is an example of the "third diffusion layer region". The second drain region 22 is an example of the "fourth diffusion layer region". However, the second drain region 22 may correspond to an example of the "third diffusion layer region", and the second source region 21 may correspond to an example of the "fourth diffusion layer region".

[0030] The second transistor 6 is located between element isolation sections 3, 3 formed on both sides of the second transistor 6 in the X direction. Between two adjacent element isolation sections 3 in the X direction, a recess (second recess) 8A is formed on the upper surface of the second substrate section 8. The bottom surface 8a of the recess 8A is formed to be one step lower than the upper surface of the element isolation section 3. In the recess 8A, a sloping section 8B is formed in the portion adjacent to the element isolation section 3, which gradually reduces the depth of the recess 8A. The top of the sloping section 8B is at approximately the same height as the upper surface of the element isolation section 3, and the top of the sloping section 8B is continuous with the upper surface of the adjacent element isolation section 3. The portion where the top of the sloping section 8B contacts the upper surface of the element isolation section 3 is the interface position B2 between the surface of the semiconductor substrate 2 and the element isolation section 3. Here, the recess 8A can be described as a recess having a bottom surface 8a that is lower in the Z direction than the interface position B2.

[0031] As shown in Figure 2, a second gate insulating film 23 with a predetermined width in the X direction is arranged on the central side of the bottom surface 8a in the recess 8A. A third silicide layer 25 and a fourth silicide layer 26 are arranged on both sides of these along the X direction. A third contact electrode 37 is provided connected to the third silicide layer 25, and a fourth contact electrode 38 is provided connected to the fourth silicide layer 26.

[0032] The second gate electrode 20 is provided on the side opposite to the semiconductor substrate 2 with respect to the second gate insulating film 23, which will be described later. The second gate electrode 20 is located above the bottom surface 8a of the recess 8A in the second substrate portion 8. In the X direction, the second gate electrode 20 is located between the second source region 21 and the second drain region 22. The second gate electrode 20 is made of a metal such as tungsten as an example, but it may also be a semiconductor layer such as polysilicon or a laminated structure of a semiconductor and a metal layer.

[0033] The second source region 21 and the second drain region 22 are formed in the second substrate portion 8 as part of the bottom surface 8a of the recess 8A. For example, the second source region 21 and the second drain region 22 are formed by doping impurities into the upper part of the second substrate portion 8 (the bottom surface 8a and the inclined portion 8B of the recess 8A). The second source region 21 and the second drain region 22 are separated from each other in the X direction. In this embodiment, each of the second source region 21 and the second drain region 22 is n - This includes a semiconductor of type 1. However, the conductivity of the second source region 21 and the second drain region 22 is not limited to the above example and may be the same as that of the first source region 11 and the first drain region 12.

[0034] The depth of the recess 8A (depth along the Z direction) is approximately 1 / 10 to 2 / 10 of the maximum depth (maximum depth along the Z direction) of the second source region 21 or the second drain region 22. For example, if the maximum depth of the second source region 21 is approximately 100 nm, it is desirable that the depth of the recess 8A be approximately 10 to 20 nm.

[0035] The second gate insulating film 23 is formed on the bottom surface 8a of the recess 8A in the second substrate portion 8. At least a portion of the second gate insulating film 23 is located between the second gate electrode 20 and the bottom surface 8a of the second substrate portion 8. The second gate insulating film 23 is formed of, for example, a silicon oxide film. In this embodiment, the thickness of the second gate insulating film 23 in the Z direction is greater than the thickness of the first gate insulating film 13 in the Z direction described above. The maximum voltage of the current flowing through the second transistor 6 is greater than the maximum voltage of the current flowing through the first transistor 5.

[0036] The insulating sidewall 29 is formed of, for example, a silicon nitride film or a silicon oxide film. The insulating sidewall 29 is in close contact with the ferroelectric layer 28 on the outside of the ferroelectric layer 28 as viewed from the center of the second transistor 6 (center of the second gate electrode 20), and covers the side of the second gate electrode 20. The bottom of the insulating sidewall 29 covers the bottom side of the ferroelectric layer 28, a part of the second source region 21, and a part of the second drain region 22. There are no particular restrictions on the height of the insulating sidewall 29 in the Z direction. The insulating sidewall 29 may be formed to a height that covers a part or all of the side surface of the second gate electrode 20.

[0037] In this embodiment, the -X-direction end of the second source region 21 reaches one side surface of the element isolation portion 3 near that end, and the +X-direction end of the second source region 21 is in contact with the -X-direction end of the second gate insulating film 23. The -X-direction end of the second drain region 22 is in contact with the +X-direction end of the second gate insulating film 23, and the +X-direction end of the second drain region 22 reaches one side surface of the element isolation portion 3 near that end.

[0038] As shown in Figure 2, the semiconductor device 1 has an insulating layer 31 laminated on a semiconductor substrate 2. The insulating layer 31 is made of a silicon oxide film or the like. The insulating layer 31 is provided so as to cover the first transistor 5, the second transistor 6, the element isolation section 3, the first substrate section 7, the second substrate section 8, the third substrate section 9, and so on.

[0039] <Contact electrodes> Next, I will explain contact electrodes. As shown in Figure 2, a first contact electrode 35 is formed above the first silicide layer 15, penetrating the insulating layer 31 in the Z direction to reach the first silicide layer 15. The lower end of the first contact electrode 35 is electrically connected to the first silicide layer 15. The first contact electrode 35 is connected to the first silicide layer 15 at its connection end 35A. A second contact electrode 36 is formed above the second silicide layer 16, penetrating the insulating layer 31 in the Z direction and reaching the second silicide layer 16. The lower end of the second contact electrode 36 is electrically connected to the second silicide layer 16.

[0040] As shown in Figure 2, a third contact electrode 37 is formed above the third silicide layer 25, penetrating the insulating layer 31 in the Z direction and reaching the third silicide layer 25. The lower end of the third contact electrode 37 is electrically connected to the third silicide layer 25. The third contact electrode 37 is connected to the third silicide layer 25 at its connection end 37A. A fourth contact electrode 38 is formed above the fourth silicide layer 26, penetrating the insulating layer 31 in the Z direction and reaching the fourth silicide layer 26. The lower end of the fourth contact electrode 38 is electrically connected to the fourth silicide layer 26.

[0041] As shown in Figure 2, a semiconductor device 1 in which a first transistor 5 is formed in a recess 7A of the semiconductor substrate 2 and a second transistor 6 is formed in a recess 8A of the semiconductor substrate 2 can be obtained, and the effects described below can be obtained. When forming a semiconductor device 1, it is necessary to use a photolithography process to align a mask, expose the required layers at the required positions, and then process each layer into the desired shape by etching or other methods. However, since the structure of each part of the semiconductor device 1 is miniaturized, it is possible that the formation positions of each element constituting the semiconductor device 1 may be misaligned due to errors in mask alignment, etc.

[0042] For example, in the semiconductor device 1 with the structure shown in Figures 1 and 2, trench grooves are formed in the insulating layer 31 by drilling holes along the Z direction, and metal elements are supplied using these trench grooves. Silicide layers 15, 16, 25, and 26 are formed by thermal diffusion of the metal elements. However, if there are alignment errors in the mask, the trench grooves and silicide layers 15, 16, 25, and 26 may be formed at positions shifted from the intended positions. Figures 3 and 4 show an example of a state in which the formation positions of the first silicide layer 15A and the second silicide layer 16A are misaligned in the -X direction due to mask alignment errors, etc. Figures 5 and 6 show an example of a state in which the formation positions of the third silicide layer 25A and the fourth silicide layer 26A are misaligned in the -X direction due to mask alignment errors, etc.

[0043] As shown in Figures 3 to 6, when each silicide layer 15A, 16A, 25A, and 26A is formed, the first silicide layer 15A and the third silicide layer 25A on the side approaching the adjacent element isolation section 3 may be formed in a position that overlaps with the element isolation section 3. However, the structure in which the first transistor 5 is formed in recess 7A and the second transistor 6 is formed in recess 8A has superior characteristics compared to the structures of Comparative Examples 1 and 2 described below.

[0044] Figures 7 and 8 show the structure of Comparative Example 1 in which the first transistor 5 is formed without providing a recess on the upper surface (front surface) of the substrate 2, and the first silicide layer 15B and the second silicide layer 16B are misaligned in the -X direction. Figures 9 and 10 show the structure of Comparative Example 1, in which the second transistor 6 is formed without providing a recess on the upper surface (front surface) of the substrate 2, and the third silicide layer 25B and the fourth diffusion layer-side silicide layer 26B are misaligned in the -X direction. In the structure of Comparative Example 1, as shown in Figure 8, an extension portion 15a is formed on the side of the misaligned first silicide layer 15B that is close to the element isolation portion 3, extending to penetrate in the depth direction of the first source region 11. Similarly, as shown in Figure 10, an extension portion 25a is formed on the side of the misaligned third silicide layer 25B that is close to the element isolation portion 3, extending to penetrate in the depth direction of the second source region 21. In the structure of Comparative Example 1, in which recesses 7A and 8A are not formed, the extension portion 15a is formed on the first silicide layer 15B and the extension portion 25a is formed on the third silicide layer 25B for the following reasons.

[0045] In the structure in which the first transistor 5 is formed in the recess 7A shown in Figure 2, if the trench groove formed in the insulating layer 31 is formed with a displacement in the -X direction, the misaligned trench groove will be formed as shown in Figure 4. Figure 4 shows the trench groove formed when the hole-shaped trench groove 31A in which the first contact electrode 35 is formed is misaligned. At the bottom of the trench groove 31A, the first silicide layer 15A is deformed, but an extension 15b is formed that extends upward (towards the +Z direction). As shown in Figure 4, the first contact electrode 35 has a structure that straddles the top of the element isolation portion 3 and the first silicide layer 15A at its connection end 35A. The extension portion 15b is formed in the first silicide layer 15A for the following reasons.

[0046] When a hole-shaped trench groove 31A is formed in the insulating layer 31, as can be seen in Figure 2, the boundary between the element isolation portion 3 and the first source region 11 has an edge portion and a sloping portion 7B of the element isolation portion 3. The hole-shaped trench groove 31A is formed by etching the insulating layer 31. Therefore, even if the etched trench groove 31A reaches the edge portion and sloping portion 7B of the element isolation portion 3 and slightly etches the edge portion and sloping portion 7B of the element isolation portion 3, the bottom of the trench groove 31A is only formed to about the position shown in Figure 4 when the etching is complete.

[0047] In contrast, as shown in Figure 8, in a structure without a recess 7A, the upper surface (surface) of the first source region 11 and the upper surface (surface) of the element isolation portion 3 are formed flush. Therefore, even if etching is stopped at an ideal timing, the upper surface of the first source region 11 and the upper surface of the element isolation portion 3 will be etched to some extent. As a result, grooves are formed on the upper surface side of the first source region 11 and the upper surface side of the element isolation portion 3 due to etching in the depth direction, and consequently, an extension portion 15a extending in the -Z direction (downward) is formed in the first silicide layer 15B.

[0048] When an extension portion 15a extending in the depth direction is formed in the first silicide layer 15B as described above, the junction leakage current increases when current is passed from the first contact electrode 35 to the first transistor 5. In contrast, in the structure shown in Figure 4, although the extension portion 15b is formed in the +Z direction, there is a first source region 11 of sufficient thickness below the extension portion 15b, so the increase in junction leakage current can be suppressed compared to the structure shown in Figure 8.

[0049] Similarly, in the structure shown in Figure 6, if a misalignment of the mask occurs, an extension portion 25b is formed in the third silicide layer 25A. However, because it has a recess 8A, the extension portion 25b is formed to extend in the +Z direction (upward) from the second source region 21. As shown in Figure 6, the third contact electrode 37 has a structure that straddles the top of the element isolation portion 3 and the third silicide layer 25A at its connection end 37A. In contrast, in the structure without the recess 8A as shown in Figure 10, the extension portion 25a is formed to extend in the -Z direction (downward) from the upper surface of the second source region 21. As a result, although the extension portion 25b is formed in the +Z direction in the structure shown in Figure 6, there is a second source region 21 of sufficient thickness below the extension portion 25b, so it has the advantage of suppressing the increase in junction leakage current compared to the structure shown in Figure 10.

[0050] In Figures 4 and 6, we assumed a case where the first contact electrode 35 and the third contact electrode 37 are misaligned in the -X direction due to mask misalignment, but misalignment can also occur in the +X direction. If the misalignment occurs in the +X direction, the second contact electrode 36 and the fourth contact electrode 38 will also be misaligned in the +X direction. In this case, the second contact electrode 36 and the fourth contact electrode 38 will overlap with the adjacent element isolation section 3, forming an extension in the +Z direction on the second silicide layer 16A and an extension in the +Z direction on the fourth silicide layer 26A. In this case, the second contact electrode 36 will straddle the top of the adjacent element isolation section 3 and the second silicide layer 16A, and the fourth contact electrode 38 will straddle the top of the adjacent element isolation section 3 and the fourth silicide layer 26A. Thus, even when the position is shifted in the +X direction, the same effects and benefits as those described earlier for the position shift in the -X direction can be obtained.

[0051] In the structure of Comparative Example 1 shown in Figures 8 and 10, the first silicide layer 15B and the third silicide layer 25B come into contact with the element isolation section 3 due to mask misalignment, resulting in the aforementioned problem. Therefore, to avoid this problem, it is conceivable to reduce the size of the first silicide layer 15B and the third silicide layer 25B.

[0052] Figures 11 and 12 show the structure of Comparative Example 2, in which the first transistor 5 employs a configuration without recesses, and the size of the first silicide layer 15' in the X and Y directions is smaller than that of the first silicide layer 15A shown in Figures 3 and 4. Comparative Example 2 shows an example where the X-direction size of the first silicide layer 15' is set to approximately half the X-direction size of the first silicide layer 15A. Comparative Example 2 also shows an example where the Y-direction size of the first silicide layer 15' is set to approximately 60% of the Y-direction size of the first silicide layer 15A. Similarly, in Comparative Example 2, the size of the second silicide layer 16' is also formed to be small, similar to the first silicide layer 15'.

[0053] Figures 13 and 14 show the structure of Comparative Example 2, in which a second transistor 6 without a recess is adopted, and the sizes of the third silicide layer 25' in the X and Y directions are smaller than those of the third silicide layer 25A shown in Figures 5 and 6. In Comparative Example 2, as an example, the X-direction size of the third silicide layer 25' is set to about half the X-direction size of the third silicide layer 25A. In Comparative Example 2, the Y-direction size of the third silicide layer 25' is set to about 60% of the Y-direction size of the third silicide layer 25A. Similarly, in Comparative Example 2, the size of the fourth silicide layer 26' is also formed to be small, similar to the third silicide layer 25'.

[0054] If the structure of Comparative Example 2 shown in Figures 11 to 14 is adopted, even if the formation positions of the contact electrodes 35' and 37' are shifted due to mask misalignment, the possibility of the contact electrodes 35' and 37' contacting the adjacent element isolation section 3 becomes low. However, as shown in Figures 11 and 12, the area of ​​the first silicide layer 15' and the second silicide layer 16' is smaller than that of the structures shown in Figures 3 and 4, resulting in a higher contact resistance in the first transistor 5. In the structures shown in Figures 11 and 12, the on-current of the transistor 5 deteriorates compared to the structures shown in Figures 3 and 4. From the above explanation, the structure of the first embodiment shown in Figures 3 and 4 has the effect of suppressing the increase in junction leakage current compared to the structure of Comparative Example 1, and improving the on-current compared to the structure of Comparative Example 2. In other words, according to the structure of the first embodiment, even if mask misalignment occurs, the on-current of both the first transistor 5 (low-voltage transistor) and the second transistor (high-voltage transistor) 6 can be improved. Furthermore, even if mask misalignment occurs, a semiconductor device 1 can be provided that can suppress the junction leakage current of both the first transistor 5 and the second transistor.

[0055] Figure 15 shows a conventional transistor structure in which a first transistor 40 and a second transistor 41 are formed adjacent to each other along the X direction of a semiconductor substrate 45 via an element isolation section 43. In this structure, silicide layers 50 and 51, described later, are formed on the side of the first transistor 40. Note that in Figure 15, the source region and drain region formed below the silicide layers 50 and 51 are omitted from the display. In the conventional structure shown in Figure 15, a dummy gate electrode 47 made of polysilicon and an insulating layer 48 are laminated on a portion of the upper surface of a semiconductor substrate 45 via a gate insulating film 46, and insulating sidewalls 49 are formed on both sides of this laminate in the X direction. A first diffusion layer side silicide layer 50 and a second diffusion layer side silicide layer 51 are formed on the semiconductor substrate surface on both sides of the gate insulating film 46 in the X direction, and a first transistor 40 is formed. Furthermore, a dummy gate electrode 55 and an insulating layer 56 are stacked on the upper surface of the other part of the semiconductor substrate 45 via a gate insulating film 53, and insulating sidewalls 57 are formed on both sides in the X direction of the dummy gate electrode 55 and the insulating layer 56, thereby forming the second transistor 41. Note that in Figure 15, the source region and drain region formed on the semiconductor substrate 45 below the dummy gate electrode 55 are omitted from the display.

[0056] In conventional structures, when forming the first diffusion layer side silicide layer 50 and the second diffusion layer side silicide layer 51 on the first transistor 40, the dummy gate electrode 55, insulating layer 56, and insulating sidewall 57 on the second transistor 41 side are covered with a protective film 58, and then the first diffusion layer side silicide layer 50 and the second diffusion layer side silicide layer 51 are formed. Therefore, after forming transistors 40 and 41, a protective film 59 is formed to cover the first transistor 40 and the second transistor 41, and then the insulating layer 60 is formed.

[0057] In the conventional structure shown in Figure 15, a step difference inevitably occurs between the first transistor 40 and the second transistor 41 due to the presence or absence of the silicide layers 50 and 51. That is, only the protective film 59 is present on the first transistor 40, while the second transistor 41 has both the protective film 58 and the protective film 59. Therefore, on the first transistor 40 side, the dummy gate electrode 47 and insulating layer 48 can be removed by methods such as dry etching, as shown in Figure 16, and then a metal gate electrode can be embedded. However, on the second transistor 41 side, there was a problem in that the polysilicon dummy gate electrode 55 remained without being removed.

[0058] In contrast, the structure shown in Figure 2 involves forming hole-shaped trench grooves in the insulating layer 31 after the formation of the first transistor 5 and the second transistor 6, and then forming the silicide layers 15, 16, 25, and 26. This solves the problems of the conventional structure. Specifically, even if transistors 5 and 6 are adjacent in the X direction separated by the element isolation section 3, metal gate electrodes 10 and 20 can be formed on both transistors 5 and 6 while forming the silicide layers 15, 16, 25, and 26 on both.

[0059] (Second Embodiment) Figure 17 is a cross-sectional view showing the structure of a first transistor, a second transistor, and a semiconductor substrate applied to a semiconductor device of the second embodiment. In the structure of the second embodiment, components equivalent to those in the structure of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified. In the second embodiment, no recess 7A is formed in the first substrate portion 7 on which the first transistor 5 is formed on the semiconductor substrate 2, and the upper surface (surface) 7a of the first substrate portion 7 is on the same plane as the upper surface of the element isolation portion 3. Therefore, in the second embodiment, no inclined portion 7B is formed in the portion of the upper side of the first source region 11 that is in contact with the element isolation portion 3. In the second embodiment, no inclined portion 7B is formed in the portion of the upper side of the first drain region 12 that is in contact with the element isolation portion 3.

[0060] The difference between the structure of the second embodiment and the structure of the first embodiment is that the recess 7A formed in the first substrate portion 7 of the first embodiment is not formed in the second embodiment. Other structural aspects are equivalent between the structure of the second embodiment and the structure of the first embodiment. For example, in the structure of the second embodiment, the fact that a recess 8A is formed in the second substrate portion 8 on which the second transistor 6 (high-voltage transistor) is formed is the same, and the structure of the semiconductor substrate 2 on the side on which the second transistor 6 is formed is the same as the structure of the first embodiment.

[0061] The structure of the second embodiment allows for the reduction of junction leakage current in the second transistor 6, where the operating voltage is high and the junction leakage current is large, similar to the first embodiment. In the second transistor 6, the size of the silicide layers 25 and 26 can be made larger than in the structure of Comparative Example 2, thereby lowering the contact resistance, and the same effects as the first embodiment can be obtained. In the structure of the second embodiment, the gate insulating film 23 of the second transistor 6 is thicker than the gate insulating film 13 of the first transistor 5. Therefore, if the depth of the recess 8A and the thickness of the gate insulating film 23 can be made close, the first transistor 5 and the second transistor 6 can be formed at equal or nearly equal height positions in the Z direction. In this case, the gate electrodes 10 and 20 formed on the first transistor 5 and the second transistor 6 can be formed at equal or close height positions in the Z direction. In this case, the process margin in the etching and film deposition process for forming the gate electrodes 10 and 20 can be increased. Furthermore, in the second embodiment, the step difference at both ends of the upper part of the diffusion layer resistance, which causes variations, is eliminated, thus suppressing variations in the resistance of the diffusion layer 9A.

[0062] Figures 18 to 23 show the manufacturing method for a similar structure of the first transistor 5, the second transistor 6, and the semiconductor substrate 2 applied to the first embodiment. In the following manufacturing method, the description is simplified by treating the two element isolation sections 3 that were formed between the first transistor 5 and the second transistor 6 in the first embodiment as a single element isolation section 3, and the manufacturing method in that case will be explained. As shown in Figure 18, a plurality of element isolation bases 70 are formed on the semiconductor substrate 72, spaced a predetermined distance apart in the X direction. To form these element isolation bases 70, for example, the following steps are performed. Multiple grooves 73 are formed on the surface side of the semiconductor substrate (silicon substrate) 72 at predetermined intervals in the X direction. After filling these grooves 73 and forming an insulating layer that covers the upper surface of the semiconductor substrate 72 to a predetermined thickness, the element isolation base 70 can be formed by removing the insulating layer on the substrate corresponding to the transistor formation region by etching or the like. Note that Figures 18 to 23 show only a cross-section of the surface layer of the semiconductor substrate 72. Due to the etching process described above, the insulating layer has a shape in which the main body portion 70A fills the groove 73 and the head portion 70B protrudes wider than the groove 73 on the upper side of the semiconductor substrate 72. The element isolation base portion 70 is formed on the semiconductor substrate 72 in the manner described above.

[0063] After the element isolation base 70 is formed, etching the upper surface of the semiconductor substrate 72 and the element isolation base 70 allows the upper surface of the semiconductor substrate 72 to be etched to a predetermined depth to form a recess 75 of a predetermined depth as shown in Figure 19, and the top 70B of the element isolation base 70 to be removed to form an element isolation portion 76. This etching allows the recess 75 to be formed, and a sloping portion 77 made of the constituent material of the semiconductor substrate 72 can be formed at the edge of the recess 75, which is the boundary with the element isolation portion 76. Next, as shown in Figure 20, the bottom surface of the recess 75 is oxidized to form a gate insulating film of the required thickness. At this time, a thin oxide film 78, which is necessary for low-voltage transistors, is formed in the recess 75 corresponding to the region where the first transistor is formed. In addition, a thick oxide film 79, which is necessary for high-voltage transistors, is formed in the recess 75 corresponding to the region where the second transistor is formed.

[0064] Next, as shown in Figure 21, a lower dummy layer 80 made of dummy polysilicon and an upper dummy layer 81 made of silicon nitride and the like are formed, and insulating sidewalls 82 are formed on the X-direction sides of these dummy layers. In the state shown in Figure 21, because there is a difference in thickness between the oxide film 78 and the oxide film 79, the upper surface height of the upper dummy layer 81 above the oxide film 78 is different from the upper surface height of the upper dummy layer 81 above the oxide film 79. A height difference indicated by arrow G in the Z direction occurs between one upper dummy layer 81 and the other upper dummy layer 81 that are spaced apart in the X direction as shown in Figure 21.

[0065] After this, an insulating layer is formed on the semiconductor substrate 72, and the thickness of the insulating layer 84 is aligned with the upper end of the insulating side wall 82 as shown in Figure 22 by planar processing such as CMP. Then, the upper dummy layer 81 and the lower dummy layer 80 are removed, and the gate electrode 87 is formed by replacing them with a ferroelectric layer 85, a work function metal layer 86, and a metal such as tungsten. As described above, a first transistor (low-voltage transistor) 88 can be formed on the side where a thin oxide film 78 is formed, and a second transistor (high-voltage transistor) 89 can be formed on the side where a thick oxide film 79 is formed.

[0066] After this, an insulating layer 90 of the required thickness is formed on top of the insulating layer 84 as shown in Figure 23. Then, hole-shaped trench grooves are formed so that they penetrate the insulating layer 84 and the insulating layer 90 in the Z direction and reach the recesses 75 in the semiconductor substrate 72 on the side of the insulating side wall 82. After this, metal for forming the silicide layer is filled into the recesses 75 of the semiconductor substrate 72 from each trench groove, and the metal is diffused by heat treatment to form silicide layers 91, 92, 93, and 94. After this, contact electrodes 95, 96, 97, and 98 are formed to fill each trench groove. Through the above process, the laminated structure shown in Figure 23 can be obtained. The stacked structure shown in Figure 23 differs from the stacked structure shown in Figure 2 only in the presence of two or only one element isolation section 3 between the first transistor 5 and the second transistor 6; the other structural aspects are the same.

[0067] In the first embodiment, the first transistor 5 is provided on the first substrate portion 7 which has a recess 7A, and the second transistor 6 is provided on the second substrate portion 8 which has a recess 8A. In the second embodiment, the first transistor 5 is provided on the first substrate portion 7 which does not have a recess 7A, and the second transistor 6 is provided on the second substrate portion 8 which has a recess 8A. Alternatively, it is also possible to adopt a configuration in which the first transistor 5 is provided on the first substrate portion 7 which has a recess 7A, and the second transistor 6 is provided on the second substrate portion 8 which does not have a recess 8A. Furthermore, since the semiconductor substrate 2 is provided with a plurality of first transistors 5 and a plurality of second transistors 6, it is possible to form all first transistors 5 in the recess 7A and all second transistors 6 in the recess 8A, but this is not the only example. For example, the recess 7A may be formed in correspondence with some of the first transistors 5, and the first transistors 5 may be formed on the first substrate portion 7 which does not have a recess 7A. For example, the recess 8A may be formed in correspondence with some of the second transistors 6, and the second transistors 6 may be formed on the second substrate portion 8 which does not have a recess 8A.

[0068] Furthermore, the first embodiment shown in Figure 2 and the second embodiment shown in Figure 17 are shown as being adjacent to each other in the X direction via the element isolation section 3. However, the adjacent arrangement of the first transistor 5 and second transistor 6 on the semiconductor substrate 2 in the X direction is just one example, and of course, the above embodiments can also be applied to a structure in which, for example, multiple first transistors 5 are adjacent to each other via multiple element isolation sections 3, and multiple second transistors 6 are adjacent to each other via multiple element isolation sections 3. One purpose of providing recesses 7A and 8A to accommodate the first transistor 5 and the second transistor 6 is to eliminate problems that occur when the contact electrodes are misaligned due to errors in mask alignment, etc. Therefore, if there are locations where the distance between the first transistor 5 formed on the semiconductor substrate 2 and the adjacent element isolation section 3, or the distance between the second transistor 6 and the adjacent element isolation section 3, is sufficiently larger than the misalignment error, the first transistor 5 or the second transistor 6 may be provided without forming recesses 7A or 8A. Thus, the structure described in the previous embodiment can be applied by selecting the first transistor 5 or the second transistor 6, which have a high degree of integration and a small distance from the adjacent element isolation section 3.

[0069] Although several embodiments and structural examples of the present invention have been described above, these embodiments and structural examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and structural examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and other structural examples are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0070] 1... Semiconductor devices (semiconductor memory devices), 2… Semiconductor substrates, 3... Element isolation section (element isolation isolation region), 5…First transistor (low-voltage transistor), 6…Second transistor (high-voltage transistor), 7...First circuit board section, 7A... recess (first recess), 7a...Bottom surface, 7B...Slope part, 8...Second circuit board section, 8A... recess (second recess), 8a...Bottom surface, 8B...Slope part, 10…Gate 1, 11...First source region (first diffusion layer region), 12...First drain region (second diffusion layer region), 13…First gate insulating film, 15, 15A...First silicide layer (silicide layer on the first diffusion layer side), 16...Second silicide layer (silicide layer on the second diffusion layer side), 20...Second gate electrode, 21...Second source region (third diffusion layer region), 22...Second drain region (fourth diffusion layer region), 23...Second gate insulating film, 25, 25A... Third silicide layer (silicide layer on the third diffusion layer side), 26...The fourth silicide layer (silicide layer on the fourth diffusion layer side), 35...First contact electrode, 36...Second contact electrode, 37...Third contact electrode, 38…Fourth contact electrode, B1, B2...interface position.

Claims

1. Semiconductor substrate and A first transistor comprising: a first diffusion layer region and a second diffusion layer region provided on the semiconductor substrate; a first gate insulating film provided on the semiconductor substrate, at least a portion of which faces the region between the first diffusion layer region and the second diffusion layer region; a first gate electrode located on the opposite side of the semiconductor substrate from the first gate insulating film; and a first silicide layer embedded on the upper surface of the first diffusion layer region and a second silicide layer embedded on the upper surface of the second diffusion layer region. A second transistor having a third diffusion layer region and a fourth diffusion layer region provided on the semiconductor substrate, a second gate insulating film provided on the semiconductor substrate and at least a portion of which faces the region between the third diffusion layer region and the fourth diffusion layer region, a second gate electrode located on the opposite side of the semiconductor substrate from the second gate insulating film, and a third silicide layer embedded on the upper surface of the third diffusion layer region and a fourth silicide layer embedded on the upper surface of the fourth diffusion layer region, An element isolation section embedded in the semiconductor substrate to separate the first transistor and the second transistor from their surrounding region. Equipped with, At least one of the first transistor and the second transistor is formed in a recess having a bottom surface located at a position lower than the interface between the element isolation portion formed on the semiconductor substrate and the semiconductor substrate. Semiconductor equipment.

2. The first gate insulating film is thinner than the second gate insulating film, the first transistor is a low-voltage transistor, and the second transistor is a high-voltage transistor. The semiconductor device according to claim 1.

3. The first silicide layer and the second silicide layer are formed in the recess where the first transistor is formed, and the third silicide layer and the fourth silicide layer are formed in the recess where the second transistor is formed. The semiconductor device according to claim 1.

4. The first transistor is formed in a first recess having a bottom surface located at a position lower than the interface between the element isolation portion formed on the semiconductor substrate and the semiconductor substrate. The second transistor is formed in a second recess having a bottom surface located at a position lower than the interface between the element isolation portion formed on the semiconductor substrate and the semiconductor substrate. The semiconductor device according to claim 1.

5. The first gate insulating film is thinner than the second gate insulating film, the first transistor is a low-voltage transistor, and the second transistor is a high-voltage transistor. The second transistor is formed in a recess having a bottom surface located at a position lower than the interface between the element isolation portion formed on the semiconductor substrate and the semiconductor substrate. The first transistor is formed on the surface of the semiconductor substrate at the same height as the interface between the element isolation portion formed on the semiconductor substrate and the semiconductor substrate, The semiconductor device according to claim 1.

6. The device has an insulating layer covering the semiconductor substrate and the element isolation portion, and includes a first contact electrode that penetrates the insulating layer in its thickness direction and connects to the first silicide layer, a second contact electrode that penetrates the insulating layer in its thickness direction and connects to the second silicide layer, a third contact electrode that penetrates the insulating layer in its thickness direction and connects to the third silicide layer, and a fourth contact electrode that penetrates the insulating layer in its thickness direction and connects to the fourth silicide layer. The semiconductor device according to claim 1.

7. The device comprises an insulating layer covering the semiconductor substrate and the element isolation portion, a first contact electrode that penetrates the insulating layer in its thickness direction and connects to the first silicide layer, a second contact electrode that penetrates the insulating layer in its thickness direction and connects to the second silicide layer, a third contact electrode that penetrates the insulating layer in its thickness direction and connects to the third silicide layer, and a fourth contact electrode that penetrates the insulating layer in its thickness direction and connects to the fourth silicide layer. In at least one of the contact electrodes of the first contact electrode, the second contact electrode, the third contact electrode, and the fourth contact electrode, at least a portion of the connection end is connected so as to span across any silicide layer adjacent to the connection end and any element isolation portion adjacent to any silicide layer. The semiconductor device according to claim 1.

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