Semiconductor equipment

Abstract

The objective is to provide a semiconductor device. [Solution] According to the embodiment, the semiconductor semiconductor has a first transistor having a first gate insulating film formed on a first channel surface of the semiconductor substrate and a first gate electrode provided thereon, a second transistor having a second gate insulating film formed on a second channel surface of the semiconductor substrate and a second gate electrode provided thereon, and is provided at a position spaced apart from the first transistor along the plane direction of the semiconductor substrate, an insulating isolation element section embedded in the surface portion of the semiconductor substrate between the first transistor and the second transistor, and a third electrode provided along the element isolation section to partition the space between the first transistor and the second transistor, wherein the bottom of the third electrode is embedded in the element isolation section and the bottom of the third electrode is positioned deeper than the channel surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] A semiconductor device including a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate is known. In this type of semiconductor device, the interval at which transistors are provided becomes finer in accordance with the high integration of circuits. The transistors provided on the semiconductor substrate are individually insulated and separated by element isolation portions embedded in the surface layer of the semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device that can reduce the width of an element isolation portion that insulates and separates transistors arranged separately from each other on a semiconductor substrate, contributing to the high integration of transistors.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment has a semiconductor substrate. The semiconductor device has a first transistor having a first gate insulating film formed on a first channel surface of the semiconductor substrate surface and a first gate electrode provided on the first gate insulating film. The semiconductor device has a second transistor having a second gate insulating film formed on a second channel surface of the semiconductor substrate surface and a second gate electrode provided on the second gate insulating film, and is provided at a position spaced apart from the first transistor along the plane direction of the semiconductor substrate. The semiconductor device has an element isolation portion embedded in a portion of the surface of the semiconductor substrate between the first transistor and the second transistor, insulating and separating the first transistor and the second transistor. The semiconductor device has a third electrode provided along the element isolation portion so as to partition the space between the first transistor and the second transistor. The bottom of the third electrode is embedded in the element isolation portion, and the bottom of the third electrode is positioned deeper than the channel surface of the first transistor and the channel surface of the second transistor. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a plan view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a partial cross-sectional view along the line A1-A2 in the figure. [Figure 3] Figure 3 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] Figure 12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] Figure 13 is a cross-sectional view showing a comparative example semiconductor device. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar function will be denoted by the same reference numeral. Duplication of these components may be omitted. "Parallel," "orthogonal," or "same" may include cases where they are "approximately parallel," "approximately orthogonal," or "approximately the same," respectively. "Connection" is not limited to mechanical connections but may include electrical connections. That is, "connection" is not limited to cases where multiple elements are directly connected but may include cases where multiple elements are connected with another element interposed between them. "Facing" means that two members overlap when viewed in a certain direction, and may include cases where another member exists between the two members.

[0008] First, we define the X, Y, and Z directions. The X and Y directions are directions along the surface of the semiconductor substrate 2, which will be described later (see Figures 1 and 2). The X direction is the direction from the first source region 11 to the first drain region 12 in the first transistor 5, which will be described later (see Figure 1), and the direction from the second source region 21 to the second drain region 22 in the second transistor 6, which will be described later (see Figure 1). The Y direction is the direction that intersects (for example, is orthogonal to) the X direction. The Z direction is the direction that intersects (for example, is orthogonal to) the X and Y directions. The Z direction is the thickness direction of the semiconductor substrate 2 (see Figure 2). In the following explanation, the side of the semiconductor substrate 2 where the gate electrodes 10 and 20 are located may be referred to as "up," and the opposite side as "down." However, these expressions are for convenience only and do not define up and down along the direction of gravity.

[0009] (First Embodiment) <Example of semiconductor device configuration> Figure 1 is a plan view showing an example configuration of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 of this embodiment is provided, as one example, as part of the circuit board of a semiconductor memory device such as a NAND flash memory. The semiconductor device 1 comprises, for example, a semiconductor substrate 2, a plurality of transistors, and a plurality of wirings. The plurality of transistors are provided on the semiconductor substrate 2.

[0010] <Configuration of semiconductor substrate, element isolation section, and transistor> Next, the configurations of the semiconductor substrate 2 and the first transistor 5 and the second transistor 6 will be described in detail. Figure 1 is a schematic plan view showing an example of the arrangement of the first transistor 5 and the second transistor 6 formed on the surface of a semiconductor substrate. The semiconductor substrate 2 is, for example, a silicon substrate containing single-crystal silicon. As shown in Figure 2, one or more element isolation insulating regions 3 (hereinafter referred to as "element isolation regions 3") formed of an insulator such as silicon oxide are embedded in the surface layer of the semiconductor substrate 2. For example, when the semiconductor substrate 2 is viewed from above, the element isolation regions 3 have a predetermined width and are arranged to surround the periphery of the first transistor 5 and the periphery of the second transistor 6. The first transistor 5 and the second transistor 6 are spaced apart in the planar direction of the semiconductor substrate 2. In Figure 1, the element isolation section 3 is located along the X direction, between the first transistor 5 and the second transistor 6. Figure 1 simply shows the location of the element isolation section 3 located between the first transistor 5 and the second transistor 6. The region where the first transistor 5 is formed is surrounded by the element isolation section 3 in a plan view to isolate it from the surrounding region, but only a portion of the element isolation section 3 is shown in Figure 1. Similarly, the region where the second transistor 6 is formed is surrounded by the element isolation section 3 in a plan view to isolate it from the surrounding region, but only a portion of the element isolation section 3 is shown in Figure 1.

[0011] Figure 2 shows a partial cross-section along the line A1-A2 shown in Figure 1. The element isolation portion 3 is embedded in the semiconductor substrate 2, for example, with a predetermined width, extending from the surface side to a predetermined depth. In the configuration shown in Figure 2, the element isolation portion 3 is formed in an inverted trapezoidal cross-section. As shown in Figure 1, the element isolation section 3 extends in a strip shape in the X direction, and the first transistor 5 and the second transistor 6 are provided on both sides in the Y direction. As can be seen by referring to Figures 1 and 2, the first transistor 5 and the second transistor 6 are provided on both sides in the width direction of the element isolation section 3. For convenience, the semiconductor substrate 2 in the region where the first transistor 5 is formed will be referred to as the first substrate section 7, and the semiconductor substrate 2 in the region where the second transistor 6 is formed will be referred to as the second substrate section 8, and will be described below. Note that the partial cross-section shown in FIG. 2 shows only the surface layer region near the surface of the semiconductor substrate 2, only the regions on both sides of the device isolation portion 3 in the Y direction show only the regions close to the device isolation portion 3, and the upper side (Z direction side) of the device isolation portion 3 shows only the region close to the device isolation portion 3. Therefore, in FIG. 2, the description of the region below the bottom of the device isolation portion 3 (-Z direction side) is omitted, only a part of the first transistor 5 close to the device isolation portion 3 is shown, and only a part of the second transistor 6 close to the device isolation portion 3 is shown.

[0012] The first substrate portion 7 is a portion that serves as a base for providing the first transistor 5, and the second substrate portion 8 is a portion that serves as a base for providing the second transistor 6. The first substrate portion 7 and the second substrate portion 8 have a well region having a polarity (different conductivity type) different from that of the source region, the drain region, and their current paths in at least a part of the region where the transistors are provided.

[0013] <2.2 Transistor> Each of the first transistor 5 and the second transistor 6 is a field effect transistor, for example, a MOSFET (Metal - Oxide - Semiconductor - Field - Effect - Transistor). In a circuit board of a semiconductor memory device such as a NAND type flash memory, a high - voltage transistor for outputting a relatively high voltage (for example, a voltage of 20V or more) and a low - voltage transistor for outputting a relatively low voltage (for example, a voltage of 10V or less) are provided. As an example, both the first transistor 5 and the second transistor 6 are high - voltage transistors capable of outputting about 30V.

[0014] <The First Transistor> The first transistor 5 includes, for example, a first gate electrode 10, a first source region 11, a first drain region 12, and a first gate insulating film 13. The first source region 11 is an example of a "first diffusion layer region." The first drain region 12 is an example of a "second diffusion layer region." However, the first drain region 12 may be an example of a "first diffusion layer region," and the first source region 11 may be an example of a "second diffusion layer region." Furthermore, it is preferable that the first transistor 5 has a high dielectric constant film (insulating film), such as a hafnium oxide film referred to as High-k, between the first gate electrode 10 and the first gate insulating film 13. A high dielectric constant film means a film with a relative dielectric constant higher than the SiO2 that constitutes the semiconductor substrate 2.

[0015] The first source region 11 and the first drain region 12 are formed by ion implantation or the like at positions spaced apart in the X direction on the surface of the first substrate portion 7 to create a diffusion layer region. A first channel region is formed between the first source region 11 and the first drain region 12 on the surface layer of the first substrate portion 7. A first gate insulating film 13 is formed covering a part of this first channel region, a part of the first source region 11, and a part of the first drain region 12. A first gate electrode 10 is formed so as to cover the upper surface of the first gate insulating film 13. The first gate electrode 10 is provided on the side opposite to the first substrate portion 7 (semiconductor substrate 2) relative to the first gate insulating film 13.

[0016] In Figure 1, the channel region located beneath the first gate insulating film 13 is hidden by the first gate electrode 10 and is not shown. As mentioned above, the first channel region is the area sandwiched between the first source region 11 and the first drain region 12 in the surface layer of the first substrate portion 7 below the first gate insulating film 13. In Figure 2, only the peripheral region of the element isolation portion 3 is shown, so only a portion of the first gate insulating film 13 provided on the first transistor 5 is shown. The surface region of the first substrate portion 7 located below the first gate insulating film 13 is the first channel region, and the surface of this first channel region facing the first gate insulating film 13 is called the first channel surface. When the channel surface of the first transistor 5 is shown in Figure 2, it is the surface indicated by reference numeral 7a.

[0017] The first gate insulating film 13 is, for example, made of a silicon oxide film obtained by oxidizing the upper surface layer of the first substrate portion 7. Therefore, the first gate insulating film 13 is formed to a predetermined depth from the upper surface position of the first substrate portion 7. The element isolation portion 3 is formed by creating grooves in the surface of the semiconductor substrate 2 and filling the grooves with an insulator.

[0018] The first gate electrode 10 includes, for example, a main electrode portion 10A made of a metal such as tungsten or aluminum, and a laminated film 10B formed to cover the circumferential and side surfaces of the main electrode portion 10A. The laminated film 10B consists of a required number of insulating films and metal films stacked in order from the side closest to the gate insulating film 13, for example. Preferably, the film in contact with the gate insulating film 13 of the laminated film 10B is a high-dielectric-constant film, such as a hafnium oxide film referred to as High-k. Although Figure 2 shows a laminated film 10B composed of multiple films stacked together as a single film, the film closest to the gate insulating film 13 may contain a high-dielectric-constant film 10a, so the reference numeral 10a is included to indicate the presence of the high-dielectric-constant film. The laminated film 10B can be described as having a film containing a high-dielectric-constant material.

[0019] The multilayer film 10B can be fabricated, for example, by reusing parts of multiple films used when manufacturing a CMOS-type metal gate transistor by creating P-type and N-type regions on a single P-type semiconductor substrate 2.

[0020] Region 14 shown in Figure 1 indicates the region where a contact electrode connected to the upper surface of the first source region 11 is provided, and region 15 indicates the region where a contact electrode connected to the upper surface of the first drain region 12 is provided. Although regions 14 and 15 are shown as rectangles in Figure 1, they may also be circular or have other shapes. Figure 2 shows the state after the laminated film 10B and the main electrode portion 10A have been formed, and the upper surface has been polished to a flush surface by CMP (chemical mechanical polishing). After polishing by CMP, an insulating layer of a predetermined thickness is formed on the polished surface, holes are made in the insulating layer leading to the first source region 11, and holes are made in the insulating layer leading to the first drain region 12, and if necessary, metal that will become the contact electrode is filled into the holes, including the formation of a silicide layer. As a result, the contact electrode is connected to the first source region 11 and the contact electrode is connected to the first drain region 12. Similarly, by forming a contact electrode in the insulating layer that is connected to the gate electrode 10, current can be supplied to the gate electrode 10, and the first transistor 5 can operate.

[0021] <Second transistor> The second transistor 6 includes, for example, a second gate electrode 20, a second source region 21, a second drain region 22, and a second gate insulating film 23. The second source region 21 is an example of a "third diffusion layer region." The second drain region 22 is an example of a "fourth diffusion layer region." However, the second drain region 22 may be an example of a "third diffusion layer region," and the second source region 21 may be an example of a "fourth diffusion layer region." Furthermore, it is preferable that the second transistor 6 has a high dielectric constant film (insulating film), such as a hafnium oxide film referred to as High-k, between the second gate electrode 20 and the second gate insulating film 23.

[0022] The second source region 21 and the second drain region 22 are formed by ion implantation or the like at positions spaced apart in the X direction on the surface of the second substrate portion 8 to create a diffusion layer region. A second channel region is formed between the second source region 21 and the second drain region 22 on the surface layer of the second substrate portion 8. A second gate insulating film 23 is formed covering a part of this second channel region, a part of the second source region 21, and a part of the second drain region 22. A second gate electrode 20 is formed so as to cover the upper surface of the second gate insulating film 23. The second gate electrode 20 is provided on the side opposite to the second substrate portion 8 (semiconductor substrate 2) relative to the second gate insulating film 23.

[0023] In Figure 1, the second channel region located beneath the second gate insulating film 23 is hidden by the second gate electrode 20 and is not shown. As mentioned above, the second channel region is the area sandwiched between the second source region 21 and the second drain region 22 in the surface layer of the second substrate portion 8 below the second gate insulating film 23. In Figure 2, only the peripheral region of the element isolation portion 3 is shown, so only a part of the second gate insulating film 23 provided on the second transistor 6 is shown. The surface region of the second substrate portion 8 located below the second gate insulating film 23 is the second channel region, and the side of the second channel region facing the second gate insulating film 23 is called the second channel surface. When the channel surface of the second transistor 6 is shown in Figure 2, it is the surface indicated by reference numeral 8a.

[0024] The second gate insulating film 23 is, for example, made of silicon oxide obtained by oxidizing a portion of the upper surface of the second substrate portion 8. Therefore, the second gate insulating film 23 is formed to a predetermined depth from the upper surface position of the second substrate portion 8. The element isolation portion 3 is formed by creating grooves in the surface of the semiconductor substrate 2 and filling the grooves with an insulator.

[0025] The second gate electrode 20 includes, for example, a main electrode portion 20A made of a metal such as tungsten or aluminum, and a laminated film 20B formed to cover the circumferential and side surfaces of the main electrode portion 20A. The laminated film 20B consists of a required number of insulating films and metal films stacked in order from the side closest to the gate insulating film 23, for example. Preferably, the film in contact with the gate insulating film 23 of the laminated film 20B is a high-dielectric-constant film, such as a hafnium oxide film referred to as High-k. Although Figure 2 shows a laminated film 20B composed of multiple films stacked together as a single film, the film closest to the gate insulating film 23 may contain a high-dielectric-constant film 20a, so the reference numeral 20a indicating the presence of the high-dielectric-constant film is also included. The laminated film 20B can be described as having a film containing a high-dielectric-constant material.

[0026] The multilayer film 20B can be fabricated, for example, by reusing parts of multiple films used when manufacturing a CMOS-type metal gate transistor by creating P-type and N-type regions on a single P-type semiconductor substrate 2.

[0027] Region 24 shown in Figure 1 indicates the region where a contact electrode connected to the upper surface of the second source region 21 is provided, and region 25 indicates the region where a contact electrode connected to the upper surface of the second drain region 22 is provided. Although regions 24 and 25 are shown as rectangles in Figure 1, they may be other shapes such as circles. Figure 2 shows the state after the laminated film 20B and the main electrode portion 20A have been formed, and the upper surface has been polished to a flush surface by CMP (chemical mechanical polishing). After polishing by CMP, an insulating layer of a predetermined thickness is formed on the polished surface, holes are made in the insulating layer leading to the second source region 21, and holes are made in the insulating layer leading to the second drain region 22. If necessary, a metal layer that will serve as a contact electrode is formed in the hole-processed portion, including the formation of a silicide layer. As a result, the contact electrode is connected to the second source region 21 and the contact electrode is connected to the second drain region 22. Similarly, by forming a contact electrode connected to the second gate electrode 20 in the insulating layer, current can be supplied to the second gate electrode 20, and the second transistor 6 can operate.

[0028] <3rd electrode> In this embodiment, a third electrode 30, which serves as a shield gate electrode, is provided to the element isolation portion 3 extending between the first transistor 5 and the second transistor 6. The third electrode 30 is formed along a groove 3A formed in the center of the upper surface of the element isolation section 3, along the length direction (X direction) of the element isolation section 3. The depth of the groove 3A is deeper than the channel surface 7a of the first transistor 5 and the channel surface 8a of the second transistor 6, and is such that it does not penetrate the element isolation section 3 in the depth direction. The channel region of the first transistor 5 refers to the region on the surface of the first substrate portion 7 between the first source region 11 and the second drain region 12 where electrons move. The channel region of the second transistor 6 refers to the region on the surface of the second substrate portion 8 between the second source region 21 and the second drain region 22 where electrons move. As an example, it is preferable that the width of the groove 3A (width in the Y direction) be about one-tenth of the width of the element separation section 3 (width in the Y direction). A partition wall-like third electrode 30 is formed in the groove 3A of the element isolation section 3, extending from the bottom of the groove 3A through the top of the groove 3A to the space between the first gate electrode 10 of the first transistor 5 and the second gate electrode 20 of the second transistor 6.

[0029] The third electrode 30 has an electrode body portion 30A formed in the center in its width direction, and a laminated film 30B formed to cover the circumferential and bottom surfaces of the electrode body portion 30A. The electrode body portion 30A is made of a metal such as tungsten or aluminum, for example. The multilayer film 30B can be fabricated, for example, by reusing parts of multiple films used when manufacturing a CMOS-type metal gate transistor by creating P-type and N-type regions on a single P-type semiconductor substrate 2.

[0030] The laminated film 30B consists of a required number of insulating films and metal films stacked in order from the side closest to the inner surface of the groove 3A, for example. Preferably, the film in contact with the inner surface of the groove 3A is a high-dielectric-constant film, such as a hafnium oxide film referred to as High-k. Although Figure 2 shows a simplified representation of the laminated film 30B as a single film, the film closest to the inner surface of the groove 3A may contain a high-dielectric-constant film 30a, so the reference numeral 30a is included to indicate the presence of the high-dielectric-constant film. The laminated film 30B can be described as having a film containing a high-dielectric-constant material. As explained above, the laminated film 30B has the same film type structure as the laminated film 10B formed around the first gate electrode 10 and the laminated film 20B formed around the second gate electrode 20.

[0031] As shown in Figure 2, a first insulating portion 35 is formed between the side surface of the +Y direction end of the first gate electrode 10 and the side surface of the -Y direction end of the third electrode 30 adjacent to the first gate electrode 10. More specifically, the first insulating portion 35 is formed between the side surface of the first layer 10a located at the +Y direction end of the laminated film 10B and the side surface of the first layer 30a located at the -Y direction end of the laminated film 30B. The first insulating portion 35 insulates and separates the first gate electrode 10 and the third electrode 30. As shown in Figure 2, a second insulating portion 36 is formed between the side surface of the -Y direction end of the second gate electrode 20 and the side surface of the +Y direction end of the third electrode 30 adjacent to the second gate electrode 20. More specifically, the second insulating portion 36 is formed between the side surface of the first layer 20a located at the -Y direction end of the laminated film 20B and the side surface of the first layer 30a located at the +Y direction end of the laminated film 30B. The second insulating portion 36 insulates and separates the second gate electrode 20 and the third electrode 30.

[0032] The bottom of the groove 3A, where the third electrode 30 is provided, is located deeper than the channel surfaces 7a and 8a in the thickness direction (Z direction) of the semiconductor substrate 2. Therefore, the bottom 30G of the third electrode 30 is located deeper than the channel surface 7a of the first transistor 5 (-Z direction) and deeper than the channel surface 8a of the second transistor 6 in the thickness direction of the semiconductor substrate 2. However, it is preferable that the third electrode 30 does not penetrate the element isolation portion 3 in the thickness direction (Z direction) of the semiconductor substrate 2.

[0033] The first insulating section 35 can be manufactured by reusing protective films, insulating films, insulating layers, etc., used when manufacturing the CMOS-type first transistor 5 and second transistor 6. In Figure 1, only the first source region 11, the first drain region 12, the gate insulating film 13, and the first gate electrode 10 are shown as the main elements constituting the first transistor 5. In contrast, as an example of a CMOS-type first transistor 5, a structure is adopted in which a cap insulating film is placed on the gate electrode 10, both sides are covered with insulating sidewalls, and multiple layers of liner insulating films are coated on top of them. These insulating films and insulating sidewalls are composed of insulating films such as silicon oxide or silicon nitride. The first insulating portion 35 and the second insulating portion 36 are composed of multiple insulating films used here. The third electrode 30 extends between the first gate electrode 10 and the second gate electrode 20 via the first insulating portion 35 and the second insulating portion 36. Therefore, the third electrode 30 is provided so as to separate the first gate electrode 10 and the second gate electrode 20. The bottom portion 30G of the third electrode 30 may be formed at a deeper position (-Z direction) in the semiconductor substrate 2 than the channel region of the first transistor 5 and the channel region of the second transistor 6.

[0034] In this embodiment, a voltage of approximately 30V may be applied to the first gate electrode 10 and the second gate electrode 20, allowing the potential of the third electrode 30 provided in the element isolation section 3 to be set to 0V. By providing the third electrode 30 with a potential of 0V, the cutoff electric field effect is strengthened, thus providing a shielding effect. This suppresses inter-element leakage current that would otherwise leak from the source / drain region of the first transistor 5 to the second transistor 6 side, by wrapping around the bottom of the element isolation section 3. Alternatively, it suppresses inter-element leakage current that would otherwise leak from the source / drain region of the second transistor 6 to the first transistor 5 side, by wrapping around the bottom of the element isolation section 3. Furthermore, if the installation of the third electrode 30 can suppress inter-element leakage current, the element isolation breakdown voltage of the first transistor 5 and the second transistor 6 can be improved compared to the conventional structure in which the third electrode 30 is not provided in the groove. In addition, if the element isolation breakdown voltage is improved, the element isolation section 3 can be made narrower than in the conventional structure, and the distance between the first transistor 5 and the second transistor 6 can be reduced. This makes it possible to achieve higher integration of the transistors installed.

[0035] <Example of transistor structure> Currently, in highly integrated semiconductor memory devices, for example, the depth of the element isolation region 3 is approximately 350 nm, and the Y-direction width of the first source region 11 and the first drain region 12 shown in Figure 1 is approximately 1800 nm. The X-direction width of the first gate electrode 10 shown in Figure 1 is approximately 1800 nm, the X-direction spacing between the first gate electrode 10 and region 14 is approximately 600 nm, and the X-direction spacing between the first gate electrode 10 and region 15 is approximately 690 nm. In this size, the width (Y-direction width) of the third electrode 30 can be set to approximately 150 nm, the Y-direction spacing between the third electrode 30 and the first gate electrode 10 to approximately 125 nm, and the Y-direction spacing between the third electrode 30 and the second gate electrode 20 to approximately 125 nm. The distance from the +Y-direction ends of the first source region 11 and the first drain region 12 to the +Y-direction end of the first gate electrode 10 overhanging the third electrode 30 can be set to approximately 100 nm. The distance from the -Y-direction ends of the second source region 21 and the second drain region 22 to the -Y-direction end of the second gate electrode 20 overhanging the third electrode 30 can be set to approximately 100 nm.

[0036] In the above case, if a groove with a depth of 320 nm is formed in the element isolation section 3, and the heights of the first insulating section 35 and the second insulating section 36 above the element isolation section 3 are set to 60 nm, the height of the third electrode 30 (height in the Z direction) can be set to approximately 380 nm. Below the bottom of the third electrode 30, a portion of the element isolation section 3 with a thickness of approximately 30 nm will remain. We will now compare the case where the third electrode 30 is positioned with the size described above, with a structure in which the third electrode is hypothetically positioned on top of the element isolation section 3.

[0037] Figure 13 shows a comparative example structure in which the lower end of the third electrode 31 is placed on the upper surface of the element isolation portion 3, the first gate electrode 33 is provided on the first gate insulating film 13 via the first semiconductor layer 32, and the second gate electrode 38 is provided on the second gate insulating film 23 via the second semiconductor layer 37.

[0038] Consider the comparative example structure shown in Figure 13, assuming the width of the third electrode 30 is 100 nm and the depth of the groove 3A provided in the element isolation section 3 is 100 nm. The relationship between the electric field and the potential difference is given by E = V / d (electric field E, potential difference V, distance d). In this case, compared to the configuration in which the lower end of the third electrode 30 is placed on the upper surface of the element isolation section 3, the electric field effect caused by the third electrode 30 acting as a shield gate electrode is 1.4 times (= 350 / 250).

[0039] As is clear from the above explanation, the structure shown in Figure 2 has a higher leakage current cutoff effect, or a higher electric field effect when acting as a shield gate electrode, compared to the structure shown in Figure 13. As an example, as mentioned above, good results can be obtained whether the depth of the groove 3A is 320 nm or 100 nm relative to the thickness of the element isolation section 3 (350 nm). From the above, by forming a groove 3A in the element isolation section 3 and providing a third electrode 30 in the groove 3A, inter-element leakage current that would otherwise leak from the source / drain region of the first transistor 5 towards the second transistor 6 by wrapping around the bottom of the element isolation section 3 can be suppressed. Alternatively, inter-element leakage current that would otherwise leak from the source / drain region of the second transistor 6 towards the first transistor 5 by wrapping around the bottom of the element isolation section 3 can be suppressed. Furthermore, if the element isolation section 3 can suppress inter-element leakage current, the element isolation breakdown voltage of the first transistor 5 and the second transistor 6 can be improved compared to the conventional structure in which the third electrode 30 is not provided in the groove. Also, an improvement in element isolation breakdown voltage allows the element isolation section 3 to be made narrower than in the conventional structure, thereby reducing the distance between the first transistor 5 and the second transistor 6. This enables higher integration of the transistors installed.

[0040] <Transistor manufacturing method> Figures 3 to 12 are diagrams illustrating an example of a manufacturing method related to the structure comprising the element isolation section and the third electrode of the first embodiment. As shown in Figure 3, a gate insulating film 41 is formed in the required locations on the semiconductor substrate 40, a first semiconductor layer 42 such as polysilicon and an insulating layer 43 such as SiN are laminated, and grooves 45 of a predetermined depth are formed in the region where the element isolation portion should be formed. An insulating filler material is deposited on the semiconductor substrate 40, and element isolation portions 46 are formed by performing CMP, ion etching, etch-back processing, etc., filling the inside of the grooves 45 up to the upper surface of the gate insulating film 41, as shown in Figure 4. Subsequently, the insulating layer 43 is removed by processes such as reactive ion etching (RIE) or wet etching (WET). Next, as shown in Figure 5, a second semiconductor layer 47 and a SiN cap insulating layer 48 are formed, and the layer above the element isolation portion 46 is etched to form a first groove 50 and a second groove 51 along the element isolation portion 46.

[0041] Subsequently, using the film used to form the protective film and insulating sidewalls of the CMOS transistor (not shown), insulating layers 52 and 53 with a laminated structure having a first layer, a second layer, and a third layer are formed inside the first groove 50 and the second groove 51, as shown in Figure 6. Next, as shown in Figure 7, the fourth layer 55 and fifth layer 56 are formed to fill the first groove 50, the second groove 51, and the insulating layers 52 and 53. Then, the top surface is flattened by removing a predetermined thickness using CMP, resulting in a structure in which the first insulating portion 57 is embedded in the first groove 50 and the second insulating portion 58 is embedded in the second groove 51, as shown in Figure 7. Subsequently, the outermost surface of the structure shown in Figure 7 is etched, for example, by reactive ion etching or wet etching to obtain the structure shown in Figure 8.

[0042] Next, as shown in Figure 9, the first semiconductor layer 42 and the second semiconductor layer 47 are removed, a photoresist layer 59 is formed as shown in Figure 10, and a groove 60 is formed in the element isolation portion 46 between the first insulating portion 57 and the second insulating portion 58 as shown in Figure 11. Next, after removing the photoresist layer 59, a plurality of films including a high dielectric constant film 61a are deposited in the region where the gate electrode of the first transistor is to be formed to form a laminated film 61B, and the electrode body portion 61A is formed to form the first gate electrode 61.

[0043] Similarly, a multilayer film 62B is formed by depositing multiple films including a high dielectric constant film 62a in the region where the gate electrode of the second transistor is to be formed, and the electrode body portion 62A is formed to form the second gate electrode 62. Similarly, multiple films including a high dielectric constant film 63a are deposited in the region where the third electrode is to be formed to form a laminated film 63B, and the electrode body portion 63A is formed to form the third electrode 63. Subsequently, the portions where the deposited film portions of the electrode bodies 61A, 62A, and 63A are connected on the upper side are polished and scraped off by CMP. This separates the first gate electrode 61, the second gate electrode 62, and the third electrode, as shown in Figure 12. By the manufacturing method described above, a structure equivalent to the structure shown in Figure 2, as shown in Figure 12, can be obtained.

[0044] Although several embodiments and structural examples of the present invention have been described above, these embodiments and structural examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and structural examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and other structural examples are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0045] 1… Semiconductor equipment, 2… Semiconductor substrates, 3... Element isolation section (element isolation isolation region), 5…First transistor (high-voltage transistor), 6…Second transistor (high-voltage transistor), 7...First circuit board section, 7a...First channel surface, 8...Second circuit board section, 10…Gate 1, 10a... High dielectric constant film, 10B... Multilayer film, 11...First source region (first diffusion layer region), 12...First drain region (second diffusion layer region), 13…First gate insulating film, 20...Second gate electrode, 20a... High dielectric constant film, 20B... Multilayer film, 21...Second source region (third diffusion layer region), 22...Second drain region (fourth diffusion layer region), 23...Second gate insulating film, 30...Third electrode, 30a... High dielectric constant film, 30B... Multilayer film, 30G...Bottom.

Claims

1. Semiconductor substrate and A first transistor having a first gate insulating film formed on a first channel surface of a semiconductor substrate and a first gate electrode provided on the first gate insulating film, A second transistor having a second gate insulating film formed on a second channel surface of the semiconductor substrate surface and a second gate electrode provided on the second gate insulating film, and provided at a position spaced apart from the first transistor along the plane direction of the semiconductor substrate, An element isolation portion is embedded in a portion of the surface of the semiconductor substrate between the first transistor and the second transistor, and isolates the first transistor and the second transistor; It has a third electrode provided along the element isolation portion so as to separate the first transistor and the second transistor, The bottom of the third electrode is embedded in the element isolation portion, and the bottom of the third electrode is positioned deeper than the channel surface of the first transistor and the channel surface of the second transistor. Semiconductor equipment.

2. The first gate electrode and the second gate electrode have a laminated structure comprising an insulating film containing a high dielectric constant material and a metal film. The semiconductor device according to claim 1.

3. The third electrode has a laminated structure comprising an insulating film containing a high dielectric constant material and a metal film. The semiconductor device according to claim 1.

4. The semiconductor substrate surface has a first diffusion layer region and a second diffusion layer region at positions that straddle the first channel surface in the planar direction, and a third diffusion layer region and a fourth diffusion layer region at positions that straddle the second channel surface in the planar direction of the semiconductor substrate surface. The third electrode extends to a position that separates the first diffusion layer region and the second diffusion layer region from the third diffusion layer region and the fourth diffusion layer region. The semiconductor device according to claim 1.

5. The bottom of the third electrode is embedded in the element isolation portion, and the bottom of the third electrode is positioned deeper than the channel region of the first transistor and the channel region of the second transistor, and does not penetrate the element isolation portion in the thickness direction. The semiconductor device according to claim 1.

6. The semiconductor device according to claim 1, wherein the bottom of the third electrode is positioned so as not to penetrate the element isolation portion in the thickness direction.

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