Semiconductor equipment

Abstract

The present invention provides a semiconductor device capable of suitably dividing a laminated film into multiple plate-like portions. [Solution] According to one embodiment, the semiconductor device comprises a laminated film that alternately includes a plurality of first insulating films and a plurality of electrode layers in a first direction, and includes a non-staircase portion and a staircase portion provided in a second direction of the non-staircase portion. The device further comprises a first support portion that includes a second insulating film provided within the staircase portion. The laminated film includes a plurality of partial laminated films stacked in the first direction, and the first support portion includes a plurality of partial support portions provided within the plurality of partial laminated films. The plurality of partial support portions include a first partial support portion having a first major axis and a first minor axis in plan view, where the angle between the second direction and the first major axis is smaller than the angle between the second direction and the first minor axis, and a second partial support portion having a second major axis and a second minor axis in plan view, where the angle between the second direction and the second major axis is larger than the angle between the second direction and the second minor axis.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Generally, a three-dimensional semiconductor memory includes a stacked film that alternately includes a plurality of insulating films and a plurality of electrode layers (e.g., word lines) in the vertical direction. When manufacturing a three-dimensional semiconductor memory, it is often necessary to form a plurality of slits in the stacked film to divide the stacked film into a plurality of plate-like portions (finger portions). In this case, due to steps or the like in the stacked film, these plate-like portions may tilt or fall.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device capable of suitably dividing a stacked film into a plurality of plate-like portions.

Means for Solving the Problems

[0005] According to one embodiment, the semiconductor device comprises a laminated film having a plurality of first insulating films and a plurality of electrode layers alternately arranged in a first direction, and including a non-staircase portion and a staircase portion provided in a second direction of the non-staircase portion. The device further comprises a first columnar portion including a charge storage layer and a semiconductor layer provided within the non-staircase portion. The device further comprises a first support portion including a second insulating film provided within the staircase portion. The laminated film comprises a plurality of partial laminated films stacked in the first direction, and the first support portion comprises a plurality of partial support portions provided within the plurality of partial laminated films, respectively. The plurality of partial support portions within the first support portion include one or more first partial support portions having a first major axis and a first minor axis in plan view, with the angle between the second direction and the first major axis being smaller than the angle between the second direction and the first minor axis, and one or more second partial support portions having a second major axis and a second minor axis in plan view, with the angle between the second direction and the second major axis being larger than the angle between the second direction and the second minor axis. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 3] This is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 4] This is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 5] This is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 6] This is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 7] This is a plan view showing the structure of a comparative example of the first embodiment. [Figure 8] This is a plan view showing the structure of the first embodiment of the semiconductor device. [Figure 9] These are plan views showing first to eighth examples of the structure of the semiconductor device according to the first embodiment. [Figure 10]It is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the first embodiment. [Figure 11] It is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment. [Figure 12] It is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the first embodiment. [Figure 13] It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 14] It is a plan view showing the structure of a semiconductor device according to the second embodiment. [Figure 15] It is a plan view showing the structure of a semiconductor device according to the second embodiment. [Figure 16] It is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. [Figure 17] It is a cross-sectional view (1 / 2) showing the manufacturing method of a semiconductor device according to the third embodiment. [Figure 18] It is a cross-sectional view (2 / 2) showing the manufacturing method of a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 18, the same components are denoted by the same reference numerals, and redundant explanations are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] The semiconductor device of the present embodiment is, for example, a three-dimensional semiconductor memory. Hereinafter, the structure of the semiconductor device of the present embodiment will be mainly described with reference to FIG. 1. In this description, FIG. 2 will also be referred to as appropriate.

[0010] The semiconductor device of this embodiment includes a substrate 1, a stacked film 2, an interlayer insulating film 3, a plurality of columnar portions 4, and a plurality of support portions 5. The stacked film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b. Each columnar portion 4 includes a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e (FIG. 2). Each support portion 5 includes an insulating film 5a. Each columnar portion 4 is an example of a first columnar portion, and each support portion 5 is an example of a first support portion or a second support portion. Each insulating film 2a in the stacked film 2 is an example of a first insulating film, and the insulating film 5a in each support portion 5 is an example of a second insulating film. The channel semiconductor layer 4d is an example of a semiconductor layer.

[0011] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows the X direction and the Y direction that are parallel to the surface of the substrate 1 and perpendicular to each other, and the Z direction that is perpendicular to the surface of the substrate 1. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may coincide with the direction of gravity or may not coincide with the direction of gravity. The Z direction is an example of a first direction, the X direction is an example of a second direction, and the Y direction is an example of a third direction.

[0012] The stacked film 2 is formed on the substrate 1 and alternately includes a plurality of insulating films 2a and a plurality of electrode layers 2b in the Z direction. Each insulating film 2a is, for example, a SiO2 film (silicon oxide film). Each electrode layer 2b includes, for example, a metal layer such as a W (tungsten) layer. Each electrode layer 2b of this embodiment functions as a word line or a selection line of a three-dimensional semiconductor memory. The stacked film 2 may be formed directly on the substrate 1 or may be formed on the substrate 1 via another film.

[0013] The stacked film 2 includes a non-step portion (flat portion) R1 and a step portion R2. The non-step portion R1 has an upper surface having a non-step shape (flat shape). The step portion R2 has an upper surface and a side surface having a stepped shape. In FIG. 1, the step portion R2 is formed in the X direction of the non-step portion R1. Further details of the stacked film 2 will be described later.

[0014] The interlayer insulating film 3 is formed on the stepped portion R2 so as to eliminate the step difference between the upper surface of the non-stepped portion R1 and the upper surface of the stepped portion R2. The interlayer insulating film 3 is, for example, a TEOS (tetraethyl orthosilicate) film or an SiO2 film.

[0015] Each columnar portion 4, as shown in Figure 1, is formed within the stepped portion R2, has a columnar shape extending in the Z direction, and penetrates the laminated film 2 in the Z direction. Furthermore, each columnar portion 4, as shown in Figure 2, includes a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e, all formed sequentially on the side surface of the laminated film 2. The block insulating film 4a is, for example, an SiO2 film. The charge storage layer 4b is, for example, a SiN film (silicon nitride film). The charge storage layer 4b in this embodiment is capable of storing signal charges in a three-dimensional semiconductor memory. The tunnel insulating film 4c is, for example, an SiO2 film. The channel semiconductor layer 4d is, for example, a polysilicon layer. The channel semiconductor layer 4d in this embodiment functions as a channel for multiple cell transistors (memory cells) and multiple selection transistors in a three-dimensional semiconductor memory. The core insulating film 4e is, for example, an SiO2 film. Further details of each columnar portion 4 will be described later.

[0016] Each support column 5, as shown in Figure 1, is formed within the stepped section R2 (or within the interlayer insulating film 3 and the stepped section R2), has a columnar shape extending in the Z direction, similar to each columnar section 4, and penetrates the laminated film 2 (or the interlayer insulating film 3 and the laminated film 2) in the Z direction. Each support column 5 also includes an insulating film 5a, as shown in Figure 1. The insulating film 5a is, for example, an SiO2 film. In this embodiment, each support column 5 functions as a support to suppress the collapse of the laminated film 2 during replacement processes, etc. Further details of each support column 5 will be described later.

[0017] Figure 3 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0018] Figure 3 shows details of the laminated film 2, the multiple columnar sections 4, and the multiple support sections 5 shown in Figure 1. The laminated film 2 includes a lower laminated film 2-1, an intermediate laminated film 2-2, and an upper laminated film 2-3, which are stacked sequentially in the Z direction. Each columnar section 4 includes a lower columnar section 4-1, an intermediate columnar section 4-2, and an upper columnar section 4-3, which are arranged sequentially in the Z direction. Each support section 5 includes a lower support section 5-1, an intermediate support section 5-2, and an upper support section 5-3, which are arranged sequentially in the Z direction. The lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3 within the laminated film 2 are examples of multiple partial laminated films. The lower support section 5-1, the intermediate support section 5-2, and the upper support section 5-3 within each support section 5 are examples of multiple partial support sections.

[0019] Each of the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3 alternately contains multiple insulating films 2a and multiple electrode layers 2b in the Z direction. In this embodiment, the lower laminated film 2-1 is the lowest laminated film among the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3, and the upper laminated film 2-3 is the highest laminated film among the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3. The intermediate laminated film 2-2 is a laminated film other than the lowest and highest among the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3.

[0020] The lower columnar portion 4-1, the intermediate columnar portion 4-2, and the upper columnar portion 4-3 within each columnar portion 4 are formed within the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3, respectively. Similar to the laminated film 2, the lower columnar portion 4-1, the intermediate columnar portion 4-2, and the upper columnar portion 4-3 within each columnar portion 4 are the lowest columnar portion, the highest columnar portion, and the columnar portions other than the lowest and highest, respectively.

[0021] Within each support section 5, the lower support section 5-1, the intermediate support section 5-2, and the upper support section 5-3 are formed within the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3, respectively. Similar to the laminated film 2, within each support section 5, the lower support section 5-1, the intermediate support section 5-2, and the upper support section 5-3 are the lowest support section, the highest support section, and the support sections other than the lowest and highest, respectively. Further details of each support section 5 will be described later.

[0022] As mentioned above, the stepped section R2 has a top surface and side surfaces that have a stepped shape (see Figure 1). Figure 3 omits the illustration of such a stepped shape. In this embodiment, such a stepped shape is formed in the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3 within the stepped section R2.

[0023] The laminated film 2, the multiple columnar parts 4, and the multiple support parts 5 shown in Figure 3 are formed, for example, as follows. First, a lower laminated film 2-1 is formed on a substrate 1, and multiple lower memory holes and multiple lower holes are formed within the lower laminated film 2-1. Next, an intermediate laminated film 2-2 is formed on the lower laminated film 2-1, and multiple intermediate memory holes and multiple intermediate holes are formed within the intermediate laminated film 2-2. Next, an upper laminated film 2-3 is formed on the intermediate laminated film 2-3, and multiple upper memory holes and multiple upper holes are formed within the upper laminated film 2-3. Next, each support part 5 is formed in a single hole including a lower hole, an intermediate hole, and an upper hole, and each columnar part 4 is formed in a single memory hole including a lower memory hole, an intermediate memory hole, and an upper memory hole. Next, slits are formed in the laminated film 2, and these slits are used to replace multiple sacrificial layers in the laminated film 2 with multiple electrode layers 2b (replacement process), and multiple insulating films 6 (described later) are formed in these slits. In this way, the semiconductor device shown in Figure 3 is manufactured. When forming the laminated film 2, the lower laminated film 2-1, the intermediate laminated film 2-2, and the upper laminated film 2-3 are each formed to alternately include multiple insulating films 2a and multiple sacrificial layers in the Z direction.

[0024] Furthermore, the laminated film 2 may include two or more intermediate laminated films 2-2 between the lower laminated film 2-1 and the upper laminated film 2-3. That is, the laminated film 2 may include four or more laminated films (one lower laminated film 2-1, two or more intermediate laminated films 2-2, and one upper laminated film 2-3).

[0025] Furthermore, the laminated film 2 does not necessarily have to include an intermediate laminated film 2-2 between the lower laminated film 2-1 and the upper laminated film 2-3. In other words, the laminated film 2 may consist of only two laminated films (one lower laminated film 2-1 and one upper laminated film 2-3).

[0026] Figure 4 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0027] Figures 1 to 3 show the XZ cross-section of the semiconductor device of this embodiment, while Figure 4 shows the YZ cross-section of the semiconductor device of this embodiment. Specifically, Figure 4 shows the YZ cross-section of the non-staircase section R1, but the columnar section 4 within the non-staircase section R1 is not shown. Similarly, Figure 5, which will be described later, shows the YZ cross-section of the staircase section R2, but the support column section 5 within the staircase section R2 is not shown.

[0028] Figure 4 shows a plurality of finger portions (plate-like portions) F formed within the laminated film 2. These finger portions F have a plate-like shape extending in the Z and X directions and are adjacent to each other in the Y direction. As will be described later, each finger portion F is formed continuously within a non-staired portion R1 and a staired portion R2 (see Figures 4 and 5). In this embodiment, a plurality of columnar portions 4 (not shown in Figure 4) are provided within the non-staired portion F1 of each finger portion F, and a plurality of support columns 5 (not shown in Figure 5) are provided within the staired portion F2 of each finger portion F. Each finger portion F is an example of a first plate-like portion.

[0029] The semiconductor device of this embodiment further comprises a plurality of insulating films 6. These insulating films 6 have a plate-like shape extending in the Z and X directions and are adjacent to each other in the Y direction. Furthermore, these insulating films 6 penetrate the laminated film 2 in the Z direction and are formed continuously within the non-staired portion R1 and the stepped portion R2. The laminated film 2 of this embodiment is divided into the plurality of finger portions F by these insulating films 6. These insulating films 6 are arranged alternately with the plurality of finger portions F in the Y direction. Each insulating film 6 is, for example, an SiO2 film. Each insulating film 6 is an example of a second plate-like portion. Note that the second plate-like portion may include an insulating film 6 and a semiconductor layer or metal layer embedded within the insulating film 6.

[0030] Figure 5 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0031] Figure 5 shows a YZ cross-section of the semiconductor device of this embodiment. Specifically, Figure 5 shows a YZ cross-section of the staircase section R2, but the support column 5 within the staircase section R5 is not shown.

[0032] As mentioned above, the multiple finger portions F and multiple insulating films 6 shown in Figure 5 are the same as the multiple finger portions F and multiple insulating films 6 shown in Figure 4. These finger portions F and insulating films 6 are formed continuously within the non-staired portion R1 and the staired portion R2.

[0033] The stair section R2 has a top surface and side surfaces that have a staircase shape (see Figure 1). In Figure 1, the top surface and side surfaces form a staircase that descends in the +X direction. In this embodiment, the stair section R2 further has a staircase shape on the side surfaces of each finger section F in the +Y direction or the -Y direction (Figure 5). Figure 5 illustrates the staircases of two of the four finger sections F. In this embodiment, each of the lower laminated film 2-1, intermediate laminated film 2-2, and upper laminated film 2-3 within each finger section F has a staircase that descends in the +Y direction or the -Y direction (Figure 5). In Figure 5, one finger section F has a staircase that descends in the +Y direction on its side surface in the +Y direction, and another finger section F has a staircase that descends in the -Y direction on its side surface in the -Y direction.

[0034] In Figure 5, one finger portion F having steps is adjacent to one insulating film 6 on the step side, and a gap is created between the finger portion F and the insulating film 6. In Figure 5, the interlayer insulating film 3 described above is formed within this gap. This is because, in this embodiment, each insulating film 6 is formed within the laminated film 2 and the interlayer insulating film 3 after the formation of the step portion R2 and the interlayer insulating film 3.

[0035] In this embodiment, each finger portion F may tilt or fall over due to the stepped portion R2 within the laminated film 2. For example, each finger portion F in this embodiment has a mirror-asymmetry shape in the Y direction due to the steps shown in Figure 5. Therefore, each finger portion F may tilt or fall over in the Y direction due to this mirror-asymmetry. A method for suppressing such tilting or falling over will be explained with reference to Figures 7 to 12.

[0036] Figure 6 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0037] Figure 6, similar to Figure 5, shows a YZ cross-section of the semiconductor device of this embodiment. As shown in Figure 6, the semiconductor device of this embodiment comprises a laminated film 2, an interlayer insulating film 3, and an interlayer insulating film 12 formed on a plurality of insulating films 6. The interlayer insulating film 12 is, for example, a TEOS film or an SiO2 film.

[0038] Figure 7 is a plan view showing the structure of a comparative example of the first embodiment.

[0039] The semiconductor device of this comparative example has the same structure as the semiconductor device of the first embodiment, as shown in Figures 1 to 6. However, while the semiconductor device of the first embodiment has the structure shown in Figure 8, which will be described later, the semiconductor device of this comparative example has the structure shown in Figure 7.

[0040] Figures 7(a), 7(b), and 7(c) show the three support columns 5 within the laminated film 2 (staircase section R2) of this comparative example. Figure 7(a) shows the planar shape (XY cross-sectional shape) of the upper support column 5-3 within each support column 5, Figure 7(b) shows the planar shape of the intermediate support column 5-2 within each support column 5, and Figure 7(c) shows the planar shape of the lower support column 5-1 within each support column 5.

[0041] As shown in Figure 7(a), each upper support section 5-3 in this comparative example has an elliptical shape in plan view. Figure 7(a) shows the major axis L1 and minor axis L2 of this ellipse (L1 > L2). In each upper support section 5-3 in this comparative example, the major axis L1 is parallel to the X direction, and therefore the angle between the X direction and the major axis L1 is 0 degrees. Also, in each upper support section 5-3 in this comparative example, the minor axis L2 is perpendicular to the X direction, and therefore the angle between the X direction and the minor axis L2 is 90 degrees. As a result, in each upper support section 5-3 in this comparative example, the angle between the X direction and the major axis L1 is smaller than the angle between the X direction and the minor axis L2.

[0042] This is also true for each intermediate support section 5-2 in this comparative example. As shown in Figure 7(b), each intermediate support section 5-2 in this comparative example has an elliptical shape in plan view. This ellipse also has the major axis L1 and minor axis L2 described above. In each intermediate support section 5-2 in this comparative example, the major axis L1 is parallel to the X direction, and the minor axis L2 is perpendicular to the X direction.

[0043] This is also true for each lower support section 5-1 in this comparative example. As shown in Figure 7(c), each lower support section 5-1 in this comparative example has an elliptical shape in plan view. This ellipse also has the major axis L1 and minor axis L2 described above. In each lower support section 5-1 in this comparative example, the major axis L1 is parallel to the X direction, and the minor axis L2 is perpendicular to the X direction.

[0044] In this specification, the term "major axis L1" is used to refer to both the line segment indicated by the symbol "L1" and the length of the line segment indicated by the symbol "L1". Similarly, in this specification, the term "minor axis L2" is used to refer to both the line segment indicated by the symbol "L2" and the length of the line segment indicated by the symbol "L2". For example, in the sentence, "The angle between the X direction and the major axis L1 is smaller than the angle between the X direction and the minor axis L2," the terms major axis L1 and minor axis L2 are used to refer to line segments. In this sense, major axis L1 and minor axis L2 are also called the major axis and minor axis, respectively. On the other hand, in the sentence, "Figure 7(a) shows the major axis L1 and minor axis L2 of this ellipse (L1>L2)," the terms major axis L1 and minor axis L2 are used to refer to the length of the line segment. In this sense, major axis L1 and minor axis L2 are also expressed as the "length of the major axis" and the "length of the minor axis," respectively.

[0045] Figure 8 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0046] Figures 8(a), 8(b), and 8(c) show the three support columns 5 within the laminated film 2 (staircase section R2) of this embodiment. Figure 8(a) shows the planar shape (XY cross-sectional shape) of the upper support column 5-3 within each support column 5, Figure 8(b) shows the planar shape of the intermediate support column 5-2 within each support column 5, and Figure 8(c) shows the planar shape of the upper support column 5-1 within each support column 5.

[0047] As shown in Figure 8(a), each upper support section 5-3 of this embodiment has an elliptical shape in plan view. Figure 8(a) shows the major axis L1 and minor axis L2 of this ellipse (L1 > L2). In each upper support section 5-3 of this embodiment, the major axis L1 is parallel to the X direction, and therefore the angle between the X direction and the major axis L1 is 0 degrees. Also, in each upper support section 5-3 of this embodiment, the minor axis L2 is perpendicular to the X direction, and therefore the angle between the X direction and the minor axis L2 is 90 degrees. As a result, in each upper support section 5-3 of this embodiment, the angle between the X direction and the major axis L1 is smaller than the angle between the X direction and the minor axis L2. Each upper support section 5-3 of this embodiment is an example of a first partial support section and an example of a third partial support section. Furthermore, the major axis L1 and minor axis L2 of each upper support column 5-3 in this embodiment are examples of the first major axis and the first minor axis, and also examples of the third major axis and the third minor axis.

[0048] This is also true for each intermediate support section 5-2 of this embodiment. As shown in Figure 8(b), each intermediate support section 5-2 of this embodiment has an elliptical shape in plan view. This ellipse also has the major axis L1 and minor axis L2 described above. In each intermediate support section 5-2 of this embodiment, the major axis L1 is parallel to the X direction, and the minor axis L2 is perpendicular to the X direction. Each intermediate support section 5-2 of this embodiment is also an example of a first partial support section and an example of a third partial support section. Furthermore, the major axis L1 and minor axis L2 of each intermediate support section 5-2 of this embodiment are also examples of a first major axis and a first minor axis, and examples of a third major axis and a third minor axis.

[0049] As shown in Figure 8(c), each lower support column 5-1 in this embodiment has an elliptical shape in plan view. This ellipse also has the major axis L1 and minor axis L2 described above. However, in each lower support column 5-1 in this embodiment, the major axis L1 is perpendicular to the X direction, and therefore the angle between the X direction and the major axis L1 is 90 degrees. Furthermore, in each lower support column 5-1 in this embodiment, the minor axis L2 is parallel to the X direction, and therefore the angle between the X direction and the minor axis L2 is 0 degrees. As a result, in each lower support column 5-1 in this embodiment, the angle between the X direction and the major axis L1 is greater than the angle between the X direction and the minor axis L2. Each lower support column 5-1 in this embodiment is an example of a second partial support column and an example of a fourth partial support column. Furthermore, the major axis L1 and minor axis L2 of each lower support column 5-1 in this embodiment are examples of a second major axis and a second minor axis, and examples of a fourth major axis and a fourth minor axis.

[0050] As shown in Figure 8(a), the planar shape of each upper support section 5-3 in this embodiment is an ellipse with a major axis L1 parallel to the X direction and a minor axis L2 perpendicular to the X direction. Hereafter, such a support section will be referred to as a "horizontal support." On the other hand, the planar shape of each lower support section 5-1 in this embodiment is an ellipse with a major axis L1 perpendicular to the X direction and a minor axis L2 parallel to the X direction, as shown in Figure 8(c). Hereafter, such a support section will be referred to as a "vertical support." Each support section 5 in this embodiment includes the upper support section 5-3 of the horizontal support, the intermediate support section 5-2 of the horizontal support, and the lower support section 5-1 of the vertical support.

[0051] In this embodiment, the lower support section 5-1 within each support section 5, i.e., the lowest support section, is a vertical support. Furthermore, the upper support section 5-3 within each support section 5, i.e., the highest support section, is a horizontal support. Furthermore, the intermediate support sections 5-2 within each support section 5, i.e., the support sections other than the lowest and highest, are horizontal supports.

[0052] In this embodiment, the major axis of the lower support section 5-1, the major axis of the intermediate support section 5-2, and the major axis of the upper support section 5-3 may be the same value (L1) or they may be different values. For example, if bowing occurs on the side of the hole when forming the hole for each support section 5, these major axes may be different values. Also, as shown in Figure 12 later, these major axes may be intentionally set to different values. Similarly, in this embodiment, the minor axis of the lower support section 5-1, the minor axis of the intermediate support section 5-2, and the minor axis of the upper support section 5-3 may be the same value (L2) or they may be different values.

[0053] Furthermore, the planar shape of each lower support portion 5-1 in this embodiment does not have to be a mathematically precise ellipse, but may be a figure that can be recognized as an ellipse (for example, an egg or an oblong). Moreover, the planar shape of each lower support portion 5-1 in this embodiment may be another figure having dimensions that can be recognized as a major axis L1 and dimensions that can be recognized as a minor axis L2. Examples of such figures are rhombuses and rectangles. In the case of a rhombuse, the lengths of the two diagonals of the rhombus can be recognized as the major axis L1 and minor axis L2. In the case of a rectangle, the lengths of the long side and short side of the rectangle can be recognized as the major axis L1 and minor axis L2. Therefore, the planar shape of each lower support portion 5-1 in this embodiment may be, for example, a figure that is close to a rhombus or a figure that is close to a rectangle.

[0054] Figure 9 is a plan view showing first to eighth examples of the structure of the semiconductor device according to the first embodiment.

[0055] In the first example, each support section 5 includes an upper support section 5-3 of a horizontal support, an intermediate support section 5-2 of a horizontal support, and a lower support section 5-1 of a horizontal support. Therefore, each support section 5 in the first example includes three horizontal supports.

[0056] In the second example, each support section 5 includes the upper support section 5-3 of the vertical support, the intermediate support section 5-2 of the horizontal support, and the lower support section 5-1 of the horizontal support. In the third example, each support section 5 includes the upper support section 5-3 of the horizontal support, the intermediate support section 5-2 of the horizontal support, and the lower support section 5-1 of the vertical support. In the fourth example, each support section 5 includes the upper support section 5-3 of the horizontal support, the intermediate support section 5-2 of the vertical support, and the lower support section 5-1 of the horizontal support. Therefore, each support section 5 in the second to fourth examples includes two horizontal supports and one vertical support.

[0057] In the fifth example, each support section 5 includes the upper support section 5-3 of the horizontal support, the intermediate support section 5-2 of the vertical support, and the lower support section 5-1 of the vertical support. In the sixth example, each support section 5 includes the upper support section 5-3 of the vertical support, the intermediate support section 5-2 of the vertical support, and the lower support section 5-1 of the horizontal support. In the seventh example, each support section 5 includes the upper support section 5-3 of the vertical support, the intermediate support section 5-2 of the horizontal support, and the lower support section 5-1 of the vertical support. Therefore, each support section 5 in the fifth to seventh examples includes one horizontal support and two vertical supports.

[0058] In the eighth example, each support section 5 includes an upper support section 5-3 of a vertical support, an intermediate support section 5-2 of a vertical support, and a lower support section 5-1 of a vertical support. Therefore, each support section 5 in the eighth example includes three vertical supports.

[0059] The displacement of each finger section F is described below. The displacement of each finger section F is the difference in the Y coordinate between the lower end and the upper end of each finger section F. The larger the displacement of each finger section F, the greater the tilt of each finger section F in the Y direction. Therefore, the larger the displacement of each finger section F, the more likely each finger section F is to tip over in the Y direction.

[0060] To investigate the effect of the vertical supports on the displacement of each finger section F, the displacements of Examples 1 to 3 were compared. The comparison revealed that the displacement of Example 2 was smaller than that of Example 1, and the displacement of Example 3 was smaller than that of Example 2 (Example 1 > Example 2 > Example 3). This result suggests that the displacement of the finger section F including the vertical supports is smaller than that of the finger section F without the vertical supports. This is presumably because the vertical supports extend in the Y direction, making it easier to suppress the increase in the displacement of each finger section F in the Y direction.

[0061] Therefore, each support column 5 in this embodiment shown in Figures 8(a) to 8(c) includes a vertical support column (lower support column 5-1). This makes it possible to effectively suppress the tilting and falling of each finger portion F compared to each support column 5 in the comparative example shown in Figures 7(a) to 7(c).

[0062] Furthermore, each support column 5 shown in Figures 8(a) to 8(c) includes a lower support column 5-1 of the vertical column, similar to Example 3. The reason is that, according to the results of Example 2 and Example 3, the displacement of the finger column F that includes the vertical column at a lower position is smaller than the displacement of the finger column F that includes the vertical column at a higher position. As a result, it is possible to effectively suppress the tilting and falling of each finger column F compared to Example 2.

[0063] Furthermore, each support section 5 shown in Figures 8(a) to 8(c) may further include an upper support section 5-3 or an intermediate support section 5-2 of a vertical support, similar to Example 5 or Example 7. Alternatively, each support section 5 shown in Figures 8(a) to 8(c) may further include an upper support section 5-3 and an intermediate support section 5-2 of a vertical support, similar to Example 8. However, the horizontal support has the effect of suppressing defects in the word wire (electrode layer 2b) within each finger section F. Therefore, it is desirable that each support section 5 in this embodiment includes one vertical support and two horizontal support sections, or two vertical support sections and one horizontal support section.

[0064] (1) First variation Figure 10 is a cross-sectional view showing the structure of a semiconductor device of a first modified example of the first embodiment.

[0065] Figures 10(a), 10(b), and 10(c) show the four support columns 5 within the laminated film 2 (staircase section R2) of this modified example. Figures 10(a) to 10(c) correspond to Figures 8(a) to 8(c), respectively.

[0066] Here, the number of vertical and horizontal supports within each support section 5 will be represented by Na and Nb, respectively. The semiconductor device of this modified example includes not only support sections 5 with Na=1 and Nb=2, but also support sections 5 with Na≠1 and Nb≠2. For example, Figures 10(a) to 10(c) show two support sections 5 with Na=1 and Nb=2, one support section 5 with Na=2 and Nb=1, and one support section 5 with Na=0 and Nb=3. Furthermore, the two support sections 5 with Na=1 and Nb=2 include a support section 5 containing the lower support section 5-1 of the vertical support, and a support section 5 containing the upper support section 5-3 of the vertical support. Thus, the semiconductor device of this modified example may include various types of support sections 5.

[0067] However, if the total number of support columns 5 in the semiconductor device of this modified example is represented by K, then it is desirable that the total number K1 of "lower support columns 5-1 of the vertical support columns" in the semiconductor device of this modified example is greater than 50% of K (K1 > 0.5K). This makes it possible to obtain the same effect as in Example 3.

[0068] In this case, it is desirable that the total number K2 of the "intermediate support portion 5-2 of the vertical support" or the total number K3 of the "upper support portion 5-3 of the vertical support" in the semiconductor device of this modified example is greater than 50% of K (K2 > 0.5K, or K3 > 0.5K). This makes it possible to obtain the same effect as in Example 5 or Example 7.

[0069] Furthermore, it is desirable that the condition K1 > 0.5K be satisfied for each finger section F in this modified example. Specifically, if the total number of support sections 5 within each finger section F in this modified example is represented by k, it is desirable that the total number k1 of "lower support sections 5-1 of the vertical support" within each finger section F in this modified example is greater than 50% of k (k1 > 0.5k).

[0070] In this modified example, it is desirable that the total number k2 of "intermediate support sections 5-2 of vertical supports" within each finger section F, or the total number k3 of "upper support sections 5-3 of vertical supports" within each finger section F, is greater than 50% of k (k2 > 0.5k, or k3 > 0.5k).

[0071] (2) Second variation Figure 11 is a cross-sectional view showing the structure of a semiconductor device of a second modified example of the first embodiment.

[0072] Figures 11(a), 11(b), and 11(c) show the three support columns 5 within the laminated film 2 (staircase section R2) of this modified example. Figures 11(a) to 11(c) correspond to Figures 8(a) to 8(c), respectively.

[0073] Each lower support column 5-1 in this modified example has a shape similar to a vertical support column. Specifically, the major axis L1 of each lower support column 5-1 is not perpendicular to the X direction, and the minor axis L2 of each lower support column 5-1 is not parallel to the X direction, but the angle between the X direction and the major axis L1 is greater than the angle between the X direction and the minor axis L2 (Figure 11(c)).

[0074] Furthermore, each intermediate support section 5-2 in this modified example has a shape similar to a horizontal support. Specifically, the major axis L1 of each intermediate support section 5-2 is not parallel to the X direction, and the minor axis L2 of each intermediate support section 5-2 is not perpendicular to the X direction, but the angle between the X direction and the major axis L1 is smaller than the angle between the X direction and the minor axis L2 (Figure 11(b)).

[0075] Similarly, each upper support section 5-3 in this modified example has a shape similar to a horizontal support. Specifically, the major axis L1 of each upper support section 5-3 is not parallel to the X direction, and the minor axis L2 of each upper support section 5-3 is not perpendicular to the X direction, but the angle between the X direction and the major axis L1 is smaller than the angle between the X direction and the minor axis L2 (Figure 11(a)).

[0076] This modified version makes it possible to obtain the same effect as in Example 3. Note that in Figure 11(c), the angle between the X direction and the major axis L1, and the angle between the X direction and the minor axis L2 may differ for each individual lower support column 5-1. The same applies to Figures 11(b) and 11(a).

[0077] (3) Third modified example Figure 12 is a cross-sectional view showing the structure of a semiconductor device of a third modified example of the first embodiment.

[0078] Figures 12(a), 12(b), and 12(c) show the four support columns 5 within the laminated film 2 (staircase section R2) of this modified example. Figures 12(a) to 12(c) correspond to Figures 8(a) to 8(c), respectively.

[0079] In this modified example, the lower support section 5-1, the intermediate support section 5-2, and the upper support section 5-3 of these support sections 5 include not only support sections having a major axis L1 and a minor axis L2, but also support sections having a major axis L1' and a minor axis L2'. In this modified example, the length of the major axis L1' is different from the length of the major axis L1 (L1'≠L1), and the length of the minor axis L2' is different from the length of the minor axis L2 (L2'≠L2). However, in this modified example, the length of the major axis L1' may be equal to the length of the major axis L1 (L1'=L1), or the length of the minor axis L2' may be equal to the length of the minor axis L2 (L2'=L2). Figures 12(a) to 12(c) illustrate three lower support sections 5-1, three intermediate support sections 5-2, and three upper support sections 5-3 having major axis L1 and minor axis L2, and one lower support section 5-1, one intermediate support section 5-2, and one upper support section 5-3 having major axis L1' and minor axis L2'.

[0080] In Figure 12(a), the major axis L1 (or L1') of each upper support section 5-3 is parallel to the X direction, and the minor axis L2 (or L2') of each upper support section 5-3 is perpendicular to the X direction. In Figure 12(b), the major axis L1 (or L1') of each intermediate support section 5-2 is parallel to the X direction, and the minor axis L2 (or L2') of each intermediate support section 5-2 is perpendicular to the X direction. In Figure 12(c), the major axis L1 (or L1') of each lower support section 5-1 is perpendicular to the X direction, and the minor axis L2 (or L2') of each lower support section 5-1 is parallel to the X direction. Therefore, each support section 5 in this modified example includes the lower support section 5-1 of the vertical support, the intermediate support section 5-2 of the horizontal support, and the upper support section 5-3 of the horizontal support.

[0081] According to this modified example, the same effects as in Example 3 can be obtained. In this modified example, the semiconductor device is equipped with a lower support section 5-1, an intermediate support section 5-2, and an upper support section 5-3 having two types of major axes (L1, L1') and minor axes (L2, L2'). Alternatively, the lower support section 5-1, intermediate support section 5-2, and upper support section 5-3 may be equipped with three or more types of major and minor axes.

[0082] As described above, each support column 5 in this embodiment includes one or more vertical support columns and one or more horizontal support columns, for example, a lower support column 5-1 of the vertical support column, an intermediate support column 5-2 of the horizontal support column, and an upper support column 5-3 of the horizontal support column. Therefore, according to this embodiment, it is possible to suitably divide the laminated film 2 into a plurality of finger portions F. For example, according to this embodiment, by forming a support column 5 including vertical support columns, it is possible to suppress tilting or falling over of each finger portion F due to the stepped portion R2 or the like in the laminated film 2.

[0083] Furthermore, the first to third modifications described above are applicable not only to the first embodiment but also to the second embodiment described later.

[0084] (Second Embodiment) Figure 13 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0085] Figure 13, like Figures 5 and 6, shows a YZ cross-section of the semiconductor device of this embodiment, specifically a YZ cross-section of the laminated film 2 (staircase portion R2) of this embodiment. The semiconductor device of this embodiment has the same components as the semiconductor device of the first embodiment. However, the semiconductor device of this embodiment includes a plurality of crosslinked portions 11 formed on a plurality of insulating films 6 and covered with interlayer insulating films 12.

[0086] Each crosslinked portion 11 is formed on a corresponding insulating film 6. In Figure 13, each crosslinked portion 11 is formed continuously on the upper surface of the insulating film 6, the upper surface of the finger portion F (or interlayer insulating film 3) in the +Y direction of the insulating film 6, and the upper surface of the finger portion F (or interlayer insulating film 3) in the -Y direction of the insulating film 6. As a result, each crosslinked portion 11 bridges the finger portion F (or interlayer insulating film 3) in the +Y direction of the insulating film 6 and the finger portion F (or interlayer insulating film 3) in the -Y direction of the insulating film 6. In this embodiment, each crosslinked portion 11 is provided, for example, to suppress deformation of each finger portion F. Figure 13 shows three crosslinked portions 11 formed on the upper surfaces of three insulating films 6.

[0087] Each crosslinked portion 11 is, for example, an insulating film, and examples of such insulating films include SiO2 films and insulating metal compound films such as metal oxide films. On the other hand, the interlayer insulating film 12 is, for example, a TEOS film or an SiO2 film.

[0088] Figure 14 is a plan view showing the structure of the semiconductor device of the second embodiment.

[0089] Figure 14 shows one of the four finger portions F shown in Figure 13, and two of the three insulating films 6 shown in Figure 13. Figure 14 further shows multiple crosslinking portions 11 formed on each insulating film 6. In Figure 14, three crosslinking portions 11 are arranged on one insulating film 6.

[0090] Furthermore, the semiconductor device of this embodiment may not only have multiple crosslinking portions 11 on each insulating film 6 within the stepped portion R2, but may also have multiple crosslinking portions 11 on each insulating film 6 within the non-stepped portion R1.

[0091] Figure 15 is a plan view showing the structure of the semiconductor device of the second embodiment.

[0092] Figures 15(a), 15(b), and 15(c) show the three support columns 5 within the laminated film 2 (staircase section R2) of this embodiment. Figure 15(a) shows the planar shape (XY cross-sectional shape) of the upper support column 5-3 within each support column 5, Figure 15(b) shows the planar shape of the intermediate support column 5-2 within each support column 5, and Figure 15(c) shows the planar shape of the upper support column 5-1 within each support column 5.

[0093] Figures 15(a) to 15(c) correspond to Figures 8(a) to 8(c), respectively. In the first embodiment, each support column 5 includes an upper support column 5-3 of the horizontal support column, an intermediate support column 5-2 of the horizontal support column, and a lower support column 5-1 of the vertical support column, as shown in Figures 8(a) to 8(c). On the other hand, in this embodiment, each support column 5 includes an upper support column 5-3 of the horizontal support column, an intermediate support column 5-2 of the vertical support column, and a lower support column 5-1 of the horizontal support column, as shown in Figures 15(a) to 15(c).

[0094] In this embodiment, each support column 5 may include an upper support column 5-3 of a vertical support column, an intermediate support column 5-2 of a horizontal support column, and a lower support column 5-1 of a horizontal support column. In other words, in each support column 5 of this embodiment, all support columns except the lowest one may be vertical supports.

[0095] Next, referring again to Figure 9, we will describe the first to eighth examples of the structure of the semiconductor device of this embodiment.

[0096] Examples 1 to 8 shown in Figure 9 are common to both the first embodiment and this embodiment. However, the influence of the vertical support on the displacement of each finger portion F differs between examples 1 to 8 of the first embodiment and examples 1 to 8 of this embodiment. Examples 1 to 8 of this embodiment will be described below.

[0097] To investigate the effect of the vertical supports on the displacement of each finger section F, the displacements of Examples 1 to 3 were compared. The comparison revealed that the displacement of Example 3 was almost the same as that of Example 1, and the displacement of Example 2 was smaller than that of Example 1 and Example 3 (Example 1 ≈ Example 3 > Example 2). According to these results, the displacement of a finger section F with a vertical support at a high position is smaller than the displacement of a finger section F without a vertical support, and also smaller than the displacement of a finger section F with a vertical support at a low position.

[0098] The semiconductor device of the first embodiment does not have a crosslinking portion 11 on each insulating film 6 (Figure 6), but the semiconductor device of this embodiment has a crosslinking portion 11 on each insulating film 6 (Figure 13). Therefore, in the first embodiment, the position of the lower end of each finger portion F does not change easily in the Y direction, while the position of the upper end of each finger portion F does change easily in the Y direction, whereas in this embodiment, both the position of the lower end and the upper end of each finger portion F does not change easily in the Y direction. In this embodiment, the position of the portion near the upper end, that is, the position of the portion within the upper laminated film 2-3 and the intermediate laminated film 2-2, changes easily in the Y direction. This is expected to be the reason why, in this embodiment, the displacement of the finger portion F with a vertical support at a high position is smaller than the displacement of the finger portion F without a vertical support, and the displacement of the finger portion F with a vertical support at a low position.

[0099] Therefore, as described with reference to Figures 15(a) to 15(c), it is desirable that each support column 5 in this embodiment includes either the upper support column 5-3 or the intermediate support column 5-2 of the vertical support column. Such configurations are illustrated in Examples 2 and 4, etc. This makes it possible to effectively suppress the tilting and falling of each finger column F in this embodiment.

[0100] Furthermore, each support column 5 in this embodiment may include an upper support column 5-3 and an intermediate support column 5-2 of the vertical support column. Such a configuration is illustrated in Example 6, etc. Alternatively, each support column 5 in this embodiment may include an upper support column 5-3, an intermediate support column 5-2, and a lower support column 5-1 of the vertical support column. However, the horizontal support column has the effect of suppressing malfunctions of the word wire (electrode layer 2b) in each finger portion F. Therefore, it is desirable that each support column 5 in this embodiment includes one vertical support column and two horizontal support columns, or two vertical support columns and one horizontal support column.

[0101] As a result, considering Examples 2, 4, and 6, in each of the support sections 5 of this embodiment, it is desirable that the lower support section 5-1 be a horizontal support, and that at least one of the intermediate support section 5-2 and the upper support section 5-3 be a vertical support.

[0102] According to this embodiment, similar to the first embodiment, the laminated film 2 can be suitably divided into a plurality of finger portions F.

[0103] Furthermore, when the semiconductor device of the first or second embodiment is manufactured by bonding substrate 1 to another substrate, the finished semiconductor device does not need to have substrate 1. An example of such a semiconductor device will be described in the third embodiment.

[0104] (Third embodiment) Figure 16 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0105] The semiconductor device of this embodiment comprises an array chip 21 and a circuit chip 22 bonded together. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer containing the array chip 21 and a circuit wafer containing the circuit chip 22 together.

[0106] The array chip 21 comprises a memory cell array 31 containing multiple memory cells, an insulating film 32 on the memory cell array 31, and an interlayer insulating film 33 below the memory cell array 31. The insulating film 32 is, for example, an SiO2 film. The interlayer insulating film 33 is, for example, a laminated film containing an SiO2 film and other insulating films. A portion of the memory cell array 31 in this embodiment corresponds to the laminated film 2 of the first or second embodiment.

[0107] The circuit chip 22 is located beneath the array chip 21. The symbol S indicates the bonding surface between the array chip 21 and the circuit chip 22. The circuit chip 22 comprises an interlayer insulating film 34 beneath the interlayer insulating film 33 and a substrate 35 beneath the interlayer insulating film 34. The interlayer insulating film 34 is, for example, a multilayer film including an SiO2 film and other insulating films. The substrate 35 is, for example, a semiconductor substrate such as a Si substrate.

[0108] Figure 16 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 35, and the Z direction, which is perpendicular to the surface of the substrate 35. The X, Y, and Z directions intersect each other. In this embodiment, as in the first and second embodiments, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0109] The array chip 21 includes multiple word lines WL as multiple electrode layers within the memory cell array 31. Figure 16 shows a stepped structure 41 within the memory cell array 31 and multiple support columns 42 provided within the stepped structure 41. Each word line WL extends in the X direction and is electrically connected to the word wiring layer 44 via a contact plug 43. Each columnar portion CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 45 and is also electrically connected to the source line SL. The bit line BL extends in the Y direction and is located below the multiple word lines WL. The source line SL extends in the X direction and is located above the multiple word lines WL. The stepped structure 41, support columns 42, columnar portion CL, and word lines WL in this embodiment correspond to the stepped portion R2, support column 5, columnar portion 4, and electrode layer 2b of the first or second embodiment, respectively.

[0110] The circuit chip 22 comprises a plurality of transistors 51. Each transistor 51 includes a gate insulating film 51a and a gate electrode 51b, which are sequentially provided on the substrate 35, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 35. The circuit chip 22 also comprises a plurality of contact plugs 52 provided on the gate electrode 51b, source diffusion layer, or drain diffusion layer of the plurality of transistors 51. The circuit chip 22 also comprises a wiring layer 53, a wiring layer 54, and a wiring layer 55. The wiring layer 53 contains a plurality of wires and is provided on the plurality of contact plugs 52. The wiring layer 54 contains a plurality of wires and is provided on the wiring layer 53. The wiring layer 55 contains a plurality of wires and is provided on the wiring layer 54.

[0111] The circuit chip 22 further comprises a plurality of via plugs 56 provided on the wiring layer 55, and a plurality of metal pads 57 provided on the plurality of via plugs 56. The metal pads 57 are, for example, metal layers including a Cu (copper) layer. The circuit chip 22 functions as a logic circuit that controls the operation of the array chip 21. This logic circuit is composed of transistors 51 and the like, and is electrically connected to the metal pads 57.

[0112] The array chip 21 comprises a plurality of metal pads 61 provided on the plurality of metal pads 57, and a plurality of via plugs 62 provided on the plurality of metal pads 61. The metal pads 61 are, for example, metal layers including a Cu layer. The array chip 21 also comprises a wiring layer 63 and a wiring layer 64. The wiring layer 63 includes a plurality of wires and is provided on the plurality of via plugs 62. The wiring layer 64 includes a plurality of wires and is provided on the wiring layer 63. The bit line BL is contained within the wiring layer 64. The logic circuit is electrically connected to the memory cell array 31 via the metal pads 61, 57, etc., and controls the operation of the memory cell array 31 via the metal pads 61, 57, etc.

[0113] The array chip 21 further comprises a plurality of via plugs 65 provided on the wiring layer 64, and metal pads 66 provided on the plurality of via plugs 65 and on the insulating film 32. The array chip 21 also comprises a passivation insulating film 67 provided on the metal pads 66 and on the insulating film 32. The metal pads 66 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device in this embodiment. The passivation insulating film 67 is, for example, a multilayer film including an SiO2 film and a SiN film, and has an opening P that exposes the upper surface of the metal pads 66. The metal pads 66 can be electrically connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc. through the opening P.

[0114] In this embodiment, a plurality of insulating films 6 (not shown) of the first or second embodiment extend in the X direction within the memory cell array 31. In addition, in this embodiment, a plurality of crosslinking portions 11 (not shown) of the second embodiment may be formed beneath these insulating films 6.

[0115] Figures 17 and 18 are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment.

[0116] Figure 17 shows an array wafer W1 containing multiple array chips 21 and a circuit wafer W2 containing multiple circuit chips 22. The orientation of the array wafer W1 in Figure 17 is the opposite of the orientation of the array chips 21 in Figure 16. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 17 shows the array wafer W1 before its orientation is reversed for bonding, and Figure 16 shows the array chips 21 after their orientation has been reversed for bonding, and after bonding and dicing.

[0117] In Figure 17, reference numeral S1 indicates the upper surface of the array wafer W1, and reference numeral S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 36 provided beneath the insulating film 32. The substrate 36 is, for example, a semiconductor substrate such as a Si substrate. The substrate 36 in this embodiment corresponds to the substrate 1 in the first or second embodiment.

[0118] In this embodiment, first, as shown in Figure 17, a memory cell array 31, an insulating film 32, an interlayer insulating film 33, a metal pad 61, a via plug 65, etc. are formed on the substrate 36 of the array wafer W1, and an interlayer insulating film 34, a transistor 51, a metal pad 57, etc. are formed on the substrate 35 of the circuit wafer W2. Next, as shown in Figure 18, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that surfaces S1 and S2 face each other. This bonds the interlayer insulating film 33 and the interlayer insulating film 34. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 61 and the metal pad 57. In this way, the substrate 36 and the substrate 35 are bonded together via the interlayer insulating films 33 and 34.

[0119] Subsequently, the substrate 36 is removed by CMP (Chemical Mechanical Polishing), and the substrate 35 is thinned by CMP. Then, the array wafer W1 and the circuit wafer W2 are cut into multiple chips (dicing). In this way, the semiconductor device shown in Figure 16 is manufactured. The metal pad 66 and the passivation insulating film 67 are formed on the insulating film 32 after the removal of the substrate 36 and the thinning of the substrate 35.

[0120] Figure 16 shows the interface between the interlayer insulating film 33 and the interlayer insulating film 34, and the interface between the metal pad 61 and the metal pad 57. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated, for example, by detecting the inclination of the side surfaces of the metal pad 61 and the metal pad 57, or by detecting the positional displacement between the side surfaces of the metal pad 61 and the metal pad 57.

[0121] According to this embodiment, the semiconductor device and its manufacturing method according to the first or second embodiment can be applied to this embodiment.

[0122] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the apparatus described herein without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of Symbols]

[0123] 1: Substrate, 2: Multilayer film, 2a: Insulating film, 2b: Electrode layer, 2-1: Lower multilayer film, 2-2: Intermediate multilayer film, 2-3: Upper multilayer film, 3: Interlayer insulating film, 4: Columnar portion, 4a: Block insulating film, 4b: Charge storage layer, 4c: Tunnel insulating film, 4d: Channel semiconductor layer, 4e: Core insulating film 4-1: Lower columnar section, 4-2: Intermediate columnar section, 4-3: Upper columnar section, 5: Support column, 5a: Insulating film, 5-1: Lower support section, 5-2: Intermediate support section, 5-3: Upper support section, 6: Insulating film, 11: Crosslinked section, 12: Interlayer insulating film, 21: Array chip, 22: Circuit chip, 31: Memory cell array, 32: Insulating film, 33: Interlayer insulating film, 34: Interlayer insulating film, 35: Substrate, 36: Substrate, 41: Stair structure part, 42: Support part, 43: Contact plug, 44: Word wiring layer, 45: Via plug, 51: Transistor, 51a: Gate insulating film, 51b: Gate electrode, 52: Contact plug, 53: Wiring layer, 54: Wiring layer, 55: Wiring layer, 56: Via plug, 57: Metal pad, 61: Metal pad, 62: Via plug, 63: Wiring layer, 64: Wiring layer, 65: Via plug, 66: Metal pad, 67: Passivation insulating film

Claims

1. A laminated film comprising a plurality of first insulating films and a plurality of electrode layers alternately in a first direction, and including a non-staircase portion and a staircase portion provided in a second direction of the non-staircase portion, A first columnar portion including a charge storage layer and a semiconductor layer provided within the non-stepped portion, The staircase portion includes a first support column portion which includes a second insulating film, The laminated film includes a plurality of partial laminated films stacked in the first direction, The first support portion includes a plurality of partial support portions provided within the plurality of partial laminated films, The plurality of partial support sections within the first support section are, One or more first partial support columns having a first major axis and a first minor axis in plan view, wherein the angle between the second direction and the first major axis is smaller than the angle between the second direction and the first minor axis, It includes one or more second partial support columns, having a second major axis and a second minor axis in plan view, wherein the angle between the second direction and the second major axis is greater than the angle between the second direction and the second minor axis. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the one or more second partial support sections include the lowest partial support section among the plurality of partial support sections within the first support section.

3. The semiconductor device according to claim 2, wherein the one or more first partial support sections include the uppermost partial support section among the plurality of partial support sections within the first support section.

4. The semiconductor device according to claim 2, wherein the one or more first partial support sections include partial support sections other than the lowest and highest of the plurality of partial support sections within the first support section.

5. The laminated film includes a plurality of first plate-like portions that extend in the first and second directions and are adjacent to each other in the third direction. The laminated film is provided with a plurality of second plate-like portions that extend in the first and second directions and are arranged alternately with the plurality of first plate-like portions in the third direction, No bridging portion is provided on the upper surface of each of the aforementioned plurality of second plate-like portions. The semiconductor device according to claim 2.

6. The semiconductor device according to claim 1, wherein the one or more first partial support sections include the lowest partial support section among the plurality of partial support sections within the first support section.

7. The semiconductor device according to claim 6, wherein the one or more second partial support sections include the uppermost partial support section among the plurality of partial support sections within the first support section.

8. The semiconductor device according to claim 6, wherein the one or more second partial support sections include partial support sections other than the lowest and highest of the plurality of partial support sections within the first support section.

9. The laminated film includes a plurality of first plate-like portions that extend in the first and second directions and are adjacent to each other in the third direction. A plurality of second plate-like portions are provided within the laminated film, extending in the first and second directions, and alternately provided with the plurality of first plate-like portions in the third direction, The system further comprises a plurality of bridging portions provided on the upper surfaces of the plurality of second plate-like portions, The semiconductor device according to claim 6.

10. The semiconductor device according to claim 1, wherein one or more first partial support columns have a first major axis parallel to the second direction and a first minor axis perpendicular to the second direction.

11. The semiconductor device according to claim 1, wherein one or more second partial support columns have a second major axis perpendicular to the second direction and a second minor axis parallel to the second direction.

12. The semiconductor device according to claim 1, wherein the length of the first major axis is equal to the length of the second major axis.

13. The semiconductor device according to claim 1, wherein the length of the first minor axis is equal to the length of the second minor axis.

14. The second support column portion, which includes the second insulating film provided within the staircase portion, The second support portion includes a plurality of partial support portions provided within the plurality of partial laminated films, The plurality of partial support sections within the second support section are, One or more third partial support columns having a third major axis and a third minor axis in plan view, wherein the angle between the second direction and the third major axis is smaller than the angle between the second direction and the third minor axis, It includes one or more fourth partial support columns having a fourth major axis and a fourth minor axis in plan view, wherein the angle between the second direction and the fourth major axis is greater than the angle between the second direction and the fourth minor axis, The semiconductor device according to claim 1.

15. The one or more second partial support sections include the lowest partial support section among the plurality of partial support sections within the first support section. The semiconductor device according to claim 14, wherein the one or more third partial support sections include the lowest partial support section among the plurality of partial support sections within the second support section.

16. The length of the first major axis is different from at least the length of the second major axis, the third major axis, and the fourth major axis, and / or The semiconductor device according to claim 14, wherein the length of the first minor axis is different from the length of at least one of the second minor axis, the third minor axis, and the fourth minor axis.

Images