Semiconductor manufacturing equipment

Abstract

To provide semiconductor manufacturing equipment that can perform electrochemical processing more easily. [Solution] The semiconductor device according to this embodiment comprises a plurality of processing tanks, an anode and a cathode, and an electrical circuit. Each of the plurality of processing tanks is capable of containing a substrate processing liquid and a first substrate. An anode and a cathode are provided for each processing tank. The electrical circuit electrically connects the plurality of first substrates held in the substrate processing liquid via the anode and cathode, and supplies power via the anode and cathode to perform electrochemical processing on the plurality of first substrates, thereby forming a semiconductor manufacturing apparatus.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor manufacturing equipment.

Background Art

[0002] In an anodizing apparatus for anodizing a substrate (silicon wafer), it is necessary to hold the silicon wafer in a liquid-tight state in a chemical solution tank. Also, when fixing the silicon wafer, it may be necessary to tightly seal it using an O-ring or the like. In this case, it is difficult to automate the introduction of the silicon wafer into the anodizing apparatus, and the development of a manufacturing apparatus assuming mass production (for example, a batch processing apparatus) becomes difficult.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] To provide semiconductor manufacturing equipment that can perform electrochemical processing more easily. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment comprises a plurality of processing tanks, an anode and a cathode, and an electrical circuit. Each of the plurality of processing tanks is capable of containing a substrate processing liquid and a first substrate. An anode and a cathode are provided for each processing tank. The electrical circuit electrically connects the plurality of first substrates held in the substrate processing liquid via the anode and cathode, and supplies power via the anode and cathode to perform electrochemical processing on the plurality of first substrates, thereby forming a semiconductor manufacturing apparatus. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows the structure of the semiconductor manufacturing apparatus according to the first embodiment. [Figure 2] This is a cross-sectional view (1 / 2) showing the structure of the substrate processing apparatus of the first embodiment. [Figure 3] This is a cross-sectional view (2 / 2) showing the structure of the substrate processing apparatus of the first embodiment. [Figure 4] This is an enlarged cross-sectional view showing the structure of the substrate processing apparatus according to the first embodiment. [Figure 5] This figure shows the electrode structure of a modified example of the first embodiment. [Figure 6] This is an enlarged cross-sectional view showing the structure of the substrate processing apparatus according to the first embodiment. [Figure 7] It is a perspective view showing the structure of the substrate holder of the first embodiment. [Figure 8] It is a cross-sectional view showing the structure of the substrate holder of the first embodiment. [Figure 9A] It is a cross-sectional view (1 / 3) showing the movement of the substrate held by the substrate holder of the first embodiment. [Figure 9B] It is a cross-sectional view (2 / 3) showing the movement of the substrate held by the substrate holder of the first embodiment. [Figure 9C] It is a cross-sectional view (3 / 3) showing the movement of the substrate held by the substrate holder of the first embodiment. [Figure 10] It is an enlarged cross-sectional view showing the structure of the substrate processing apparatus of the second embodiment. [Figure 11] It is a cross-sectional view showing the structure of the substrate processing apparatus of the third embodiment. [Figure 12] It is a cross-sectional view showing the structure of the semiconductor device of the fourth embodiment. [Figure 13] It is an enlarged cross-sectional view showing the structure of the semiconductor device of the fourth embodiment. [Figure 14A] It is a cross-sectional view (1 / 2) showing the manufacturing method of the semiconductor device of the fourth embodiment.... [Figure 14B] It is a cross-sectional view (1 / 2) showing the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 14C] It is a cross-sectional view (1 / 2) showing the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 15A] It is a cross-sectional view (full) showing the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 15B] It is a cross-sectional view (full) showing the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 15C] It is a cross-sectional view (full) showing the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 16A] It is a cross-sectional view (1 / 5) showing the details of the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 16B] It is a cross-sectional view (1 / 5) showing the details of the manufacturing method of the semiconductor device of the fourth embodiment. [Figure 17A]This is a cross-sectional view (2 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 17B] This is a cross-sectional view (2 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 18A] This is a cross-sectional view (3 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 18B] This is a cross-sectional view (3 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 19A] This is a cross-sectional view (4 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 19B] This is a cross-sectional view (4 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 20A] This is a cross-sectional view (5 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 20B] This is a cross-sectional view (5 / 5) showing details of the manufacturing method for the semiconductor device according to the fourth embodiment. [Figure 21] This is a cross-sectional view showing the structure of a semiconductor device of a modified example of the fourth embodiment. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0009] (First Embodiment) Figure 1 shows the structure of the semiconductor manufacturing apparatus 100 according to the first embodiment.

[0010] The semiconductor manufacturing apparatus 100 includes a transport device 201, a wafer supply device 202 (wafer loader), a substrate processing device 101, a cleaning device 203, and a drying device 204.

[0011] The transport device 201 transports the transport carrier C between the wafer supply device 202, the substrate processing device 101, the cleaning device 203, and the drying device 204. The transport carrier C can accommodate multiple substrates W.

[0012] The wafer supply device 202 supplies multiple substrates W, which are housed in one transport carrier C, to another transport carrier C.

[0013] The substrate processing apparatus 101 processes multiple substrates W. The substrate processing apparatus 101 is a batch processing apparatus.

[0014] The cleaning device 203 cleans the multiple substrates W that have been processed by the substrate processing device 101. The cleaning device 203 performs a rinsing process.

[0015] The drying device 204 dries the multiple substrates W that have been cleaned by the cleaning device 203.

[0016] Next, we will describe the details of the substrate processing apparatus 101.

[0017] Figures 2 and 3 are cross-sectional views showing the structure of the substrate processing apparatus 101 according to the first embodiment.

[0018] The substrate processing apparatus 101 is a device for processing the substrate W, and is, for example, an anodic deposition apparatus for forming a porous layer on the surface of the substrate W by an anodic deposition method. Figures 2 and 3 show different longitudinal sections of the substrate processing apparatus 101.

[0019] Figures 2 and 3 show the X, Y, and Z directions perpendicular to each other. In this specification, the +Z direction is treated as the up direction, and the -Z direction is treated as the down direction. Furthermore, the direction parallel to the Z direction is treated as the up and down direction, and the direction perpendicular to the Z direction is treated as the horizontal direction. The -Z direction may or may not coincide with the direction of gravity.

[0020] The substrate processing apparatus 101 comprises an outer container 111, an inner container 112, a partition wall 113, an electrode 131, an electrode 132, and an electrical circuit 133.

[0021] As shown in Figures 2 and 3, an inner container 112 is placed inside an outer container 111, and a partition wall 113 is placed inside the inner container 112. As a result, the inner container 112 forms a storage tank T which includes an inner tank T1 inside the partition wall 113 and an outer tank T2 between the partition wall 113 and the inner container 112. The storage tank T stores an electrolyte solution. The electrolyte solution is supplied to the inner tank T1 from a weighing tank (not shown), and the electrolyte solution that overflows from the inner tank T1 over the partition wall 113 is collected in the outer tank T2. The inner tank T1 can accommodate multiple substrates W. The planar shape of these substrates W is, for example, circular or rectangular. The planar shape of the substrate W illustrated in Figure 2 is circular. The storage tank T, electrolyte solution, and substrates W are examples of a processing tank, substrate processing liquid, and first substrate, respectively. The substrates W are, for example, semiconductor wafers such as Si (silicon) wafers.

[0022] Multiple electrodes 131 and 132 are provided. The substrate W, illustrated in Figure 3, is positioned between electrodes 131 and 132. Details of the configuration of electrodes 131, 132, the substrate W, and their surroundings will be explained later with reference to Figure 4.

[0023] In the example shown in Figure 2, electrodes 131 and 132 are arranged in an inner tank T1 and are used to electrically process each substrate W. Each substrate W is held between electrodes 131 and 132 in the inner tank T1. Electrodes 131 and 132 can process multiple substrates W simultaneously (batch processing). For example, if electrode 131 is the anode and electrode 132 is the cathode, a porous layer can be formed on the electrode 132 side of each substrate W by anodization. The electrode 132 side of each substrate W is an example of the first surface, and the electrode 131 side of each substrate W is an example of the second surface. Each substrate W is held by a substrate holder 162 such that the former surface faces the electrode 132 side and the latter surface faces the electrode 131 side.

[0024] The electrical circuit 133 supplies power to electrodes 131 and 132. Details of the electrical circuit 133 will be explained later, referring to Figure 4.

[0025] Figure 4 is an enlarged cross-sectional view showing the structure of the substrate processing apparatus 101 of the first embodiment.

[0026] Figure 4 shows the inner container 112, electrodes 131 and 132, electrical circuit 133, and storage tank T (inner tank T1) as described above. The substrate processing apparatus 101 further includes a control unit 155, as shown in Figure 4.

[0027] Figure 4 further shows the electrolyte L contained in the inner tank T1. The electrolyte L corresponds to the electrolyte solution described above. The electrolyte L is, for example, an aqueous solution of HF (hydrogen fluoride).

[0028] In Figure 4, electrode 131 is the anode and electrode 132 is the cathode, and a porous layer is formed on the electrode 132 side of each substrate W by anodizing. The porous layer is formed, for example, by making a material layer that has been previously formed on the electrode 132 side of each substrate W porous. If the material layer is a polysilicon layer (semiconductor layer), the porous layer becomes a porous polysilicon layer (porous semiconductor layer). The material layer is an example of the first layer. On the other hand, the porous layer may also be formed within each substrate W by making a part of each substrate W porous near the electrode 132 side of each substrate W.

[0029] The control unit 155 controls various operations of the substrate processing apparatus 101. For example, the control unit 155 controls the operation of electrical circuits 133 and other components to carry out the anodic deposition process.

[0030] The inner tank T1 has multiple inner tanks T11 to T1n (where n is a natural number greater than or equal to 2). The number of inner tanks T11 to T1n is, for example, 25, but is not limited to this.

[0031] Each of the inner tanks T11 to T1n is capable of containing the electrolyte L and the substrate W.

[0032] Electrodes 131 and 132 are provided in each inner chamber T11 to T1n. That is, each inner chamber T11 to T1n is provided with a pair of electrodes 131 and 132.

[0033] The substrate W shown in Figure 4 is fixed to the electrode 131.

[0034] The electrical circuit 133 includes a connection circuit 1331 and a power supply unit 1332.

[0035] The connection circuit 1331 electrically connects multiple substrates W (internal cells T11 to T1n) held in the electrolyte L via electrodes 131 and 132. The connection circuit 1331 illustrated in Figure 4 connects multiple substrates W (internal cells T11 to T1n) in the electrolyte L in series via electrodes 131 and 132.

[0036] The power supply unit 1332 performs anodic deposition on multiple substrates W by energizing electrodes 131 and 132, that is, by supplying power through electrodes 131 and 132. The power supply unit 1332 is, for example, a current source. The power supply unit 1332 supplies power through electrodes 131 and 132 by controlling the current flowing through the multiple substrates W using current control. With current control, a uniform current flows through all substrates W.

[0037] Next, we will describe the details of the structure of electrode 131.

[0038] The planar shape of electrode 131 is, for example, the same as the planar shape of substrate W. The planar shape of electrode 131 is, for example, circular.

[0039] The material requirements for electrode 131 are, for example, that it does not dissolve in HF solution, is not oxidized at the Si anodic oxidation potential (-1.2V vs. NHE), is not reduced at the hydrogen evolution potential (0V vs. NHE), and is less easily reduced than oxygen.

[0040] Electrode 131 includes, for example, a base metal that is less susceptible to oxidation (has a higher standard potential) than the substrate W material (e.g., Si), a compound semiconductor that is less susceptible to oxidation than the substrate W material, carbon, or a conductive polymer. Base metals that are less susceptible to oxidation than the substrate W material include, for example, W, Mo, Co, Cu, or Zn. Compound semiconductors that are less susceptible to oxidation than the substrate W material include, for example, InTiO or IGZO.

[0041] Conductive polymers include, for example, polyacetylene, poly(p-phenylenevinylene), polypyrrole, polythiophene, polyaniline, or poly(p-phenylene sulfide).

[0042] Figure 5 shows the structure of the electrode 131 in a modified version of the first embodiment. The modified version of the first embodiment differs from the first embodiment in that a coating film 131c is provided.

[0043] The electrode 131 includes a coating film 131c that covers at least a portion of the electrode 131. The coating film 131c is conductive. The coating film 131c contains a material different from the material of the electrode 131. The coating film 131c is provided on the surface of the electrode 131 in the region that is in direct contact with the substrate W. This prevents the coating film 131c from directly contacting the electrode 131 with the substrate W, and prevents the substrate W from being contaminated by the material of the electrode 131.

[0044] The material requirements for the coating film 131c are, for example, that it is insoluble in HF solution and not oxidized to the Si anodic oxidation potential (-1.2V vs. NHE).

[0045] The electrode 131 contains, for example, a precious metal such as platinum (Pt). The coating film 131c contains, for example, a conductive polymer. Note that if the coating film 131c contains a conductive polymer, the electrode 131 is not limited to a precious metal and may contain materials other than conductive polymers as described above.

[0046] Next, we will explain the details of how to hold the substrate W.

[0047] Figure 6 is an enlarged cross-sectional view showing the structure of the substrate processing apparatus 101 of the first embodiment.

[0048] The substrate processing apparatus 101 further comprises an electrode holder 161 and a substrate holder 162. Note that the substrate holder 162 is omitted in Figure 6.

[0049] The electrode holder 161 holds multiple electrodes 131. The electrode holder 161 also holds the electrodes 131 so that the electrodes 131 on which the substrate W is held can be inserted into and removed from the electrolyte L.

[0050] The substrate holder 162 is capable of holding the substrate W so as to fix the substrate W to the electrode 131.

[0051] The multiple electrodes 132 are fixed, for example, to each of the inner chambers T11 to T1n.

[0052] Figure 7 is a perspective view showing the structure of the substrate holder 162 of the first embodiment. Figure 8 is a cross-sectional view showing the structure of the substrate holder 162 of the first embodiment.

[0053] The substrate processing apparatus 101 further includes a jig 131j. The jig 131j holds the electrode 131. The jig 131j illustrated in Figure 7 holds the outer periphery of the electrode 131. The electrode 131 illustrated in Figure 8 is in contact with the second surface of the substrate W.

[0054] The substrate holder 162 is capable of holding the substrate W such that the first surface of the substrate W is exposed to the electrolyte L. The portion of the substrate holder 162 that fixes the substrate W has, for example, an annular shape. The substrate holder 162 and the electrode 131 are provided so as to sandwich the outer periphery of the substrate W.

[0055] Furthermore, O-rings 162a and 162b are provided. O-ring 162a is provided between the substrate holder 162 and the substrate W. O-ring 162b is provided between the substrate W and the electrode 131 (jig 131j). The O-ring 162b prevents the electrolyte L from entering the second surface side of the substrate W.

[0056] Figures 9A to 9C are cross-sectional views showing the movement of the substrate W held in the substrate holder 162 of the first embodiment.

[0057] First, as shown in Figure 9A, the wafer supply device 202 supplies the substrate W, which is housed in the transport carrier C, onto the electrode 131.

[0058] Next, as shown in Figure 9B, the substrate holder 162 securely fixes multiple substrates W to each of the multiple electrodes 131.

[0059] Next, as shown in Figure 9C, the transport device 201 places the electrodes 131 and the substrate W into the electrolyte L. The electrode holder 161 holds the multiple electrodes 131 so that they can be moved in and out of the electrolyte L of the inner tanks T11 to T1n. Note that the substrate holder 162 is omitted in Figure 9C.

[0060] As shown in Figures 9A to 9C, multiple substrates W are fixed to multiple electrodes 131 by substrate holders 162 and placed in electrolyte L. This eliminates the need to fix the substrates W to be anodized in a liquid-tight state. As a result, the automation of introducing multiple substrates W into the substrate processing apparatus 101 can be made easier. In addition, the electrode holders 161 and substrate holders 162 make it easier to process multiple substrates W simultaneously (batch processing).

[0061] As described above, according to the first embodiment, each of the multiple inner tanks T11 to T1n is capable of containing electrolyte L and substrate W. The connection circuit 1331 electrically connects the multiple substrates W held in the electrolyte L via electrodes 131 and 132. The power supply unit 1332 supplies power via electrodes 131 and 132 to perform anodic deposition on the multiple substrates W. This allows multiple substrates W to be anodized simultaneously (batch processing), and a porous layer can be formed on the surface of the substrates W in a batch manner. Therefore, anodic deposition can be performed more easily.

[0062] Furthermore, the first embodiment is not limited to anodic conversion treatment and may be used for other electrochemical treatments. In other electrochemical treatments, the electrode 132 (cathode) may be fixed to the substrate W and be able to be moved in and out of the electrolyte L.

[0063] Furthermore, as explained with reference to Figures 9A to 9C, the automation of introducing multiple substrates W into the substrate processing apparatus 101 can be made easier. In addition, the electrode holder 161 and substrate holder 162 make it easier to process multiple substrates W simultaneously (batch processing).

[0064] Furthermore, the substrate holder 162 illustrated in Figures 7 and 8 is a mechanical holding mechanism, but it may also be a vacuum chuck.

[0065] In addition, additives such as surfactants and alcohols (e.g., IPA) may be added to the electrolyte L.

[0066] (Second Embodiment) Figure 10 is an enlarged cross-sectional view showing the structure of the substrate processing apparatus 101 of the second embodiment. The second embodiment differs from the first embodiment in that multiple substrates W are connected in parallel.

[0067] The connection circuit 1331 connects multiple substrates W (internal cells T11 to T1n) in the electrolyte L in parallel via electrodes 131 and 132.

[0068] The substrate processing apparatus 101 further comprises a reference electrode 163. The reference electrode 163 is located inside one of the inner chambers T11 to T1n. The reference electrode 163 is, for example, a hydrogen electrode or an Ag / AgCl electrode.

[0069] The power supply unit 1332 is, for example, a voltage source. Based on the detection result of the reference electrode 163, the power supply unit 1332 supplies power via electrode 131 (working electrode) and electrode 132 (counter electrode) by voltage control, which controls the voltage applied to the multiple substrates W. The power supply unit 1332 controls the potential of electrode 131, which is the working electrode, using the reference electrode (3-electrode system).

[0070] In the second embodiment, compared to the first embodiment, multiple substrates W are connected in parallel. This allows voltage to be supplied to electrodes 131 and 132 by voltage control. In the case of series connection and current control, the voltage applied to each substrate W may not necessarily be the same depending on the condition of each substrate W. In contrast, in the second embodiment, the voltage applied to each substrate W (each inner chamber T11 to T1n) can be made more equal, and the anodic deposition of each substrate W can be made more uniform. As a result, variations between substrates W in batch processing can be suppressed.

[0071] Furthermore, in the second embodiment, any voltage that causes anodizing of Si can be applied to each substrate W.

[0072] Furthermore, in the second embodiment, even if the number of substrates to be processed increases, it is possible to suppress the increase in the total applied voltage. In the case of series connection and current control, the more substrates W to be processed, the larger the overall voltage becomes. In contrast, in the second embodiment, the same voltage can be supplied to all substrates W1 (internal chambers T11 to T1n). Therefore, the more substrates W to be processed, the more preferable parallel connection and voltage control become.

[0073] As in the second embodiment, multiple substrates W may be connected in parallel. The semiconductor manufacturing apparatus 100 according to the second embodiment can obtain the same effects as the first embodiment.

[0074] (Third embodiment) Figure 11 is a cross-sectional view showing the structure of the substrate processing apparatus 101 of the third embodiment. The third embodiment differs from the first embodiment in that the electrolyte L in the inner tanks T11 to T1n is circulated.

[0075] The substrate processing apparatus 101 further comprises an electrolyte supply unit 153 and an electrolyte discharge unit 153a. The electrolyte supply unit 153 and the electrolyte discharge unit 153a are provided for each inner tank T11 to T1n.

[0076] The electrolyte supply unit 153 supplies electrolyte L into the inner tanks T11 to T1n. In this embodiment, the electrolyte supply unit 153 circulates the electrolyte L within the substrate processing apparatus 101 by supplying the electrolyte L discharged from the inner tanks T11 to T1n back into the storage tank T.

[0077] The electrolyte discharge section 153a discharges the electrolyte L from within the inner tanks T11 to T1n. The electrolyte discharge section 153a discharges reaction by-products of the anodic conversion treatment (e.g., SiF6). 2- The electrolyte L is discharged as waste liquid containing the reaction byproducts. If reaction byproducts accumulate in the inner tanks T11 to T1n, the chemical equilibrium may be disrupted, making it difficult for the desired reaction to occur. Discharging the reaction byproducts can suppress the decrease in reaction efficiency.

[0078] Therefore, the electrolyte supply unit 153 and the electrolyte discharge unit 153a, which serve as circulation paths, circulate the electrolyte L in the inner tanks T11 to T1n at a substantially constant flow rate during the anodic conversion process so as to maintain a substantially constant concentration (HF and surfactant) of the electrolyte L (chemical solution) near the substrate W.

[0079] The substrate processing apparatus 101 may also be further equipped with a temperature control unit. The temperature control unit controls the temperature of the electrolyte L supplied by the electrolyte supply unit 153. For example, if the temperature of the electrolyte L in the inner tanks T11 to T1n rises due to the application of voltage, the supplied electrolyte L may be temperature-controlled to cool the electrolyte L in the inner tanks T11 to T1n.

[0080] As in the third embodiment, the electrolyte L in the inner tanks T11 to T1n may be circulated. The semiconductor manufacturing apparatus 100 according to the third embodiment can obtain the same effects as the first embodiment. Furthermore, the semiconductor manufacturing apparatus 100 according to the third embodiment may be combined with the second embodiment.

[0081] (Fourth Embodiment) Figure 12 is a cross-sectional view showing the structure of a semiconductor device according to the fourth embodiment. The semiconductor device in Figure 12 is, for example, a three-dimensional flash memory.

[0082] The semiconductor device shown in Figure 12 comprises a circuit region 1 including a CMOS (Complementary Metal Oxide Semiconductor) circuit and an array region 2 including a memory cell array. The memory cell array has multiple memory cells for storing data, and the CMOS circuit includes peripheral circuits that control the operation of the memory cell array. The semiconductor device shown in Figure 12 is manufactured, for example, by bonding a circuit wafer including the circuit region 1 and an array wafer including the array region 2, as will be described later. The symbol S indicates the bonding surface between the circuit region 1 and the array region 2.

[0083] In Figure 12, circuit region 1 comprises a substrate 11, a transistor 12, an interlayer insulating film 13, a plurality of contact plugs 14, a wiring layer 15 containing a plurality of wires, a via plug 16, and a metal pad 17. Figure 12 shows three of the plurality of wires in the wiring layer 15 and the three contact plugs 14 provided beneath these wires. Substrate 11 is an example of a second substrate.

[0084] In Figure 12, the array region 2 comprises an interlayer insulating film 21, a metal pad 22, a via plug 23, a wiring layer 24 containing multiple wirings, multiple contact plugs 25, a laminated film 26, multiple columnar portions 27, a source layer 28, and an insulating film 29. Figure 12 shows one of the multiple wirings in the wiring layer 24, and three contact plugs 25 and three columnar portions 27 provided on this wiring.

[0085] Furthermore, as shown in Figure 12, the laminated film 26 includes a plurality of electrode layers 31 and a plurality of insulating layers 32. Each columnar portion 27 includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The source layer 28 includes a semiconductor layer 37 and a metal layer 38.

[0086] The structure of the semiconductor device of this embodiment will be described below with reference to Figure 12.

[0087] The substrate 11 is, for example, a semiconductor substrate such as a Si substrate. The transistor 12 comprises a gate insulating film 12a and a gate electrode 12b formed sequentially on the substrate 11, and a source diffusion layer and a drain diffusion layer (not shown) formed within the substrate 11. The transistor 12 constitutes, for example, the CMOS circuit described above. The interlayer insulating film 13 is formed on the substrate 11 so as to cover the transistor 12. The interlayer insulating film 13 is, for example, an SiO2 film (silicon oxide film), or a multilayer film including an SiO2 film and other insulating films.

[0088] The contact plug 14, wiring layer 15, via plug 16, and metal pad 17 are formed within the interlayer insulating film 13. Specifically, the contact plug 14 is located on the substrate 11 or on the gate electrode 12b of the transistor 12. In Figure 12, the contact plug 14 on the substrate 11 is located on the source diffusion layer and drain diffusion layer (not shown) of the transistor 12. The wiring layer 15 is located on the contact plug 14, and the via plug 16 is located on the wiring layer 15. The metal pad 17 is located above the substrate 11 and on the via plug 16. The metal pad 17 is, for example, a metal layer containing a Cu (copper) layer.

[0089] The interlayer insulating film 21 is formed on the interlayer insulating film 13. The interlayer insulating film 21 is, for example, an SiO2 film, or a laminated film including an SiO2 film and other insulating films.

[0090] The metal pad 22, via plug 23, wiring layer 24, and contact plug 25 are formed within the interlayer insulating film 21. Specifically, the metal pad 22 is located on the metal pad 17 above the substrate 11. The metal pad 22 is, for example, a metal layer containing a Cu layer. The via plug 23 is located on the metal pad 22, and the wiring layer 24 is located on the via plug 23. Figure 12 shows one of several wirings within the wiring layer 24, which functions, for example, as a bit line. The contact plug 25 is located on the wiring layer 24.

[0091] The laminated film 26 is provided on an interlayer insulating film 21 and includes a plurality of electrode layers 31 and a plurality of insulating layers 32 that are alternately stacked in the Z direction. The electrode layer 31 is, for example, a metal layer including a W (tungsten) layer and functions as a word line. The insulating layer 32 is, for example, an SiO2 film.

[0092] Each columnar portion 27 is provided within the laminated film 26 and includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The memory insulating film 33 is formed on the side surface of the laminated film 26 and has a tubular shape extending in the Z direction. The channel semiconductor layer 34 is formed on the side surface of the memory insulating film 33 and has a tubular shape extending in the Z direction. The core insulating film 35 and the core semiconductor layer 36 are formed on the side surface of the channel semiconductor layer 34 and have a rod-shaped shape extending in the Z direction. Specifically, the core semiconductor layer 36 is arranged on the contact plug 25, and the core insulating film 35 is arranged on the core semiconductor layer 36.

[0093] The memory insulating film 33, as described later, includes, for example, a block insulating film, a charge storage layer, and a tunnel insulating film in that order. The block insulating film is, for example, an SiO2 film. The charge storage layer is, for example, a SiN film (silicon nitride film). The tunnel insulating film is, for example, an SiO2 film or a SiON film (silicon oxynitride film). The channel semiconductor layer 34 is, for example, a polysilicon layer. The core insulating film 35 is, for example, an SiO2 film. The core semiconductor layer 36 is, for example, a polysilicon layer. Each memory cell in the memory cell array described above is composed of the channel semiconductor layer 34, a charge storage layer, an electrode layer 31, etc.

[0094] The channel semiconductor layer 34 and core semiconductor layer 36 within each columnar portion 27 are electrically connected to the metal pad 22 via contact plugs 25, wiring layers 24, and via plugs 23. Thus, the memory cell array in array region 2 is electrically connected to the peripheral circuit in circuit region 1 via the metal pads 22 and 17. This makes it possible to control the operation of the memory cell array by the peripheral circuit.

[0095] The source layer 28 includes a semiconductor layer 37 and a metal layer 38 formed sequentially on the laminated film 26 and the columnar portion 27, and functions as a source wire. In this embodiment, the channel semiconductor layer 34 of each columnar portion 27 is exposed from the memory insulating film 33, and the semiconductor layer 37 is formed directly on the channel semiconductor layer 34. Furthermore, the metal layer 38 is formed directly on the semiconductor layer 37. Thus, the source layer 28 is electrically connected to the channel semiconductor layer 34 and the core semiconductor layer 36 of each columnar portion 27. The semiconductor layer 37 is, for example, a polysilicon layer. The metal layer 38 includes, for example, a W layer, a Cu layer, or an Al (aluminum) layer.

[0096] The insulating film 29 is formed on the source layer 28. The insulating film 29 is, for example, an SiO2 film.

[0097] Figure 13 is an enlarged cross-sectional view showing the structure of the semiconductor device of the fourth embodiment.

[0098] Figure 13 shows three electrode layers 31 and three insulating layers 32 contained within the laminated film 26, and one columnar portion 27 provided within the laminated film 26. The memory insulating film 33 within this columnar portion 27 includes, as described above, a block insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c, which are formed sequentially on the side surface of the laminated film 26. The block insulating film 33a is, for example, an SiO2 film. The charge storage layer 33b is, for example, a SiN film. The tunnel insulating film 33c is, for example, an SiO2 film or a SiON film.

[0099] On the other hand, each electrode layer 31 includes a barrier metal layer 31a and an electrode material layer 31b. The barrier metal layer 31a is, for example, a TiN film (titanium nitride film). The electrode material layer 31b is, for example, a W layer. As shown in Figure 13, each electrode layer 31 in this embodiment is formed on the lower surface of the upper insulating layer 32, the upper surface of the lower insulating layer 32, and the side surface of the block insulating film 33a via a block insulating film 39. The block insulating film 39 is, for example, an Al2O3 film (aluminum oxide film) and functions as a block insulating film of each memory cell together with the block insulating film 33a.

[0100] Figures 14A to 14C and 15A to 15C are cross-sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment. The semiconductor device of this embodiment is manufactured by bonding a circuit wafer W1 and an array wafer W2, which will be described later. The circuit wafer W1 is used to manufacture circuit region 1, and the array wafer W2 is used to manufacture array region 2. The circuit wafer W1 and the array wafer W2 have a disc shape.

[0101] First, a substrate 41 for the array wafer W2 is prepared (Figure 14A). The substrate 41 is, for example, a semiconductor substrate such as a Si substrate. Substrate 41 corresponds to the substrate W in the first embodiment. Substrate 41 is an example of the first substrate.

[0102] Next, a porous layer 42 is formed on the substrate 41 (Figure 14B). The porous layer 42 is, for example, a porous semiconductor layer such as a porous polysilicon layer. The porous layer 42 is formed, for example, by forming a material layer for forming the porous layer 42 on the substrate 41 and creating voids in the material layer. In other words, the porous layer 42 is formed by making the material layer porous. If the material layer is a polysilicon layer (semiconductor layer), the porous layer 42 becomes a porous polysilicon layer (porous semiconductor layer). Porousizing the material layer is performed, for example, by setting the substrate 41 with the material layer formed on it in the substrate processing apparatus 101 described above and applying an anodic deposition method to the material layer. As a result, the material layer is transformed into a porous layer 42 by the anodic deposition method. The material layer is an example of the first layer. The porous layer 42 may be formed in the substrate 41 or on the substrate 41 via other layers.

[0103] Next, a cap insulating film 43 is formed on the porous layer 42 (Figure 14C). The cap insulating film 43 includes an insulating film 43a formed on the porous layer 42 and an insulating film 43b formed on the insulating film 43a. The insulating film 43a is, for example, an SiO2 film. The insulating film 43b is, for example, a SiN film.

[0104] Next, an insulating film 44 is formed on the cap insulating film 43 (Figure 15A). The insulating film 44 is, for example, an SiO2 film.

[0105] Next, a laminated film 26 and an interlayer insulating film 21 are formed sequentially on the insulating film 44 (Figures 15B and 15C). Details of the laminated film 26 and the interlayer insulating film 21 are as described above with reference to Figure 12. Figures 15B and 15C schematically show the structure of the laminated film 26 and the interlayer insulating film 21. The steps shown in Figures 15B and 15C, and subsequent steps, will be described later with reference to Figures 16A to 20B.

[0106] Figures 16A to 20B are cross-sectional views showing details of the manufacturing method for a semiconductor device according to the fourth embodiment.

[0107] Figures 16A to 17B show details of the process shown in Figures 15B and 15C. First, an insulating film 44 is formed on the cap insulating film 43, and a laminated film 26' is formed on the insulating film 44 (Figure 16A). The laminated film 26' is a film for forming the laminated film 26 by a replacement process. The laminated film 26' is formed to alternately include a plurality of sacrificial layers 31' and a plurality of insulating layers 32. The sacrificial layer 31' is, for example, a SiN film.

[0108] Next, multiple memory holes H1 are formed that penetrate the laminated film 26' and the insulating film 44, and a memory insulating film 33, a channel semiconductor layer 34, and a core insulating film 35 are sequentially formed within each memory hole H1 (Figure 16A). As a result, multiple columnar portions 27 extending in the Z direction are formed within these memory holes H1. The memory insulating film 33 is formed by sequentially forming a block insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c within each memory hole H1 (see Figure 13).

[0109] Next, an insulating film 45 is formed on the laminated film 26' and the columnar portion 27 (Figure 16A). The insulating film 45 is, for example, an SiO2 film.

[0110] Next, a slit (not shown) is formed through the insulating film 45 and the laminated film 26', and the sacrificial layer 31' is removed by wet etching using the slit (Figure 16B). As a result, multiple cavities H2 are formed between the insulating layers 32 within the laminated film 26'.

[0111] Next, multiple electrode layers 31 are formed within these cavities H2 through the slits (Figure 17A). As a result, a laminated film 26, which alternately includes multiple electrode layers 31 and multiple insulating layers 32, is formed between the insulating film 44 and the insulating film 45 (replacement process). Furthermore, a structure is formed above the substrate 41 in which the multiple columnar portions 27 penetrate the laminated film 26. When forming the electrode layers 31 within each cavity H2, a block insulating film 39, a barrier metal layer 31a, and an electrode material layer 31b are formed sequentially within each cavity H2 (see Figure 13).

[0112] Next, the insulating film 45 is removed, a portion of the core insulating film 35 within each columnar portion 27 is removed, and a core semiconductor layer 36 is embedded in the area where a portion of the core insulating film 35 was removed (Figure 17B). As a result, each columnar portion 27 is processed into a structure including a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36.

[0113] Next, an interlayer insulating film 21, metal pads 22, via plugs 23, a wiring layer 24, and a plurality of contact plugs 25 are formed on the laminated film 26 and the columnar portion 27 (Figure 17B). In this process, each of the contact plugs 25 is formed on the core semiconductor layer 36 of the corresponding columnar portion 27, and the wiring layer 24, via plugs 23, and metal pads 22 are formed sequentially on these contact plugs 25. Note that Figure 17B shows the same state as shown in Figure 15C.

[0114] Figure 18A shows the process of bonding a circuit wafer W1 and an array wafer W2 (bonding process). The circuit wafer W1 shown in Figure 18A is manufactured by preparing a substrate 11 and forming transistors 12, an interlayer insulating film 13, a plurality of contact plugs 14, a wiring layer 15, via plugs 16, and metal pads 17 on the substrate 11 (see Figure 12). In this process, the transistors 12 are formed on the substrate 11, and their contact plugs 14 are formed on the substrate 11 or on the transistors 12. Furthermore, the wiring layer 15, via plugs 16, and metal pads 17 are formed sequentially on these contact plugs 14.

[0115] Next, the orientation of the array wafer W2 is reversed, and the circuit wafer W1 and the array wafer W2 are bonded together by mechanical pressure (Figure 18A). As a result, the interlayer insulating film 13 and the interlayer insulating film 21 are bonded together. Next, the circuit wafer W1 and the array wafer W2 are annealed (Figure 18A). As a result, the metal pads 17 and 22 are bonded together. In this way, the substrate 11 and the substrate 41 are bonded together with the interlayer insulating films 13, 21, the laminated film 26, the insulating film 44, the cap insulating film 43, and the porous layer 42 sandwiched between them, and the substrate 41 is stacked on top of the substrate 11. Each metal pad 22 is placed on the corresponding metal pad 17.

[0116] Next, a physical force F is applied to the array wafer W2 using a blade or water jet (Figure 18B). For example, force F is applied to the cross-section of the porous layer 42. As a result, the porous layer 42 is fractured. This allows the substrate 11 and substrate 41 to be separated (Figure 19A). In Figures 18A and 19A, force F is applied to the cross-section of the porous layer 42, causing the porous layer 42 to fracture, thus separating the substrate 11 and substrate 41 at the location of the porous layer 42. As a result, a portion of the porous layer 42 remains on the surface of substrate 41, and the remainder of the porous layer 42 remains on the surface of substrate 11. Furthermore, the memory cell array and CMOS circuit described above also remain on the surface of substrate 11. The porous layer 42 is divided into a portion on the substrate 41 side and a portion on the substrate 11 side. The former portion is an example of the first portion, and the latter portion is an example of the second portion. The porous layer 42 functions as a separation layer (exfoliation layer) for separating (exfoliating) the substrate 41 from the substrate 11.

[0117] The porous layer 42 in this embodiment contains numerous voids and is therefore prone to cracking. Thus, applying a force F to the porous layer 42 can cause it to break. Alternatively, the substrate 11 and substrate 41 may be separated by the rupture of a material other than the porous layer 42 (e.g., a cap insulating film 43), either in place of or together with the porous layer 42. In this case, the force F may be applied to this material.

[0118] In this embodiment, instead of grinding the substrate 41, the substrate 41 is removed from the substrate 11 by peeling it off. This makes it possible to prevent damage to the substrate 41 and to reuse the substrate 41. In this embodiment, after separating the substrate 11 and the substrate 41, the porous layer 42 and other materials remaining on the surface of the substrate 41 are removed, and the substrate 41 is reused in the bonding process shown in Figure 18A. This makes it possible to avoid the waste of using multiple substrates 41. The force F applied to the porous layer 42 may be applied mechanically, such as by a blade, or fluidly, such as by a water jet, or by other means.

[0119] Next, the porous layer 42 and the cap insulating film 43 on top of the substrate 11 are removed (Figure 19B). As a result, the insulating film 44 and each columnar portion 27 are exposed on top of the substrate 11. The process shown in Figure 19B is performed, for example, by CMP (Chemical Mechanical Polishing) or etching. In the process shown in Figure 19B, the substrate 11 may be further thinned by CMP or etching.

[0120] Next, the insulating film 44 and a portion of the memory insulating film 33 of each columnar portion 27 are removed by etching (Figure 20A). The portion of the memory insulating film 33 that is removed is, for example, the portion exposed from the laminated film 26. As a result, a portion of the channel semiconductor layer 34 of each columnar portion 27 is exposed from the memory insulating film 33 at a position higher than the laminated film 26.

[0121] Next, a semiconductor layer 37, a metal layer 38, and an insulating film 29 are formed sequentially on the laminated film 26 and the columnar portions 27 (Figure 20B). As a result, the source layer 28 is formed on the channel semiconductor layer 34 of each columnar portion 27 and is electrically connected to the channel semiconductor layer 34 of each columnar portion 27.

[0122] Subsequently, the circuit wafer W1 and array wafer W2 are cut into multiple chips. These chips are cut so that each chip contains a circuit region 1 and an array region 2. In this way, the semiconductor device shown in Figure 12 is manufactured.

[0123] The semiconductor device of this embodiment may be sold in the state shown in Figure 12, or in the state shown in Figure 17B or Figure 18A.

[0124] Figure 21 is a cross-sectional view showing the structure of a modified semiconductor device of the fourth embodiment. The semiconductor device described with reference to Figures 12 to 20B may have the structure shown in Figure 21 instead of the structure shown in Figure 12.

[0125] The semiconductor device of this modified example comprises a circuit region 1 and an array region 2, similar to the semiconductor device of the fourth embodiment. In addition to the components shown in Figure 12, the circuit region 1 includes wiring layers 15' and 15'' that electrically connect the wiring layer 15 and the via plug 16. In addition to the components shown in Figure 12, the array region 2 includes a wiring layer 24' that electrically connects the via plug 23 and the wiring layer 24. Each of the wiring layers 15', 15'', and 24' contains multiple wirings, similar to the wiring layer 15 and the wiring layer 24.

[0126] Figure 21 shows multiple word lines WL (electrode layers 31) within the laminated film 26, multiple columnar portions 27 penetrating the laminated film 26, and a stepped structure 51 of the laminated film 26. Each word line WL is electrically connected to the word wiring layer 53 via a contact plug 52 at the stepped structure 51. Each columnar portion 27 is electrically connected to the bit line BL via a contact plug 25 and is also electrically connected to the source layer 28. In this modified example, the word wiring layer 53 and bit line BL are included in the wiring layer 24.

[0127] The array region 2 further includes a plurality of via plugs 61 provided on the wiring layer 24, metal pads 62 provided on these via plugs 61 and the insulating film 29, and a passivation film 63 provided on the metal pads 62 and the insulating film 29. The passivation film 63 is a multilayer insulating film including, for example, a silicon oxide film or a silicon nitride film, and has openings P that expose the upper surface of the metal pads 62. The metal pads 62 are external connection pads of the semiconductor device in this modified example and can be connected to a mounting substrate or other devices via solder balls, metal bumps, bonding wires, etc.

[0128] As described above, the semiconductor device of this embodiment is manufactured using a porous layer 42 formed by the substrate processing apparatus 101 of the first embodiment. Therefore, according to this embodiment, it is possible to suitably form a porous layer 42 on the surface of the substrate 41. Furthermore, according to this embodiment, it is possible to reuse the substrate 41 by peeling it off the substrate 11.

[0129] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0130] 100 Semiconductor manufacturing equipment, 101 Substrate processing equipment, 131 Electrode, 131c Coating film, 133 Electrical circuit, 1331 Connection circuit, 1332 Power supply unit, 132 Electrode, 153 Electrolyte supply unit, 153a Electrolyte discharge unit, 161 Electrode holder, 162 Substrate holder, L Electrolyte, W Substrate

Claims

1. Multiple processing tanks, each capable of containing a substrate processing solution and a first substrate, an anode and a cathode are provided in each of the aforementioned processing tanks, An electrical circuit that electrically connects a plurality of first substrates held in the substrate processing liquid via the anode and cathode, and supplies power via the anode and cathode to perform electrochemical processing on the plurality of first substrates, A semiconductor manufacturing device equipped with the following features.

2. The semiconductor manufacturing apparatus according to claim 1, wherein the electrochemical treatment is an anodic conversion treatment.

3. The semiconductor manufacturing apparatus according to claim 1, further comprising a substrate holder capable of holding the first substrate so as to fix the first substrate to the anode.

4. The semiconductor manufacturing apparatus according to claim 3, wherein the substrate holder is capable of holding the first substrate such that the first surface of the first substrate is exposed to the substrate processing liquid.

5. The semiconductor manufacturing apparatus according to claim 3, wherein the substrate holder is capable of holding a plurality of first substrates so as to fix a plurality of first substrates to each of a plurality of anodes.

6. The semiconductor manufacturing apparatus according to claim 3, further comprising an electrode holder for holding a plurality of anodes so that the plurality of anodes can be inserted into and removed from the substrate processing liquid of each of the plurality of processing tanks.

7. The semiconductor manufacturing apparatus according to claim 1, wherein the anode comprises a base metal less susceptible to oxidation than the material of the first substrate, a compound semiconductor less susceptible to oxidation than the material of the first substrate, carbon, a conductive polymer, or a noble metal.

8. The semiconductor manufacturing apparatus according to claim 1, wherein the anode has a coating film that covers at least a portion of the region of the anode, is conductive, and contains a material different from the material of the anode.

9. The semiconductor manufacturing apparatus according to claim 8, wherein the coating film comprises a conductive polymer.

10. The semiconductor manufacturing apparatus according to claim 1, wherein the electrical circuit connects a plurality of first substrates in series via the anode and the cathode.

11. The semiconductor manufacturing apparatus according to claim 10, wherein the electrical circuit supplies power via the anode and the cathode by controlling the current flowing through a plurality of first substrates.

12. The semiconductor manufacturing apparatus according to claim 1, wherein the electrical circuit connects a plurality of the first substrates in parallel via the anode and the cathode.

13. The semiconductor manufacturing apparatus according to claim 10, wherein the electrical circuit supplies power via the anode and the cathode by controlling the voltage applied to a plurality of first substrates.

14. The semiconductor manufacturing apparatus according to claim 1, further comprising a circulation path provided for each of the processing tanks for circulating the substrate processing liquid within the processing tank.

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