Integrated circuit package including glass core substrate

Abstract

The present invention provides microelectronic assemblies and IC package substrates in which the glass core substrate is less susceptible to damage caused by mechanical and / or thermal stress. [Solution] The microelectronic assembly 100 comprises: a first layer having a first dielectric, a third dielectric, and a first glass portion between the first and third dielectrics; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second and fourth dielectrics; and a third layer between the first and second layers, comprising a bulk glass material. Here, the first layer is physically bonded to the first surface of the third layer, and the second layer is physically bonded to the second surface of the third layer.

Description

Background Art

[0001] Over the past few decades, the scaling of features within integrated circuits (ICs) has been a driving force for the growing semiconductor industry and new applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to ever finer features enables an increase in the density of functional units on the limited area of a semiconductor chip. For example, reducing the size of transistors allows more memory or logic devices to be incorporated into the chip, leading to the production of more capable products. However, the driving force of continuously increasing capacity is not without problems. The need to optimize the manufacture and performance of each component (e.g., of each transistor) is becoming increasingly important.

[0002] In parallel with optimization at the transistor level, the landscape of advanced IC packaging is evolving rapidly to meet the expectations for performance and the requirements of transistor size reduction. Currently, multiple IC dies are commonly coupled together within a multi-die IC package to integrate multiple features or functions and facilitate connection to other components such as a package substrate. For example, an IC package can include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.

[0003] Integrating multiple dies into a single IC package offers significant benefits, but it also increases complexity due to the proximity of multiple materials with different material properties. When an IC package undergoes multiple processing stages with varying temperature and pressure loads, the individual materials within the package may behave differently, leading to out-of-plane deformation of various layers, known as "package warping." One approach to address package warping is to use a rigider core to which different IC dies are mounted. In recent years, glass cores have been explored as an alternative to organic resin-based cores (e.g., cores based on the use of build-up films). Glass is considered more robust than organic resin-based materials and offers several advantages, including superior thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, light transmittance, and compatibility with improved semiconductor properties. However, a major challenge to the widespread adoption of glass cores is their high susceptibility to damage caused by mechanical and / or thermal stresses. [Brief explanation of the drawing]

[0004] The embodiments will be easily understood by combining the following detailed description with the accompanying drawings. For the sake of this explanation, similar structural elements are denoted by the same reference numerals. Embodiments are shown in several of the accompanying drawings as examples, not as limitations.

[0005] [Figure 1] This is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0006] [Figure 2A] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 2B] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 2C]This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 2D] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 2E] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0007] [Figure 3A] This is a schematic top view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 3B] This is a schematic top view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 3C] This is a schematic top view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0008] [Figure 4A] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 4B] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0009] [Figure 5A] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5B] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5C] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5D] This is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0010] [Figure 6-1]Figures 6A and 6B are schematic cross-sectional views showing various manufacturing stages of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 6-2] Figures 6C and 6D are schematic cross-sectional views showing various manufacturing stages of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0011] [Figure 7-1] Figures 7A and 7B are schematic cross-sectional views showing various manufacturing stages of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 7-2] Figures 7C and 7D are schematic cross-sectional views showing various manufacturing stages of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0012] [Figure 8] Figures 8A and 8B are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0013] [Figure 9-1] Figures 9A and 9B are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 9-2] Figures 9C and 9D are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0014] [Figure 10-1] Figures 10A and 10B are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 10-2] Figures 10C and 10D are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 10-3]Figures 10E and 10F are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 10-4] Figures 10G and 10H are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0015] [Figure 11-1] Figures 11A and 11B are schematic top views showing various manufacturing stages of FIGS. 10A and 10B according to some embodiments of the present disclosure. [Figure 11-2] Figures 11C and 11D are schematic top views showing various manufacturing stages of FIGS. 10C and 10D according to some embodiments of the present disclosure. [Figure 11-3] Figures 11E and 11F are schematic top views showing various manufacturing stages of FIGS. 10E and 10F according to some embodiments of the present disclosure. [Figure 11-4] Figures 11G and 11H are schematic top views showing various manufacturing stages of FIGS. 10G and 10H according to some embodiments of the present disclosure.

[0016] [Figure 12-1] Figures 12A and 12B are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 12-2] Figure 12C is a schematic cross-sectional view showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0017] [Figure 13-1] Figure 13A is a schematic cross-sectional view showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 13-2] Figures 13B and 13C are schematic cross-sectional views showing various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0018] [Figure 14-1] Figures 14A and 14B are simplified cross-sectional views illustrating various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 14-2] Figures 14C and 14D are simplified cross-sectional views illustrating various manufacturing stages of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0019] [Figure 15] This is a cross-sectional view of a device package which may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0020] [Figure 16] This is a side cross-sectional view of a device assembly which may include one or more microelectronic assemblies according to any embodiment disclosed herein.

[0021] [Figure 17] This is a block diagram of an exemplary computing device which may include one or more microelectronic assemblies according to any of the embodiments disclosed herein. [Modes for carrying out the invention]

[0022] Structures and assemblies disclosed herein may include a glass core, also referred to herein as a “glass layer,” the glass core having through-glass vias (TGVs) extending through the glass core for front-to-back connections between two different substrates. The substrates may include a dielectric material having conductive paths internally formed on the surface of the glass core. Conductive paths through the dielectric material may provide routing for design flexibility, and uniform diameters of the TGVs may provide dimensional stability and improved connectivity. Compared to conventional epoxy cores, glass cores offer several advantages, including, among others, higher through-glass via (TGV) density, lower signal loss, and lower overall thickness variation (TTV). Another advantage is that glass cores enable high aspect ratio TGVs. Higher aspect ratio TGVs are required to achieve the desired finer pitch.

[0023] As mentioned above, a major challenge to the widespread adoption of glass cores is that glass is highly susceptible to damage caused by mechanical and / or thermal stress. One source of mechanical and thermal stress in glass is the dicing process (sometimes referred to as “dicing” or “cutting”) that takes place during the manufacture of glass cores. Dicing is the process of applying mechanical force to the surface of a glass panel by a cutting tool (e.g., a glass cutter, diamond blade, or saw) to separate (e.g., dicing or cutting) the panel into individual glass units having a smaller form factor than the panel itself. The mechanical force applied by the cutting tool can create localized stress concentrations (e.g., areas of higher stress) on or near the surface where the cutting tool contacts the glass, for example, at or near the edges of individual glass units, where, as used herein, the term “edge” refers to the side / sidewall between the top and bottom surfaces of a glass unit, glass core, or glass panel. Because glass is a brittle material characterized by its lack of ductility (for example, its limited ability to undergo significant plastic deformation before fracture), localized stress concentrations often lead to crack formation at the edges of isolated glass units. In addition to applying mechanical stress to the glass, isolation can also generate thermal stress due to friction between the cutting tool and the glass, causing the cutting surface to heat up. This heat can cause localized expansion and contraction of the glass, further accelerating crack formation and propagation.

[0024] Separation is not the only source of stress and damage that can affect the glass core. The presence of materials with different CTEs (e.g., conductive pathways in the build-up layer and / or metals in the dielectric material) above and / or below the glass core adds stress to the glass (such stress is referred to as "CTE mismatch-induced stress"), further exacerbating the crack formation problem. Even if cracks do not form immediately during separation, cutting brittle materials like glass often results in individual glass units with rough, jagged, or otherwise uneven edges. If thermal cycling is repeated during the operation of a microelectronic assembly containing a glass core with such edges, the glass surface may gradually weaken due to CTE mismatch-induced stress, leading to crack formation at that point. Furthermore, even before separation, glass may have minute surface scratches or defects that can act as starting points for crack formation, so the addition of additional mechanical and / or thermal stress increases the severity of crack growth.

[0025] Once a crack begins to form, it tends to propagate through the glass, and additional mechanical and / or thermal stresses increase the severity of crack propagation. In particular, stress concentrations at the edges of the glass unit promote further expansion of the crack into the glass, and due to the inherent brittleness of the glass, it becomes especially susceptible to crack propagation. Crack propagation can even split the glass volume into two halves, one of which is the bottom halves and the other the top halves, around a plane parallel to the top / bottom surfaces of the glass volume and approximately in the center of the glass volume, forming a single structure.

[0026] The foregoing indicates that crack formation and propagation in glass impair the structural integrity of the glass, and that microelectronic assemblies with glass cores are particularly prone to failure over time. Embodiments of this disclosure relate to various techniques, as well as relevant devices and methods for mitigating (e.g., reducing or mitigating) crack formation and propagation in glass. In particular, embodiments of this disclosure are based on providing various edge features during or after the unitization of glass panels into individual glass units. Various embodiments of the embodiments disclosed herein may enable unitization without breakage, may help reduce the cost and complexity of assembling multi-die IC packages compared to conventional approaches, and may further improve the reliability and functionality of these IC packages in use.

[0027] Accordingly, microelectronic assemblies and related devices and methods are disclosed herein. In some embodiments, a microelectronic assembly may comprise a glass layer having a first surface and an opposing second surface, wherein the glass layer has a first cavity in the first surface; a second cavity in the second surface; and through-glass vias (TGVs) extending through the glass layer between the top surface of the first cavity and the bottom surface of the second cavity, the TGVs comprising a conductive material; a first dielectric in the first cavity, the first dielectric comprising a first conductive path electrically coupled to the TGVs; and a second dielectric in the second cavity, the second dielectric comprising a second conductive path electrically coupled to the TGVs. In some embodiments, the microelectronic assembly may comprise: a first layer having a first dielectric, a third dielectric, and a first glass portion between the first and third dielectrics; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second and fourth dielectrics; and a third layer between the first and second layers, comprising a bulk glass material, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer.

[0028] The structures, assemblies, packages, and methods of the devices and systems disclosed herein may have several innovative embodiments, none of which alone represent all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described herein are described below in the description and accompanying drawings.

[0029] In the following detailed description, various exemplary implementations may be described using terminology commonly used by those skilled in the art to communicate the essence of their research to others skilled in the art.

[0030] The terms “circuit” and “circuitry” refer to one or more passive and / or active electrical and / or electronic components arranged to work together to provide a desired function. These terms also refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical hardware electrical and / or electronic components.

[0031] The term "integrated circuit" refers to a circuit integrated onto a monolithic semiconductor or similar material.

[0032] In some embodiments, the IC dies disclosed herein may include a substantially single-crystal semiconductor as a substrate, such as silicon or germanium, on which an integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor substrate may include, for example, N-type or P-type materials. The die may include, for example, bulk silicon (or other bulk semiconductor material) or a crystalline substrate formed using a semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) structure. In some other embodiments, one or more substrates of the IC die may include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, Group III-V, Group II-VI, or Group IV materials, which may or may not be combined with silicon. In yet another embodiment, the substrate may include a compound semiconductor having, for example, a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In yet another embodiment, the substrate may include a proprietary IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in an alternative embodiment, nominal impurity dopant levels may be present. In yet another embodiment, the die may include an amorphous material such as a polymer; for example, the substrate may include a silica-filled epoxy. In yet another embodiment, the substrate may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, zinc indium oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the substrates may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, zinc indium oxide, nickel oxide, niobium oxide, copper peroxide (IGZO), indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten sulfide, N or P type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum, gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of the following: gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, ruthenium oxide, tungsten oxide, zinc oxide, zinc oxide, zinc oxide, zinc oxide, gallium oxide, titanium oxide, titanium oxide, indium oxide, zinc and black phosphorus. While some examples of materials for dies are described herein, any material or structure that can serve as a base (e.g., substrate) upon which the IC circuits and structures described herein can be built is included in the spirit and scope of this disclosure.

[0033] Unless otherwise specified, an IC die as described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a particular function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of the following: a memory device, a memory array, or control logic configured to control a memory device and an array). In another such example, the term "calculation die" may be used to describe a die that includes one or more ICs that implement logic / calculation circuitry (e.g., an IC that implements one or more of the following: input / output (I / O) functions, arithmetic operations, or data pipelines).

[0034] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “chiplet,” “die,” and “IC die” are used interchangeably in this specification.

[0035] The term “optical structure” includes configurations manufactured within an IC for receiving, converting, and / or transmitting optical signals as described herein. It may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0036] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials, such as N-type or P-type materials. The PIC may include, for example, bulk silicon (or other bulk semiconductor materials) or a crystalline substrate formed using an SOI structure (or generally, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum arsenide, aluminum arsenide, indium aluminum arsenide, indium gallium antimonide, gallium nitride, indium gallium nitride, or gallium antimonide, or other combinations of Group III-N or Group IV materials. In some embodiments, the PIC may include amorphous materials such as polymers. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, comprising a carrier material (such as glass or silicon carbide) as a substrate having a thin semiconductor layer on which the active surface containing transistors and similar components is located. While some examples of materials for the PIC are described herein, any material or structure that can serve as a foundation upon which the PIC may be built is included in the spirit and scope of this disclosure.

[0037] Unless otherwise specified, the term “insulate” means “electrically insulate,” and the term “conduct” means “electrically conduct.” When referring to optical signals, and / or devices, components, and elements that operate with or use optical signals, the term “conduct” may also mean “optically conduct.”

[0038] Terms such as "oxide," "carbide," and "nitride" refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively.

[0039] The term "high dielectric constant dielectric" refers to a material with a dielectric constant higher than that of silicon oxide, while the term "low dielectric constant dielectric" refers to a material with a dielectric constant lower than that of silicon oxide.

[0040] The term “insulating materials” refers to substantially electrically nonconductive solid materials (and / or liquid materials that solidify after the processing described herein). They may include, but are not limited to, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. Further examples of insulating materials are materials such as underfills and molds or molds used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0041] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those monolithically integrated within the IC, those mounted on the IC, or those connected to the IC. The ICs described herein may be either analog or digital and, depending on the components associated with the IC, may be used in multiple applications, such as microprocessors, optoelectronic circuits, logic blocks, and audio amplifiers. The ICs described herein may be used on a single IC die or as part of a chipset to perform one or more associated functions within a computer.

[0042] In various embodiments of this disclosure, the transistors described herein may be field-effect transistors (FETs), such as metal-oxide-semiconductor (MOS) FETs (MOSFETs). Generally, an FET is a three-terminal device that includes source, drain, and gate terminals and controls the current flowing through the device using an electric field. An FET typically includes a gate stack comprising a channel material, a source region and a drain region located inside and / or above the channel material, and a gate electrode material, alternatively referred to as a "work function" material, located above a portion of the channel material between the source and drain regions ("channel portion"), and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0043] In a general sense, “interconnection” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides an electrical connection between two electrical components, facilitating the communication of electrical signals between them; an optical interconnection provides an optical connection between two optical components, facilitating the communication of optical signals between them. As used herein, both electrical interconnections and optical interconnections are included in the term “interconnection.” The nature of the interconnection being described should be understood herein in reference to the signaling medium associated with them. Thus, when used in reference to an electronic device such as an IC that operates using electrical signals, the term “interconnection” describes any element formed of a conductive material to provide an electrical connection to and / or between various such elements associated with the IC. In such cases, the term “interconnection” can refer to both conductive traces (sometimes also called “wires,” “metal wires,” or “trenches”) and conductive vias (sometimes also called “vias” or “metal vias”). In some cases, conductive traces and vias may be referred to as “conductive traces” and “conductive vias,” respectively, to emphasize that these elements contain a conductive material such as metal. Similarly, when used in reference to devices that also operate with optical signals, such as PICs, “interconnection” may also describe any element formed of an optically conductive material that provides an optical connection to one or more elements associated with the PIC. In such cases, the term “interconnection” may refer to optical waveguides (e.g., structures that guide and restrict optical waves), including optical fibers, optical splitters, optical couplers, optical couplers, and optical vias.

[0044] The term "waveguide" typically refers to any structure that functions to guide the propagation of light from one place to another through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), and borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O and 2-8 wt% Al2O3), etc. Waveguides can be formed using a variety of techniques, including but not limited to forming waveguides in situ. For example, in some embodiments, waveguides can be formed in situ within glass using low-temperature interglass junctions or by laser direct writing. Waveguides formed in situ may have low-loss properties.

[0045] The term "conductive trace" can be used to describe a conductive element insulated by an insulating material. Within an IC die, such an insulating material includes an interlayer low-dielectric dielectric provided within the IC die. Within a package substrate and printed circuit board (PCB), such an insulating material includes an organic material such as a build-up film, polyimide, or epoxy resin. Such conductive wires are typically located at several levels or layers of a metallization stack.

[0046] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive wires at different levels of a metallization stack. For this purpose, vias may be substantially perpendicular to the surface of an IC die / chip or support structure above which an IC structure is provided, and may interconnect two conductive wires at adjacent levels or two conductive wires at non-adjacent levels.

[0047] The term “package substrate” may be used to describe any substrate material that facilitates the packaging of any set of semiconductor dies and / or other electrical components, such as passive electrical components. As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated glass fiber (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, and silicon carbide. In addition, as used herein, a package substrate may refer to a substrate including a build-up layer (e.g., an ABF layer).

[0048] The term "metallization stack" may be used to refer to a stack of one or more interconnects that provide connectivity to different circuit components on an IC die / chip and / or package substrate.

[0049] As used herein, the term “pitch” of interconnections refers to the distance between the centers of adjacent interconnections.

[0050] In the context of a stack of dies coupled to each other, or in the context of dies coupled to a package substrate, the term “interconnection” may also refer to die-to-die (DTD) interconnections and die-to-package-to-substrate (DTPS) interconnections, respectively. A DTD interconnection may also be referred to as a first-level interconnection (FLI). A DTPS interconnection may also be referred to as a second-level interconnection (SLI). Although not specifically shown in all the figures herein for the sake of simplicity, when a DTD or DTPS interconnection is described, the surface of a first die may include a first set of conductive contacts, and the surface of a second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts of the first set may be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnection. In some embodiments, the pitch of the DTD interconnection may differ from the pitch of the DTPS interconnection, while in other embodiments, these pitches may be substantially the same.

[0051] It will be noted that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided within the IC package described herein and may not be labeled to avoid complicating the drawings. In various embodiments, the underfill levels may comprise the same or different insulating materials. In some embodiments, the underfill levels may comprise a thermosetting epoxy containing silicon oxide particles; in some embodiments, the underfill levels may comprise any suitable material capable of performing underfill functions such as supporting the die and reducing thermal stress on the interconnects. In some embodiments, the selection of the underfill material may be based on design considerations such as form factor, size, stress, and operating conditions; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions, among several factors, including curing temperature, glass transition temperature, viscosity, and chemical resistance; in some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0052] In some embodiments, one or more levels of solder resist (e.g., liquid epoxy, liquid photoimaging dielectric, dry film photoimaging dielectric, acrylic, solvent) may be provided within the IC package described herein and may not be labeled or illustrated in order to avoid complicating the drawings. The solder resist may be a liquid or dry film material containing a photoimaging dielectric. In some embodiments, the solder resist may be non-photoimaging.

[0053] The terms “substantially,” “close,” “approximately,” “near,” and “about” generally refer to being within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of specific values ​​described herein or known in the art.

[0054] For example, terms indicating the orientation of various elements or any other angle between these elements, such as "coplanar," "perpendicular," "orthogonal," and "parallel," generally refer to being within + / - 5% to 20% of the target value, based on the context of specific values ​​described herein or known in the art.

[0055] The term "connected" means a direct connection between multiple things that are connected without any intermediate devices (which may be one or more of mechanical, electrical, and / or thermal connections), while the term "bonded" means either a direct connection between multiple connected things, or a connection through one or more passive or active intermediate devices.

[0056] The description may use the phrase "in one embodiment," or "in one embodiment," which may each refer to one or more of the same or different embodiments.

[0057] Furthermore, terms such as “equipped with,” “includes,” and “have” as used in reference to some of the embodiments of this disclosure are synonymous.

[0058] This disclosure may use descriptions based on perspectives such as “above,” “below,” “top,” “bottom,” and “side”; however, such descriptions are used for the sake of clarity and are not intended to limit the use of the disclosed embodiments.

[0059] As used herein, the terms “over,” “under,” “between,” and “on” refer to the relative position of one material layer or component with respect to another layer or component. For example, a layer placed above or below another layer may be in direct contact with that other layer, or may have one or more intervening layers. Furthermore, a layer placed between two layers may be in direct contact with one or both of those two layers, or may have one or more intervening layers. In contrast, a first layer described as being “on” a second layer refers to a layer that is in direct contact with the second layer. Similarly, unless otherwise explicitly stated, a feature placed between two features may be in direct contact with an adjacent feature, or may have one or more intervening layers.

[0060] As used herein, the term “arrangement” refers to location, place, position, and / or arrangement, rather than any specific method of formation.

[0061] When the term "interval" is used in reference to a measurement range, it includes the end of the measurement range.

[0062] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). Where used herein, the notation A / B / C means (A), (B), and / or (C).

[0063] Certain elements may be referred to in the singular form in this specification, but such elements may include multiple sub-elements. For example, “conductive material” may include one or more conductive materials. In another example, “dielectric material” may include one or more dielectric materials.

[0064] Unless otherwise specified, the use of ordinal numbers such as “first,” “second,” and “third” to describe a common object merely indicates that different examples of similar objects are being referred to, and is not intended to suggest that the objects described in this way must be in a given order, temporally, spatially, in order, or in any other manner.

[0065] In the following detailed description, references are made to the accompanying drawings, which form part of this specification, illustrating possible embodiments. It should be understood that other embodiments may be used and structural or logical modifications may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive.

[0066] The attached drawings are not necessarily drawn to scale.

[0067] If included in the attached drawing, the coordinates identify thickness or height by the z dimension, width by the y dimension, and length by the x dimension. Diameter, cross-section, or surface area may be identified by the xy dimensions.

[0068] In these drawings, unless otherwise stated, the same reference numeral refers to the same or similar element / material shown, such that the description of an element / material with a given reference numeral provided in the context of one of these drawings is applicable to other drawings in which the same element / material with the same reference numeral may be shown.

[0069] Furthermore, while these drawings may show some schematic diagrams of exemplary structures of the various devices and assemblies described herein with precise angles and lines, it should be understood that such schematic diagrams may not reflect actual process limitations that could cause any of the structures described herein to appear less "ideal" when inspected using images from appropriate characterization tools such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profile meters. In such images of actual structures, possible processing and / or surface defects, such as surface roughness, curvature or misalignment, pits or scratches, edges of material that are not perfectly straight, tapered vias or other openings, unintended corner rounding or variations in the thickness of different material layers, accidental twisting, edge or combinatorial misalignment within crystalline regions, and / or accidental misalignment defects of a single atom or group of atoms may also be visible. Other defects common in the field of device manufacturing and / or packaging, not listed herein, may also be present.

[0070] In these figures, various components (e.g., interconnections) are shown aligned (e.g., at their respective interfaces) simply for illustrative purposes; note that in reality, some or all of them may be misaligned. In addition, there may be other components not shown in the figures to avoid complexity, such as bond pads, landing pads, metallizations, etc., present within the assembly. Furthermore, these figures are intended to show the relative placement of components within an assembly, and generally, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal mitigation). For example, in some further embodiments, the assemblies shown in these figures may include more dies along with other electrical components. Additionally, while some components of the assembly are shown in these figures as flat rectangles or formed as cuboids, this is simply for illustrative purposes; embodiments of these assemblies may be curved, rounded, or otherwise irregular in shape, as indicated by, and in some cases unavoidable as a result of, the manufacturing processes used to produce the various components.

[0071] In these drawings, a specific number and arrangement of structures and components are presented for illustrative purposes, and in various embodiments, any desired number or arrangement of such structures and components may exist.

[0072] Furthermore, unless otherwise specified, the structures shown in these figures may take on any suitable form or shape depending on the material properties, manufacturing process, and operating conditions.

[0073] For convenience, if there is a set of drawings designated by different letters (e.g., Figures 2A to 2E), such a set may be referred to herein without those letters (e.g., "Figure 2"). Similarly, if there is a set of reference numerals designated by different numbers and / or letters (e.g., 148-1, 148-2), such a set may be referred to herein without those numbers (e.g., "148").

[0074] Various operations may be described sequentially as multiple distinct actions or operations in the manner most useful for understanding the claimed subject matter. However, the order of description should not be interpreted as suggesting that these operations are necessarily order-dependent. In particular, these operations do not have to be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed, and / or the operations described may be omitted in additional embodiments.

[0075] Figure 1 is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The microelectronic assembly 100 has a first cavity 113-1 on the bottom surface 171-1 (for example, the top of cavity 113-1 is on the first surface 170-1 of the core 103), a second cavity 113-2 on the opposing top surface 171-2 (for example, the bottom of cavity 113-2 is on the second surface 170-2 of the core 103), and at least partially within the first cavity 113-1 (for example, a portion of the core 103 is at least partially within the first substrate 148-1 The core 103 may include a first substrate 148-1 (at least partially nested within the cavity of the core 103 so as to extend along sides 173-1A, 173-1B) and a second substrate 148-2 (at least partially nested within the cavity of the core 103 so as to extend at least partially within the second cavity 113-2 so as to extend at least partially within the cavity of the core 103 so as to extend at least partially within the sides 173-2A, 173-2B of the second substrate 148-2). The first and second substrates 148-1, 148-2 may include conductive paths 196 through a dielectric material (e.g., including conductive traces and / or conductive vias, as shown). The substrate 148 may include a set of first conductive contacts 172 on the bottom surface of the substrate 148 and a set of second conductive contacts 174 on the top surface of the substrate 148, where a conductive path 196 electrically couples the individual first and second conductive contacts 172, 174. The microelectronic assembly 100 may further include through-glass vias (TGVs) 110 within the core 103 that electrically couple the first substrate and the second substrates 148-1, 148-2. The TGVs 110 may have any suitable size and shape. The thickness 193 of an individual TGV 110 may be between 50 microns and 2 millimeters (i.e., between 50 microns and 1 millimeter). The diameter (e.g., xy dimension) of an individual TGV 110 may be between 5 microns and 100 microns (e.g., between 20 microns and 50 microns).In Figure 1, the TGV110 is shown as having straight, parallel edges; however, in various embodiments, these edges may be tapered, tapered towards the center (e.g., having an hourglass shape as shown in Figures 2D and 2E), and / or have other irregularities, depending on the processing conditions for producing the TGV110. The TGV110 may be formed using any suitable process, for example, including laser drilling through via openings to penetrate the core 103 and depositing conductive material into the openings. The TGV110 may be formed from any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. In some embodiments, the pitch of the TGV110 may be between 25 microns and 200 microns (e.g., between 75 microns and 150 microns). The conductive paths 196 of the first and second substrates 148-1, 148-2 may be electrically coupled to the TGV110 by interconnects 152 which may include solder.

[0076] The first and second substrates 148-1, 148-2 may be manufactured using any suitable technique, such as a semi-additive method, subtractive etching technique, or other conventional substrate packaging techniques. In some embodiments, the dielectric material of the substrate 148 may include bismaleimide triazine (BT) resin, polyimide material, epoxy material (e.g., glass-reinforced epoxy matrix material or epoxy build-up film), molding material, oxide material (e.g., silicon dioxide or spin-on oxide), or low-dielectric and ultra-low-dielectric dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). As used herein, the core 103 having the second substrate 148-2 and / or the first substrate 148-1 may be referred to as a package substrate. The TGV 110 within the core 103 may enable power, ground, and signal connections to components located on either side of the core 103, for example, between the dies 114-1, 114-2 and the circuit board 131.

[0077] The material of core 103 may include glass, such as bulk clear glass, and may also be referred to herein as a “glass layer.” As used herein, the term “core” refers to the structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, BOROFLOAT glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, core 103 may be bulk glass or a substantial volume / layer of glass, facing a material that may contain glass particles, such as a glass fiber reinforced polymer. Such glass materials are typically amorphous and often transparent amorphous solids. In some embodiments, core 103 may be an amorphous solid glass layer. In some embodiments, the core 103 may comprise silicon and oxygen, as well as one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the core 103 may comprise a material such as any of the above-mentioned materials, having at least about 0.5% by weight of silicon, for example, between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the core 103 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the core 103 may comprise at least 23% by weight of silicon and / or at least 26% by weight of oxygen, and in some further embodiments, the core 103 may further comprise at least 5% by weight of aluminum. In some embodiments, the core 103 may contain any of the materials described above, and may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the core 103 may be a layer of glass that does not contain an organic adhesive or organic material.Core 103 can be distinguished from a “prepreg” or “RF4” core of a PCB substrate, which typically includes glass fibers embedded in a resin organic material such as epoxy. In some embodiments, the cross-section of core 103 in the xz, yz, and / or xy planes of the exemplary coordinate system shown in Figure 1 may be substantially rectangular.

[0078] The total thickness 191 of the core 103 may depend on the method by which the cavity 113 is formed within the core 103. For example, in some embodiments, if the cavity is formed by removing material from the core 103 (as described later with reference to, for example, Figure 6), the total thickness 191 of the core 103 may be between 50 microns and 2 millimeters (i.e., between 100 microns and 1 millimeter). In another example, in some embodiments, if the cavity is formed by bonding 106-1, 106-2, glass portions 115-1, 115-2 to the core 103 (as described later with reference to, for example, glass portion 715 in Figure 7), the total thickness 191 of the core 103 may be between 150 microns and 6 millimeters (i.e., between 500 microns and 3 millimeters). In some embodiments, the thicknesses 195-1, 195-2 of the glass portions 115-1, 115-2 are the same length (e.g., substantially equal). In some embodiments, the thicknesses 195-1 and 195-2 of the glass portions 115-1 and 115-2 are of different lengths (for example, different).

[0079] The microelectronic assembly 100 may further include dies 114-1 and 114-2 electrically coupled to the upper surface of a second substrate 148-2 by an interconnect 150. In particular, conductive contacts 122 on the bottom surfaces of dies 114-1 and 114-2 may be electrically and mechanically coupled to conductive contacts 174 on the upper surface of the second substrate 148-2 by the interconnect 150. The interconnect 150 may enable electrical coupling between dies 114-1 and 114-2 through conductive paths 196 in the substrate 148-2. The interconnect 150 disclosed herein may take any suitable form. In some embodiments, a set of interconnects 150 may include solder 132 (e.g., solder bumps or balls that undergo thermal reflow to form the interconnect 150). The interconnect 150, which includes solder, may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed within a non-conductive material. In some embodiments, the anisotropic conductive material may include microconductive particles embedded in a binder or thermosetting adhesive film (e.g., thermosetting biphenyl-type epoxy resin, or acrylic-based material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper, which are subsequently coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is not compressed, there may be no conductive pathway from one side of the material to the other. However, when an anisotropic conductive material is sufficiently compressed (for example, by conductive contacts on either side of the anisotropic conductive material), conductive material near the region of compression may come into contact with each other to form conductive pathways from one side of this film to the other within the region of compression.In some embodiments, the interconnect 150 disclosed herein may have a pitch between approximately 18 microns and 75 microns. Figure 1 shows dies 114-1 and 114-2 electrically coupled to the substrate 148-2 by the interconnect 150, but the dies 114-1 and 114-2 may be electrically coupled by any suitable interconnect, which may have a pitch between 2 microns and 70 microns.

[0080] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include dielectric materials such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-dielectric constant or ultra-low-dielectric constant dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimaging-capable dielectrics, and / or benzocyclobutene-based polymers). In some embodiments, the insulating material of the die 114 may include semiconductor materials such as silicon, germanium, or III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon dioxide or silicon nitride. The conductive paths within the die 114 may include conductive traces and / or conductive vias, and any of the conductive contacts within the die 114 may be connected in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 114). The conductive paths within the die 114 may be bounded by liner materials, such as adhesive liners and / or barrier liners, as appropriate. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is monolithic silicon, a fan-out or fan-in package die or die stack (e.g., stacked wafers, stacked dies or stacked multilayer dies).In various embodiments, die 114 may include, some of, or one or more of, a central processing unit (CPU), a memory device (e.g., a high-bandwidth memory device), logic circuits, input / output circuits, transceivers such as field-programmable gate array transceivers, gate array logic such as field-programmable gate array logic for power supply circuits, III-V or III-N devices such as III-N or III-N amplifiers (e.g., GaN amplifiers), peripheral component interconnect express (PCIe) circuits, double data rate (DDR) transfer circuits, or other electronic components known in the art. In some embodiments, die 114-1 and die 114-2 may include different functions. As used herein, the term “function” in relation to a die means one or more functions (e.g., capabilities, tasks, operations, actions, instructions, executions, etc.) that the die can perform. For example, die 114-1 may be a CPU, and die 114-2 may be a graphics processing unit (GPU or memory). In other embodiments, dies 114-1 and 114-2 may include the same or similar functions. For example, dies 114-1 and 114-2 may each include memory.

[0081] The microelectronic assembly 100 in Figure 1 may also include a bridge die 202 at least partially within the dielectric material of the second substrate 148-2 (e.g., at least partially nested within a cavity). The bridge die 202 may be electrically coupled to the dies 114 (e.g., dies 114-1 and 114-2) by an interconnect 150. In particular, conductive contacts 122 on the bottom surface of the die 114 may be electrically and mechanically coupled by solder to conductive contacts 124 on the top surface of the bridge die 202 to form the interconnect 150. The bridge die 202 may have appropriate circuitry on / within the semiconductor substrate for connection at the speed of silicon interconnects with a small footprint. In some embodiments, the bridge die 202 may include active components such as transistors and diodes, in addition to a bridge circuit that includes metallization traces, vias, and passive components to enable electrical coupling between the two ICs; in other embodiments, the bridge die 202 may include a bridge circuit that includes metallization traces, vias, and passive components to enable electrical coupling between die 114-1 and die 114-2, and may not include active components.

[0082] The microelectronic assembly 100 in Figure 1 may also include an overmolding material 135 that seals the die 114 (for example, on and around the die 114 and interconnect 150). The overmolding material 135 may extend from the top surface of the second substrate 148-2 to the top surface of the die 114. In some embodiments, the overmolding material 135 may be a molding material, resin material, or epoxy material, such as an organic polymer containing inorganic silicon oxide or aluminum oxide particles. In some embodiments (not shown), other components, such as a heat sink, may be bonded to the microelectronic assembly 100 based on specific needs.

[0083] The microelectronic assembly 100 in Figure 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the dies 114-1, 114-2 and the second substrate 148-2 around the associated interconnect 150, between the core 103 around the associated interconnect 152 and the respective first and second substrates 148-1, 148-2, and / or between the bridge die 202 and the second substrate around the associated interconnect 150. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy bundle that assists in soldering the dies 114-1 and 114-2 to the second substrate 148-2 when forming the interconnect 150, and then polymerizes and seals the interconnect 150. The underfill process may include dispensing liquid underfill material, allowing the material to flow and fill the gaps between the grids around the interconnect 150, and allowing the assembly to undergo a curing process such as firing to solidify the material. In some embodiments, the underfill material 127 may be omitted. Although Figure 1 shows two separate underfill 127 portions under the dies 114-1 and 114-2, the underfill 127 may be a single underfill 127 under the dies 114-1 and 114-2. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that can reduce or minimize stress between the die 114 and the second substrate 148-2 resulting from non-uniform thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may be a value intermediate between the CTE of the second substrate 148-2 (e.g., the CTE of the dielectric material of substrate 148) and the CTE of the insulating material of the die 114. In some embodiments, a non-conductive film (NCF) may surround the interconnect 152.

[0084] The microelectronic assembly 100 in Figure 1 may also include a circuit board 131. In particular, conductive contacts 172 on the bottom surface of the first substrate 148-1 may be electrically coupled to conductive contacts 146 on the top surface of the circuit board 131 by interconnects 190. The interconnects 190 disclosed herein may take any suitable form, including any of the forms described above with reference to solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement, or interconnects 150. As shown in Figure 1, in some embodiments, a set of interconnects 190 may include solder 136 (e.g., solder bumps or balls that undergo thermal reflow to form the interconnects 190). In some embodiments, the interconnects 190 disclosed herein may have pitches between about 50 microns and 300 microns. In some embodiments, underfill material 127 may extend between the first substrate 148-1 and the circuit board 131 around the associated interconnects 190. The circuit board 131 may be, for example, a motherboard and may have other components mounted thereon. As is known in the art, the circuit board may include conductive paths and other conductive contacts for transferring power, ground, and signals through the circuit board. In some embodiments, the interconnect 190 does not have to be coupled to the circuit board 131, but instead may be coupled to another IC package, interposer, or any other suitable component.

[0085] In some embodiments, one or more levels of solder resist (e.g., liquid epoxy, liquid photoimaging polymer, dry film photoimaging polymer, acrylic, solvent) may be provided within the IC package described herein and may not be labeled or illustrated in order to avoid complicating the drawings. The solder resist may be a liquid or dry film material containing a photoimaging polymer. In some embodiments, the solder resist may be non-photoimaging.

[0086] Figure 2A shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 1, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the core 103 includes a plurality of cavities 113 in the respective first and second surfaces 170-1, 170-2 having the respective first and second substrates 148-1, 148-2. As shown in Figure 2A, the first and second substrates 148-1, 148-2 and their respective components (e.g., die 114, bridge die 202 and / or overmolding material 135) may be referred to as subassemblies 101 (e.g., subassemblies 101-1, 101-2, respectively), and may be referred to as such in subsequent figures for the sake of brevity and clarity.

[0087] Figure 2B shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2A, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the conductive paths 196 of the first and second substrates 148-1, 148-2 are conductively coupled to the TGV 110 of the core 103 by interconnects 154 which may include, among other things, metal-metal interconnects, solder-metal interconnects, and tin-solder interconnects. As shown in Figure 2B, in some embodiments, conductive pads or traces may be present between the TGV 110 and the conductive paths 196. In other embodiments, as shown in Figure 2C, the TGV 110 and the conductive paths 196 may be in direct physical contact with each other.

[0088] Figure 2C shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2B, except for differences which will be further described. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 further includes buffer materials 105-1, 105-2 on the respective first and second surfaces 170-1, 170-2 of the core 103 between the respective first and second substrates 148-1, 148-2. The buffer material 105 may include any suitable material, including an inorganic dielectric such as silicon oxide or an organic dielectric such as polyimide. The buffer material 105 may function as an interface layer between the core 103 and the respective substrates 148-1, 148-2. In some embodiments, the dielectric material of the substrate 148 and the buffer material 105 may be the same material. In some embodiments, the thickness (e.g., z-height) of the buffer material 105 is between 0.1 microns and 50 microns.

[0089] Figure 2D shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2C, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the buffer material 105 is omitted and the microelectronic assembly 100 also includes undercuts 208 along the sidewalls of the first and second cavities 113-1, 113-2 on the respective first and second surfaces 170-1, 170-2 of the core 103. In some embodiments, the undercuts 208 may have a width (e.g., y dimension) between 2 microns and 20 microns and may extend along the entire depth (e.g., z dimension) of the cavity.

[0090] Figure 2E shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2D, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 further includes a conductive foil layer 204 attached to the bottom surface 171-1 and top surface 171-2 of the core 103 (e.g., the bottom and top surfaces of the core 103 outside the cavity 113) by a bonding material 206. The conductive foil layer 204 may contain any suitable conductive material such as copper and may have any suitable thickness (e.g., z dimension), for example, the thickness of the conductive foil layer may be between 10 microns and 70 microns (e.g., between 15 microns and 35 microns). The bonding material 206 may include any suitable material for physically attaching the conductive foil layer 204 to the core 103, e.g., an adhesive material, a molding material, or a dielectric material.

[0091] Figures 1 and 2 show a microelectronic assembly 100 having a specific number and arrangement of subassemblies 101 and components within those subassemblies 101, but the microelectronic assembly 100 may have any appropriate number and arrangement of subassemblies 101 and components within those subassemblies 101. For example, as shown in Figure 3, the microelectronic assembly 100 may include multiple subassemblies 101 that are communicatively coupled.

[0092] Figure 3A shows a schematic top view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 includes a core 103 having 12 subassemblies 101 (e.g., 101-1 to 101-12), the subassemblies 101 being coupled to each other in a communicative manner by a path 303. Although Figure 3A shows communication paths 303 between adjacent subassemblies 101 (for example, between subassemblies 101-1 and 101-2 and subassemblies 101-1 and 101-5, rather than between subassemblies 101-1 and 101-6), a subassembly 101 can be communicatively coupled to a non-adjacent subassembly 101 by using multiple paths 303 between adjacent subassemblies 101 (for example, subassembly 101-1 can be communicatively coupled to subassembly 101-6 through paths 303 between subassemblies 101-1, 101-5 and subassemblies 101-5, 101-6). In some embodiments, a subassembly 101 can be communicatively coupled to other non-adjacent subassemblies 101 by paths directly between non-adjacent subassemblies (for example, subassembly 101-1 may have a direct communication path to subassembly 101-6 via paths 498 or 496, as described later with reference to Figure 4). In some embodiments, the subassembly 101 may be communically coupled by an electrical path (e.g., shown in Figure 4). In some embodiments, the subassembly 101 may be communically coupled by an optical path (e.g., shown in Figure 5).

[0093] Figure 3B shows a schematic top view of exemplary microelectronic assemblies according to several embodiments of the present disclosure. The configuration of the embodiments shown in this figure is similar to that of Figure 3A, except for differences which will be described further. Figure 3B shows exemplary microelectronic assemblies 100-1 to 100-4 before disassembly along saw street 107. Microelectronic assembly 100-1 includes a core 103 having two subassemblies 101-1 and 101-2 that are communicatively coupled by path 303. Microelectronic assembly 100-2 includes a core 103 having two subassemblies 101-3 and 101-4 that are communicatively coupled by path 303. Microelectronic assembly 100-3 includes a core 103 having four subassemblies 101-5, 101-6, 101-9, and 101-10 that are communicatively coupled by path 303. The microelectronic assembly 100-4 includes a core 103 having four subassemblies 101-7, 101-8, 101-11, and 101-12 that are communicatively coupled by a path 303. The saw path 107 runs along the thickest portion of the core 103 (e.g., thickness 191 shown in Figure 1), which can add structural rigidity to reduce warping of the panel during assembly and stress-induced failure of the core 103.

[0094] Figure 3C shows a schematic top view of an exemplary microelectronic assembly according to several embodiments of the present disclosure. The configuration of the embodiments shown in this figure is similar to that of Figure 3B, with differences which will be described further. Figure 3C shows exemplary microelectronic assemblies 100-1 to 100-4 before isolation along a saw street 107, where the isolated microelectronic assemblies 100-1 to 100-4 have the same number and arrangement of subassemblies 101-1 to 101-6. Microelectronic assemblies 100-1 to 100-4 include a core 103 having six subassemblies 101-1 to 101-6 communicated together by a path 303. The saw street 107 is along the thickest portion of the core 103 (e.g., thickness 191 shown in Figure 1), which can reduce stress-induced fracture of the core 103 during isolation.

[0095] Figure 4A shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2A, except for differences which will be further described. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 further includes a circuit board 131 which is electrically coupled to a first substrate 148-1 of subassemblies 101-1, 101-2 by interconnects 190. The circuit board 131 also includes conductive paths 498. Each of the subassemblies 101-1, 101-2 may be electrically coupled by the conductive paths 498 in the circuit board 131. In some embodiments, the subassembly 101 may be electrically coupled to an interposer, an organic substrate patch, or another substrate instead of a circuit board.

[0096] Figure 4B shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2A, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 further includes each circuit board 131 electrically coupled to the first substrate 148-1 of each subassembly 101-1 and 101-2 by interconnect 190, and the second substrate 148-2 of each subassembly 101-1 and 101-2 is electrically coupled by dielectric material including a conductive path 496 on the upper surface 171-2 of the core 103. The dies 114 in each subassembly 101-1 and 101-2 may be electrically coupled by the conductive path 496. In some embodiments, the conductive path 496 may electrically couple non-adjacent subassemblies (e.g., subassemblies 101-1 and 101-6 in Figure 3A). In some embodiments, the dielectric material containing the conductive path 496 may also be referred to as a redistribution layer (RDL) and may be formed using a redistribution layer (RDL) process (e.g., a semi-additive method). Figure 4B shows the first substrate 148-1 of subassemblies 101-1 and 101-2 electrically coupled to their respective circuit boards, but the first substrate 148-1 of subassemblies 101-1 and 101-2 may be electrically coupled to their respective interposers or other substrates instead of the circuit boards.

[0097] Figure 5A shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to several embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2A, except for differences which will be further described. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 further includes photonic components for transmitting and receiving optical signals. As shown in Figure 5A, the microelectronic assembly 100 may include a subassembly 101 further including a photonic integrated circuit (PIC) 104, a logic integrated circuit (XPU) 128, and a microprocessor die 516. The die 114 may function as an electrical integrated circuit (EIC) and may be electrically coupled to a bridge die 202, a microprocessor die 516, and a PIC 104 by an interconnect 150. The PIC104 in subassembly 101-1 can transmit and receive optical signals to and from the PIC104 in subassembly 101-2 via an optical path 560 through the glass portion 115 of the core 103 between the respective subassemblies 101-1 and 101-2. As used herein, the term “optical path” refers to the path or trajectory through which light propagates from one place to another via an optical medium. In some embodiments, the optical path 560 may include one or more waveguides or other structures that guide the path of light. In some embodiments, the optical path 560 may include reflectors or other components configured to transmit signals from vertical to transverse or from transverse to vertical. In some embodiments, the optical path 560 may be formed after the mounting of the PIC104 (e.g., a waveguide laser-written in situ, as described above). The microelectronic assembly 100 containing the photonic component may be referred to herein as a “photonic package” or “photonic assembly,” and the die 114 containing the EIC circuit may be referred herein as an EIC die 114.

[0098] The PIC104 may include optical elements for transmitting and / or receiving optical signals, and conductive contacts on the bottom surface of the PIC104 may be electrically and mechanically coupled to conductive contacts on the top surface of the EIC die 114 by interconnect 150. The optical elements may be optically coupled to an optical path 560 through the glass portion 115 of the core 103 between subassemblies 101-1 and 101-2. Exemplary optical elements included in the PIC104 include electromagnetic radiation sources, electro-optical devices, and waveguides. In many embodiments, the optical elements may be fabricated on the surface of the PIC104 using any known method in the art, including semiconductor photolithography and deposition methods. As shown in Figure 5A, the PIC104 may be configured to transmit and / or receive optical signals at its bottom surface. For example, the PIC104 may include optical elements at its bottom surface, such as a grating coupler, which enables the PIC104 to transmit and / or receive light through its bottom surface (e.g., vertical transmission and reception of light). In some embodiments, as shown in Figure 5A, the PIC 104 may have a bottom surface that is physically coupled to the glass portion 115 and has a layered contour for transmitting light at the bottom. In other embodiments, as shown in Figure 5C, the PIC 104 may have a flat bottom surface that is physically coupled to the glass portion 115 and has a flat bottom surface for transmitting light at the bottom. In some embodiments, as shown in Figure 5B, the PIC 104 may be configured to transmit and / or receive optical signals on its sides and / or bottom. In such examples, the PIC 104 may include optical elements that enable the PIC 104 to transmit and / or receive light (e.g., lateral transmission and reception of light) through its sides which are substantially perpendicular to the bottom, such as edge couplers, v-groove arrays, or inclined reflectors with grating couplers. The PIC 104 may be physically coupled to the glass portion 115 of the core 103 using any suitable mounting means, e.g., optical glue or fusion bonding. The optical glue may contain any suitable material that allows optical signals to pass through while functioning to adhere the PIC104 and the glass portion 115 of the core 103.The materials may include, but are not limited to, UV-curable photoadhesives, epoxy, silicon, modified silanes, and acrylates. Fusion bonding may include a layer of bonding material, such as alumina, photoepoxy, or silicon dioxide, on the bonding surface. In some embodiments, the bonding material may cover the optical elements on the surface of the PIC104 and may function as a protective layer to maintain the integrity of the optical elements during manufacturing processes that the PIC104 may undergo, such as mounting, solder reflow, grinding, polishing, underfill, and molding. The layer of bonding material may ensure, for example, that the optical transmission properties of the optical elements are not impaired by contamination of the mold or underfill material during the manufacturing process, or that the optical function is not impaired by rupture, breakage, or other destructive events during the manufacturing process. The layer of bonding material may also function to prevent leakage of optical signals from the optical elements during the operation of the PIC104. For example, if a silicon dioxide material is used, the bonding material may further function to provide an oxide-oxide bond between the optical elements of the PIC104 and the glass portion 115 of the core 103. In another example, the bonding material may function to provide a nitride-nitride bond between the optical elements of the PIC104 and the glass portion 115 of the core 103, when silicon nitride material is used. The silicon oxide layer in an oxide-oxide bond or the silicon nitride layer in a nitride-nitride bond may be bonded first by van der Waals forces and then by high-temperature fusion bonding. Oxide-oxide and nitride-nitride bonds can reduce optical signal loss.

[0099] The EIC die 114 may be configured to electrically integrate the PIC 104, the microprocessor die 516, and the XPU 128 via the bridge die 202 to realize the intended function of the microelectronic assembly 100. For example, the EIC die 114 may be an application-specific IC (ASIC) containing one or more switch or driver / receiver circuits used in optical communication systems. In some embodiments, the EIC die 114 may include circuits for communication between two or more IC dies, for example, between the XPU 128, the microprocessor die 516, and the PIC 104. In some embodiments, the EIC die 114 may include active components, such as one or more transistors, voltage converters, transimpedance amplifiers (TIAs), serializers and deserializers (SERDES), clock and data recovery (CDR) components, and a microcontroller. In some embodiments, the EIC die 114 may have enough passive circuitry to enable interconnection to the PIC 104 and other components in the microelectronic assembly 100 without any active components.

[0100] The XPU128 may include any suitable IC functions. In some embodiments, the XPU128 may include a processor integrated circuit (XPU) having processing functions, such as a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), ASIC, and accelerator. In various embodiments, the XPU may be one or more voltage converters, transimpedance amplifiers (TIAs), clock and data recovery (CDR) components, microcontrollers, etc., or may include these. Although Figure 5A shows the XPU128, EIC die 114, and microprocessor die 516 as separate ICs, in some embodiments, a single IC may include the XPU, microprocessor, and / or EIC functions, so that one or more of the XPU128, EIC die 114, and microprocessor die 516 may be omitted from the microelectronic assembly 100. In some embodiments, the microelectronic assembly 100 may include multiple XPU128s, multiple EIC dies 114, and multiple microprocessor dies 516. In some embodiments, the EIC die 114 may function as an interconnect die and a bridge die 202 and may be omitted from the microelectronic assembly 100.

[0101] Figure 5B shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 5A, except for differences which will be further described. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 also includes a glass portion 115 having a notch for physically coupling a PIC 104 having a flat bottom surface, and the PIC 104 is further configured to transmit and / or receive optical signals on its sides and bottom surface. The microelectronic assembly 100 further shows optical paths 560 having different contours, where optical path 560A has a curved contour and optical path 560B has a straight contour. While Figures 5A and 5B show a microelectronic assembly 100 having a specific number of optical paths with a specific contour, the microelectronic assembly 100 may have any suitable number of optical paths with any suitable contour, including, for example, straight lines, multiple straight lines, curves, parabolas, inclined lines, U-shapes, etc., and combinations thereof.

[0102] Figure 5C shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 5A, except for differences which will be described further. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 also includes three subassemblies 101-1, 101-2, and 101-3, where subassembly 101-2 includes a plurality of PICs 104A and 104B, a plurality of EIC dies 114, a plurality of microprocessor dies 516, and a plurality of bridge dies 202. In particular, the PIC104 of subassembly 101-1 is optically coupled to the PIC104A of subassembly 101-2 by an optical path 560-1 through the glass portion 115-1 of the core 103, and the PIC104B of subassembly 101-2 is optically coupled to the PIC104 of subassembly 101-3 by an optical path 560-2 through the glass portion 115-2 of the core 103. Figure 5C shows a specific number and arrangement of photonic components within subassembly 101, but the microelectronic assembly 100 may have any appropriate number and arrangement of photonic components within subassembly 101, and the number and arrangement of photonic components may depend on the number of subassemblies 101 and the number of optical paths 560 between subassemblies 101 within the microelectronic assembly 100.

[0103] Figure 5D shows a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 5C, except for differences which will be further described. The configuration of the microelectronic assembly 100 is as described herein, except that the microelectronic assembly 100 also includes an optical polymer 505 within the cavity 113-2 and around the subassembly 101, where the optical path 560 extends through the optical polymer 505 around subassembly 101-1, through the glass portion 115 between subassemblies 101-1 and 101-2, and through the optical polymer 505 around subassembly 101-2. The optical polymer may include any suitable optical polymer, e.g., siloxanes and acrylates. In some embodiments, the optical polymer 505 may provide mechanical stability to the microelectronic assembly 100. Figures 5A to 5D show a substrate 148 electrically coupled to the TGV 110 by interconnection 152, but the substrate 148 may be electrically coupled to the TGV 110 by any suitable interconnection disclosed herein, such as interconnection 154 in Figure 2B and interconnection 156 in Figure 2C.

[0104] Any suitable technique may be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 6A to 6D are side cross-sectional views of various stages in an exemplary process for manufacturing a microelectronic assembly 100 similar to Figure 2A, according to various embodiments. The operations described below with reference to Figures 6A to 6D (and other accompanying drawings representing the manufacturing process) are shown in a specific order, but these operations may be performed in any suitable order. Furthermore, additional operations not shown may be performed without departing from the scope of this disclosure. Also, various of the operations described herein with reference to Figures 6A to 6D may be modified in accordance with this disclosure to manufacture other microelectronic assemblies 100 disclosed herein.

[0105] Figure 6A shows an assembly including a core 103 having a bottom surface 171-1 and a top surface 171-2. The core 103 may have any suitable dimensions; for example, the core 103 may include a full-panel glass core with a surface area of ​​approximately 500 mm × 500 mm (e.g., xy dimensions), or a quarter-panel glass core with a surface area of ​​approximately 250 mm × 250 mm. The core 103 may have a thickness (e.g., z dimension) between 50 microns and 2 mm.

[0106] Figure 6B shows the assembly after the cavity 613 and via opening 611 have been formed in the core 103. The cavity 613 may include a first cavity 613-1 formed on the bottom surface 171-1 of the core 103 and a second cavity 613-2 formed on the top surface 171-2 of the core 103. The first cavity 613-1 includes the top surface 170-1, and the second cavity 613-2 includes the bottom surface 170-2. The cavity 613 and via opening 611 may be formed using any suitable process including lithography, laser-assisted wet etching, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching. The cavity 613 and via opening 611 may have any suitable shape. For example, the cavity 613 may have substantially vertical sidewalls or inclined sidewalls that narrow towards the bottom of the cavity 613, and the via opening 611 may have substantially vertical sidewalls for forming rectangular vias, inclined sidewalls for forming conical vias, or inclined double sidewalls for forming hourglass vias. The shapes of the cavity 613 and the via opening 611 may depend on the process used to form the cavity 613 and the via opening 611 (e.g., a lithography process for vertical sidewalls and a laser drilling process for inclined sidewalls).

[0107] Figure 6C shows the assembly after plating the via opening 611 of Figure 6B with a conductive material to form TGV110, and after plating the conductive pads 174 and 172 on the first surface 170-1 and second surface 170-2 of the core 103, respectively. TGV110 may contain any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, and may be deposited using any suitable process, including lithography, electroplating, or electroless plating.

[0108] Figure 6D shows the assembly after forming the interconnect 152, forming substrates 148-1, 148-2 on the first and second surfaces 170-1, 170-2 of the core 103, embedding the bridge die 202 in the second substrate 148-2, attaching the dies 114-1, 114-2 to the top surface of the second substrate 148-2 by forming the interconnect 150, and depositing the underfill material 127. The assembly in Figure 6D may be manufactured using conventional package substrate manufacturing techniques. The dielectric of substrate 148 may be deposited using any suitable technique including lamination, and may be removed using any suitable technique, such as laser patterning or lithography, to form a cavity for arranging the bridge die 202 inside. In some embodiments, the bridge die 202 may be omitted. The conductive path 196 may be any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, and may be deposited using any suitable process, including lithography, electroplating, or electroless plating. In some embodiments, substrates 148-1 and 148-2, including the bridge die 202 and die 114, may be manufactured separately as subassemblies and then mounted to the core 103 by being placed in their respective cavities 613-1, 613-2 and forming interconnects 152. As shown, the assembly in Figure 6D may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 6D to form other microelectronic assemblies 100; for example, by separating them through the glass portion 115 (for example, in each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 6D by forming interconnects 190 similar to those in Figures 1 and 4A.

[0109] Figures 7A to 7D are side cross-sectional views of various stages in an exemplary process for manufacturing a microelectronic assembly 100 similar to Figure 2B, according to various embodiments. Figure 7A shows an assembly including a core 103 having a first surface 170-1, an opposing second surface 170-2, a TGV 110, and conductive pads 174, 172 on the first surface 170-1 and the second surface 170-2 of the core 103, respectively. In some embodiments, the conductive pads 174, 172 may be omitted. The core 103 may have any suitable dimensions; for example, the core 103 may include a full-panel glass core with a surface area of ​​approximately 500 mm × 500 mm (e.g., xy dimensions), or a quarter-panel glass core with a surface area of ​​approximately 250 mm × 250 mm. The core 103 may have a thickness (e.g., z dimension) between 50 microns and 2 mm.

[0110] Figure 7B shows the assembly after the glass portions 715-1 and 715-2 are placed on the first surface 170-1 and second surface 170-2 of the core 103, respectively. The glass portions 715-1 and 715-2 may have any suitable dimensions for forming the respective cavities 713-1 and 713-2. In some embodiments, the glass portion 715 may have a thickness (z dimension) between 50 microns and 2 millimeters.

[0111] Figure 7C shows the assembly after the glass portions 715-1 and 715-2 are mechanically bonded to the first and second surfaces 170-1 and 170-2 of the core 103, respectively, to form cavities 713-1 and 713-2. The glass portions 715 may be attached to the core 103 by oxide-oxide joints 106 (e.g., 106-1 and 106-2, respectively), where the glass material of the glass portions 715 and the glass material of the core 103 are bonded to each other. In some embodiments, after bonding, the individual glass portions 715 may become undetectable (e.g., have a seamless interface) so that the core 103 appears as a single component. In some embodiments, after bonding, a seam of the interface may exist at the interface between the individual glass portions 715 and the core 103.

[0112] Figure 7D shows the assembly after forming substrates 148-1, 148-2 on the first and second surfaces 170-1, 170-2 of the core 103, forming interconnects 154, embedding a bridge die 202 in the second substrate 148-2, forming interconnects 150 to mount dies 114-1, 114-2 to the top surface of the second substrate 148-2, and depositing underfill material 127. The assembly in Figure 7D can be manufactured using any suitable technique, including, for example, the conventional package substrate manufacturing techniques described above with reference to Figure 6D. As shown, the assembly in Figure 7D itself may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 7D to form other microelectronic assemblies 100; for example, by separating them through the glass portion 115 (for example, in each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 7D by forming interconnects 190 similar to those in Figure 1.

[0113] Figures 8A and 8B are side cross-sectional views of various stages in an exemplary process for manufacturing a microelectronic assembly 100 similar to Figure 4B, according to various embodiments. Figure 8A shows the assembly after forming cavities 113-1, 113-2 in a core 103 having a TGV 110, forming substrates 148-1, 148-2 on the first and second surfaces 170-1, 170-2 of the core 103, forming an interconnect 154, embedding a bridge die 202 in the second substrate 148-2, and forming a conductive path 496 through dielectric material on the upper surface 171-2 of the glass portion 115 of the core 103. The assembly in Figure 8A may be manufactured using any suitable technique, including, for example, the manufacturing techniques described above with reference to Figures 6 and / or 7. The conductive path 496 through the dielectric material may be formed using conventional package substrate techniques or redistribution layer (RDL) processes (e.g., semi-additive methods).

[0114] Figure 8B shows the assembly after the dies 114-1 and 114-2 are mounted on the upper surface of the second substrate 148-2 by forming an interconnect 150 and after the underfill material 127 is deposited. As shown, the dies 114-1 and 114-2 in the subassemblies 101-1, 101-2, and 101-3 can be electrically coupled by a conductive path 496. As shown, the assembly in Figure 8B itself may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 8B in order to form other microelectronic assemblies 100; for example, by separating them through the glass portion 115 (for example, in each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching one or more circuit boards 131 to the bottom surface of the microelectronic assembly 100 of Figure 8B by forming interconnects 190 similar to those in Figure 4A or Figure 4B.

[0115] Figures 9A to 9D are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 of Figure 2C according to various embodiments. Figure 9A shows an assembly including a core 103 having cavities 113-1, 113-2, a TGV 110 extending between the first and second surfaces 170-1, 170-2 through the core 103, and buffer material 105-1, 105-2 on the first and second surfaces 170-1, 170-2 of the core 103. The assembly may be manufactured using any suitable technique described above, for example, with reference to Figures 6 and / or 7. The buffer material 105 may be deposited using any suitable technique, including lamination, spin coating, spray coating, and slit coating. As described above with reference to Figure 2C, the buffer material 105 may include any suitable material and may have any suitable dimensions.

[0116] Figure 9B shows the assembly after via openings 911 have been formed in the buffer material 105-1, 105-2 on the first and second surfaces 170-1, 170-2 of the core 103. The via openings 911 can be formed using any suitable process, including lithography or laser drilling. The via openings 911 can have any suitable shape. For example, the via openings 911 may have inclined sidewalls to form a conical via, or substantially vertical sidewalls to form a rectangular opening. The shape of the via openings 911 may depend on the process used to form them (e.g., a lithography process for rectangular vias and a laser drilling process for conical vias).

[0117] Figure 9C shows the assembly after the conductive material has been deposited in the via opening 913 to form the conductive path 196 and interconnect 154. The conductive path 196 may contain any suitable conductive material such as copper and may be deposited using any suitable process including lithography, electroplating, or electroless plating.

[0118] Figure 9D shows the assembly after forming substrates 148-1, 148-2 on buffer materials 105-1, 105-2 on the first and second surfaces 170-1, 170-2 of the core 103, respectively, embedding a bridge die 202 in the second substrate 148-2, attaching dies 114-1, 114-2 to the top surface of the second substrate 148-2 by forming interconnects 150, and depositing underfill material 127. The assembly in Figure 9D can be manufactured using any suitable technique, including, for example, the conventional package substrate manufacturing techniques described above with reference to Figures 6 and / or 7. As shown, the assembly in Figure 9D itself may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 9D to form other microelectronic assemblies 100; for example, by separating them through the glass portion 115 (for example, in each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 9D by forming interconnects 190 similar to those in Figure 1.

[0119] Figures 10A to 10H are side section views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 of Figures 2D and 2E according to various embodiments, and Figures 11A to 11H are top views of these stages. Figure 10A shows an assembly including a core 103 having a conductive foil layer 204 attached to the bottom surface 171-1 and top surface 171-2 of the core 103 by a bonding material 206. The conductive foil layer 204 and bonding material 206 extend beyond the footprint of the core 103. Figure 11A shows the conductive foil layer 204 on the top surface of the core 103 and extending beyond the footprint of the core 103 (e.g., xy dimensions shown by dashed lines). The core 103 may have any suitable dimensions, including thicknesses between 50 microns and 2 millimeters (e.g., z dimension).

[0120] Figure 10B shows the assembly after the extended portion of the conductive foil layer 204 has been bent together with the bonding material 206 and attached to the side 171-3 of the core 103. The conductive foil layer 204 may completely seal the core 103 and may function to protect the core 103, in particular the side 171-3. The assembly in Figure 10B may be formed by any suitable technique, e.g., by compressing the assembly using a rubber press. Figure 11B shows the conductive foil layer 204 on the top surface of the core 103, where the surface area (e.g., xy dimensions) of the conductive foil layer 204 is reduced due to bending and attachment to the side 171-3.

[0121] Figure 10C shows the assembly after multiple portions of the conductive foil layer 204 and bonding material 206 have been removed, and openings have been formed in the conductive foil layer 204 to expose the bottom and top surfaces 171-1, 171-2 of the core 103. The conductive foil layer 204 may be cut out and removed using any suitable technique, including the use of a conventional router or laser ablation. The bonding material 206 may be removed using any suitable technique, including a desmear or plasma etching process. Figure 11C shows the conductive foil layer 204 on the top surface of the core 103 after multiple portions have been removed to expose the top surface 171-2 of the core 103. The remaining portions of the conductive foil layer 204 may form a frame, and the removed portions are where cavities are formed, as will be described later with reference to Figure 10D.

[0122] Figure 10D shows the assembly after the cavity 1013 and via opening 1011 have been formed in the core 103. The cavity 1013 may include a first cavity 1013-1 formed on the bottom surface 171-1 of the core 103 and a second cavity 1013-2 formed on the top surface 171-2 of the core 103. The first cavity 1013-1 includes the top surface 170-1, and the second cavity 1013-2 includes the bottom surface 170-2. The cavity 1013 may be formed using any suitable process, including laser-assisted wet etching. Cavities 1013 may have any suitable shape and may further include undercuts 208 along the sidewalls of the first and second cavities 1013-1, 1013-2 on the first and second surfaces 170-1, 170-2 of the core 103 (as described above with reference to, for example, Figures 2D and 2E). Cavities 1013 may have any suitable dimensions and may have depths between 5 microns and 25 microns (e.g., z dimension), depending on the amount of exposure during the laser-assisted wet etching process, where approximately 10% of the glass thickness may be removed. In some embodiments, cavities 1013 may have greater depths (e.g., between 10 microns and 50 microns). Via openings 1011 may have any suitable shape. For example, the via opening 1011 may have two inclined sidewalls for forming an hourglass-shaped via, an inclined sidewall for forming a cone-shaped via, or a substantially vertical sidewall for forming a rectangular via, as shown. The via opening 1011 may be formed using any suitable process described above, for example, with reference to Figure 6B. Figure 11D shows a conductive foil layer 204 on the upper surface of the core 103 with several portions removed to expose the cavity 1013-2 and the via opening 1011 formed on the upper surface 171-2 of the core 103.

[0123] Figure 10E shows the assembly after the via opening 1011 has been plated with a conductive material to form the TGV110. The TGV110 may contain any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, and may be deposited using any suitable process, including lithography, electroplating, or electroless plating. Figure 11E shows a top view of the TGV110 after the via opening 1011 has been plated with a conductive material.

[0124] Figure 10F shows the assembly after forming substrates 148-1, 148-2 on the first and second surfaces 170-1, 170-2 of the core 103, embedding a bridge die 202 in the second substrate 148-2 and forming an interconnect 150 to mount the dies 114-1, 114-2 to the upper surface of the second substrate 148-2, and depositing the underfill material 127. The assembly in Figure 10F can be manufactured using the conventional package substrate manufacturing techniques described above with reference to Figure 6D. Figure 11F shows the conductive foil layer 204 on the upper surface of the core 103 after several parts have been removed, exposing the substrate 148-2 with the mounted dies 114-1, 114-2 in the cavity 1013-2.

[0125] Figure 10G shows the assembly after the conductive foil layer 204 and bonding material 206 have been removed from the sides 171-3 of the core 103. The conductive foil layer 204 and bonding material 206 can be removed using any suitable technique, e.g., selective metal etching and plasma etching processes. Figure 11G shows the conductive foil layer 204 on the top surface of the core 103 after multiple portions have been removed from the sides 171-3 (e.g., the surface area (i.e., xy dimensions) of the assembly has been reduced as a result of removing the conductive foil layer 204 and bonding material 206 from the sides 171-3). As shown, the assemblies in Figures 10G and 11G themselves may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assemblies 100 of Figures 10G and 11G to form other microelectronic assemblies 100 similar to those in Figure 2E; for example, by separating (each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assemblies 100 of Figures 10G and 11G by forming interconnects 190 similar to those in Figure 1.

[0126] Figure 10H shows the assembly after the conductive foil layer 204 and bonding material 206 have been removed from the bottom and top surfaces 171-1, 171-2 of the core 103. The conductive foil layer 204 and bonding material 206 can be removed using any suitable technique, e.g., selective metal etching process and plasma etching process. Figure 11H shows the top surface 171-2 of the core 103 after the conductive foil layer 204 and bonding material 206 have been removed from the bottom and top surfaces 171-1, 171-2 of the core 103. As shown, the assemblies in Figures 10H and 11H themselves may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assemblies 100 of Figures 10H and 11H to form other microelectronic assemblies 100 similar to those in Figure 2D; for example, by separating (each portion of the core 103 having a thickness of 191 as shown in Figure 1), performing surface finishing operations such as depositing insulating material 135 on and around dies 114-1, 114-2, depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assemblies 100 of Figures 10H and 11H by forming interconnects 190 similar to those in Figure 1.

[0127] Figures 12A to 12C are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 of Figure 5A, according to various embodiments. Figure 12A shows an assembly including a core 103 having cavities 113-1, 113-2 and a TGV 110 extending between the first and second surfaces 170-1, 170-2 of the core 103. The assembly of Figure 12A may be manufactured using any suitable technique described above, for example, with reference to Figures 6 and / or 7.

[0128] Figure 12B shows the assembly after substrates 148-1, 148-2 are formed on the first and second surfaces 170-1, 170-2 of the core 103, respectively, an interconnect 152 is formed, a bridge die 202 is embedded in the second substrate 148-2, an interconnect 150 is formed to mount the EIC die 114 and XPU 128 to the top surface of the second substrate 148-2, and an interconnect 150 is formed to mount the microprocessor die 516 and PIC 104 to the top surface of the EIC die 114. The PIC 104 may have a layered bottom surface and may be optically bonded to the flat top surface 171-2 of the glass portion 115-2 using any suitable technique such as optical glue. The assembly in Figure 12B may be manufactured using any suitable technique, including the conventional package substrate manufacturing techniques described above, for example with reference to Figures 6 and / or 7.

[0129] Figure 12C shows the assembly after forming an optical path 560 between the PIC104 of subassembly 101-1 and the PIC104 of subassembly 101-2 through the glass portion 115-2. The optical path 560 may be formed by any suitable technique, including laser direct writing. In some embodiments, the optical path 560 may be formed before mounting the PIC104, and the PIC104 may be optically aligned with the optical path 560 before mounting. As shown, the assembly in Figure 12C itself may be a microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 12C to form other microelectronic assemblies 100; for example, performing surface finishing operations such as depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and mounting a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 12C by forming an interconnect 190 similar to that in Figure 1. Figure 12 shows a microelectronic assembly 100 having two subassemblies 101, but the microelectronic assembly 100 may have any appropriate number of subassemblies 101, and multiple microelectronic assemblies 100 may be manufactured together and then undergo a unitization process as described above with reference to Figure 3.

[0130] Figures 13A to 13C are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 of Figure 5B according to various embodiments. Figure 13A shows an assembly including a core 103 having notches 1317 (e.g., notches) in the upper surface 171-2 of the glass portion 115-2 and extending through cavities 113-1, 113-2 and between the first and second surfaces 170-1, 170-2 of the core 103. The notches 1317 may be formed using any suitable technique including lithography, laser-assisted wet etching, laser drilling (e.g., laser ablation using an excimer laser) or plasma etching. The notches 1317 may have any suitable shape for setting the PIC 104 into the notches 1317 (e.g., as shown in Figure 13B). The assembly of Figure 13A may be manufactured using any suitable technique described above, for example with reference to Figures 6 and / or 7.

[0131] Figure 13B shows the assembly after substrates 148-1, 148-2 are formed on the first and second surfaces 170-1, 170-2 of the core 103, respectively, an interconnect 152 is formed, a bridge die 202 is embedded in the second substrate 148-2, an interconnect 150 is formed to mount the EIC die 114 and XPU 128 to the top surface of the second substrate 148-2, and an interconnect 150 is formed to mount the microprocessor die 516 and PIC 104 to the top surface of the EIC die 114. The PIC 104 may have a flat bottom surface and may be optically coupled to a notch 1317 on the top surface 171-2 of the glass portion 115-2 using any suitable technique such as optical glue. The assembly in Figure 13B may be manufactured using any suitable technique, including the conventional package substrate manufacturing techniques described above, for example with reference to Figures 6 and / or 7.

[0132] Figure 13C shows the assembly after forming optical paths 560A and 560B between the PIC104 of subassembly 101-1 and the PIC104 of subassembly 101-2 through the glass portion 115-2. The optical paths 560A and 560B can be formed by any suitable technique, including laser direct writing. In some embodiments, the optical paths 560A and 560B may be formed before mounting the PIC104, and the PIC104 may be optically aligned with the optical paths 560A and 560B before mounting. As shown, the assembly in Figure 13C may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 13C to form other microelectronic assemblies 100; for example, performing surface finishing operations such as depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 13C by forming interconnects 190 similar to those in Figure 1. Although Figure 13 shows a microelectronic assembly 100 having two subassemblies 101, the microelectronic assembly 100 may have any appropriate number of subassemblies 101, and multiple microelectronic assemblies 100 may be manufactured together and then undergo a unitization process as described above with reference to Figure 3.

[0133] Figures 14A to 14D are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 of Figure 5D according to various embodiments. Figure 14A shows an assembly including a core 103 having cavities 113-1, 113-2 and a TGV 110 extending between the first and second surfaces 170-1, 170-2 of the core 103, where cavities 113-1 and 113-2 have different dimensions such that glass portion 115-2 is narrower than glass portion 115-1 (for example, cavity 113-2 has a larger y dimension or width). The glass portion 115-2 may be narrowed using any suitable technique, including lithography, laser-assisted wet etching, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching, when forming the cavity 113-2 (for example, as described above with reference to Figure 6), or when the glass portion 715-2 is mounted and bonded to the core 103, as described above with reference to Figure 7. The assembly in Figure 14A may be manufactured using any suitable technique described above, for example with reference to Figures 6 and / or 7.

[0134] Figure 14B shows the assembly after substrates 148-1 and 148-2 have been formed on the first and second surfaces 170-1 and 170-2 of the core 103, respectively, an interconnect 152 has been formed, the bridge die 202 has been embedded in the second substrate 148-2, the EIC die 114 and XPU 128 have been mounted on the top surface of the second substrate 148-2 by forming an interconnect 150, and the microprocessor die 516 and PIC 104 have been mounted on the top surface of the EIC die 114 by forming an interconnect 150. The assembly in Figure 14B may be manufactured using any suitable technique, including, for example, the conventional package substrate manufacturing techniques described above with reference to Figures 6 and / or 7.

[0135] Figure 14C shows the assembly after the optical polymer 505 has been deposited inside the cavity 113-2 and around the substrate 148-2, XPU 128, EIC die 114, microprocessor die 516, and PIC 104. The optical polymer 505 can be deposited using any suitable technique, such as spin coating, spray coating, or slit coating. In some embodiments, the optical polymer 505 can be cured after deposition. In some embodiments, the optical polymer can completely cover the substrate 148-2, XPU 128, EIC die 114, microprocessor die 516, and PIC 104.

[0136] Figure 14D shows the assembly after forming an optical path 560 between the PIC 104 of subassembly 101-1 and the PIC 104 of subassembly 101-2 through the optical polymer 505 and the glass portion 115-2. The optical path 560 may be formed by any suitable technique, including laser direct writing. As shown, the assembly in Figure 14D itself may be a microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 14D to form other microelectronic assemblies 100; for example, performing surface finishing operations such as depositing solder resist, depositing solder 136 on the bottom surface of the first substrate 148-1, and attaching a circuit board 131 to the bottom surface of the microelectronic assembly 100 of Figure 14D by forming an interconnect 190 similar to that in Figure 1. Figure 14 shows a microelectronic assembly 100 having two subassemblies 101, but the microelectronic assembly 100 may have any appropriate number of subassemblies 101, and multiple microelectronic assemblies 100 may be manufactured together and then undergo a unitization process as described above with reference to Figure 3.

[0137] The packages disclosed herein, for example, any of these microelectronic assemblies 100, or any further embodiments described herein, may be contained within any suitable electronic component. Figures 15 to 17 show various examples of packages, assemblies, and devices that may be used with or include any of the IC packages disclosed herein.

[0138] Figure 15 is a side cross-sectional view of an exemplary IC package 2200 which may include a microelectronic assembly according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0139] As shown in Figure 15, the package support 2252 may be formed of an insulator (e.g., ceramic, build-up film, epoxy film with filler particles inside, etc.) and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between different locations on the first surface 2272 and / or between different locations on the second surface 2274. These conductive paths may take the form of any interconnection structure including wires and / or vias, as described above, for example with reference to Figure 1.

[0140] The package support 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through the package support 2252, thereby enabling circuits in the die 2256 and / or interposer 2257 to be electrically coupled to various conductive contacts 2264 (or to other devices, not shown, contained within the package support 2252).

[0141] The IC package 2200 may include an interposer 2257 coupled to a package support 2252 via conductive contacts 2261 of the interposer 2257, a first-level interconnect (FLI) 2265, and conductive contacts 2263 of the package support 2252. The FLI 2265 shown in Figure 15 is a solder bump, but any suitable FLI 2265, such as a solder bump, solder post, or bond wire, may be used.

[0142] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254, FLI 2258, and conductive contacts 2260 of the interposer 2257. In various embodiments, the interposer 2257 may include a core 103 containing glass as described herein. The conductive contacts 2260 may allow circuits within the die 2256 to be electrically coupled to various conductive contacts 2261 (or to other devices (not shown) included in the interposer 2257) by being coupled to a conductive path (not shown) through the interposer 2257. The FLI 2258 shown in Figure 15 is a solder bump, but any suitable FLI 2258, such as a solder bump, solder post, or bond wire, may be used. As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an interface between different components; a conductive contact may be recessed into the surface of a component, coplanar with that surface, or extend away from that surface, and may take any suitable form (e.g., a conductive pad or socket).

[0143] In some embodiments, an underfill material 2266 may be positioned between the package support 2252 and the interposer 2257 around the FLI 2265, and a mold 2268 may be positioned around the die 2256 and the interposer 2257 and in contact with the package support 2252. In some embodiments, the underfill material 2266 may be the same as the mold 2268. Exemplary materials that may be used for the underfill material 2266 and the mold 2268 are, as appropriate, epoxy. A second level interconnect (SLI) 2270 may be coupled to a conductive contact 2264. The SLI 2270 shown in Figure 15 is a solder ball (e.g., for a ball grid array (BGA) configuration), but any suitable SLI 2270 (e.g., a pin in a pin grid array configuration or a land in a land grid array configuration) may be used. The SLI2270 can be used to couple the IC package 2200 to a circuit board (e.g., a motherboard), an interposer, or another component, such as another IC package known in the art and described later with reference to Figure 17.

[0144] In embodiments where the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry for performing any desired function. For example, in addition to one or more of the dies 2256 that include the components of the die 114 described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high-bandwidth memory), etc. In some embodiments, at least some of the dies 2256 do not need to include the components of the die 114 described herein.

[0145] The IC package 2200 shown in Figure 15 is a flip-chip package, but other package architectures may be used. For example, the IC package 2200 may be a BGA package such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown within the IC package 2200, the IC package 2200 may contain any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, which are located on the first or second surface 2272 of the package support 2252, or on either surface of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0146] Figure 16 is a side cross-sectional view of an IC device assembly 2300 which may include a component having one or more microelectronic assemblies 100 according to any embodiment disclosed herein. The IC device assembly 2300 includes a number of components arranged above a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components arranged above a first surface 2340 and an opposing second surface 2342 of the circuit board 2302; generally, components may be arranged above one or both of surfaces 2340 and 2342. In particular, any suitable component of the IC device assembly 2300 may include one or more microelectronic assemblies 100 according to any embodiment disclosed herein; for example, any of the IC packages described later with reference to the IC device assembly 2300 may take the form of any embodiment of the IC package 2200 described above with reference to Figure 15.

[0147] In some embodiments, the circuit board 2302 may be a PCB comprising a plurality of metal layers separated from each other by insulating layers and interconnected by conductive vias. One or more of these metal layers may be formed with a desired circuit pattern to transfer electrical signals (optionally, in conjunction with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB package support.

[0148] Figure 16 shows that in some embodiments, the IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to a first surface 2340 of a circuit board 2302 by a coupling component 2316. Not shown for the sake of not complicating the drawing, in some embodiments, the package-on-interposer structure 2336 may include a core 103, such as a glass layer. In other embodiments, the package-on-interposer structure 2336 may not include a core. The coupling component 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (as shown), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0149] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 by a coupling component 2318. In some embodiments, the IC package 2320 may include a microelectronic assembly 100 and other components described herein that are not shown for the sake of not complicating the drawings. The coupling component 2318 may take any suitable form depending on the desired function, such as the forms described above with reference to the coupling component 2316. In some embodiments, the IC package 2320 may be or include an IC package 2200, for example, as described above with reference to Figure 15.

[0150] Although a single IC package 2320 is shown in Figure 16, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intervening package support used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may redistribute connections to a wider pitch or reroute some connections to different connections. For example, the interposer 2304 may couple the IC package 2320 to the BGA of the coupling component 2316 for coupling to the circuit board 2302.

[0151] In the embodiment shown in Figure 16, the IC package 2320 and the circuit board 2302 are mounted on opposing sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be mounted on the same side of the interposer 2304. In some embodiments, three or more components may be interconnected by the interposer 2304.

[0152] The interposer 2304 may be formed from an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed from an alternative rigid or flexible material. Such material may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include a metal interconnect 2308 and vias 2310 including a TSV 2306. The interposer 2304 may further include embedded devices 2314, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take any form of package-on-interposer structure known in the art.

[0153] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to a first surface 2340 of a circuit board 2302 by a coupling component 2322. The coupling component 2322 may take any form of the embodiments described above with reference to the coupling component 2316, and the IC package 2324 may take any form of the embodiments described above with reference to the IC package 2320.

[0154] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to a second surface 2342 of a circuit board 2302 by a coupling component 2328. The package-on-package structure 2334 may include IC packages 2326 and 2332, coupled together by a coupling component 2330 such that IC package 2326 is positioned between the circuit board 2302 and IC package 2332. The coupling components 2328 and 2330 may take any form of the embodiments of the coupling component 2316 described above, and IC packages 2326 and / or 2332 may take any form of the embodiments of the IC package 2320 described above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0155] Figure 17 is a block diagram of an exemplary computing device 2400 which may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable component of the computing device 2400 may include a microelectronic assembly 100 containing glass according to any of the embodiments disclosed herein. In another example, one or more components of the computing device 2400 may include any embodiment of the IC package 2200 (for example, as shown in Figure 15). In yet another example, one or more components of the computing device 2400 may include an IC device assembly 2300 (for example, as shown in Figure 16).

[0156] Although numerous components are shown in Figure 17 as being included in the computing device 2400, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be mounted on one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SOC die.

[0157] Additionally, in various embodiments, the computing device 2400 does not have to include one or more of the components shown in Figure 17, but it may include interface circuits for coupling to one or more components. For example, the computing device 2400 does not have to include the display device 2406, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 2406 can be coupled. In another set of examples, the computing device 2400 does not have to include the audio input device 2418 or the audio output device 2408, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 2418 or the audio output device 2408 can be coupled.

[0158] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0159] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips); note that the terms “chip,” “die,” and “IC die” are used interchangeably herein. For example, the communication chip 2412 may be configured to manage multiple wireless communications for data transfer to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. This term does not imply that the devices in question do not include any wires, although this may not be the case in some embodiments.

[0160] The 2412 communication chip may implement any of the numerous wireless standards or protocols, including Institute of Electrical and Electronics Engineers (IEEE) standards, such as Wi-Fi® (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2")). IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX® networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), and Evolved HSPA (E-HSPA or LTE network). The communication chip 2412 may operate in accordance with GSM® Evolved High-Speed ​​Data Transmission (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chip 2412 may operate in accordance with several other radio protocols. The computing device 2400 may include an antenna 2422 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0161] In some embodiments, the communication chip 2412 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 2412 may comprise multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0162] The computing device 2400 may include a battery / power supply circuit 2414. The battery / power supply circuit 2414 may include a circuit for coupling components of the computing device 2400 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the computing device 2400 (e.g., AC line power).

[0163] The computing device 2400 may include a display device 2406 (or the corresponding interface circuit described above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0164] The computing device 2400 may include an audio output device 2408 (or the corresponding interface circuit described above). The audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headset, or earbuds.

[0165] The computing device 2400 may include an audio input device 2418 (or the corresponding interface circuit described above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0166] The computing device 2400 may include a GPS device 2416 (or the corresponding interface circuit described above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400 in a manner known in the art.

[0167] The computing device 2400 may include other output devices 2410 (the interface circuits described above or corresponding to them). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0168] The computing device 2400 may include other input devices 2420 (or the corresponding interface circuits described above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, imaging devices, cursor control devices such as keyboards and mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0169] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA®), ultramobile personal computer, etc.), a desktop computing device, a server device or other network-connected computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0170] The above description of illustrated implementations of the Disclosure, including matters described in the Abstract, is not intended to be exhaustive or to limit the Disclosure to the exact form disclosed. While specific implementations and examples of the Disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the Disclosure, as will be recognized by those skilled in the art.

[0171] The following paragraphs provide various examples of embodiments disclosed herein.

[0172] Example 1 provides a microelectronic assembly comprising: a glass layer having a first surface and a second surface facing the first surface; a first dielectric layer on the first surface of the glass layer, the first dielectric layer having a first side surface and a second side surface facing the first side surface; a second dielectric layer on the second surface of the glass layer, the second dielectric layer having a third side surface and a fourth side surface facing the third side surface; a first glass portion on the first surface of the glass layer on the first side surface of the first dielectric layer; a second glass portion on the first surface of the glass layer on the second side surface of the first dielectric layer; a third glass portion on the second surface of the glass layer on the third side surface; and a fourth glass portion on the second surface of the glass layer on the fourth side surface.

[0173] Example 2 provides the microelectronic assembly described in Example 1, wherein the glass layer thickness is between 50 microns and 2 millimeters.

[0174] Example 3 provides the microelectronic assembly described in Example 1 or 2, wherein the thickness of the first glass portion is between 50 microns and 2 millimeters.

[0175] Example 4 provides a microelectronic assembly according to any one of Examples 1 to 3, wherein the thickness of the second glass portion is between 50 microns and 2 millimeters.

[0176] Example 5 provides a microelectronic assembly according to any one of Examples 1 to 4, further comprising: a through-glass via (TGV) in a glass layer having a conductive material; a first conductive path in a first dielectric layer electrically coupled to at least one of the TGVs; and a second conductive path in a second dielectric layer electrically coupled to at least one of the TGVs.

[0177] Example 6 provides the microelectronic assembly according to Example 5, further comprising a die located on a second dielectric layer and electrically coupled to a second conductive path within the second dielectric layer.

[0178] Example 7 provides the microelectronic assembly described in Example 6, further comprising an interconnect die that is at least partially located within a second dielectric layer and electrically coupled to the die.

[0179] Example 8 provides a microelectronic assembly according to any one of Examples 5 to 7, further comprising a circuit board located in the first dielectric layer and electrically coupled to the first conductive path.

[0180] Example 9 provides the microelectronic assembly described in Example 6 or 7, further comprising insulating material surrounding the die.

[0181] Example 10 provides a microelectronic assembly comprising a glass layer having a first surface and an opposing second surface, wherein the glass layer has a first cavity in the first surface; a second cavity in the second surface; and through-glass vias (TGVs) extending through the glass layer between the top surface of the first cavity and the bottom surface of the second cavity, the TGVs comprising a conductive material; a first dielectric material in the first cavity, the first dielectric material comprising a first conductive path electrically coupled to the TGVs; and a second dielectric material in the second cavity, the second dielectric material comprising a second conductive path electrically coupled to the TGVs.

[0182] Example 11 provides the microelectronic assembly described in Example 10, wherein the total thickness of the glass layer is between 50 microns and 2 millimeters.

[0183] Example 12A. A microelectronic assembly as described in Example 10, wherein the thickness of the first cavity is between 5 microns and 120 microns.

[0184] Example 12B. The microelectronic assembly described in Example 10, wherein the thickness of the second cavity is between 5 microns and 120 microns.

[0185] Example 12C. The microelectronic assembly according to Example 10, wherein the thickness of the glass layer between the first cavity and the second cavity is between 50 microns and 1.2 millimeters.

[0186] Example 13 provides a microelectronic assembly according to Example 10 or 11, wherein a first conductive path is electrically coupled to the TGV by a first interconnection including solder, and a second conductive path is electrically coupled to the TGV by a second interconnection including solder.

[0187] Example 14 provides the microelectronic assembly described in Example 13, further comprising a first underfill material around the first interconnection and between the first dielectric and the upper surface of the first cavity; and a second underfill material around the second interconnection and between the second dielectric and the bottom surface of the second cavity.

[0188] Example 15 provides a microelectronic assembly according to any one of Examples 10 to 14, further comprising insulating material in a second cavity around a second dielectric.

[0189] Example 16 provides a microelectronic assembly according to any one of Examples 10 to 15, further comprising a die located on a second dielectric and electrically coupled to a second conductive path within the second dielectric.

[0190] Example 17 provides the microelectronic assembly according to Example 16, wherein the die is a first die, the second conductive path in the second dielectric is one of a plurality of second conductive paths, and the microelectronic assembly further comprises a second die on the second dielectric, which is electrically coupled to one or more of the second conductive paths in the second dielectric.

[0191] Example 18 provides the microelectronic assembly described in Example 17, further comprising an interconnecting die that is at least partially located within a second dielectric and electrically coupled to the first die and the second die.

[0192] Example 19 provides the microelectronic assembly described in Example 18, further comprising a circuit board located in the first dielectric and electrically coupled to the first conductive path.

[0193] Example 20 provides a microelectronic assembly comprising: a first layer having a first dielectric, a third dielectric, and a first glass portion between the first and third dielectrics; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second and fourth dielectrics; and a third layer between the first and second layers, comprising a bulk glass material, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer.

[0194] Example 21 provides the microelectronic assembly described in Example 20, wherein the thickness of the third layer is between 50 microns and 2 millimeters.

[0195] Example 22 provides the microelectronic assembly described in Example 20 or 21, wherein the thickness of the first layer is between 50 microns and 2 millimeters.

[0196] Example 23 provides a microelectronic assembly according to any one of Examples 20 to 22, wherein the thickness of the second layer is between 50 microns and 2 millimeters.

[0197] Example 24 provides a microelectronic assembly according to any one of Examples 20 to 23, further comprising: a through-glass via (TGV) in a third layer through a bulk glass material containing a conductive material; a first conductive path in a first dielectric electrically coupled to at least one of the TGVs; a second conductive path in a second dielectric electrically coupled to at least one of the TGVs; a third conductive path in a third dielectric electrically coupled to at least one of the TGVs; and a fourth conductive path in a fourth dielectric electrically coupled to at least one of the TGVs.

[0198] Example 25 provides the microelectronic assembly described in Example 24, further comprising a first die located on a second dielectric and electrically coupled to a second conductive path within the second dielectric; and a second die located on a fourth dielectric and electrically coupled to a fourth conductive path within the fourth dielectric.

[0199] Example 26 provides the microelectronic assembly according to Example 25, further comprising a fifth dielectric on a second glass portion between a second dielectric and a fourth dielectric; and a fifth conductive path through the fifth dielectric electrically coupling the first die and the second die.

[0200] Example 27 provides a microelectronic assembly according to Example 25 or 26, further comprising a substrate in a first layer, a conductive path in which the substrate is electrically coupled to a first conductive path in a first dielectric and to a third conductive path in a third dielectric, wherein a first die is electrically coupled to a second die by the conductive path in the substrate, the first conductive path and the third conductive path.

[0201] Example 28 provides a microelectronic assembly according to any one of Examples 25 to 27, wherein the first die is one of a plurality of first dies, the second die is one of a plurality of second dies, and the microelectronic assembly further comprises a first interconnect die that is at least partially in a second dielectric and electrically coupled to at least two of the plurality of first dies; and a second interconnect die that is at least partially in a fourth dielectric and electrically coupled to at least two of the plurality of second dies.

[0202] Example 29 provides the microelectronic assembly described in Example 28, further comprising a first insulating material surrounding a plurality of first dies and a second insulating material surrounding a plurality of second dies.

[0203] Example 30 provides a microelectronic assembly according to any one of Examples 24 to 29, further comprising: a first photonic integrated circuit (PIC) on a second dielectric, the first PIC being electrically coupled to a second conductive path in the second dielectric; and a second PIC on a fourth dielectric, the second PIC being electrically coupled to a fourth conductive path in the fourth dielectric, wherein the second PIC is optically coupled to the first PIC by an optical path through a second glass portion between the second and fourth dielectrics.

[0204] Example 31 provides the microelectronic assembly described in Example 30, wherein the optical path includes a waveguide.

[0205] Example 32 provides the microelectronic assembly described in Example 31, wherein the waveguide is a waveguide that is laser-written.

[0206] Example 33 provides a microelectronic assembly according to any one of Examples 30 to 32, further comprising a first PIC and a first electrical integrated circuit (EIC) die and a first processor integrated circuit (XPU) conductively coupled to a second conductive path in a second dielectric; and a second PIC and a second EIC die and a second XPU conductively coupled to a fourth conductive path in a fourth dielectric.

[0207] Example 34 provides a microelectronic assembly comprising: a first layer having a first dielectric, a third dielectric, and a first glass portion between the first and third dielectrics; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second and fourth dielectrics; and a third layer between the first and second layers, the third layer having a bulk glass material, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer; and the first glass portion includes a first undercut adjacent to the first dielectric and a second undercut adjacent to the third dielectric.

[0208] Example 35 provides the microelectronic assembly according to Example 34, wherein the second glass portion further includes a third undercut on the second surface of the third layer adjacent to the second dielectric, and a fourth undercut on the second surface of the third layer adjacent to the fourth dielectric.

[0209] Example 36 provides a microelectronic assembly according to Example 34 or 35, wherein a first glass portion frames a first dielectric and a third dielectric, and a second glass portion frames a second dielectric and a fourth dielectric.

[0210] Example 37 provides the microelectronic assembly according to Example 36, wherein the first dielectric is one of a plurality of first dielectrics, the third dielectric is one of a plurality of third dielectrics, the first glass portion is one of a plurality of first glass portions, the second dielectric is one of a plurality of second dielectrics, the fourth dielectric is one of a plurality of fourth dielectrics, and the second glass portion is one of a plurality of second glass portions.

[0211] Example 38 provides a microelectronic assembly according to any one of Examples 34 to 37, further comprising: a first material on the surface of a first glass portion, wherein the surface of the first glass portion faces a third layer, and the first material comprises an adhesive material or a molding material; and a second material on the first material on the surface of the first glass portion, wherein the second material comprises a conductive material having a thickness between 10 microns and 70 microns.

[0212] Example 39 provides the microelectronic assembly according to Example 38, further comprising a first material on the surface of a second glass portion, wherein the surface of the second glass portion faces a third layer; and a second material on the first material on the surface of the second glass portion.

[0213] Example 40 provides the microelectronic assembly described in Example 39, wherein a first glass portion frames a first dielectric and a third dielectric, and a second glass portion frames a second dielectric and a fourth dielectric.

[0214] Example 41 provides the microelectronic assembly according to Example 40, wherein the first dielectric is one of a plurality of first dielectrics, the third dielectric is one of a plurality of third dielectrics, the first glass portion is one of a plurality of first glass portions, the second dielectric is one of a plurality of second dielectrics, the fourth dielectric is one of a plurality of fourth dielectrics, and the second glass portion is one of a plurality of second glass portions.

[0215] Example 42 provides a microelectronic assembly according to any one of Examples 34 to 41, wherein the third layer has a plurality of through-glass vias (TGVs), the first dielectric includes a first conductive path electrically coupled to at least one of the plurality of TGVs, the second dielectric includes a second conductive path electrically coupled to at least one of the plurality of TGVs, the third dielectric includes a third conductive path electrically coupled to at least one of the plurality of TGVs, and the fourth dielectric includes a fourth conductive path electrically coupled to at least one of the plurality of TGVs.

[0216] Example 43 provides the microelectronic assembly described in Example 42, further comprising a die located on a first dielectric and electrically coupled to a first conductive path by interconnection.

[0217] Example 44 provides the microelectronic assembly according to Example 43, wherein the die is a first die, the interconnection is a first interconnection, and the microelectronic assembly further comprises a second die which is at least partially within the first dielectric and electrically coupled to the first die by the second interconnection.

[0218] Example 45 provides the microelectronic assembly described in Example 44, further comprising a third die electrically coupled to the second die by a third interconnection.

[0219] Example 46 provides the microelectronic assembly described in Example 45, further comprising insulating material surrounding the first die and the third die.

[0220] Example 47 provides a microelectronic assembly comprising a glass layer having a first surface and an opposing second surface, wherein the glass layer includes a first cavity in the first surface, the first cavity including a first undercut along the sidewall of the first cavity; a second cavity in the second surface, the second cavity including a second undercut along the sidewall of the second cavity; and a through-glass via (TGV) extending through the glass layer between the top surface of the first cavity and the bottom surface of the second cavity, the TGV being made of a conductive material; a first dielectric in the first cavity, the first dielectric including a first conductive path electrically coupled to the TGV; and a second dielectric in the second cavity, the second dielectric including a second conductive path electrically coupled to the TGV.

[0221] [Other possible items] [Item 1] A glass layer having a first surface and an opposing second surface. Equipped with, The aforementioned glass layer is A first cavity within the first surface; The second cavity within the second surface; and Through the glass layer, a through-glass via (TGV) extends between the upper surface of the first cavity and the bottom surface of the second cavity. It has, The aforementioned TGV is, Conductive materials; The first dielectric in the first cavity, the first dielectric includes a first conductive path electrically coupled to the TGV; and The second dielectric in the second cavity includes a second conductive path electrically coupled to the TGV. including, Microelectronic assembly. [Item 2] The microelectronic assembly described in item 1, wherein the total thickness of the glass layer is between 50 microns and 2 millimeters. [Item 3] The microelectronic assembly described in item 1, wherein the total thickness of the glass layer is between 150 microns and 6 millimeters. [Item 4] The microelectronic assembly according to item 1, wherein the first conductive path is electrically coupled to the TGV by a first interconnection, and the second conductive path is electrically coupled to the TGV by a second interconnection. [Item 5] The first interconnection and the second interconnection include solder, and the microelectronic assembly is A first underfill material surrounding the first interconnection and between the first dielectric and the upper surface of the first cavity; and The second underfill material is located around the second interconnection and between the second dielectric and the bottom surface of the second cavity. The microelectronic assembly described in item 4 further comprises the features described in item 4. [Item 6] insulating material in the second cavity surrounding the second dielectric The microelectronic assembly described in item 1 further includes the features described in item 1. [Item 7] A die located on the second dielectric and electrically coupled to the second conductive path within the second dielectric. The microelectronic assembly described in item 1 further includes the features described in item 1. [Item 8] A circuit board electrically coupled to the first conductive path in the first dielectric. The microelectronic assembly described in item 1 further includes the features described in item 1. [Item 9] A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer comprising bulk glass material is located between the first and second layers, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer. A microelectronic assembly equipped with [the following features]. [Item 10] The total thickness of the third layer is between 50 microns and 2 millimeters, as described in item 9 of the microelectronic assembly. [Item 11] Through-glass vias (TGVs) in the third layer through the bulk glass material containing a conductive material; A first conductive path within the first dielectric, electrically coupled to at least one of the TGVs; A second conductive path within the second dielectric, electrically coupled to at least one of the TGVs; A third conductive path within the third dielectric, electrically coupled to at least one of the aforementioned TGVs; A fourth conductive path within the fourth dielectric, electrically coupled to at least one of the aforementioned TGVs; A first die on the second dielectric, electrically coupled to the second conductive path within the second dielectric; and A second die on the fourth dielectric, electrically coupled to the fourth conductive path within the fourth dielectric. The microelectronic assembly described in item 9 further includes the features described in item 9. [Item 12] A fifth dielectric on the second glass portion between the second dielectric and the fourth dielectric; and A fifth conductive path passing through the fifth dielectric, which electrically couples the first die and the second die. The microelectronic assembly described in item 11 further comprises the following: [Item 13] The substrate in the first layer includes a conductive path that is electrically coupled to the first conductive path in the first dielectric and to the third conductive path in the third dielectric, wherein the first die is electrically coupled to the second die by the conductive path in the substrate, the first conductive path and the third conductive path. The microelectronic assembly described in item 11 further comprises the following: [Item 14] A first photonic integrated circuit (PIC) on the second dielectric, the first PIC being electrically coupled to the second conductive path in the second dielectric; and The second PIC is located on the fourth dielectric, and the second PIC is electrically coupled to the fourth conductive path within the fourth dielectric, where the second PIC is optically coupled to the first PIC by an optical path passing through the second glass portion between the second and fourth dielectrics. The microelectronic assembly described in item 11 further comprises the following: [Item 15] The optical path includes a waveguide, as described in item 14, in the microelectronic assembly. [Item 16] The waveguide is a laser-written waveguide, as described in item 15 of the microelectronic assembly. [Item 17] A first electrical integrated circuit (EIC) die and a first processor integrated circuit (XPU) conductively coupled to the second conductive path in the first PIC and the second dielectric; and The second EIC die and the second XPU are electrically coupled to the second PIC and the fourth conductive path within the fourth dielectric. The microelectronic assembly described in item 14 further comprises the following: [Item 18] A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer between the first and second layers, the third layer having a bulk glass material Equipped with, Here, The first layer is physically bonded to the first surface of the third layer, and the second layer is physically bonded to the second surface of the third layer; and The first glass portion includes a first undercut adjacent to the first dielectric and a second undercut adjacent to the third dielectric. Microelectronic assembly. [Item 19] A first material on the surface of the first glass portion, wherein the surface of the first glass portion is opposite to the third layer, wherein the first material includes an adhesive material or a molding material; and A second material on the first material on the surface of the first glass portion, wherein the second material is a conductive material having a thickness between 10 microns and 70 microns. The microelectronic assembly described in item 18 further comprises the following: [Item 20] The first material on the surface of the second glass portion, wherein the surface of the second glass portion faces the third layer; and The second material on the first material on the surface of the second glass portion The microelectronic assembly described in item 19 further comprises the following: [Item 21] A glass layer having a first surface and an opposing second surface. Equipped with, The aforementioned glass layer is A first cavity within the first surface; The second cavity within the second surface; and Through the glass layer, a through-glass via (TGV) extends between the upper surface of the first cavity and the bottom surface of the second cavity. It has, The aforementioned TGV is, Conductive materials; The first dielectric in the first cavity, the first dielectric includes a first conductive path electrically coupled to the TGV; and The second dielectric in the second cavity includes a second conductive path electrically coupled to the TGV. including, Microelectronic assembly. [Item 22] The microelectronic assembly described in item 21, wherein the total thickness of the glass layer is between 50 microns and 2 millimeters. [Item 23] The total thickness of the glass layer is between 150 microns and 6 millimeters, as described in item 21, for the microelectronic assembly. [Item 24] The microelectronic assembly according to any one of items 21 to 23, wherein the first conductive path is electrically coupled to the TGV by a first interconnection, and the second conductive path is electrically coupled to the TGV by a second interconnection. [Item 25] The first interconnection and the second interconnection include solder, and the microelectronic assembly is A first underfill material surrounding the first interconnection and between the first dielectric and the upper surface of the first cavity; and The second underfill material is located around the second interconnection and between the second dielectric and the bottom surface of the second cavity. The microelectronic assembly described in item 24 further comprises the following: [Item 26] insulating material in the second cavity surrounding the second dielectric A microelectronic assembly as described in any one of items 21 to 25, further comprising: [Item 27] A die located on the second dielectric and electrically coupled to the second conductive path within the second dielectric. A microelectronic assembly as described in any one of items 21 to 26, further comprising: [Item 28] The die is a first die, the second conductive path in the second dielectric is one of a plurality of second conductive paths, and the microelectronic assembly is A second die on the second dielectric, electrically coupled to one or more of the second conductive paths within the second dielectric. The microelectronic assembly described in item 27 further comprises the following: [Item 29] An interconnect die that is at least partially located within the second dielectric and electrically coupled to the first die and the second die. The microelectronic assembly described in item 28 further includes the features described therein. [Item 30] A circuit board electrically coupled to the first conductive path in the first dielectric. A microelectronic assembly further comprising any one of items 21 to 29. [Item 31] A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer comprising bulk glass material is located between the first and second layers, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer. An integrated circuit (IC) package that includes [a specific feature / feature]. [Item 32] The IC package described in item 31, wherein the thickness of the third layer is between 50 microns and 2 millimeters. [Item 33] Through-glass vias (TGVs) in the third layer passing through the bulk glass material containing the conductive material; A first conductive path in the first dielectric electrically coupled to at least one of the TGVs; A second conductive path in the second dielectric electrically coupled to at least one of the TGVs; A third conductive path in the third dielectric electrically coupled to at least one of the TGVs; A fourth conductive path in the fourth dielectric electrically coupled to at least one of the TGVs; A first die on the second dielectric and electrically coupled to the second conductive path in the second dielectric; and A second die on the fourth dielectric and electrically coupled to the fourth conductive path in the fourth dielectric The IC package according to item 31, further comprising. [Item 34] A fifth dielectric on the second glass portion between the second dielectric and the fourth dielectric; and A fifth conductive path passing through the fifth dielectric electrically coupling the first die and the second die The IC package according to item 33, further comprising. [Item 35] A substrate in the first layer, the substrate including a conductive path electrically coupled to the first conductive path in the first dielectric and electrically coupled to the third conductive path in the third dielectric, wherein the first die is electrically coupled to the second die by the conductive path in the substrate, the first conductive path, and the third conductive path The IC package according to item 33 or 34, further comprising. [Item 36] A first photonic integrated circuit (PIC) on the second dielectric, the first PIC being electrically coupled to the second conductive path in the second dielectric; and A second PIC on the fourth dielectric, the second PIC being electrically coupled to the fourth conductive path in the fourth dielectric, wherein the second PIC is optically coupled to the first PIC by an optical path passing through the second glass portion between the second dielectric and the fourth dielectric The IC package according to any one of items 33 to 35, further comprising [Item 37] The IC package according to item 36, wherein the optical path includes a waveguide. [Item 38] A first electrical integrated circuit (EIC) die and a first processor integrated circuit (XPU) conductively coupled to the second conductive path in the first PIC and the second dielectric; and A second EIC die and a second XPU conductively coupled to the fourth conductive path in the second PIC and the fourth dielectric The IC package according to item 36, further comprising [Item 39] A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer between the first layer and the second layer, the third layer having a bulk glass material Comprising Here The first layer is physically bonded to the first surface of the third layer, and the second layer is physically bonded to the second surface of the third layer; and The first glass portion includes a first undercut adjacent to the first dielectric and a second undercut adjacent to the third dielectric Substrate. [Item 40] The substrate according to item 39, wherein the second glass portion further includes a third undercut on the second surface of the third layer adjacent to the second dielectric, and a fourth undercut on the second surface of the third layer adjacent to the fourth dielectric. [Item 41] The substrate according to item 39 or 40, wherein the first glass portion borders the first dielectric and the third dielectric, and the second glass portion borders the second dielectric and the fourth dielectric. [Item 42] A first material on the surface of the first glass portion, wherein the surface of the first glass portion is opposite to the third layer, wherein the first material includes an adhesive material or a molding material; and A second material is placed on the first material, wherein the second material is a conductive material having a thickness between 10 microns and 70 microns. A substrate as described in any one of items 39 to 41, further comprising: [Item 43] The first material on the surface of the second glass portion, wherein the surface of the second glass portion faces the third layer; and The second material on the first material on the surface of the second glass portion A circuit board as described in item 42, further comprising the features described therein. [Item 44] The substrate according to any one of items 39 to 43, wherein the third layer has a plurality of through-glass vias (TGVs), the first dielectric includes a first conductive path electrically coupled to at least one of the plurality of TGVs, the second dielectric includes a second conductive path electrically coupled to at least one of the plurality of TGVs, the third dielectric includes a third conductive path electrically coupled to at least one of the plurality of TGVs, and the fourth dielectric includes a fourth conductive path electrically coupled to at least one of the plurality of TGVs. [Item 45] The substrate according to any one of items 39 to 44, wherein the first dielectric is one of a plurality of first dielectrics, the third dielectric is one of a plurality of third dielectrics, the first glass portion is one of a plurality of first glass portions, the second dielectric is one of a plurality of second dielectrics, the fourth dielectric is one of a plurality of fourth dielectrics, and the second glass portion is one of a plurality of second glass portions.

Claims

1. A glass layer having a first surface and an opposing second surface. Equipped with, The aforementioned glass layer is A first cavity within the first surface; The second cavity within the second surface; and Through the glass layer, a through-glass via (TGV) extends between the upper surface of the first cavity and the bottom surface of the second cavity. It has, The aforementioned TGV is, conductive materials; The first dielectric in the first cavity, the first dielectric includes a first conductive path electrically coupled to the TGV; and The second dielectric in the second cavity includes a second conductive path electrically coupled to the TGV. including, Microelectronic assembly.

2. The microelectronic assembly according to claim 1, wherein the total thickness of the glass layer is between 50 microns and 2 millimeters.

3. The microelectronic assembly according to claim 1, wherein the total thickness of the glass layer is between 150 microns and 6 millimeters.

4. The microelectronic assembly according to claim 1, wherein the first conductive path is electrically coupled to the TGV by a first interconnection, and the second conductive path is electrically coupled to the TGV by a second interconnection.

5. The first interconnection and the second interconnection include solder, and the microelectronic assembly is A first underfill material surrounding the first interconnection and between the first dielectric and the upper surface of the first cavity; and The second underfill material is located around the second interconnection and between the second dielectric and the bottom surface of the second cavity. The microelectronic assembly according to claim 4, further comprising:

6. insulating material in the second cavity surrounding the second dielectric The microelectronic assembly according to claim 1, further comprising:

7. A die located on the second dielectric and electrically coupled to the second conductive path within the second dielectric. The microelectronic assembly according to claim 1, further comprising:

8. The die is a first die, the second conductive path in the second dielectric is one of a plurality of second conductive paths, and the microelectronic assembly is A second die on the second dielectric, electrically coupled to one or more of the second conductive paths within the second dielectric. The microelectronic assembly according to claim 7, further comprising:

9. An interconnect die that is at least partially located within the second dielectric and electrically coupled to the first die and the second die. The microelectronic assembly according to claim 8, further comprising:

10. A circuit board electrically coupled to the first conductive path in the first dielectric. A microelectronic assembly according to any one of claims 1 to 9, further comprising:

11. A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer comprising bulk glass material is located between the first layer and the second layer, wherein the first layer is physically bonded to a first surface of the third layer, and the second layer is physically bonded to a second surface of the third layer. An integrated circuit (IC) package that includes [a specific feature / feature].

12. The IC package according to claim 11, wherein the thickness of the third layer is between 50 microns and 2 millimeters.

13. A through-glass via (TGV) in the third layer passing through the bulk glass material containing a conductive material; A first conductive path within the first dielectric, electrically coupled to at least one of the TGVs; A second conductive path within the second dielectric, electrically coupled to at least one of the TGVs; A third conductive path within the third dielectric, electrically coupled to at least one of the TGVs; A fourth conductive path within the fourth dielectric, electrically coupled to at least one of the TGVs; A first die on the second dielectric, electrically coupled to the second conductive path within the second dielectric; and A second die on the fourth dielectric, electrically coupled to the fourth conductive path within the fourth dielectric. The IC package according to claim 11, further comprising:

14. A fifth dielectric on the second glass portion between the second dielectric and the fourth dielectric; and A fifth conductive path passing through the fifth dielectric, which electrically couples the first die and the second die. The IC package according to claim 13, further comprising:

15. The substrate in the first layer includes a conductive path that is electrically coupled to the first conductive path in the first dielectric and to the third conductive path in the third dielectric, wherein the first die is electrically coupled to the second die by the conductive path in the substrate, the first conductive path and the third conductive path. The IC package according to claim 13, further comprising:

16. A first photonic integrated circuit (PIC) on the second dielectric, the first PIC being electrically coupled to the second conductive path in the second dielectric; and The second PIC is located on the fourth dielectric, and the second PIC is electrically coupled to the fourth conductive path within the fourth dielectric, where the second PIC is optically coupled to the first PIC by an optical path passing through the second glass portion between the second and fourth dielectrics. The IC package according to any one of claims 13 to 15, further comprising the above.

17. The IC package according to claim 16, wherein the optical path includes a waveguide.

18. A first electrical integrated circuit (EIC) die and a first processor integrated circuit (XPU) conductively coupled to the second conductive path in the first PIC and the second dielectric; and The second EIC die and the second XPU are electrically coupled to the second PIC and the fourth conductive path within the fourth dielectric. The IC package according to claim 16, further comprising:

19. A first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; A second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and A third layer between the first and second layers, the third layer having a bulk glass material. Equipped with, Here, The first layer is physically bonded to the first surface of the third layer, and the second layer is physically bonded to the second surface of the third layer; and The first glass portion includes a first undercut adjacent to the first dielectric and a second undercut adjacent to the third dielectric. substrate.

20. The substrate according to claim 19, wherein the second glass portion further includes a third undercut on the second surface of the third layer adjacent to the second dielectric, and a fourth undercut on the second surface of the third layer adjacent to the fourth dielectric.

21. The substrate according to claim 19, wherein the first glass portion borders the first dielectric and the third dielectric, and the second glass portion borders the second dielectric and the fourth dielectric.

22. A first material on the surface of the first glass portion, wherein the surface of the first glass portion faces the third layer, and the first material includes an adhesive material or a molding material; and A second material is placed on the first material, wherein the second material is a conductive material having a thickness between 10 microns and 70 microns. The substrate according to claim 19, further comprising:

23. The first material on the surface of the second glass portion, wherein the surface of the second glass portion faces the third layer; and The second material on the first material on the surface of the second glass portion The substrate according to claim 22, further comprising:

24. The substrate according to claim 19, wherein the third layer has a plurality of through-glass vias (TGVs), the first dielectric includes a first conductive path electrically coupled to at least one of the plurality of TGVs, the second dielectric includes a second conductive path electrically coupled to at least one of the plurality of TGVs, the third dielectric includes a third conductive path electrically coupled to at least one of the plurality of TGVs, and the fourth dielectric includes a fourth conductive path electrically coupled to at least one of the plurality of TGVs.

25. The substrate according to any one of claims 19 to 24, wherein the first dielectric is one of a plurality of first dielectrics, the third dielectric is one of a plurality of third dielectrics, the first glass portion is one of a plurality of first glass portions, the second dielectric is one of a plurality of second dielectrics, the fourth dielectric is one of a plurality of fourth dielectrics, and the second glass portion is one of a plurality of second glass portions.

Images