Semiconductor equipment

Abstract

To provide a semiconductor device with excellent transistor characteristics. [Solution] The semiconductor device comprises a substrate, an oxide semiconductor layer spaced apart from the substrate in a first direction intersecting the substrate surface and containing a first metal element and oxygen (O), a first wiring facing a part of the oxide semiconductor layer, a gate insulating film provided between the oxide semiconductor layer and the first wiring, a first conductive layer in contact with one end of the oxide semiconductor layer in the first direction and containing a second metal element and oxygen (O), a second wiring electrically connected to one end of the oxide semiconductor layer in the first direction, and a first insulating portion in contact with the second wiring. The first insulating portion includes a first region and a second region located between the first region and the second wiring, wherein the concentration of the first or second metal element in the second region is greater than the concentration of the first or second metal element in the first region.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device.

Background Art

[0002] A semiconductor device including an oxide semiconductor layer, a first wiring facing the oxide semiconductor layer, and a gate insulating film provided between the oxide semiconductor layer and the first wiring is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device having excellent transistor characteristics.

Means for Solving the Problems

[0005] A semiconductor device according to one embodiment includes a substrate, an oxide semiconductor layer spaced apart from the substrate in a first direction intersecting the surface of the substrate and containing a first metal element and oxygen (O), a first wiring facing a part of the oxide semiconductor layer, a gate insulating film provided between the oxide semiconductor layer and the first wiring, a first conductive layer in contact with one end of the oxide semiconductor layer in the first direction and containing a second metal element and oxygen (O), a second wiring electrically connected to one end of the oxide semiconductor layer in the first direction, and a first insulating portion in contact with the second wiring. The first insulating portion includes a first region and a second region between the first region and the second wiring, and the concentration of the first metal element or the second metal element in the second region is greater than the concentration of the first metal element or the second metal element in the first region.

Brief Description of the Drawings

[0006] [Figure 1]This is a schematic circuit diagram showing a part of the configuration of a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor device. [Figure 3] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor device. [Figure 4] This is a schematic plan view showing a part of the configuration of the semiconductor device. [Figure 5] This is a schematic plan view showing a part of the configuration of the semiconductor device. [Figure 6] This is a schematic plan view showing a part of the configuration of the semiconductor device. [Figure 7] This diagram illustrates the metal element concentration distribution in a part of the configuration of the semiconductor device. [Figure 8] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device. [Figure 9] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 10] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 11] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19]This is a schematic cross-sectional view showing a partial configuration of a modified example of the semiconductor device according to the first embodiment. [Figure 20] This figure illustrates the concentration distribution of metal elements in some of the configurations of the modified example. [Figure 21] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor device according to the third embodiment. [Figure 27] This is a schematic plan view showing a part of the configuration of the semiconductor device. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 34] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 35] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor device according to the fourth embodiment. [Figure 37] This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 39] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 41] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view illustrating the manufacturing method. [Modes for carrying out the invention]

[0007] Next, a semiconductor device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0009] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0010] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0011] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0012] [First Embodiment] [Circuit Configuration] The semiconductor device according to the first embodiment includes, for example, a memory cell array MCA and a peripheral circuit PC as shown in Figure 1.

[0013] The memory cell array MCA comprises multiple bit lines BL, multiple word lines WL, multiple plate lines PL, and multiple memory cells MC connected to these multiple bit lines BL, multiple word lines WL, and multiple plate lines PL. Each of the multiple memory cells MC connected to one word line WL is connected to a different bit line BL. Furthermore, each of the multiple memory cells MC connected to one bit line BL is connected to a different word line WL.

[0014] Each memory cell MC comprises a selection transistor ST and a capacitor Cap connected in series between the bit line BL and the plate line PL.

[0015] The selection transistor ST is a field-effect transistor comprising a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. A word line WL is connected to the gate electrode of the selection transistor ST.

[0016] The capacitor Cap is a capacitor including a pair of electrodes and an insulating film. The capacitor Cap includes a memory section.

[0017] The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage and outputs it to a voltage supply line, a decode circuit that connects a desired voltage supply line to each wiring (bit line BL, word line WL, and plate line PL) in the memory cell array MCA, a sense amplifier circuit that detects the current or voltage of the bit line BL, and the like.

[0018] FIG. 2 is a schematic cross-sectional view showing a part of the configuration of the semiconductor device. As shown in FIG. 2, the semiconductor device according to the first embodiment includes a substrate Sub and a transistor layer L spaced apart from the substrate Sub in the Z direction Tr and a wiring layer L Tr provided above the transistor layer L ML and a wiring layer L ML provided above the wiring layer L UL and a capacitor layer L Tr provided below the transistor layer L CP and a plate line layer L CP provided below the capacitor layer L PT and a peripheral circuit layer L PT provided on the substrate Sub below the plate line layer L PC and includes. The substrate Sub includes, for example, P-type silicon (Si) containing a P-type impurity such as boron (B).

[0019] Also, as shown in FIG. 2, the semiconductor device according to the first embodiment includes a memory region R MC provided on the substrate Sub and a peripheral region R PC and includes.

[0020] [Structure of the memory region R MC Next, referring to FIGS. 2 to 6, the structure of the memory region R MC will be described. FIG. 3 is a view of the memory region R MC ​Figure 4 is a schematic cross-sectional view showing a part of the configuration of Figure 3, cut along line AA' and viewed in the direction of the arrow. Figure 5 is a schematic cross-sectional view showing a part of the configuration of Figure 3, cut along line BB' and viewed in the direction of the arrow. Figure 6 is a schematic cross-sectional view showing a part of the configuration of Figure 3, cut along line CC' and viewed in the direction of the arrow. Note that in Figure 6, a part of the configuration shown in Figure 5 is shown by a dotted line.

[0021] Memory area R MC transistor layer L Tr For example, as shown in Figure 3, the capacitor layer L CP It comprises an insulating layer 111 provided on the upper surface and an insulating layer 113 provided above the insulating layer 111. Furthermore, the memory area R MC transistor layer L Tr As shown in Figure 4, for example, it comprises multiple insulating layers 112 and multiple conductive layers 150 arranged alternately in the X direction, provided between insulating layer 111 and insulating layer 113. MC transistor layer L Tr As shown in Figure 4, for example, it comprises a plurality of semiconductor layers 130 arranged in the X and Y directions corresponding to a plurality of conductive layers 150, and an insulating layer 140 provided on the outer surface of the semiconductor layers 130.

[0022] Furthermore, as shown in Figure 4, for example, the positions in the Y direction of the multiple semiconductor layers 130 corresponding to one conductive layer 150 and the multiple semiconductor layers 130 corresponding to the other conductive layer 150 may be different for two adjacent conductive layers 150 in the X direction.

[0023] The insulating layer 111, insulating layer 112, and insulating layer 113 include, for example, silicon oxide (SiO2).

[0024] The semiconductor layer 130 is stretched, for example, in the Z direction and has a substantially cylindrical shape. The semiconductor layer 130 is an oxide semiconductor and functions, for example, as the channel region of a selective transistor ST (Figure 1). The semiconductor layer 130 includes, for example, at least one element selected from the metallic element group GP1 and oxygen (O). The metallic element group GP1 includes indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), calcium (Ca), and cadmium (Cd). The semiconductor layer 130 may also contain, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0025] The insulating layer 140 is stretched, for example, in the Z direction and has a substantially cylindrical shape. The insulating layer 140 functions, for example, as a gate insulating film of a selection transistor ST (Figure 1). The insulating layer 140 contains, for example, silicon oxide (SiO2). The insulating layer 140 may also have a laminated structure of silicon oxide (SiO2) and silicon nitride (SiN) or other high dielectric constant insulating layer.

[0026] The conductive layer 150 functions, for example, as the gate electrodes of multiple selection transistors ST aligned in the Y direction, and as the word line WL of the memory cell array MCA (Figure 1). The conductive layer 150 may also include, for example, tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0027] Memory area R MC Wiring layer L ML For example, as shown in Figure 3, the transistor layer L Tr Plug layer L provided on the upper surface PL And, the plug layer L PL Bit line layer L provided on the upper surface BL and bit line layer L BL It comprises a conductive layer 192 and an insulating layer 190H provided on the upper surface.

[0028] Plug layer L PL For example, as shown in Figures 3 and 5, at a position corresponding to the semiconductor layer 130, the transistor layer LTr The device comprises conductive layers 170, 171, and 172, arranged in order on the upper surface, and an insulating layer 175L. The conductive layers 170, 171, and 172 are each electrically connected to the semiconductor layer 130. The insulating layer 175L is provided on the outer circumferential surfaces of the conductive layers 170, 171, and 172, for example, as shown in Figures 3 and 5. Hereinafter, the structure including the conductive layers 170, 171, and 172 may be referred to as plug PG.

[0029] The structure, including the plug PG and the insulating layer 175L, has a substantially cylindrical shape extending in the Z direction, as shown in Figures 3 and 5, for example, and is arranged in multiples in the X and Y directions. The plug PG functions, for example, as the source electrode of a selection transistor ST. An insulating layer 173H is provided between the multiple structures, including the plug PG and the insulating layer 175L.

[0030] The conductive layer 170 includes, for example, at least one element selected from the metallic element group GP2, and oxygen (O). The metallic element group GP2 includes indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo). The conductive layer 170 may also be, for example, indium tin oxide (InSnO).

[0031] The conductive layer 171 includes, for example, titanium nitride (TiN).

[0032] The conductive layer 172 includes, for example, tungsten (W), aluminum (Al), molybdenum (Mo), etc.

[0033] The insulating layers 173H and 175L will be described later.

[0034] Bit layer L BL For example, as shown in Figures 3 and 6, the plug layer L is located at a position corresponding to the conductive layer 172. PLThe device comprises conductive layers 181, 182, and 184, which are sequentially provided on at least a portion of the upper surface. The conductive layers 181, 182, and 184 are electrically connected to a plurality of conductive layers 172 that are aligned in the X direction corresponding to the conductive layers 181, 182, and 184 (Figure 6).

[0035] The structure, which includes conductive layers 181, 182, and 184, extends in the X direction and is arranged in a row in the Y direction, as shown in Figures 3 and 6, for example. Conductive layers 181, 182, and 184 function, for example, as bit lines BL (Figure 1) of a memory cell array MCA. An insulating layer 183H is provided between these structures arranged in the Y direction.

[0036] The conductive layer 181 and the conductive layer 184 include, for example, titanium nitride (TiN).

[0037] The conductive layer 182 contains, for example, metallic elements such as tungsten (W), aluminum (Al), and molybdenum (Mo).

[0038] The insulating layer 183H will be discussed later.

[0039] The insulating layer 190H will be discussed later.

[0040] The conductive layer 192 is stretched in the Z direction, as shown in Figures 2 and 3, for example, and has a substantially cylindrical shape. The lower surface of the conductive layer 192 is connected to the conductive layer 184. The conductive layer 192 may also contain, for example, tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0041] Wiring layer L UL For example, as shown in Figure 2, the wiring layer L ML The device comprises a wiring 301 provided on the upper surface, a wiring 302 provided on the upper surface of the wiring 301 and connected to the wiring 301, and a wiring 303 provided on the upper surface of the wiring 302 and connected to the wiring 302. An insulating layer 304, such as silicon oxide (SiO2), is provided between the wiring 301, the wiring 302, and the wiring 303.

[0042] Wires 301, 302, and 303 function, for example, as wiring that supplies voltage and current to the bit line BL. Wires 301, 302, and 303 include, for example, copper (Cu), tungsten (W), aluminum (Al), etc.

[0043] Memory area R MC capacitor layer L CP As shown in Figures 2 and 3, for example, it comprises a plurality of conductive layers 120 provided corresponding to a plurality of semiconductor layers 130 and connected to the lower ends of each of the plurality of semiconductor layers 130, a plurality of conductive layers 201 provided corresponding to these plurality of conductive layers 120 and connected to the lower ends of each of the plurality of conductive layers 120, and a plurality of conductive layers 121 provided on the outer circumferential surfaces of the plurality of conductive layers 120 and the outer circumferential and lower surfaces of the plurality of conductive layers 201. CP It comprises an insulating layer 202 provided on the outer and lower surfaces of the conductive layer 121, and a conductive layer 203 provided on the outer and lower surfaces of the insulating layer 202 (Figure 3). In the following description, these memory areas R MC capacitor layer L CP The configuration that realizes the capacitor Cap (Figure 1) provided therein is sometimes called the "capacitor structure CP10". The capacitor structure CP10 includes, for example, a conductive layer 120, a conductive layer 121, a conductive layer 201, an insulating layer 202, and a conductive layer 203. Between the multiple capacitor structures CP10, an insulating layer 100 such as silicon oxide (SiO2) is provided.

[0044] The conductive layer 120 functions, for example, as part of the drain electrode of the selection transistor ST (Figure 1) and as part of one of the electrodes of the capacitor Cap (Figure 1). The conductive layer 120 is substantially circular in the XY cross-section and may have a plug shape. The conductive layer 120 contains, for example, the same material as the conductive layer 170. The conductive layer 120 may be, for example, indium tin oxide (InSnO).

[0045] The conductive layer 121 functions, for example, as part of one electrode of the capacitor Cap (Figure 1). The conductive layer 121 may be made of, for example, titanium nitride (TiN).

[0046] The conductive layer 201 functions as part of one electrode of the capacitor Cap (Figure 1). The conductive layer 201 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

[0047] The insulating layer 202 functions as an insulating layer between the electrodes of the capacitor Cap (Figure 1). The insulating layer 202 includes, for example, aluminum oxide (AlO). The insulating layer 202 may also be, for example, silicon oxide (SiO2) or other insulating metal oxides.

[0048] The conductive layer 203 functions, for example, as the other electrode of the capacitor Cap (Figure 1). The conductive layer 203 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

[0049] Memory area R MC Plate layer L PT For example, as shown in Figure 2, the capacitor layer L CP The device includes a conductive layer 204 provided on its lower surface. The conductive layer 204 is electrically connected to a plurality of conductive layers 203. The conductive layer 204 functions, for example, as a plate wire PL (Figure 1). The conductive layer 204 may include, for example, tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0050] [Peripheral region R PC [Structure] Surrounding region R PC transistor layer L Tr As shown in Figure 2, for example, the device comprises a portion of the conductive layer 150 that functions as a word line WL, and an electrode 151 connected to the lower end of the conductive layer 150. The electrode 151 may include, for example, tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0051] Surrounding region RPC capacitor layer L CP As shown in Figure 2, for example, it comprises multiple electrodes CC extending in the Z direction. The electrodes CC, for example, are connected to electrode 151 at the upper end and to the plate wire layer L at the lower end. PT It is electrically connected to a portion of the multiple conductive layers 205 described later. The electrode CC may include, for example, tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0052] Surrounding region R PC Plate layer L PT As shown in Figure 2, for example, the device comprises multiple conductive layers 205. The conductive layers 205 may contain, for example, the same material as conductive layer 204.

[0053] Surrounding region R PC Peripheral circuit layer L PC As shown in Figure 2, for example, the circuit comprises a plurality of transistors TrP1 provided on a substrate Sub, and a plurality of electrodes 210 connected to the plurality of transistors TrP1. The plurality of electrodes 210 are connected to a conductive layer 205 at their upper ends. Each of the plurality of electrodes 210 is connected to the source region, drain region, gate electrode, etc., of the plurality of transistors TrP1. The plurality of transistors TrP1 constitute, for example, a peripheral circuit PC (Figure 1).

[0054] [Insulating layers: 173H, 183H, 190H, 175L] Insulating layer 173H, insulating layer 183H, and insulating layer 190H (Figure 3) are hereafter referred to as insulating layers belonging to insulating layer group H, or simply as insulating layer group H. Transistor layer L Tr More capacitor layer L CP In the areas farther from the surface, an insulating layer belonging to insulating layer group H is formed, as shown in Figure 3, for example.

[0055] Insulating layer group H includes, for example, a relatively high-density material. Insulating layer group H includes, for example, a highly crystalline film, which makes it difficult for oxygen (O) to diffuse through grain boundaries or highly amorphous regions.

[0056] Insulating layer group H includes, for example, silicon (Si) and oxygen (O). Insulating layer group H also includes, for example, relatively high-density silicon oxide (SiO2).

[0057] The insulating layer group H is formed, for example, by CVD (Chemical Vapor Deposition). When forming the insulating layer group H by CVD, it is formed at a relatively high temperature, for example, around 400°C.

[0058] The insulating layer group H is formed, for example, by ALD (Atomic Layer Deposition). When forming the insulating layer group H by ALD, for example, the oxidation conditions in the oxidation step after supplying the raw material elements are set to conditions that facilitate crystallization, densification, etc., such as a relatively high oxygen partial pressure and a relatively long processing time.

[0059] The insulating layer 175L may be referred to below as an insulating layer belonging to insulating layer group L, or simply as insulating layer group L.

[0060] Insulating layer group L includes, for example, a material with relatively low density. Insulating layer group L includes, for example, a film with low crystallinity, which is prone to oxygen (O) diffusion through grain boundaries and highly amorphous regions.

[0061] The insulating layer group L includes, for example, silicon (Si) and oxygen (O). The insulating layer group L also includes, for example, relatively low-density silicon oxide (SiO2).

[0062] The insulating layer group L is formed, for example, by CVD. When forming the insulating layer group L by CVD, it is formed at a relatively low temperature, for example, at a stage temperature of about 300°C.

[0063] The insulating layer group L is formed, for example, by ALD. When forming the insulating layer group L by ALD, for example, the oxidation conditions in the oxidation step after supplying the raw material elements are set to conditions that do not easily promote crystallization, densification, etc., such as a relatively low oxygen partial pressure and a relatively short processing time.

[0064] The density of insulating layer group H is greater than the density of insulating layer group L. Note that density here refers to film density. For example, the average density of the multiple materials constituting insulating layer group H is greater than the average density of the multiple materials constituting insulating layer group L. The densities of the materials contained in insulating layer group H and insulating layer group L can be measured, for example, by electron energy loss spectroscopy, X-ray reflectivity, etc.

[0065] [Concentration of metal elements in insulating layers 173H and 175L] Figure 7 is a diagram illustrating the metal element concentration distribution in a part of the configuration of the semiconductor memory device according to this embodiment. The lower part of Figure 7 is the plug layer L PL This is the corresponding figure. The upper part of Figure 7 is a graph showing the concentration of metal elements along the FF' line shown at the bottom of Figure 7.

[0066] The insulating layer 175L and the insulating layer 173H each contain, for example, at least one element selected from the metal element group GP1 or the metal element group GP2, and oxygen (O). The insulating layer 175L and the insulating layer 173H may also be insulating layers in which at least one element selected from the metal element group GP1 or the metal element group GP2 is diffused into an insulating film such as silicon oxide (SiO2). This is due to the diffusion of metal element group GP1 from the semiconductor layer 130 and metal element group GP2 from the conductive layer 170 into the insulating layers 175L and 173H during the oxygen supply process described later (Figure 14).

[0067] In the following explanation, for example, the total concentration of one or more elements selected from metal element group GP1 or metal element group GP2 in the insulating layer 175L, insulating layer 173H, and conductive layer 172 may be referred to as the metal element concentration.

[0068] The graph at the top of Figure 7 shows the position P inside the insulating layer 173H. 11 The concentration of metal elements in concentration De 11 , position P inside the insulating layer 175L 12 The concentration of metal elements in concentration De 12 , position P inside the conductive layer 172 13 The concentration of metal elements in concentration De 13 This is shown as such.

[0069] Concentration De inside the 175L insulating layer 12 This is the concentration De inside the insulating layer 173H. 11 It is higher than that. The insulating layer 175L includes, for example, a relatively low-density film, and the insulating layer 173H includes, for example, a relatively high-density film. Metal elements diffuse more easily into the low-density film than into the high-density film. Therefore, in the oxygen supply process described later (Figure 14), a relatively large amount of metal elements diffuse from the semiconductor layer 130 and the conductive layer 170 to the insulating layer 175L, and a relatively small amount of metal elements diffuse into the insulating layer 173H.

[0070] Concentration De inside the conductive layer 172 13 This is the concentration De inside the insulating layer 173H. 11 It is lower than that. The conductive layer 170 contains a material that does not readily allow other metallic elements to diffuse, such as tungsten (W). Therefore, in the oxygen supply process described later, a very small amount of metallic elements diffuse into the conductive layer 172.

[0071] The concentration of metal elements can be measured, for example, by energy dispersive X-ray spectroscopy, electron energy loss spectroscopy, or the like.

[0072] [Manufacturing method] Next, the method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 8 to 18. Figures 8 to 18 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to the first embodiment. Note that the drawings relating to the manufacturing method below are schematic, and some components may be omitted for the sake of explanation.

[0073] In this manufacturing method, a peripheral circuit layer L is placed above the substrate Sub (not shown). PC (Figure 2) and plate layer L PT (Figure 2) and the capacitor layer L CP (Figure 2) and are formed. Also, as shown in Figure 8, for example, the capacitor layer L CP An insulating layer 111, an insulating layer 112 (Figure 4), a conductive layer 150, and an insulating layer 113 are formed sequentially on the upper surface. This process is carried out, for example, by CVD and RIE (Reactive Ion Etching).

[0074] Next, an opening TH10 is formed, for example, as shown in Figure 9. The opening TH10 extends in the Z direction, penetrating the insulating layer 113, the conductive layer 150, and the insulating layer 111, exposing the conductive layer 120 (Figure 3). This process is carried out, for example, by RIE.

[0075] Next, as shown in Figure 10, for example, an insulating layer 140 and a semiconductor layer 130 are formed in the opening TH10. The insulating layer 140 is formed by first forming an insulating layer containing the same material as the insulating layer 140 on the inner surface and bottom surface of the opening TH10, and then removing the portion of the insulating layer formed on the bottom surface of the opening TH10. The semiconductor layer 130 is formed in contact with the inner surface of the insulating layer 140 and to embed the opening TH10. This process is carried out by, for example, ALD, CVD, RIE, CMP (Chemical Mechanical Planarization), etc.

[0076] Next, as shown in Figure 11, for example, conductive layers 170', 171', and 172' are sequentially formed on the upper surface of the structure shown in Figure 10. The conductive layers 170', 171', and 172' each contain the same material as conductive layers 170, 171, and 172, for example. This process is carried out by, for example, CVD.

[0077] Next, as shown in Figure 12, for example, a mask material is formed at the positions corresponding to conductive layer 170, conductive layer 171, and conductive layer 172 by photolithography or the like, and the conductive layers 170, conductive layer 171, and conductive layer 172 are formed by removing the parts not covered by the mask material. This process is carried out by, for example, RIE.

[0078] Next, as shown in Figure 13, for example, an insulating layer 175La is formed on the upper surface of the insulating layer 113, the sides of the conductive layer 170, conductive layer 171, and conductive layer 172, and on the upper surface of the conductive layer 172. The insulating layer 175La contains the same material as the insulating layer 175L. The insulating layer 175La may contain at least one element selected from the metal element group GP1 or the metal element group GP2, but the concentration of the metal element in the insulating layer 175La is lower than the concentration of the metal element in the insulating layer 175L. This process is carried out by CVD or ALD, etc.

[0079] Next, as shown in Figure 14, for example, oxygen is supplied to the semiconductor layer 130 via oxygen supply paths PA10 and PA11. This process causes the metal elements in metal element group GP1 to diffuse from the semiconductor layer 130 to the insulating layer 175La. Additionally, the metal elements in metal element group GP2 diffuse from the conductive layer 170 to the insulating layer 175La. This diffusion transforms the insulating layer 175La into insulating layer 175Lb. Insulating layer 175Lb contains the same material as insulating layer 175L. The metal element concentration in insulating layer 175Lb is equivalent to that of insulating layer 175L. This process is carried out, for example, by annealing at approximately 500°C under an oxygen (O) atmosphere.

[0080] The oxygen supply path PA10 is a path that can supply oxygen (O) from the upper surface of the semiconductor layer 130, for example, via an insulating layer 175 Lb and a conductive layer 170 such as indium tin oxide (InSnO).

[0081] The oxygen supply path PA11 is a path that can supply oxygen (O) from the side of the semiconductor layer 130, for example, via an insulating layer 175Lb, an insulating layer 113 made of silicon oxide (SiO2), and an insulating layer 140.

[0082] Next, as shown in Figure 15, for example, the upper surface portion of the insulating layer 113 and the upper surface portion of the conductive layer 172 are removed from the insulating layer 175b to form the insulating layer 175L. This process is carried out, for example, by RIE.

[0083] Next, as shown in Figure 16, for example, an insulating layer containing the same material as the insulating layer 173H is formed on the upper surface of the structure shown in Figure 15, and the upper surface is removed until the upper portion of the conductive layer 172 is exposed, thereby forming the insulating layer 173H. This process is carried out by, for example, CVD, ALD, CMP, etc. During this process and subsequent processes, metal elements included in the metal element group GP1 or metal element group GP2 diffuse from the semiconductor layer 130, conductive layer 170, and insulating layer 175L into the insulating layer 173H.

[0084] Next, as shown in Figure 17, for example, an insulating layer 183H' containing the same material as insulating layer 183H is formed on the upper surface of the structure shown in Figure 16. This process is carried out, for example, by CVD.

[0085] Next, as shown in Figure 18, for example, conductive layers 181, 182, 184, and insulating layer 183H are formed. This step may be carried out by, for example, the damascene method. In the damascene method of this step, openings are formed in the insulating layer 183H' in the portion where conductive layers 181, 182, and 184 are to be formed, and conductive layers 181, 182, and 184 are formed inside these openings. This step can be carried out by, for example, CVD, RIE, and CMP.

[0086] Next, on the upper surface of the structure shown in Figure 18, a wiring layer L UL The semiconductor device according to the first embodiment is manufactured by forming (Figure 2), etc.

[0087] [Comparative Example] Comparative Example 1 lacks the insulating layer 175L (Figure 3) provided on the outer surface of the plug PG (Figure 3), and instead has only a high-density insulating layer, such as insulating layer 173H, between adjacent plugs PG (Figure 3). In a configuration like that of Comparative Example 1, in the oxygen supply process (Figure 14), there is no low-density insulating layer 175L that is permeable to oxygen, so a sufficient amount of oxygen may not be supplied to the semiconductor layer 130. In such a case, good switching characteristics of the selection transistor ST (Figure 1) may not be obtained.

[0088] Comparative Example 2 lacks the insulating layer 173H (Figure 3) provided between adjacent plugs PG (Figure 3), and instead has only a low-density insulating layer, such as insulating layer 175L, between adjacent plugs PG. In a configuration like that of Comparative Example 2, for example, during the oxygen supply process (Figure 14), a large amount of metal elements may diffuse into the low-density insulating layer, causing electrical conductivity between adjacent plugs PG.

[0089] [effect] In the semiconductor device according to this embodiment, during the oxygen supply process (Figure 14), a sufficient amount of oxygen can be supplied to the semiconductor layer 130 via the oxygen-permeable insulating layer 175Lb. Therefore, good switching characteristics of the selection transistor ST (Figure 1) can be obtained.

[0090] Furthermore, in the semiconductor device according to this embodiment, by providing an insulating layer 173H containing a high-density material that does not easily diffuse metal elements between adjacent plugs PG (Figure 3), good insulation can be achieved between adjacent plugs PG.

[0091] [Modified version of the first embodiment] Next, a modified example of the semiconductor device according to the first embodiment will be described with reference to Figure 19. Figure 19 is a schematic cross-sectional view showing a part of the configuration of the semiconductor device according to this modified example.

[0092] The semiconductor device according to this modified example is basically configured the same as the semiconductor device according to the first embodiment (Figure 3). However, the semiconductor device according to this modified example (Figure 19) has a cavity 176 inside the insulating layer 173H.

[0093] The cavity 176 refers to a so-called space surrounded by solid materials arranged around the portion containing the cavity 176, while the portion containing the cavity 176 does not contain any solid materials. The cavity 176 is a space containing, for example, air consisting of a mixture of multiple gases such as nitrogen, oxygen, and noble gases. The cavity 176 may be degassed so that it does not contain any gases.

[0094] Figure 20 is a diagram illustrating the metal element concentration distribution in this modified example. The lower part of Figure 20 shows the plug layer L. PL This is the corresponding figure. The upper part of Figure 20 is a graph showing the concentration of metal elements in the region along the GG' line shown at the bottom of Figure 20.

[0095] The graph at the top of Figure 20 shows the position P between the insulating layer 175L and the cavity 176 within the insulating layer 173H. 11 The concentration of metal elements in concentration De 11 , at position P, which is the end of the insulating layer 173H in contact with the cavity 176. 14 The concentration of metal elements in concentration De 14 This is shown as such.

[0096] Concentration De 14 is, concentration De 11 It is higher than that. Metal elements tend to diffuse and segregate towards the edges of the insulating layer 173H in contact with the cavity 176. Therefore, in the oxygen supply process (Figure 14), a relatively large amount of metal elements diffuse to the edges of the insulating layer 173H in contact with the cavity 176.

[0097] In the example shown in Figure 20, the concentration De 14 is, concentration De 12 Higher than, but concentration De 14 and circuitsDe 12 It can be of the same degree, and concentration De14 is concentration De 12 It can be even lower.

[0098] [Second Embodiment] Next, a semiconductor device according to the second embodiment will be described using Figures 21 to 25.

[0099] The semiconductor device according to this embodiment is basically configured in the same way as the semiconductor device according to the first embodiment (Figure 3). However, the semiconductor device according to this embodiment is manufactured by a manufacturing method that differs in some respects from the first embodiment.

[0100] [Manufacturing method] Figures 21 to 25 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to this embodiment.

[0101] The semiconductor device according to this embodiment is basically manufactured in the same manner as the semiconductor device according to the first embodiment. However, in the manufacturing method of the semiconductor device according to this embodiment, the steps shown in Figures 21 to 25 are performed after the steps described with reference to Figures 8 to 13.

[0102] For example, in the process shown in Figure 21, the upper surface portion of the insulating layer 113 and the upper surface portion of the conductive layer 172 are removed from the insulating layer 175La to form the insulating layer 175La_2. This process is carried out, for example, by RIE.

[0103] Next, as shown in Figure 22, for example, an insulating layer containing the same material as the insulating layer 173H is formed on the upper surface of the structure shown in Figure 21, and the upper surface is removed until the upper portion of the conductive layer 172 is exposed, thereby forming the insulating layer 173H. This process is carried out by, for example, CVD, ALD, CMP, etc.

[0104] Next, as shown in Figure 23, for example, an insulating layer 183L is formed on the upper surface of the structure shown in Figure 22. The insulating layer 183L is, for example, an insulating layer belonging to insulating layer group L. This process is carried out by, for example, CVD or ALD.

[0105] Next, as shown in Figure 24, for example, oxygen is supplied to the semiconductor layer 130 through oxygen supply paths PA20 and PA21. This process causes the metal elements in the metal element group GP1 to diffuse from the semiconductor layer 130 to the insulating layer 175La_2. Additionally, the metal elements in the metal element group GP2 diffuse from the conductive layer 170 to the insulating layer 175La_2. This diffusion transforms the insulating layer 175La_2 into the insulating layer 175L. This process is carried out, for example, by annealing at approximately 500°C in an oxygen (O) atmosphere.

[0106] The oxygen supply path PA20 is a path that can supply oxygen (O) from the upper surface of the semiconductor layer 130 via, for example, an insulating layer 183L, an insulating layer 175L, and a conductive layer 170 such as indium tin oxide (InSnO).

[0107] The oxygen supply path PA21 is a path that can supply oxygen (O) from the side of the semiconductor layer 130 via, for example, insulating layer 183L, insulating layer 175L, and insulating layers 113 and 140 made of silicon oxide (SiO2).

[0108] Next, the insulating layer 183L is removed, for example, as shown in Figure 25. This step is performed by, for example, wet etching, RIE, etc.

[0109] Next, perform the same steps as those described with reference to Figures 17 and 18, and also perform the wiring layer L UL By forming (Figure 2), etc., the semiconductor device according to the second embodiment is manufactured.

[0110] [effect] In the semiconductor device according to this embodiment, the oxidation of the conductive layer 172 can be prevented by supplying oxygen to the semiconductor layer 130 via the insulating layer 183L (Figure 24).

[0111] [Third Embodiment] Next, a semiconductor device according to the third embodiment will be described with reference to Figures 26 and 27.

[0112] The semiconductor device according to this embodiment is basically configured the same as the semiconductor device according to the first embodiment (Figure 3). However, unlike the first embodiment, the semiconductor device according to this embodiment (Figure 26) includes insulating layers 185L provided on both sides in the Y direction of the conductive layer 181, conductive layer 182, and conductive layer 184, respectively.

[0113] The insulating layer 185L is, for example, an insulating layer belonging to insulating layer group L. The insulating layer 185L overlaps with the insulating layer 175L when viewed from the Z direction, as shown in Figure 27, and includes a portion PT30 that is in contact with the insulating layer 175L.

[0114] The insulating layer 185L and the insulating layer 183H each contain, for example, at least one element selected from the metal element group GP1 or the metal element group GP2, and oxygen (O). The insulating layer 185L and the insulating layer 183H may also be insulating layers in which at least one element selected from the metal element group GP1 or the metal element group GP2 is diffused into an insulating film such as silicon oxide (SiO2). This is due to the fact that in the oxygen supply step (Figure 34) and the steps after Figure 34, metal element group GP1 diffuses from the semiconductor layer 130 and metal element group GP2 diffuses from the conductive layer 170 to the insulating layer 185L and the insulating layer 183H.

[0115] In the following explanation, for example, the total concentration of one or more elements selected from metal element group GP1 or metal element group GP2 in the insulating layer 185L, insulating layer 183H, and conductive layer 182 may be referred to as the metal element concentration.

[0116] The concentration of metal elements inside insulating layer 185L is higher than the concentration of metal elements inside insulating layer 183H. Insulating layer 185L contains, for example, a relatively low-density film, while insulating layer 183H contains, for example, a relatively high-density film. Therefore, in the oxygen supply process described later (Figure 34), a relatively large amount of metal elements diffuse from semiconductor layer 130 and conductive layer 170 to insulating layer 185L, and a relatively small amount of metal elements diffuse to insulating layer 183H.

[0117] The concentration of metal elements inside the conductive layer 182 is lower than the concentration of metal elements inside the insulating layer 183H. The conductive layer 182 contains materials that do not readily allow other metal elements to diffuse, such as tungsten (W). Therefore, in the oxygen supply process described later (Figure 34), only a very small amount of metal elements diffuse into the conductive layer 182.

[0118] [Manufacturing method] Figures 28 to 35 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to this embodiment.

[0119] The semiconductor device according to this embodiment is basically manufactured in the same manner as the semiconductor device according to the second embodiment. However, in the manufacturing method of the semiconductor device according to this modified example, the steps shown in Figures 28 to 35 are performed after the steps described with reference to Figure 22.

[0120] For example, in the process shown in Figure 28, conductive layers 181', 182', and 184' are formed sequentially on the upper surface of the structure shown in Figure 22. Conductive layers 181', 182', and 184' each contain the same material as conductive layers 181, 182, and 184, respectively. This process is carried out, for example, by CVD.

[0121] Next, as shown in Figure 29, for example, a mask material is formed at the positions corresponding to conductive layer 181, conductive layer 182, and conductive layer 184 by photolithography or the like, and the conductive layers 181, conductive layer 182, and conductive layer 184 are formed by removing the parts not covered by the mask material. This process is carried out by, for example, RIE.

[0122] Next, as shown in Figure 30, for example, an insulating layer 185La is formed on the upper surface of the insulating layer 173H, on both sides of the conductive layer 181, conductive layer 182, and conductive layer 184, and on the upper surface of the conductive layer 184. The insulating layer 185La contains the same material as the insulating layer 185L. The insulating layer 185La may contain at least one element selected from the metal element group GP1 or the metal element group GP2, but the concentration of the metal element in the insulating layer 185La is lower than the concentration of the metal element in the insulating layer 185L. This process is carried out by, for example, CVD or ALD.

[0123] Next, as shown in Figure 31, for example, the upper surface portion of the insulating layer 173H and the upper surface portion of the conductive layer 184 are removed from the insulating layer 185La to form the insulating layer 185La_2. This process is carried out, for example, by RIE.

[0124] Next, as shown in Figure 32, for example, an insulating layer containing the same material as insulating layer 183H is formed on the upper surface of the structure shown in Figure 31, and the upper surface is removed until the upper portion of the conductive layer 184 is exposed, thereby forming insulating layer 183H_2. Insulating layer 183H_2 is, for example, an insulating layer belonging to insulating layer group H. This process is carried out by, for example, CVD, ALD, CMP, etc.

[0125] Next, as shown in Figure 33, for example, an insulating layer 190L is formed on the upper surface of the structure shown in Figure 32. The insulating layer 190L is, for example, an insulating layer belonging to insulating layer group L. This process is carried out by, for example, CVD or ALD.

[0126] Next, as shown in Figure 34, for example, oxygen is supplied to the semiconductor layer 130 through oxygen supply paths PA30 and PA31. In this process, the metal elements contained in metal element group GP1 diffuse from the semiconductor layer 130 to the insulating layer 175La_2 and insulating layer 185La_2. Also, the metal elements contained in metal element group GP2 diffuse from the conductive layer 170 to the insulating layer 175La_2 and insulating layer 185La_2. Through this diffusion, the insulating layer 175La_2 and insulating layer 185La_2 become the insulating layer 175L and insulating layer 185L. This process is carried out, for example, by annealing at about 500°C in an oxygen (O) atmosphere.

[0127] The oxygen supply path PA30 is a path that can supply oxygen (O) from the upper surface of the semiconductor layer 130 via, for example, the insulating layer 190L, insulating layer 185L, insulating layer 175L, and a conductive layer 170 such as indium tin oxide (InSnO). Furthermore, the path between insulating layer 185L and insulating layer 175L in the oxygen supply path PA30 may be via the portion PT30 (Figure 27) where insulating layer 185L and insulating layer 175L are in direct contact, or it may be via a portion of insulating layer 173H.

[0128] The oxygen supply path PA31 is a path that can supply oxygen (O) from the side surface of the semiconductor layer 130, for example, via insulating layer 190L, insulating layer 185L, insulating layer 175L, and insulating layers 113 and 140 such as silicon oxide (SiO2). Furthermore, the path between insulating layer 185L and insulating layer 175L in the oxygen supply path PA31 may be via the portion PT30 (Figure 27) where insulating layer 185L and insulating layer 175L are in direct contact, or it may be via insulating layer 173H in part.

[0129] Next, the insulating layer 190L and insulating layer 183H_2 are removed, for example, as shown in Figure 35. This step is carried out by, for example, wet etching, RIE, etc.

[0130] Next, for example, an insulating layer containing the same material as insulating layer 183H is formed on the upper surface of the structure shown in Figure 35, thereby forming the structure described with reference to Figure 26.

[0131] [effect] In the semiconductor device according to this embodiment, compared to the first and second embodiments, a step of supplying oxygen to the semiconductor layer 130 (Figure 34) is performed in a later step, thereby recovering oxygen deficiencies caused by oxygen detachment from the semiconductor layer 130 during the manufacturing process, and supplying a sufficient amount of oxygen to the semiconductor layer 130. Therefore, good switching characteristics of the selection transistor ST (Figure 1) can be obtained.

[0132] [Fourth Embodiment] Next, a semiconductor device according to the fourth embodiment will be described using Figure 36.

[0133] The semiconductor device according to this embodiment is basically configured the same as the semiconductor device according to the third embodiment (Figure 26). However, unlike the third embodiment, the semiconductor device according to this embodiment (Figure 36) is equipped with an insulating layer 475L instead of an insulating layer 175L.

[0134] The insulating layer 475L is provided in contact with the outer surfaces of the conductive layers 170 and 171, a portion of the outer surface of the conductive layer 172, and a portion of the lower surface of the conductive layer 181, as shown in Figure 36, for example. A portion of the upper surface of the insulating layer 475L is in contact with the lower surface of the insulating layer 185L.

[0135] The insulating layer 475L is, for example, an insulating layer belonging to insulating layer group L.

[0136] The insulating layer 475L includes, for example, at least one element selected from the metal element group GP1 or the metal element group GP2, and oxygen (O). The insulating layer 475L may also be an insulating layer in which at least one element selected from the metal element group GP1 or the metal element group GP2 is diffused into an insulating film such as silicon oxide (SiO2). This is due to the fact that in the oxygen supply step (Figure 42) and the steps after Figure 42 described later, the metal element group GP1 diffuses from the semiconductor layer 130 and the metal element group GP2 diffuses from the conductive layer 170 into the insulating layer 475L.

[0137] In the following explanation, for example, the total concentration of one or more elements selected from metal element group GP1 or metal element group GP2 in the insulating layer 475L may be referred to as the metal element concentration.

[0138] The concentration of metal elements inside the insulating layer 475L is higher than the concentration of metal elements inside the insulating layer 173H. The insulating layer 475L contains, for example, a relatively low-density film, while the insulating layer 173H contains, for example, a relatively high-density film. Therefore, in the oxygen supply process described later (Figure 42), a relatively large amount of metal elements diffuse from the semiconductor layer 130 and the conductive layer 170 to the insulating layer 475L, and a relatively small amount of metal elements diffuse to the insulating layer 173H.

[0139] [Manufacturing method] Figures 37 to 42 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to this embodiment.

[0140] The semiconductor device according to this embodiment is basically manufactured in the same manner as the semiconductor device according to the third embodiment. However, in the manufacturing method of the semiconductor device according to this embodiment, the steps shown in Figures 37 to 41 are performed instead of the steps described with reference to Figures 28 to 31.

[0141] For example, in the process shown in Figure 37, a portion of the insulating layer 175La_2 (Figure 22) is removed to form insulating layer 175La_3. Additionally, a portion of the upper surface of insulating layer 173H is removed. Note that in this process, etching proceeds more easily in insulating layer 175La_2, which contains a lower-density material, than in insulating layer 173H. This process is carried out, for example, by wet etching, RIE, etc.

[0142] Next, as shown in Figure 38, for example, an insulating layer containing the same material as the insulating layer 175L is formed on the upper surface of the structure shown in Figure 37, and the upper surface is removed until the upper portion of the conductive layer 172 is exposed, thereby forming the insulating layer 175La_4. This process is carried out by, for example, CVD, ALD, CMP, etc.

[0143] Next, as shown in Figure 39, for example, conductive layers 181, 182, and 184 are formed in the same manner as described with reference to Figures 28 and 29.

[0144] Next, as shown in Figure 40, for example, an insulating layer 185La is formed on the upper surfaces of the insulating layer 175La_4 and the conductive layer 172, on both sides of the conductive layer 181, conductive layer 182, and conductive layer 184, and on the upper surface of the conductive layer 184. This process is carried out by, for example, CVD, ALD, etc.

[0145] Next, as shown in Figure 41, for example, the upper surfaces of insulating layer 173H and conductive layer 172, and the upper surface of conductive layer 184 are removed from insulating layer 185La and insulating layer 175La_4 to form insulating layer 185La_2 and insulating layer 475La. This process is carried out by, for example, RIE.

[0146] Next, the insulating layer 183H_2 is formed in the same manner as described with reference to Figure 32.

[0147] Next, an insulating layer 190L is formed in the same manner as described with reference to Figure 33.

[0148] Next, as shown in Figure 42, for example, oxygen is supplied to the semiconductor layer 130 through oxygen supply paths PA40 and PA41. In this process, the metal elements contained in metal element group GP1 diffuse from the semiconductor layer 130 to the insulating layer 475La and insulating layer 185La_2. Also, the metal elements contained in metal element group GP2 diffuse from the conductive layer 170 to the insulating layer 475La and insulating layer 185La_2. Through this diffusion, the insulating layer 475La and insulating layer 185La_2 become the insulating layer 475L and insulating layer 185L. This process is carried out, for example, by annealing at about 500°C in an oxygen (O) atmosphere.

[0149] The oxygen supply path PA40 is a path that can supply oxygen (O) from the upper surface of the semiconductor layer 130 via, for example, an insulating layer 190L, an insulating layer 185L, an insulating layer 475L, and a conductive layer 170 such as indium tin oxide (InSnO).

[0150] The oxygen supply path PA41 is a path that can supply oxygen (O) from the side of the semiconductor layer 130 via insulating layers 113 and 140, such as insulating layer 190L, insulating layer 185L, insulating layer 475L, and silicon oxide (SiO2).

[0151] [effect] In the semiconductor device according to this embodiment, in the oxygen supply process (Figure 42), since the oxygen supply paths PA40 and PA41 are all composed of insulating layers containing low-density material, a sufficient amount of oxygen can be supplied to the semiconductor layer 130. Therefore, good switching characteristics of the selection transistor ST (Figure 1) can be obtained.

[0152] [Other embodiments] The semiconductor devices according to the first to fourth embodiments have been described above. However, the semiconductor devices according to these embodiments are merely examples, and the specific configuration, operation, etc., can be adjusted as appropriate.

[0153] For example, the above explanation described an example in which a capacitor Cap (Figure 1) is connected to a selection transistor ST (Figure 1). In such an example, the shape, structure, etc., of the capacitor Cap can be adjusted as appropriate.

[0154] Furthermore, the above explanation described an example in which a capacitor Cap (Figure 1) is used as the memory section connected to the selection transistor ST (Figure 1). However, the memory section does not have to be a capacitor Cap. For example, the memory section may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other materials, and record data by utilizing the properties of these materials. For example, in any of the structures described above, one of these materials may be included in the insulating layer between the electrodes forming the capacitor Cap.

[0155] Furthermore, in the above explanation, an example was shown in which the semiconductor layer 130, which functions as the channel region of the selection transistor ST (Figure 1), is stretched in the Z direction and has a substantially cylindrical shape. However, the semiconductor layer 130 may also have a substantially cylindrical shape that is stretched in the Z direction. In addition, an insulating layer containing silicon oxide (SiO2) or the like, which has a substantially cylindrical shape that is stretched in the Z direction, may be provided inside the semiconductor layer 130.

[0156] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0157] Sub...substrate, 130...semiconductor layer, 140...insulating layer, 150...conductive layer, 170...conductive layer, 173H...insulating layer, 175L...insulating layer.

Claims

1. circuit board and An oxide semiconductor layer containing a first metal element and oxygen (O) is spaced apart from the substrate in a first direction intersecting the surface of the substrate, A first wiring facing a part of the oxide semiconductor layer, A gate insulating film is provided between the oxide semiconductor layer and the first wiring, A first conductive layer containing a second metal element and oxygen (O) is in contact with one end of the oxide semiconductor layer in the first direction, A second wiring electrically connected to the first conductive layer, The first insulating part in contact with the second wiring and Equipped with, The first insulating portion is, The first area and, A second region located between the first region and the second wiring, The concentration of the first metal element or the second metal element in the second region is Greater than the concentration of the first metal element or the second metal element in the first region. Semiconductor equipment.

2. The density of the second region is lower than the density of the first region. The semiconductor device according to claim 1.

3. The first insulating portion comprises a first insulating layer including the first region and a second insulating layer including the second region. The second insulating layer is provided between the first insulating layer and the second wiring. The density of the second insulating layer is lower than the density of the first insulating layer. The semiconductor device according to claim 1.

4. The first insulating layer and the second insulating layer contain silicon (Si) and oxygen (O). The semiconductor device according to claim 3.

5. The first metallic element is, Indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), calcium (Ca), and cadmium (Cd) It is one element selected from the group consisting of [the specified elements]. The semiconductor device according to claim 1.

6. The second metal element is Indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo) It is one element selected from the group consisting of [the specified elements]. The semiconductor device according to claim 1.

7. A third wiring is electrically connected to one end of the second wiring in the first direction and extends in a second direction intersecting the first direction, The second insulating part in contact with the third wiring and Equipped with, The second insulating portion is, The third area and, A fourth region located between the third region and the third wiring, Includes, The concentration of the first metal element or the second metal element in the fourth region is Greater than the concentration of the first or second metal element in the third region. The semiconductor device according to claim 1.

8. The density of the fourth region is lower than the density of the third region. The semiconductor device according to claim 7.

9. The second insulating portion comprises a third insulating layer including the third region and a fourth insulating layer including the fourth region. The fourth insulating layer is provided between the third insulating layer and the third wiring, The density of the fourth insulating layer is lower than the density of the third insulating layer. The semiconductor device according to claim 7.

10. A capacitor layer is provided between the substrate and the oxide semiconductor layer. The capacitor layer comprises a capacitor structure electrically connected to the oxide semiconductor layer. The semiconductor device according to claim 1.

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