Semiconductor device, semiconductor memory device, and method for manufacturing a semiconductor device.

Abstract

To provide a semiconductor device with excellent transistor characteristics. [Solution] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer between the first electrode and the second electrode, and a gate electrode facing the oxide semiconductor layer. The gate electrode includes a first portion and a second portion with the oxide semiconductor layer in between. The first portion has a first end on the first electrode side and a second end on the second electrode side, and the second portion has a third end on the first electrode side and a fourth end on the second electrode side. The first distance between the inside of the first end and the inside of the third end is greater than the second distance between the inside of the second end and the inside of the fourth end, and the third distance between the outside of the first end and the outside of the third end is greater than the second distance between the outside of the second end and the outside of the fourth end.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, a semiconductor memory device, and a method for manufacturing a semiconductor device.

Background Art

[0002] An oxide semiconductor transistor that forms a channel in an oxide semiconductor layer has excellent characteristics such that the channel leakage current during the off operation is extremely small. Therefore, for example, it is possible to apply the oxide semiconductor transistor to a switching transistor of a memory cell of a Dynamic Random Access Memory (DRAM).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device having excellent transistor characteristics.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, wherein in a first cross section parallel to a first direction connecting the first electrode and the second electrode, the gate electrode includes a first portion and a second portion, and in a second direction perpendicular to the first direction, the oxide semiconductor layer is provided between the first portion and the second portion, the first portion has a first end on the first electrode side and a second end on the second electrode side, and the first end has a first endpoint in contact with the gate insulating layer and a second endpoint opposite to the first endpoint The second portion has two endpoints, the second end having a third endpoint in contact with the gate insulating layer and a fourth endpoint opposite to the third endpoint, the second portion having a third endpoint on the first electrode side and a fourth endpoint on the second electrode side, the third end having a fifth endpoint in contact with the gate insulating layer and a sixth endpoint opposite to the fifth endpoint, the fourth end having a seventh endpoint in contact with the gate insulating layer and an eighth endpoint opposite to the seventh endpoint, the first distance between the first endpoint and the fifth endpoint is greater than the second distance between the third endpoint and the seventh endpoint, the third distance between the second endpoint and the sixth endpoint is greater than the fourth distance between the fourth endpoint and the eighth endpoint. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] An explanatory diagram illustrating an example of the shape of the gate electrode of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6]A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 20] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 21] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 22] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 23] A diagram illustrating the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment. [Figure 24] Explanatory diagram of the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment. [Figure 25] Schematic cross-sectional view of the semiconductor device according to the modified example of the first embodiment. [Figure 26] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 27] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 28] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 29] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 30] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 31] Explanatory diagram of the operation and effects of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 32] Explanatory diagram of the operation and effects of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 33] Schematic cross-sectional view of the semiconductor device according to the third embodiment. [Figure 34] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 35] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 36] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 37] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 38] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 39] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 40] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 41] Schematic cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the third embodiment. [Figure 42] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 43] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 44] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 45] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 46] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 47] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 48] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 49] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 50] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 51] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 52] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 53] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 54] Equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment. [Figure 55] A schematic cross-sectional view of a semiconductor memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described may be omitted from the description as appropriate.

[0008] Furthermore, for convenience, the terms "upper," "lower," "upper part," or "lower part" may be used in this specification. "Upper," "lower," "upper part," or "lower part" are terms that indicate relative positions within the drawings and do not define positions relative to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of components constituting semiconductor devices and semiconductor memory devices described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, a transmission electron microscope (TEM) can be used to measure the thickness, distance between components, and grain size of components constituting semiconductor devices and semiconductor memory devices. Additionally, X-ray photoelectron spectroscopy (XPS), hard X-ray photoelectron spectroscopy (HAXPES), or electron energy loss spectroscopy (EELS) can be used to identify the constituent materials of semiconductor devices and semiconductor memory devices and to measure the relative abundance of those materials.

[0010] In this specification, "metal" refers to a general term for substances that exhibit metallic properties, and for example, metal compounds such as metal nitrides and metal carbides that exhibit metallic properties are included in the scope of "metal".

[0011] (First embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer. In a first cross-section parallel to a first direction connecting the first electrode and the second electrode, the gate electrode includes a first portion and a second portion. In a second direction perpendicular to the first direction, an oxide semiconductor layer is provided between the first portion and the second portion. The first portion has a first end on the first electrode side and a second end on the second electrode side, the first end has a first endpoint in contact with the gate insulating layer and a second endpoint opposite to the first endpoint, and the second end has a third endpoint in contact with the gate insulating layer and a fourth endpoint opposite to the third endpoint. The second portion has a third end on the first electrode side and a fourth end on the second electrode side, the third end having a fifth endpoint in contact with the gate insulating layer and a sixth endpoint opposite the fifth endpoint, and the fourth end having a seventh endpoint in contact with the gate insulating layer and an eighth endpoint opposite the seventh endpoint. The first distance between the first endpoint and the fifth endpoint is greater than the second distance between the third endpoint and the seventh endpoint, and the third distance between the second endpoint and the sixth endpoint is greater than the fourth distance between the fourth endpoint and the eighth endpoint.

[0012] Figures 1 and 2 are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view of Figure 1, AA'. In Figure 1, the vertical direction is referred to as the first direction. In Figure 1, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first direction. The first direction is the direction connecting the lower electrode 12 and the upper electrode 14.

[0013] Figure 1 is a cross-section parallel to the first direction. Figure 1 is an example of the first cross-section.

[0014] The semiconductor device of the first embodiment is a transistor 100. Transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. Transistor 100 has a gate electrode that surrounds the oxide semiconductor layer in which the channel is formed. Transistor 100 is a so-called Surrounding Gate Transistor (SGT). Transistor 100 is a so-called vertical transistor.

[0015] The transistor 100 comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, and an interlayer insulating layer 22. The gate electrode 18 comprises a first portion 18a and a second portion 18b.

[0016] The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode.

[0017] The lower electrode 12 is provided beneath the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. The lower electrode 12 is in contact with the oxide semiconductor layer 16, for example. The lower electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.

[0018] The lower electrode 12 is a conductor. The lower electrode 12 includes, for example, an oxide conductor. The lower electrode 12 is, for example, an oxide conductor layer.

[0019] The lower electrode 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The lower electrode 12 includes, for example, indium tin oxide. The lower electrode 12 is, for example, an indium tin oxide layer.

[0020] The lower electrode 12 contains, for example, tin (Sn) and oxygen (O). The lower electrode 12 contains, for example, tin oxide. The lower electrode 12 is, for example, a tin oxide layer.

[0021] The lower electrode 12 contains, for example, a metal. The lower electrode 12 is, for example, a metal layer.

[0022] The lower electrode 12 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The lower electrode 12 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0023] The lower electrode 12 may, for example, have a laminated structure of multiple conductors. The lower electrode 12 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the lower electrode 12 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0024] The upper electrode 14 is provided on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. The upper electrode 14 is in contact with the oxide semiconductor layer 16, for example. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0025] The upper electrode 14 is a conductor. The upper electrode 14 includes, for example, an oxide conductor. The upper electrode 14 is, for example, an oxide conductor layer.

[0026] The upper electrode 14 includes, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 includes, for example, indium tin oxide. The upper electrode 14 is, for example, an indium tin oxide layer.

[0027] The upper electrode 14 contains, for example, tin (Sn) and oxygen (O). The upper electrode 14 contains, for example, tin oxide. The upper electrode 14 is, for example, a tin oxide layer.

[0028] The upper electrode 14 contains, for example, a metal. The upper electrode 14 is, for example, a metal layer.

[0029] The upper electrode 14 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The upper electrode 14 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0030] The upper electrode 14 may, for example, have a laminated structure of multiple conductors. The upper electrode 14 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the upper electrode 14 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0031] The lower electrode 12 and the upper electrode 14 are formed from, for example, the same material. The lower electrode 12 and the upper electrode 14 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The lower electrode 12 and the upper electrode 14 contain, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide layers.

[0032] The oxide semiconductor layer 16 is provided between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is in contact with, for example, the lower electrode 12. The oxide semiconductor layer 16 is in contact with, for example, the upper electrode 14.

[0033] A channel is formed in the oxide semiconductor layer 16 that serves as a current path when the transistor 100 is turned on.

[0034] The oxide semiconductor layer 16 is an oxide semiconductor. For example, the oxide semiconductor layer 16 is amorphous.

[0035] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), as well as zinc (Zn) and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.

[0036] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 includes, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 is, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0037] The oxide semiconductor layer 16 has a chemical composition different from, for example, the chemical composition of the lower electrode 12 and the chemical composition of the upper electrode 14.

[0038] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0039] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm to 200 nm. The length of the oxide semiconductor layer 16 in the second direction is, for example, 10 nm to 100 nm.

[0040] The fifth distance (d5 in Figure 1) in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the lower electrode 12 is greater than the sixth distance (d6 in Figure 1) in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the upper electrode 14. The fifth distance d5 is, for example, 1.1 times or more and 3 times or less of the sixth distance d6.

[0041] The width in the second direction of the portion sandwiched between the oxide semiconductor layer 16 and the gate insulating layers 20 on both sides widens from the upper electrode 14 toward the lower electrode 12. The oxide semiconductor layer 16 has a so-called inverse tapered shape.

[0042] The oxide semiconductor layer 16 contains voids 17.

[0043] The gate electrode 18 faces the oxide semiconductor layer 16. The gate electrode 18 is positioned such that its position coordinate in the first direction is between the position coordinates of the lower electrode 12 and the upper electrode 14 in the first direction.

[0044] As shown in Figure 2, the gate electrode 18 is provided surrounding the oxide semiconductor layer 16. The gate electrode 18 is provided around the oxide semiconductor layer 16.

[0045] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metallic compound, or a semiconductor. The gate electrode 18 includes, for example, tungsten (W).

[0046] The length of the gate electrode 18 in the first direction is, for example, between 10 nm and 100 nm.

[0047] The gate electrode 18 includes a first portion 18a and a second portion 18b in a cross-section parallel to the first direction. In the second direction, an oxide semiconductor layer 16 is provided between the first portion 18a and the second portion 18b.

[0048] The first portion 18a has a first end E1 on the lower electrode 12 side and a second end E2 on the upper electrode 14 side. The first end E1 has a first endpoint P1 in contact with the gate insulating layer 20 and a second endpoint P2 on the opposite side of the first endpoint P1. The second end E2 has a third endpoint P3 in contact with the gate insulating layer 20 and a fourth endpoint P4 on the opposite side of the third endpoint P3.

[0049] The second portion 18b has a third end E3 on the lower electrode 12 side and a fourth end E4 on the upper electrode 14 side. The third end E3 has a fifth endpoint P5 in contact with the gate insulating layer 20 and a sixth endpoint P6 on the opposite side of the fifth endpoint P5. The fourth end E4 has a seventh endpoint P7 in contact with the gate insulating layer 20 and an eighth endpoint P8 on the opposite side of the seventh endpoint P7.

[0050] The first distance between the first endpoint P1 and the fifth endpoint P5 (d1 in Figure 1) is greater than the second distance between the third endpoint P3 and the seventh endpoint P7 (d2 in Figure 1). Also, the third distance between the second endpoint P2 and the sixth endpoint P6 (d3 in Figure 1) is greater than the fourth distance between the fourth endpoint P4 and the eighth endpoint P8 (d4 in Figure 1).

[0051] Figure 3 is an explanatory diagram of an example of the shape of the gate electrode of the semiconductor device according to the first embodiment. Figure 3 is an enlarged view showing an example of the second end E2 of the first portion 18a of the gate electrode 18.

[0052] Let's assume that the corner of the second end E2 of the first portion 18a opposite to the oxide semiconductor layer 16 is rounded, as shown in Figure 3. In this case, the intersection of the line segment A1, which is an extension of the straight portion of the upper surface of the second end E2 from the third endpoint P3 of the second end E2, and the line segment A2, which is an extension of the straight portion of the side surface of the first portion 18a, is defined as the fourth endpoint P4.

[0053] As shown in Figure 1, the distance in the second direction between the first portion 18a and the second portion 18b of the gate electrode 18, which has the oxide semiconductor layer 16 in between, increases from the upper electrode 14 towards the lower electrode 12, both on the inner surface on the oxide semiconductor layer 16 side and on the outer surface on the opposite side of the oxide semiconductor layer 16.

[0054] The gate insulating layer 20 is provided between the oxide semiconductor layer 16 and the gate electrode 18. The gate insulating layer 20 is provided surrounding the oxide semiconductor layer 16. The gate insulating layer 20 is provided between the lower electrode 12 and the upper electrode 14.

[0055] The gate insulating layer 20 does not come into contact with, for example, the lower electrode 12. The gate insulating layer 20 comes into contact with, for example, the upper electrode 14.

[0056] The gate insulating layer 20 is, for example, an oxide, a nitride, or an oxynitride. The gate insulating layer 20 includes, for example, silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The gate insulating layer 20 is, for example, a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer.

[0057] The gate insulating layer 20 may have, for example, a multilayer structure. The gate insulating layer 20 may have, for example, a multilayer structure of nitride and oxide. The gate insulating layer 20 may have, for example, a multilayer structure of silicon nitride layer and silicon oxide layer. The thickness of the gate insulating layer 20 is, for example, 2 nm or more and 10 nm or less.

[0058] The lower electrode 12 is separated from the gate insulating layer 20 in a first direction, for example. In the first direction, an interlayer insulating layer 22 is provided between the lower electrode 12 and the gate insulating layer 20, for example.

[0059] The interlayer insulating layer 22 surrounds, for example, the lower electrode 12, the upper electrode 14, the oxide semiconductor layer 16, and the gate insulating layer 20. The interlayer insulating layer 22 is provided, for example, between the lower electrode 12 and the gate electrode 18. The interlayer insulating layer 22 is provided, for example, between the upper electrode 14 and the gate electrode 18.

[0060] The interlayer insulating layer 22 is an insulator. The interlayer insulating layer 22 is, for example, an oxide, nitride, or oxynitride. The interlayer insulating layer 22 contains, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 22 contains, for example, silicon oxide. The interlayer insulating layer 22 is, for example, silicon oxide. The interlayer insulating layer 22 contains, for example, silicon (Si) and nitrogen (N). The interlayer insulating layer 22 contains, for example, silicon nitride. The interlayer insulating layer 22 is, for example, silicon nitride.

[0061] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0062] Figures 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, and 22 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 4 to 22 each show a cross-section corresponding to Figure 1. Figures 4 to 22 are diagrams showing an example of a method for manufacturing transistor 100.

[0063] The following explanation will be given using the example of a transistor 100 where the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the interlayer insulating layer 22 is a silicon nitride layer and a silicon oxide layer.

[0064] An example of a semiconductor device manufacturing method according to the first embodiment involves forming a first film on a first conductive layer, etching the first film to form a columnar body in which the first width on the side of the first conductive layer is wider than the second width on the opposite side of the first conductive layer, embedding the columnar body with a first insulating film, etching a part of the first insulating film to expose a part of the columnar body, embedding the columnar body with a first metal film, etching a part of the first metal film to expose a part of the columnar body, covering the columnar body with a second insulating film, etching the second insulating film to form a side wall on the side of the columnar body, and the columnar body and The sidewall is filled with a third insulating film, the third insulating film is etched to form a first opening in which the sidewall and the first metal film are exposed, the first metal film is etched using the third insulating film and the sidewall as a mask, the first opening is filled with a fourth insulating film, the fourth insulating film on top of the columnar body is removed to expose the columnar body, the columnar body is etched and removed to form a second opening in which the first metal film is exposed on the side, a fifth insulating film is formed inside the second opening, the fifth insulating film at the bottom of the second opening is etched and removed, and the second opening is filled with a semiconductor film. Also, when etching the fifth insulating film at the bottom of the second opening, the first conductive layer is exposed.

[0065] First, a first silicon oxide film 32, an amorphous silicon film 33, and a first silicon nitride film 34 are formed on the indium tin oxide layer 31 formed within the silicon nitride layer 30 (Figure 4). The first silicon oxide film 32, the amorphous silicon film 33, and the first silicon nitride film 34 are formed, for example, by the Chemical Vapor Deposition (CVD) method. Alternatively, an aluminum oxide film may be formed instead of the first silicon oxide film 32.

[0066] The silicon nitride layer 30 ultimately becomes the interlayer insulating layer 22. The indium tin oxide layer 31 ultimately becomes the lower electrode 12. A portion of the first silicon oxide film 32 ultimately becomes the interlayer insulating layer 22. The indium tin oxide layer 31 is an example of the first conductive layer. The amorphous silicon film 33 is an example of the first film.

[0067] Next, the first silicon nitride film 34 and the amorphous silicon film 33 are etched to form columnar bodies 35 (Figure 5). The columnar bodies 35 are formed such that the first width on the side facing the indium tin oxide layer 31 (w1 in Figure 5) is wider than the second width on the opposite side facing the indium tin oxide layer 31 (w2 in Figure 5). The columnar bodies 35 are, for example, cylindrical or rectangular prisms. The columnar bodies 35 are formed, for example, using lithography and reactive ion etching (RIE).

[0068] After etching the amorphous silicon film 33, the first silicon oxide film 32 is etched in succession.

[0069] Next, the columnar body 35 is embedded with a second silicon oxide film 36 (Figure 6). The second silicon oxide film 36 is formed, for example, by deposition using the CVD method and planarization treatment using the chemical mechanical polishing (CMP) method. The first silicon nitride film 34 functions, for example, as a stopper film when performing the CMP method. The second silicon oxide film 36 is an example of the first insulating film.

[0070] Next, a portion of the second silicon oxide film 36 is etched to expose a portion of the columnar body 35 (Figure 7). The second silicon oxide film 36 is etched, for example, using the RIE method.

[0071] Next, the columnar body 35 is embedded with a tungsten film 37 (Figure 8). The tungsten film 37 is formed, for example, using the CVD method. The tungsten film 37 is an example of the first metal film. A portion of the tungsten film 37 will ultimately become the gate electrode 18.

[0072] Next, the upper surface of the tungsten film 37 is flattened (Figure 9). The tungsten film 37 is flattened by the CMP method. The first silicon nitride film 34 functions, for example, as a stopper film when performing the CMP method.

[0073] Next, a portion of the tungsten film 37 is etched to expose a portion of the columnar body 35 (Figure 10). The tungsten film 37 is etched, for example, using the RIE method.

[0074] Next, the columnar body 35 is covered with a second silicon nitride film 38 (Figure 11). The second silicon nitride film 38 is formed, for example, by a CVD method. The second silicon nitride film 38 is an example of a second insulating film.

[0075] Next, the second silicon nitride film 38 is etched to form side walls 39 on the sides of the columnar body 35 (Figure 12). The side walls 39 are formed, for example, using the RIE method.

[0076] Next, the columnar body 35 and the side wall 39 are filled with a third silicon oxide film 40 (Figure 13). The third silicon oxide film 40 is formed, for example, by the CVD method. The third silicon oxide film 40 is an example of a third insulating film.

[0077] Next, the third silicon oxide film 40 is etched to form a first opening 41 in which the side wall 39 and the tungsten film 37 are exposed (Figure 14). The first opening 41 is formed using lithography and RIE.

[0078] Next, the tungsten film 37 is etched using the third silicon oxide film 40 and the sidewall as a mask (Figure 15).

[0079] Next, the side wall 39 is removed (Figure 16). The side wall 39 is removed, for example, using a wet etching method.

[0080] Next, the first opening 41 is filled with the fourth silicon oxide film 42 (Figure 17). The fourth silicon oxide film 42 is formed, for example, by the CVD method. The fourth silicon oxide film 42 is an example of the fourth insulating film.

[0081] Next, the fourth silicon oxide film 42 on the columnar body 35 is removed, exposing the upper surface of the columnar body 35 (Figure 18). The fourth silicon oxide film 42 is removed, for example, by the CMP method.

[0082] Next, the columnar body 35 is etched away to form a second opening 43 on the side surface, exposing the tungsten film 37 (Figure 19). The amorphous silicon film 33 forming the columnar body 35 is etched using, for example, a wet etching method. The second opening 43 has a so-called reverse tapered shape.

[0083] Next, a fourth silicon oxide film 44 is formed in the second opening 43 (Figure 20). The fourth silicon oxide film 44 is formed, for example, by the CVD method. The fourth silicon oxide film 44 is an example of a fifth insulating film. A portion of the fourth silicon oxide film 44 ultimately becomes the gate insulating layer 20.

[0084] Next, the fourth silicon oxide film 44 at the bottom of the second opening 43 is etched and removed (Figure 21). At this time, a portion of the first silicon oxide film 32 is also etched, exposing the surface of the indium tin oxide layer 31. The etching of the fourth silicon oxide film 44 is performed using the RIE method.

[0085] Next, the second opening 43 is filled with an indium gallium zinc oxide film 45 (Figure 22). The indium gallium zinc oxide film 45 is formed, for example, by CVD and then planarized by CMP. Because the second opening 43 has an inverse tapered shape, voids are formed in the indium gallium zinc oxide film 45 that fills the second opening 43.

[0086] The indium gallium zinc oxide film 45 ultimately becomes an oxide semiconductor layer 16. The indium gallium zinc oxide film 45 is an example of a semiconductor film.

[0087] Subsequently, the upper electrode 14 of the indium tin oxide layer is formed using known process techniques.

[0088] The transistor 100 shown in Figures 1 and 2 is manufactured by the above manufacturing method.

[0089] In the example manufacturing method described above, an amorphous silicon film was used as the first film, but it is also possible to use a carbon film as the first film, for example.

[0090] Next, the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0091] Figure 23 is an explanatory diagram illustrating the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment. Figure 23 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a comparative example. Figure 23 is a diagram corresponding to Figure 21 of the manufacturing method according to the first embodiment.

[0092] The comparative example of the semiconductor device manufacturing method differs from the first embodiment of the semiconductor device manufacturing method in that the opening 43x corresponding to the second opening 43 of the first embodiment of the semiconductor device manufacturing method has a forward tapered shape.

[0093] In the process shown in Figure 23, the fourth silicon oxide film 44 at the bottom of the second opening 43 is etched and removed. In this process, the fourth silicon oxide film 44 is etched using the RIE method.

[0094] The RIE method is an anisotropic etching method that utilizes ion impacts perpendicular to the substrate. In this process, the surface of the fourth silicon oxide film 44 formed on the side of the opening 43x is directly exposed to the ion impacts. As a result, processing damage remains on the fourth silicon oxide film 44.

[0095] The fourth silicon oxide film 44 ultimately becomes the gate insulating layer. Because processing damage remains in the gate insulating layer, the reliability of the gate insulating layer decreases. Specifically, for example, the time-dependent dielectric breakdown characteristics (TDDB characteristics) of the gate insulating layer deteriorate.

[0096] Figure 24 is an explanatory diagram illustrating the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment. Figure 24 corresponds to Figure 21 of the manufacturing method according to the first embodiment.

[0097] The second opening 43 of the semiconductor device manufacturing method of the first embodiment has an inverse tapered shape. Therefore, as shown in Figure 24, when etching the fourth silicon oxide film 44 using the RIE method, the surface of the fourth silicon oxide film 44 formed on the side of the second opening 43 is not directly exposed to ionic shock. As a result, no processing damage remains on the fourth silicon oxide film 44.

[0098] Therefore, the reliability of the gate insulating layer 20 is improved compared to the semiconductor device manufacturing method of the comparative example. Thus, a transistor 100 with improved reliability can be realized.

[0099] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the first embodiment, a semiconductor device with excellent transistor characteristics can be realized.

[0100] (modified version) The semiconductor device of the modified embodiment differs from the semiconductor device of the first embodiment in that the first thickness in the first direction of the portion of the first electrode that is in contact with the oxide semiconductor layer is thinner than the second thickness in the first direction of the portion of the first electrode that is closest to the gate insulating layer in the first direction.

[0101] Figure 25 is a schematic cross-sectional view of a semiconductor device of a modified example of the first embodiment. Figure 25 corresponds to Figure 2 of the first embodiment.

[0102] A semiconductor device in a modified example of the first embodiment is a transistor 110.

[0103] In transistor 110, the first thickness (t1 in Figure 25) in the first direction of the portion of the lower electrode 12 that is in contact with the oxide semiconductor layer 16 is thinner than the second thickness (t2 in Figure 25) in the first direction of the portion of the lower electrode 12 that is closest to the gate insulating layer 20 in the first direction. The first thickness t1 is, for example, 0.5 times or more and 0.95 times or less of the second thickness t2.

[0104] The lower electrode 12 of the transistor 110 has a recess on the surface facing the oxide semiconductor layer 16, and the oxide semiconductor layer 16 is provided within the recess.

[0105] The transistor 110 can be manufactured, for example, in the process shown in Figure 21 of the method for manufacturing a semiconductor device according to the first embodiment, by etching the surface of the indium tin oxide layer 31 when etching and removing the fourth silicon oxide film 44 and the first silicon oxide film 32 at the bottom of the second opening 43.

[0106] In transistor 110, the contact area between the oxide semiconductor layer 16 and the lower electrode 12 increases. Therefore, the contact resistance between the oxide semiconductor layer 16 and the lower electrode 12 is reduced. Thus, a transistor with reduced on-resistance can be realized.

[0107] According to the semiconductor device and method for manufacturing the semiconductor device of the modified embodiment of the first embodiment, a transistor with improved reliability can be realized, similar to the first embodiment. Furthermore, a transistor with reduced on-resistance can be realized.

[0108] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the first embodiment and its modified form, a semiconductor device with excellent transistor characteristics can be realized.

[0109] (Second embodiment) The method for manufacturing a semiconductor device in the second embodiment differs from the method for manufacturing a semiconductor device in that, before etching the first film, a second film with a different chemical composition from the first film is further formed on the first film, the second film is etched before etching the first film, leaving the second film on the columnar body, the second film is also embedded when the columnar body and side walls are filled with a third insulating film, the second film is also embedded, and after removing the fourth insulating film on the columnar body, the second film is etched and removed before the columnar body is exposed. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0110] An example of a method for manufacturing a semiconductor device according to the second embodiment will be described.

[0111] Figures 26, 27, 28, 29, and 30 are schematic cross-sectional views showing an example of a semiconductor device manufacturing method according to the second embodiment. Figures 26 to 30 each show a cross-section corresponding to Figure 1 of the first embodiment. Figures 26 to 30 show another example of a method for manufacturing the transistor 100 according to the first embodiment.

[0112] First, a first silicon oxide film 32, an amorphous silicon film 33, a boron carbide film 46, and a first silicon nitride film 34 are formed on the indium tin oxide layer 31 formed in the silicon nitride layer 30 (Figure 26). The first silicon oxide film 32, amorphous silicon film 33, boron carbide film 46, and first silicon nitride film 34 are formed, for example, by CVD.

[0113] The chemical composition of the boron carbide film 46 differs from that of the amorphous silicon film 33. The boron carbide film 46 is an example of a second film.

[0114] Next, the first silicon nitride film 34, the boron carbide film 46, the amorphous silicon film 33, and the first silicon oxide film 32 are etched to form columnar bodies 35 (Figure 27). The boron carbide film 46 is left on top of the columnar bodies 35.

[0115] Subsequently, the same steps as those shown in Figures 6 to 12 of the manufacturing method for the semiconductor device of the first embodiment are performed.

[0116] Next, the columnar body 35, the boron carbide film 46, and the side wall 39 are filled with a third silicon oxide film 40 (Figure 28). The third silicon oxide film 40 is formed, for example, by the CVD method. The third silicon oxide film 40 is an example of a third insulating film.

[0117] Next, the third silicon oxide film 40 is etched to form a first opening 41 in which the side wall 39 and the tungsten film 37 are exposed (Figure 29). The first opening 41 is formed using lithography and RIE.

[0118] Next, the tungsten film 37 is etched using the third silicon oxide film 40 and the side wall 39 as a mask (Figure 30).

[0119] Subsequently, the same steps as those shown in Figures 16 to 22 of the manufacturing method for the semiconductor device of the first embodiment are performed. Furthermore, the upper electrode 14 of the indium tin oxide layer is formed.

[0120] Furthermore, after removing the fourth silicon oxide film 42 on the columnar body 35, and before exposing the columnar body 35, the boron carbide film 46 is etched and removed. Then, the amorphous silicon columnar body 35 is removed to form the second opening 43.

[0121] The transistor 100 shown in Figures 1 and 2 is manufactured by the above manufacturing method.

[0122] In the example of the manufacturing method described above, a boron carbide film was used as the second film, but it is also possible to use a boron nitride film as the first film, for example.

[0123] Next, the operation and effects of the semiconductor device manufacturing method according to the second embodiment will be described.

[0124] Figures 31 and 32 are explanatory diagrams illustrating the operation and effects of the semiconductor device manufacturing method according to the second embodiment. Figures 31 and 32 correspond to Figures 29 and 30 of the manufacturing method according to the second embodiment.

[0125] Figures 31 and 32 show a case where misalignment in the lithography method causes a lateral misalignment in the first opening 41 formed in the third silicon oxide film 40. As shown in Figure 31, for example, the first opening 41 overlaps the upper part of the columnar body 35 due to the misalignment. That is, the upper part of the columnar body 35 is exposed.

[0126] In this case, as shown in Figure 32, since the boron carbide film 46, which has a high etching selectivity ratio for etching the tungsten film 37, is located on the columnar body 35, etching of the amorphous silicon film 33 forming the columnar body 35 is suppressed. In other words, if the boron carbide film 46 is not provided, and the first opening 41 is misaligned and overlaps the top of the columnar body 35, the amorphous silicon film 33 may be etched, potentially leading to manufacturing defects.

[0127] According to the semiconductor device manufacturing method of the second embodiment, for example, manufacturing defects caused by misalignment are suppressed, and the manufacturing yield of semiconductor devices is improved.

[0128] As described above, the semiconductor device manufacturing method of the second embodiment enables the realization of a transistor with improved reliability, similar to the first embodiment. Furthermore, it enables the realization of a transistor with improved manufacturing yield. The semiconductor device manufacturing method of the second embodiment enables the realization of a semiconductor device with excellent transistor characteristics.

[0129] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the oxide semiconductor layer includes a first region that is partially in contact with the first electrode, and the first length of the first region in the second direction is longer than the second length of the first electrode in the second direction. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0130] Figure 33 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. Figure 33 corresponds to Figure 2 of the first embodiment.

[0131] The semiconductor device of the third embodiment is a transistor 300.

[0132] The oxide semiconductor layer 16 of the transistor 300 includes a first region 16x. A portion of the first region 16x is in contact with the lower electrode 12. The first length (L1 in Figure 33) of the bottom of the first region 16x in a second direction is longer than the second length (L2 in Figure 33) of the lower electrode 12 in a first direction. The first length L1 is, for example, between 1.1 and 2 times the second length L2.

[0133] Next, an example of a method for manufacturing a semiconductor device according to the third embodiment will be described.

[0134] Figures 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, and 53 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the third embodiment. Figures 34 to 53 each show a cross-section corresponding to Figure 1. Figures 34 to 53 show an example of a method for manufacturing a transistor 300.

[0135] The following explanation will be based on the example of a transistor 300 where the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the interlayer insulating layer 22 is a silicon nitride layer and a silicon oxide layer.

[0136] An example of a semiconductor device manufacturing method of the third embodiment involves forming a first film on a first conductive layer, etching the first film to form a columnar body in which the first width on the side of the first conductive layer is wider than the second width on the opposite side of the first conductive layer, embedding the columnar body with a first insulating film, etching a part of the first insulating film to expose a part of the columnar body, embedding the columnar body with a first metal film, etching a part of the first metal film to expose a part of the columnar body, covering the columnar body with a second insulating film, etching the second insulating film to form a side wall on the side of the columnar body, and the columnar body and The sidewall is filled with a third insulating film, the third insulating film is etched to form a first opening in which the sidewall and the first metal film are exposed, the first metal film is etched using the third insulating film and the sidewall as a mask, the first opening is filled with a fourth insulating film, the fourth insulating film on top of the columnar body is removed to expose the columnar body, the columnar body is etched and removed to form a second opening in which the first metal film is exposed on the side, a fifth insulating film is formed inside the second opening, the fifth insulating film at the bottom of the second opening is etched and removed, and the second opening is filled with a semiconductor film. Furthermore, before forming the first film, a third film having a different chemical composition from the first film is formed on the first conductive layer. After etching the first film, the third film is etched such that the third width of the third film on the side of the first conductive layer is wider than the first width. After etching the fifth insulating film at the bottom, the third film is further etched to expose the first conductive layer.

[0137] First, an aluminum oxide film 50, an amorphous silicon film 33, and a first silicon nitride film 34 are formed on an indium tin oxide layer 31 formed within a silicon nitride layer 30 (Figure 34). The aluminum oxide film 50, the amorphous silicon film 33, and the first silicon nitride film 34 are formed, for example, by a CVD method.

[0138] The silicon nitride layer 30 ultimately becomes the interlayer insulating layer 22. The indium tin oxide layer 31 ultimately becomes the lower electrode 12. The indium tin oxide layer 31 is an example of the first conductive layer. The chemical composition of the aluminum oxide film 50 is different from that of the amorphous silicon film 33. The aluminum oxide film 50 is an example of the third film. The amorphous silicon film 33 is an example of the first film.

[0139] Next, the first silicon nitride film 34 and the amorphous silicon film 33 are etched to form columnar bodies 35 (Figure 35). The columnar bodies 35 are formed such that the first width on the side facing the indium tin oxide layer 31 (w1 in Figure 35) is wider than the second width on the opposite side of the indium tin oxide layer 31 (w2 in Figure 35). The columnar bodies 35 are, for example, cylindrical or rectangular prisms. The columnar bodies 35 are formed, for example, using lithography and RIE.

[0140] Furthermore, after etching the amorphous silicon film 33, the aluminum oxide film 50 is etched such that the third width (w3 in Figure 35) on the indium tin oxide layer 31 side of the aluminum oxide film 50 is wider than the first width (w1 in Figure 35). This is known as tapered etching.

[0141] Next, the columnar body 35 is embedded with a second silicon oxide film 36 (Figure 36). The second silicon oxide film 36 is formed, for example, by deposition using the CVD method and planarization treatment using the CMP method. The first silicon nitride film 34 functions, for example, as a stopper film when performing the CMP method. The second silicon oxide film 36 is an example of the first insulating film.

[0142] Next, a portion of the second silicon oxide film 36 is etched to expose the columnar body 35 (Figure 37). The second silicon oxide film 36 is etched, for example, using the RIE method.

[0143] Next, the columnar body 35 is embedded with a tungsten film 37 (Figure 38). The tungsten film 37 is formed, for example, by the CVD method. The tungsten film 37 is an example of the first metal film. A portion of the tungsten film 37 will ultimately become the gate electrode 18.

[0144] Next, the upper surface of the tungsten film 37 is flattened (Figure 39). The tungsten film 37 is flattened by the CMP method. The first silicon nitride film 34 functions, for example, as a stopper film when performing the CMP method.

[0145] Next, a portion of the tungsten film 37 is etched to expose a portion of the columnar body 35 (Figure 40). The tungsten film 37 is etched, for example, using the RIE method.

[0146] Next, the columnar body 35 is covered with a second silicon nitride film 38 (Figure 41). The second silicon nitride film 38 is formed, for example, by a CVD method. The second silicon nitride film 38 is an example of a second insulating film.

[0147] Next, the second silicon nitride film 38 is etched to form side walls 39 on the sides of the columnar body 35 (Figure 42). The side walls 39 are formed, for example, using the RIE method.

[0148] Next, the columnar body 35 and the side wall 39 are filled with a third silicon oxide film 40 (Figure 43). The third silicon oxide film 40 is formed, for example, by the CVD method. The third silicon oxide film 40 is an example of a third insulating film.

[0149] Next, the third silicon oxide film 40 is etched to form a first opening 41 in which the side wall 39 and the tungsten film 37 are exposed (Figure 44). The first opening 41 is formed using lithography and RIE.

[0150] Next, the tungsten film 37 is etched using the third silicon oxide film 40 and the sidewall as a mask (Figure 45).

[0151] Next, the side wall 39 is removed (Figure 46). The side wall 39 is removed, for example, using a wet etching method.

[0152] Next, the first opening 41 is filled with the fourth silicon oxide film 42 (Figure 47). The fourth silicon oxide film 42 is formed, for example, by the CVD method. The fourth silicon oxide film 42 is an example of the fourth insulating film.

[0153] Next, the fourth silicon oxide film 42 on the columnar body 35 is removed, exposing the upper surface of the columnar body 35 (Figure 48). The fourth silicon oxide film 42 is removed, for example, by the CMP method.

[0154] Next, the columnar body 35 is etched away to form a second opening 43 on the side surface, exposing the tungsten film 37 (Figure 49). The amorphous silicon film 33 forming the columnar body 35 is etched using, for example, a wet etching method. The second opening 43 has a so-called reverse tapered shape.

[0155] Next, a fourth silicon oxide film 44 is formed in the second opening 43 (Figure 50). The fourth silicon oxide film 44 is formed, for example, by a CVD method. The fourth silicon oxide film 44 is an example of a fifth insulating film. A portion of the fourth silicon oxide film 44 ultimately becomes the gate insulating layer 20.

[0156] Next, the fourth silicon oxide film 44 at the bottom of the second opening 43 is etched and removed (Figure 51).

[0157] Next, the aluminum oxide film 50 at the bottom of the second opening 43 is etched away to expose the surface of the indium tin oxide layer 31 (Figure 52). The aluminum oxide film 50 is removed, for example, by a wet etching method.

[0158] Next, the second opening 43 is filled with an indium gallium zinc oxide film 45 (Figure 53). The indium gallium zinc oxide film 45 is formed, for example, by CVD and then planarized by CMP. Because the second opening 43 has an inverse tapered shape, voids are formed in the indium gallium zinc oxide film 45 that fills the second opening 43.

[0159] The indium gallium zinc oxide film 45 ultimately becomes an oxide semiconductor layer 16. The indium gallium zinc oxide film 45 is an example of a semiconductor film.

[0160] Subsequently, the upper electrode 14 of the indium tin oxide layer is formed using known process techniques.

[0161] The transistor 300 shown in Figure 33 is manufactured using the above manufacturing method.

[0162] In the example manufacturing method described above, an amorphous silicon film was used as the first film, but it is also possible to use a carbon film as the first film, for example. Furthermore, while an aluminum oxide film was used as the third film, it is also possible to use a hafnium oxide film or a zirconium oxide film, for example.

[0163] Next, the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the third embodiment will be described.

[0164] As shown in Figure 51, the manufacturing method of the semiconductor device in the third embodiment has a reverse taper shape when etching the fourth silicon oxide film 44 using the RIE method, similar to the manufacturing method of the semiconductor device in the first embodiment. Therefore, no processing damage remains on the fourth silicon oxide film 44. Thus, similar to the manufacturing method of the semiconductor device in the first embodiment, the reliability of the gate insulating layer 20 is improved, and a transistor 300 with improved reliability can be realized.

[0165] Furthermore, in the semiconductor device manufacturing method of the third embodiment, when etching the fourth silicon oxide film 44 using the RIE method, as shown in Figure 51, the surface of the indium tin oxide layer 31 is covered with the aluminum oxide film 50 and is not exposed. Therefore, no RIE processing damage remains on the surface of the indium tin oxide layer 31. For example, if processing damage remains on the surface of the indium tin oxide layer 31 which becomes the lower electrode 12, the contact resistance between the oxide semiconductor layer 16 and the lower electrode 12 will increase.

[0166] According to the semiconductor device manufacturing method of the third embodiment, no processing damage from RIE remains on the surface of the indium tin oxide layer 31. Therefore, the contact resistance between the oxide semiconductor layer 16 and the lower electrode 12 is reduced. Thus, a transistor with reduced on-resistance can be realized.

[0167] Furthermore, in the semiconductor device manufacturing method of the third embodiment, an aluminum oxide film 50 is formed between the amorphous silicon film 33 forming the columnar body 35 and the indium tin oxide layer 31. By forming the aluminum oxide film 50, abnormal growth of indium tin oxide is suppressed, and for example, short-circuit defects between adjacent lower electrodes 12 can be suppressed. Therefore, according to the semiconductor device manufacturing method of the third embodiment, for example, the manufacturing yield of semiconductor devices is improved.

[0168] Furthermore, in the transistor 300 of the third embodiment, the first length of the first region 16x of the oxide semiconductor layer 16 in the second direction (L1 in Figure 33) is longer than the second length of the lower electrode 12 in the second direction (L2 in Figure 33). Therefore, compared to the transistor 100 of the first embodiment, for example, the contact area between the oxide semiconductor layer 16 and the lower electrode 12 is increased. Consequently, the contact resistance between the oxide semiconductor layer 16 and the lower electrode 12 is reduced. Thus, a transistor with reduced on-resistance can be realized.

[0169] As described above, according to the semiconductor device and manufacturing method of the third embodiment, a transistor with improved reliability can be realized, similar to the first embodiment. Furthermore, a transistor with improved manufacturing yield can be realized. Furthermore, a transistor with reduced on-resistance can be realized. According to the semiconductor device and manufacturing method of the third embodiment, a semiconductor device with excellent transistor characteristics can be realized.

[0170] (Fourth embodiment) The semiconductor memory device of the fourth embodiment comprises the semiconductor device of the first embodiment and a capacitor electrically connected to the first electrode.

[0171] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory 400 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0172] In the following, some descriptions that overlap with the first embodiment will be omitted.

[0173] Figure 54 is an equivalent circuit diagram of a semiconductor memory device according to the fourth embodiment. Although Figure 54 illustrates the case where there is one memory cell MC, multiple memory cell MCs may be provided, for example, in an array.

[0174] The semiconductor memory 400 comprises a memory cell MC, a word line WL, a bit line BL, and a plate line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. In Figure 54, the region enclosed by the dashed line is the memory cell MC.

[0175] The word wire WL is electrically connected to the gate electrode of the switching transistor TR. The bit wire BL is electrically connected to one of the source and drain electrodes of the switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of the switching transistor TR. The other electrode of capacitor CA is connected to the plate wire PL.

[0176] Memory cells (MC) store data by accumulating electric charge in capacitors (CA). Data is written to and read by turning on a switching transistor (TR).

[0177] For example, a switching transistor TR is turned on while a desired voltage is applied to the bit line BL, and data is written to the memory cell MC.

[0178] Furthermore, for example, by turning on a switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and data from the memory cell MC is read out.

[0179] Figure 55 is a schematic cross-sectional view of a semiconductor memory device according to the fourth embodiment. Figure 55 shows a cross-section of the memory cell MC of the semiconductor memory 400.

[0180] The semiconductor memory 400 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, and an interlayer insulating layer 22.

[0181] The switching transistor TR comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, and a gate insulating layer 20.

[0182] The switching transistor TR has the same structure as the transistor 100 in the first embodiment.

[0183] Capacitor CA is provided between the silicon substrate 10 and the switching transistor TR. Capacitor CA is provided between the silicon substrate 10 and the lower electrode 12. Capacitor CA is electrically connected to the lower electrode 12.

[0184] The capacitor CA comprises a cell electrode 71, a plate electrode 72, and a capacitor insulating film 73. The cell electrode 71 is electrically connected to the lower electrode 12. The cell electrode 71 is, for example, in contact with the lower electrode 12.

[0185] The cell electrode 71 and plate electrode 72 are made of, for example, titanium nitride. The capacitor insulating film 73 has a layered structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0186] The gate electrode 18 is electrically connected to, for example, a word line WL (not shown). The upper electrode 14 is electrically connected to, for example, a bit line BL (not shown). The plate electrode 72 is connected to, for example, a plate line PL (not shown).

[0187] The semiconductor memory 400 applies an oxide semiconductor transistor with extremely low channel leakage current during off-operation to the switching transistor TR. Therefore, a DRAM with excellent charge retention characteristics is realized.

[0188] Furthermore, the switching transistor TR of the semiconductor memory 400 has a highly reliable gate insulating layer 20. Therefore, the reliability of the semiconductor memory 400 is improved.

[0189] In the fourth embodiment, a semiconductor memory to which the transistor of the first embodiment is applied was described as an example; however, the semiconductor memory of the embodiment of the present invention may also be a semiconductor memory to which the transistor of the third embodiment is applied.

[0190] According to the semiconductor memory device of the fourth embodiment, a semiconductor memory device with excellent transistor characteristics can be realized.

[0191] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0192] 12 Lower electrode (first electrode) 14. Upper electrode (second electrode) 16 Oxide semiconductor layer 16x First region 17 Void 18 Guard gate 18a Part 1 18b Part 2 20 Gate insulating layer 31. Indium tin oxide layer (first conductive layer) 33 Amorphous silicon film (first film) 35 Columnar body 36. Second silicon oxide film (first insulating film) 37. Tungsten film (first metal film) 38. Second silicon nitride film (second insulating film) 39 Side wall 40. Third silicon oxide film (third insulating film) 41 First opening 42. Fourth silicon oxide film (fourth insulating film) 43 Second opening 44. Fourth silicon oxide film (fifth insulating film) 45. Indium gallium zinc oxide film (semiconductor film) 46. ​​Boron carbide membrane (second membrane) 50. Aluminum oxide film (third film) 100 Transistors (Semiconductor Devices) 110 Transistors (Semiconductor Devices) 300 Transistors (Semiconductor Devices) 400 Semiconductor memory (semiconductor storage device) CA Capacitor d1 First distance d2 Second distance d3 Third distance d4 The fourth distance t1 First thickness t2 Second thickness w1 First width w2 Second width w3 Third width E1 First end E2 Second end E3 Third end E4 Fourth end L1 First length L2 Second length P1 First endpoint P2 Second endpoint P3 Third endpoint P4 Fourth endpoint P5 Fifth endpoint P6 Sixth endpoint P7 Seventh endpoint P8 Eighth endpoint

Claims

1. The first electrode and The second electrode and An oxide semiconductor layer provided between the first electrode and the second electrode, A gate electrode facing the oxide semiconductor layer, The gate insulating layer is provided between the gate electrode and the oxide semiconductor layer, In a first cross-section parallel to the first direction connecting the first electrode and the second electrode, The aforementioned gate electrode includes a first part and a second part, In a second direction perpendicular to the first direction, the oxide semiconductor layer is provided between the first portion and the second portion. The first portion has a first end on the first electrode side and a second end on the second electrode side, the first end has a first endpoint in contact with the gate insulating layer and a second endpoint opposite to the first endpoint, the second end has a third endpoint in contact with the gate insulating layer and a fourth endpoint opposite to the third endpoint, The second portion has a third end on the first electrode side and a fourth end on the second electrode side, the third end has a fifth endpoint in contact with the gate insulating layer and a sixth endpoint opposite to the fifth endpoint, and the fourth end has a seventh endpoint in contact with the gate insulating layer and an eighth endpoint opposite to the seventh endpoint, A semiconductor device in which the first distance between the first endpoint and the fifth endpoint is greater than the second distance between the third endpoint and the seventh endpoint, and the third distance between the second endpoint and the sixth endpoint is greater than the fourth distance between the fourth endpoint and the eighth endpoint.

2. The semiconductor device according to claim 1, wherein, in the first cross-section, the fifth distance in the second direction of the portion of the oxide semiconductor layer in contact with the first electrode is greater than the sixth distance in the second direction of the portion of the oxide semiconductor layer in contact with the second electrode.

3. The semiconductor device according to claim 2, wherein the fifth distance is 1.1 times or more the sixth distance.

4. The semiconductor device according to claim 1, wherein the first thickness in the first direction of the portion of the first electrode in contact with the oxide semiconductor layer is thinner than the second thickness in the first direction of the portion of the first electrode closest to the gate insulating layer in the first direction.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes voids.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a first region that is in contact with a portion of the first electrode, and the first length of the first region in the second direction is longer than the second length of the first electrode in the second direction.

7. The semiconductor device according to claim 1, wherein the first electrode is separated from the gate insulating layer in the first direction.

8. The semiconductor device according to claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

9. The semiconductor device according to claim 1, A capacitor electrically connected to the first electrode, A semiconductor memory device equipped with the following features.

10. A first film is formed on the first conductive layer. The first film is etched to form a columnar body in which the first width on the side with the first conductive layer is wider than the second width on the opposite side of the first conductive layer. The columnar body is embedded in a first insulating film, A portion of the first insulating film is etched to expose a portion of the columnar body. The columnar body is embedded with a first metal film, A portion of the first metal film is etched to expose a portion of the columnar body. The columnar body is covered with a second insulating film, The second insulating film is etched to form a side wall on the side surface of the columnar body. The columnar body and the side wall are embedded with a third insulating film. The third insulating film is etched to form a first opening in which the side wall and the first metal film are exposed. The first metal film is etched using the third insulating film and the side wall as a mask. The first opening is filled with a fourth insulating film. Remove the fourth insulating film on the columnar body, The columnar body is exposed, The columnar body is etched and removed, and a second opening is formed on the side surface in which the first metal film is exposed. A fifth insulating film is formed in the second opening. The fifth insulating film at the bottom of the second opening is etched and removed. A method for manufacturing a semiconductor device, wherein the second opening is filled with a semiconductor film.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the first conductive layer is exposed when etching the fifth insulating film at the bottom of the second opening.

12. Before etching the first film, a second film having a different chemical composition from the first film is further formed on the first film. Before etching the first film, the second film is etched, leaving the second film on the columnar body. When embedding the columnar body and the side wall with the third insulating film, the second film is also embedded. A method for manufacturing a semiconductor device according to claim 10, wherein after removing the fourth insulating film on the columnar body, and before exposing the columnar body, the second film is etched and removed.

13. Before forming the first film, a third film having a different chemical composition from the first film is further formed on the first conductive layer. After etching the first film, the third film is etched such that the third width of the third film on the side of the first conductive layer is wider than the first width. A method for manufacturing a semiconductor device according to claim 10, wherein after etching the fifth insulating film at the bottom, the third film is further etched to expose the first conductive layer.

14. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor film is an oxide semiconductor film.

15. The method for manufacturing a semiconductor device according to claim 10, wherein the first film is an amorphous silicon film or a carbon film.

16. The method for manufacturing a semiconductor device according to claim 12, wherein the second film is a boron carbide film or a boron nitride film.

17. The method for manufacturing a semiconductor device according to claim 13, wherein the third film is an aluminum oxide film.

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