Semiconductor devices and transmitting devices

Abstract

It enables reliable, high-speed serial transmission. [Solution] The semiconductor device includes a first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel signal or a serial signal; a second circuit that adjusts the output impedance of the output node of the first circuit; and a third circuit that controls the power supply voltage of at least a portion of the circuit of the first circuit in accordance with the adjustment of the output impedance by the second circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a transmission device.

Background Art

[0002] M-PHY has attracted attention as a circuit for performing high-speed serial transmission inside electronic devices such as smartphones. M-PHY is a standard formulated by the MIPI (Mobile Industry Processor Interface) Alliance. In the M-PHY standard, the amplitude level of the output signal is limited for low-power operation. Also, in the M-PHY standard, since signal transmission is performed with DC coupling, the common-mode voltage of the output signal becomes important. That is, in a communication standard that performs signal transmission with DC coupling, the common-mode voltage of the output signal is important.

[0003] If there are variations in the output resistance value of the transmission device, the amplitude and common-mode voltage of the output signal fluctuate. As a countermeasure against this, for example, if a circuit for adjusting the output resistance value is provided in the transmission device, the amplitude of the output signal decreases. With such a countermeasure, there is a risk that the M-PHY specifications regarding the output amplitude, output resistance, and common-mode voltage cannot be satisfied.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, one embodiment of the present invention provides a semiconductor device and a transmitting device that can perform reliable high-speed serial transmission. [Means for solving the problem]

[0006] To solve the above problems, according to one embodiment of the present invention, a first circuit outputs a second signal which is a serial signal based on a first signal which is a parallel signal or a serial signal, A second circuit adjusts the output impedance of the output node of the first circuit, The system includes a third circuit that controls the power supply voltage of at least a portion of the circuit of the first circuit in accordance with the adjustment of the output impedance by the second circuit, Semiconductor equipment is provided. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing the schematic configuration of a communication system according to one embodiment. [Figure 2] A block diagram showing the schematic configuration of a transmitting device according to one embodiment. [Figure 3] A block diagram showing an example of the internal configuration of a PISO circuit. [Figure 4] A block diagram showing the internal configuration of the SST circuit. [Figure 5] A circuit diagram showing an example of the internal configuration of one SST unit and one impedance adjustment circuit. [Figure 6] Figure 5 shows the correspondence between the enable signal and adjustment code input to the SST driver and impedance adjustment circuit, and the operating state of the impedance adjustment circuit. [Figure 7] A diagram showing the correspondence between multiple impedance adjustment circuits and each bit of the adjustment code according to the first embodiment. [Figure 8] A flowchart illustrating an example of the processing operation of a communication system. [Figure 9] This figure shows an example of a lookup table illustrating the correspondence between adjustment codes and the power supply voltage of the SST circuit. [Figure 10] Voltage waveform diagram showing the output amplitude value of the serial signal output by the transmission device according to the first embodiment and the common mode voltage. [Figure 11] Circuit diagram of the main part of the transmission device according to a comparative example. [Figure 12] Voltage waveform diagram showing the output amplitude value of the serial signal output by the transmission device according to a comparative example and the common mode voltage. [Figure 13] Circuit diagram showing an example of the internal configuration of one SST driver and one impedance adjustment circuit in the transmission device according to the second embodiment. [Figure 14] Diagram showing the correspondence between the enable signal and adjustment code input to the SST driver and impedance adjustment circuit of FIG. 13 and the operating state of the impedance adjustment circuit. [Figure 15] Circuit diagram showing an example of the internal configuration of one SST driver and one impedance adjustment circuit in the transmission device according to the third embodiment. [Figure 16] Diagram showing the correspondence between the enable signal and adjustment code input to the SST driver and impedance adjustment circuit of FIG. 15 and the operating state of the impedance adjustment circuit. [Figure 17] Diagram showing the correspondence between each bit of the plurality of impedance adjustment circuits and the adjustment code according to the third embodiment. [Figure 18] Circuit diagram showing an example of the internal configuration of one SST driver and one impedance adjustment circuit in the transmission device according to a modification of the third embodiment. [Figure 19] Diagram showing the correspondence between the enable signal and adjustment code input to the SST driver and impedance adjustment circuit of FIG. 18 and the operating state of the impedance adjustment circuit.

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of a semiconductor device and a transmission device will be described with reference to the drawings. In the following, the main components of the semiconductor device and the transmission device will be mainly described, but the semiconductor device and the transmission device may have components and functions that are not illustrated or described. The following description does not exclude components and functions that are not illustrated or described.

[0009] (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a communication system 1 according to the first embodiment. The communication system 1 in FIG. 1 includes a transmission device 2, a reception device 3, and a differential transmission line 4. The transmission device 2 and the reception device 3 perform high-speed serial transmission via the differential transmission line 4. More specifically, the transmission device 2 outputs a differential serial signal to the differential transmission line 4. The transmission device 2 has a function of converting a parallel signal into a differential serial signal. The differential serial signal output by the transmission device 2 is, for example, a signal encoded in a predetermined format. Although the encoding format is not limited, in this specification, an example of encoding a binary signal by PAM (Pulse Amplitude Modulation) will be described.

[0010] The reception device 3 receives the differential serial signal from the transmission device 2 and decodes it into the original binary signal. The length of the differential transmission line 4 is not limited. The transmission device 2 and the reception device 3 may be mounted on separate semiconductor chips or may be mounted within the same semiconductor package.

[0011] FIG. 2 is a block diagram showing a schematic configuration of the transmission device 2 according to the first embodiment. The transmission device 2 in FIG. 2 has a PISO (Parallel In Serial Out) circuit 11, a clock generation circuit 13, and a semiconductor device 15. The semiconductor device 15 includes an SST (Source Serial Termination) circuit 12 and a power supply circuit 14. The SST circuit 12 and the power supply circuit 14 may be mounted on the same semiconductor chip. At least one of the PISO circuit 11 or the clock generation circuit 13 may be mounted on this semiconductor chip, or they may be mounted on separate semiconductor devices.

[0012] The PISO circuit 11 outputs a first signal, which is either a parallel signal or a serial signal. For example, the PISO circuit 11 outputs a first signal obtained by converting a parallel signal to a serial signal. Alternatively, for example, the PISO circuit 11 converts a fourth signal, which is a parallel signal of the first bit sequence, into a first signal, which is a parallel signal of the second bit sequence with fewer bits than the first bit sequence, and outputs it.

[0013] The clock generation circuit 13 generates a first clock signal CLK1 that synchronizes the first signal output from the PISO circuit 11, and a second clock signal CLK2 that synchronizes the second signal output from the SST circuit 12. The second clock signal CLK2 is, for example, a frequency-divided signal of the first clock signal CLK1.

[0014] The SST circuit 12 outputs a second signal, which is a serial signal, based on the first signal output from the PISO circuit 11. The second signal is, for example, a differential serial signal. In this specification, the SST circuit 12 may be referred to as the first circuit, and the PISO circuit 11 may be referred to as the conversion circuit.

[0015] As described later, the SST circuit 12 has multiple SST units, each SST unit having a serial signal generation circuit and an SST driver. The serial signal generation circuit outputs an output signal after processing the first signal. The SST driver generates and outputs a second signal based on the output signal of the serial signal generation circuit.

[0016] The power supply circuit 14 controls the power supply voltage of at least a portion of the SST circuit 12 in accordance with the adjustment of the output resistance of the SST circuit 12. Specifically, the power supply circuit 14 controls the power supply voltage of the SST driver in the SST circuit 12 according to the result of adjusting the output resistance. The power supply circuit 14 may be, for example, an LDO (Low Drop Out) regulator. An LDO regulator can operate even with a small voltage difference between the input voltage and the output voltage, can suppress heat generation, and has excellent power efficiency. In this specification, the power supply circuit 14 may be referred to as the third circuit.

[0017] The power supply circuit 14 controls the power supply voltage of at least a portion of the circuit (e.g., the SST driver) of the SST circuit 12 so that the output resistance of the SST circuit 12, the amplitude value of the serial signal output from the SST circuit 12, and the common-mode voltage meet predetermined standards.

[0018] Figure 3 is a block diagram showing an example of the internal configuration of the PISO circuit 11. The PISO circuit 11 in Figure 3 has an FFE (Feed Forward Equalizer) processing unit 21 and two multiplexers 22a and 22b.

[0019] The FFE processing unit 21 performs FFE processing to increase the Nyquist frequency gain related to the data transmission bandwidth when converting the fourth signal, which is a parallel signal, into the first signal. FFE processing is a process to compensate for waveform distortion and ISI (Inter-Symbol Interference) of the differential serial signal output from the transmitter 2.

[0020] The PISO circuit 11 outputs a first signal that has undergone FFE processing in the FFE processing unit 21. The first signal is, for example, a differential parallel signal or a serial signal. This specification mainly describes an example in which the PISO circuit 11 outputs a first signal that is a differential parallel signal. For example, the PISO circuit 11 outputs M-type differential first signals DP_n<1:0>, DN_n<1:0>, where M is any integer greater than or equal to 2. The PISO circuit 11 synchronizes the M-type first signal DP_n <0> , DN_n <0> After outputting at the same time, the DP_n of group M is output at a timing when the first clock signal CLK1 is shifted by half a cycle. <1> , DN_n <1> Outputs.

[0021] Figure 4 is a block diagram showing the internal configuration of the SST circuit 12. The SST circuit 12 has M SST units 23 connected in parallel and a plurality of impedance adjustment circuits (Imp.adj) 16. The M SST units 23 are each associated with M pairs of differential first signals DP_n<1:0> and DN_n<1:0> output from the PISO circuit 11. That is, the input signals MUXIN_P and MUXIN_N of each SST unit 23 are the corresponding pairs of first signals DP_n<1:0> and DN_n<1:0> output from the PISO circuit 11. In this specification, the SST unit 23 may be referred to as the fifth circuit.

[0022] Each SST unit 23 outputs differential signals OUT_P and OUT_N, which are obtained by converting the corresponding pair of first signals DP_n<1:0> and DN_n<1:0> into serial signals.

[0023] The output nodes nd of the M SST units 23 are connected to each other. In this specification, the node to which the output nodes nd of the M SST units 23 are connected is called the common connection node n1. More precisely, of the differential signals OUT_P and OUT_N output from each SST unit 23, the output nodes nd_p that output one of the signals OUT_P are connected to each other, and the output nodes nd_n that output the other signal OUT_N are connected to each other. In this specification and drawings, the output nodes nd_p and nd_n may be referred to as output node nd (or common connection node n1).

[0024] When the PISO circuit 11 outputs the PAM4 signal, any four first signals DP_n<1:0> and DN_n<1:0> are output in parallel. These four first signals DP_n<1:0> and DN_n<1:0> are input to a corresponding SST unit 23. Each SST unit 23 generates differential serial signals OUT_P and OUT_N. The voltage levels of the signals OUT_P and OUT_N generated in parallel by each SST unit 23 may differ. However, no problems arise even if the output node nd of each SST unit 23 is connected to the common connection node n1.

[0025] In this way, the SST circuit 12 outputs differential second signals SSTOUT_P and SSTOUT_N, which are obtained by wired together the M differential signals OUT_P and OUT_N generated in parallel by the M SST units 23 at the common connection node n1.

[0026] Multiple impedance adjustment circuits 16 are connected to the common connection node n1. The number of impedance adjustment circuits 16 connected to the common connection node n1 is arbitrary. Each of the multiple impedance adjustment circuits 16 has the same circuit configuration and the same output resistance.

[0027] The impedance adjustment circuit 16 adjusts the output impedance of the common connection node n1 of the SST driver (SST circuit 12). In this specification, the impedance adjustment circuit 16 may be referred to as the second circuit, the fourth circuit, or Imp.adj. In this specification, an example is given in which the output impedance adjusted by the impedance adjustment circuit 16 is the output resistance.

[0028] Each impedance adjustment circuit 16 is, for example, a circuit that terminates a common connection node n1 to a power supply voltage node or a ground voltage node. The power supply voltage node is a node that supplies the power supply potential to some of the circuits of the SST circuit 12. The ground voltage node is a node that supplies the reference potential when the SST circuit 12 is operating. The impedance adjustment circuit 16 adjusts the output resistance between the common connection node n1 of the SST circuit 12 and the power supply voltage node or ground voltage node.

[0029] As will be described later, some of the impedance adjustment circuits 16 are connected to the common connection node n1 of the SST circuit 12. The more impedance adjustment circuits 16 connected to the common connection node n1 of the SST circuit 12 there are, the smaller the output resistance of the SST circuit 12 becomes, and the smaller the amplitude of the second signals OUT_P and OUT_N becomes.

[0030] Each of the M SST units 23 has a common circuit configuration. Figure 5 is a circuit diagram showing an example of the internal configuration of one SST unit 23 and one impedance adjustment circuit 16. As shown in Figure 5, each of the M SST units 23 has a serial signal generation circuit 24 and an SST driver 25. Each output node nd of each SST unit 23 is connected to the common connection node n1 of the SST circuit 12. In addition, multiple impedance adjustment circuits 16 are connected to the common connection node n1 of the SST circuit 12. In practice, although omitted in Figure 5, multiple impedance adjustment circuits 16 are connected to each of the output node nd_p, which is connected to the common connection node n1_p that outputs the second signal SSTOUT_P, and the output node nd_n, which is connected to the common connection node n1_n that outputs the second signal SSTOUT_N. In this specification, the serial signal generation circuit 24 may be referred to as the sixth circuit, and the SST driver 25 as the seventh circuit.

[0031] The serial signal generation circuit 24 has two sets of multiplexers 26 and buffer circuits 27. Each set of multiplexers 26 receives the corresponding set of first signals DP_n<1:0> or DN_n<1:0> output from the PISO circuit 11 as input signals MUXIN_P or MUXIN_N. One set of multiplexers 26 and buffer circuits 27 converts the first signal DP_n<1:0> into a serial signal, the third signal MUXOUT_P, and outputs it. The other set of multiplexers 26 and buffer circuits 27 converts the first signal DN_n<1:0> into a serial signal, the third signal MUXOUT_N, and outputs it. The third signals MUXOUT_P and MUXOUT_N are output in parallel at the same timing and input to the SST driver 25. In Figure 5, the input signals SSTIN_P and SSTIN_N of the SST driver 25 are the third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24.

[0032] One set of multiplexers 26 includes a first inverter 28, a second inverter 29, a first transfer gate 30, and a second transfer gate 31. The first inverter 28 and the second inverter 29 invert the first signal DP_n<1:0>. The first transfer gate 30 allows the inverted output signal of the first inverter 28 to pass through when the second clock signal CLK2 is high, for example, and blocks the inverted output signal of the first inverter 28 when the second clock signal CLK2 is low. The second transfer gate 31 allows the inverted output signal of the second inverter 29 to pass through when the second clock signal CLK2 is low, for example, and blocks the inverted output signal of the second inverter 29 when the second clock signal CLK2 is high. The other set of multiplexers 26 has the same configuration and operates in the same way as the one set of multiplexers 26.

[0033] Both the buffer circuit 27 of one set and the buffer circuit 27 of the other set have a third inverter 32 and a fourth inverter 33 that are connected in cascaded order. The buffer circuit 27 of one set buffers and outputs the serial signal output from the multiplexer 26 of one set. The buffer circuit 27 of the other set buffers and outputs the serial signal output from the multiplexer 26 of the other set. As a result, the buffer circuits 27 output the third signals MUXOUT_P and MUXOUT_N, which are serial signals.

[0034] The SST driver 25 has two PMOS transistors Q1 and Q2 and two NMOS transistors Q3 and Q4, which are cascode-connected between a power supply voltage node to which the power supply voltage VDD2 is supplied and a ground voltage node. An enable signal ENB is input to the gate of transistor Q1. Both gates of transistors Q2 and Q3 are connected to the input node of the SST driver 25. Both drains of transistors Q2 and Q3 are connected to one end of resistor R1, and the other end of resistor R1 is connected to the output node nd (common connection node n1) of the SST driver 25. An enable signal EN is input to the gate of transistor Q4. In this specification, the SST driver 25 may be referred to as the sixth circuit.

[0035] In this specification, the letter "B" at the end of a signal name indicates logical inversion. For example, the inverted signal of the enable signal EN is the enable signal ENB.

[0036] The resistance values ​​of the resistors R1 connected to each output node n of the M SST drivers 25 contained in the M SST units 23 are not necessarily the same, and can take on any of several resistance values.

[0037] When the enable signal EN is at a high level (the enable signal ENB is at a low level), the SST driver 25 turns on both transistors Q1 and Q4, inverting and outputting the serial signal output from the serial signal generation circuit 24. Since the common connection node n1 of the SST circuit 12 and resistor R1 are connected to the output node nd of each SST driver 25, the amplitude of the serial signal output from the SST circuit 12 changes depending on the value of these resistors R1. In other words, by adjusting the resistance value of the resistor R1 connected to the output node nd of each SST driver 25, the signal amplitude of the second serial signals SSTOUT_P and SSTOUT_N can be controlled.

[0038] A predetermined number of impedance adjustment circuits 16 are connected to the common connection node n1, which is the output node of the SST circuit 12, from among multiple (for example, 15) impedance adjustment circuits 16. Depending on how many impedance adjustment circuits 16 are connected to the output node n1 of the SST circuit 12, the signal amplitude of the second signals SSTOUT_P and SSTOUT_N output from the SST circuit 12 changes.

[0039] The impedance adjustment circuit 16 shown in Figure 5 includes resistors R2 and R3, one end of which is connected to the common connection node n1 of the SST circuit 12; two NMOS transistors Q5 and Q6, which are cascode-connected between the other end of resistor R2 and the ground voltage node; and two NMOS transistors Q7 and Q8, which are cascode-connected between the other end of resistor R3 and the ground voltage node. The adjustment code ADJ is input to both gates of transistors Q5 and Q7, and the enable signal EN is input to both gates of transistors Q6 and Q8.

[0040] As described later, the number of impedance adjustment circuits 16 selected differs depending on the bit value of the adjustment code ADJ. Each of the multiple impedance adjustment circuits 16 has resistors R2 and R3 with the same resistance value, but the bit value of the adjustment code ADJ changes the number of impedance adjustment circuits 16 connected to the common connection node n1 of the SST circuit 12, thereby switching and controlling the output resistance of the common connection node n1. In this specification, an example is described in which, when the MSB bit of the adjustment code ADJ is 1, the number of impedance adjustment circuits 16 connected to the common connection node n1 of the SST circuit 12 is increased.

[0041] The adjustment code ADJ is a bit string signal containing multiple bits. When a bit in the adjustment code ADJ and the enable signal EN are both at a high level, the corresponding NMOS transistors Q5, Q6, Q7, and Q8 in the impedance adjustment circuit 16 are turned on. The other end of resistor R2 and the other end of resistor R3 in the corresponding impedance adjustment circuit 16 are both connected to the ground voltage node, which is equivalent to a circuit in which resistors R2 and R3 are connected in parallel between the output node nd of the SST driver 25 and the ground voltage node. The impedance adjustment circuit 16 is connected between the output node nd of the SST driver 25 and the ground voltage node. In other words, the impedance adjustment circuit 16 is a GND-terminated circuit.

[0042] If the adjustment code ADJ has a bit a, in this specification, ADJ <a-1:0>It is sometimes written as follows. In this case, the impedance adjustment circuit 16 is 2 (a+1) -1 is provided. Therefore, the common connection node n1 of the SST circuit 12 has a maximum of 2 (a+1) -One impedance adjustment circuit 16 is connected.

[0043] Each of the multiple (e.g., 15) impedance adjustment circuits 16 turns transistors Q5 and Q7 on or off according to the corresponding adjustment code. The number of impedance adjustment circuits 16 that turn transistors Q5 and Q7 on changes the output resistance of each SST driver 25, and consequently, the output resistance of the SST circuit 12 also changes.

[0044] Thus, the impedance adjustment circuit 16 shown in Figure 5 becomes a GND-terminated circuit that is connected between the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12) and the ground voltage node when transistors Q5 to Q8 are turned on.

[0045] Figure 6 shows the enable signal EN and adjustment code ADJ input to the SST driver 25 and impedance adjustment circuit 16 in Figure 5. This diagram shows the correspondence between the operation state of the impedance adjustment circuit 16 and the signal level. 'a' represents a bit in the adjustment code ADJ, for example, 'a' is any integer from 0 to 3. When the enable signal EN is high (the enable signal ENB is low), the SST driver 25 and the impedance adjustment circuit 16 are enabled. On the other hand, when the enable signal EN is low, the adjustment code ADJ is enabled. Regardless of the value of each bit, the impedance adjustment circuit 16 is disconnected from the output node nd of the SST driver 25 and enters an unselected (unused) state.

[0046] When the enable signal EN is at a high level, the adjustment code ADJ When the signal level becomes high, the impedance adjustment circuit 16 becomes a circuit that connects the GND-terminated output resistor to the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12). In this case, the output resistor will be a value corresponding to the resistance values ​​of the parallel-connected resistors R2 and R3.

[0047] When the enable signal EN is at a high level, the adjustment code ADJ When the signal level drops to a low level, transistors Q5 and Q7 turn off, and the impedance adjustment circuit 16 is disconnected from the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12). In other words, in this case, the impedance adjustment circuit 16 becomes unselected (unused).

[0048] Figure 7 shows the correspondence between the multiple impedance adjustment circuits 16 and each bit of the adjustment code ADJ according to the first embodiment. Figure 7 shows an example where the adjustment code ADJ has 3 bits, i.e., 15 impedance adjustment circuits 16 are provided.

[0049] As shown in Figure 7, each of the M output nodes nd of the SST units 23 is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ <0> When the level is high, one impedance adjustment circuit Imp.adj <0> The output is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ <1> When the level is high, two impedance adjustment circuits Imp.adj <1> ~ <2> The output is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ <2> When the level is high, four impedance adjustment circuits Imp.adj <3> ~ <6> This is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ <3> When the level is high, the 8 impedance adjustment circuits Imp.adj <7> ~ <14> This is connected to the common connection node n1 of the SST circuit 12.

[0050] Thus, the number of impedance adjustment circuits 16 connected to the common connection node n1 of the SST circuit 12 differs for each bit of the adjustment code ADJ. Note that Figure 7 is just one example, and the correspondence between each bit of the adjustment code ADJ and the number of impedance adjustment circuits 16 connected to the common connection node n1 of the SST circuit 12 can be changed in various ways.

[0051] The power supply circuit 14 controls the level of the power supply voltage VDD2 of the SST driver 25 according to the adjustment code ADJ. On the other hand, the power supply voltage VDD1 of the serial signal generation circuit 24 in each SST unit 23 is at a fixed level regardless of the adjustment code ADJ.

[0052] The communication system 1 in Figure 1 includes, for example, a transmitting device 2 including a controller (SoC: System on a Chip) and a receiving device 3 including a storage device (not shown) such as NAND flash memory. Figure 8 is a flowchart showing an example of the processing operation of the communication system 1.

[0053] First, the controller (not shown) of the transmitter 2 determines the output resistance value as seen from the common connection node n1 of the SST circuit 12 (S1). The controller of the transmitter 2 uses the resistance variation value sent from the receiver 3 to determine the output resistance value as seen from the common connection node n1 of the SST circuit 12, based on the output resistance of the transmitter 2, the amplitude value of the serial signal received by the receiver 3, and the common-mode voltage of the serial signal. For example, the above-mentioned output resistance value is determined so that the amplitude value of the serial signal received by the receiver 3 becomes a desired value. The common-mode voltage of the serial signal also affects the amplitude value of the serial signal received by the receiver 3, so the above-mentioned output resistance value is determined taking the common-mode voltage into consideration.

[0054] Next, the controller of the transmitter 2 generates an adjustment code ADJ (S2) so that the value of the output resistance as seen from the common connection node n1 of the SST circuit 12 becomes a desired value.

[0055] Next, the controller or power supply circuit 14 of the transmitting device 2 determines the power supply voltage VDD2 of the SST driver 25 in order to compensate for waveform distortion and ISI of the serial signal received by the receiving device 3 (S3).

[0056] Figure 9 shows an example of a lookup table that shows the correspondence between the adjustment code ADJ and the power supply voltage VDD2 of the SST circuit 12. By providing a memory unit that stores the lookup table in Figure 9 in the power supply circuit 14, the power supply circuit 14 can quickly determine the power supply voltage VDD2 of the SST circuit 12 based on the adjustment code ADJ from the controller.

[0057] The lookup table in Figure 9 stores the adjustment code ADJ, the desired power supply voltage (DRV power supply voltage) VDD2, the voltage drop due to parasitic resistance in the power supply line, the output variation of the SSTOUT output of the SST circuit 12 generated by the power supply circuit 14, and the correspondence between these values ​​and the center value of the power supply voltage output by the power supply circuit 14. The power supply circuit 14 has variations in power supply voltage due to manufacturing variations, and the power supply line has parasitic resistance, so in order to supply the desired power supply voltage VDD2 to the SST driver 25, the power supply circuit 14 needs to generate an optimal power supply voltage. By preparing the lookup table in Figure 9 in advance, the power supply circuit 14 can generate an optimal power supply voltage according to the adjustment code ADJ.

[0058] The M-PHY standard specifies the output amplitude, output resistance, and common-mode voltage of the transmitted serial signal. Figure 10 is a waveform diagram showing the output amplitude and common-mode voltage of the serial signal output by the transmitter 2 according to the first embodiment. In Figure 10, the horizontal axis is the adjustment code ADJ, and the vertical axis is the voltage value. Figure 10 shows waveforms w1 to w4 of the common-mode voltage corresponding to the power supply voltage VDD2 of the SST driver 25, and waveforms w6 to w9 of the output amplitude (voltage value) of the serial signal from the SST driver 25. Waveforms w1 to w4 correspond to waveforms w6 to w9, respectively.

[0059] As shown in Figure 10, as the adjustment code ADJ increases, the output resistance of the SST driver 25 decreases, resulting in smaller output amplitude values ​​and common-mode voltages for the serial signal. The M-PHY standard requires that when the adjustment code ADJ is a certain value P, the output amplitude value of the serial signal and the common-mode voltage must be within the specified range. In Figure 10, by adjusting the power supply voltage VDD2 of the SST driver 25, the common-mode voltage (waveform w1) when the adjustment code ADJ is a certain value P is lower than the specified common-mode voltage value Vref0, and the output amplitude (waveform w6) of the SST driver 25 can be set to be greater than the specified value Vref1, thus satisfying the M-PHY specifications.

[0060] Figure 11 is a circuit diagram of a portion of the transmitting device 200 according to one comparative example. More specifically, Figure 11 is a circuit diagram showing an example of the circuit configuration of the SST unit 23 and impedance adjustment circuit 160 according to one comparative example. In Figure 11, components common to Figure 5 are denoted by the same reference numerals, and the differences will be explained below.

[0061] The circuit configuration of the SST unit 23 in Figure 11 is the same as that of the SST unit 23 in Figure 5.

[0062] The impedance adjustment circuit 160 shown in Figure 11, which is a comparative example, has a different circuit configuration from the impedance adjustment circuit 16 in Figure 5. The impedance adjustment circuit 160 in Figure 11 has resistors R110 and R120, one end of which is connected to the output node nd of the SST driver 25, two PMOS transistors Q110 and Q120, which are cascode-connected between the node to which the power supply voltage VDD2 is supplied and the other end of resistor R110, and two NMOS transistors Q130 and Q140, which are cascode-connected between the other end of resistor R120 and the ground voltage node. The resistors R110 and R120 are trimmed according to the adjustment code ADJ to make their resistance values ​​variable. An enable signal ENB is input to both gates of the two PMOS transistors Q110 and Q120, and an enable signal EN is input to both gates of the two NMOS transistors Q130 and Q140. Thus, the impedance adjustment circuit 160 in one comparative example is a circuit terminated to the power supply voltage VDD2 and also terminated to the ground voltage. In one comparative example, since the power supply voltage VDD2 of the SST driver 25 is fixed, even if the resistors R110 and R120 of the impedance adjustment circuit 160 are adjusted according to the adjustment code ADJ, the common mode voltage cannot be varied.

[0063] Furthermore, the power supply voltage VDD2 of the SST driver 25 in one comparative example has a constant voltage level that is independent of the adjustment code. In other words, in one comparative example, once the power supply voltage VDD2 of the SST driver 25 is set, it is not possible to change the power supply voltage VDD2 thereafter.

[0064] Figure 12 is a waveform diagram showing the output amplitude value and common-mode voltage of the serial signal output by the transmitter 2 according to one comparative example. Figure 12 illustrates the waveforms w11 to w14 of the common-mode voltage corresponding to the power supply voltage VDD2 of the SST driver 25, and the waveforms w16 to w19 of the output amplitude value (voltage value) of the serial signal from the SST driver 25. Waveforms w11 to w14 correspond to waveforms w16 to w19, respectively.

[0065] As shown in Figure 12, the common-mode voltage increases as the power supply voltage VDD2 of the SST driver 25 increases, and the common-mode voltage hardly changes even when the adjustment code is changed. For this reason, when the adjustment code is set to a predetermined value P, even if the output amplitude (waveform w16) of the SST driver 25 can be set to be greater than the standard value Vref3, the common-mode voltage will exceed the upper limit Vref2 specified in the M-PHY standard, and the specifications will no longer be met.

[0066] Thus, in the first embodiment, the impedance adjustment circuit 16 is provided which is not terminated at the power supply voltage VDD2 node but terminated at the ground voltage node, and the power supply voltage VDD2 of the SST driver 25 is variably adjusted according to the adjustment code ADJ. As the adjustment code ADJ increases, the common mode voltage can be lowered, and the specifications for the common mode voltage defined in the M-PHY standard can be met.

[0067] Furthermore, in the first embodiment, since the power supply voltage VDD2 of the SST driver 25 is variably controlled according to the adjustment code ADJ, the output amplitude value of the serial signal output from the SST circuit 12 can be optimized even if the adjustment code ADJ increases. Therefore, the specifications for the common-mode voltage and the output amplitude value of the serial signal output from the SST circuit 12 as defined in the M-PHY standard can be met regardless of the adjustment code ADJ.

[0068] (Second embodiment) In the first embodiment, the impedance adjustment circuit 16 was terminated to a ground voltage node, while in the second embodiment, the impedance adjustment circuit 16a is terminated to a power supply voltage node. In this specification, termination to a node supplied with the power supply voltage VDD2 (power supply voltage node) is sometimes referred to as VDD termination.

[0069] Figure 13 is a circuit diagram showing an example of the internal configuration of one SST driver 25 and one impedance adjustment circuit 16a in the transmitting device 2 according to the second embodiment. The SST circuit 12 according to the second embodiment has a plurality of impedance adjustment circuits 16a and M SST drivers 25 having the same circuit configuration as in Figure 5. Figure 13 shows one impedance adjustment circuit 16a and one SST driver 25.

[0070] The impedance adjustment circuit 16a in Figure 13 includes resistors R11 and R12, each having one end connected to the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12), PMOS transistors Q11 and Q12 cascode-connected between the power supply voltage node and the other end of resistor R11, and PMOS transistors Q13 and Q14 cascode-connected between the power supply voltage node and the other end of resistor R12.

[0071] The circuit configuration of the SST driver 25 in Figure 13 is the same as that of the SST driver 25 in Figure 5. Although omitted in Figure 13, the output node of the serial signal generation circuit 24, which has the same circuit configuration as in Figure 5, is connected to the input node SSTIN of the SST driver 25, but the serial signal generation circuit 24 is not shown in Figure 15.

[0072] The gates of transistors Q11 and Q13 are each input to the enable signal ENB. The gates of transistors Q12 and Q14 are each input to the adjustment code ADJB. The adjustment code ADJB is the inverse signal of the adjustment code ADJ.

[0073] Figure 14 shows the enable signal and adjustment code ADJB input to the SST driver 25 and impedance adjustment circuit 16a in Figure 13. This diagram shows the correspondence between the operation state of the impedance adjustment circuit 16a and the signal level. 'a' is, for example, any integer from 0 to 3. When the enable signal ENB is low, the SST driver 25 and the impedance adjustment circuit 16a are enabled. On the other hand, when the enable signal ENB is high, the adjustment code ADJB... Regardless of the value of each bit, the impedance adjustment circuit 16a is disconnected from the output node nd of the SST driver 25 and enters a deselected (unused) state.

[0074] When the enable signal ENB is low, the adjustment code ADJB When the voltage is at a low level, the impedance adjustment circuit 16a becomes a circuit in which resistors R11 and R12 are connected in parallel between the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12) and the power supply voltage node to which the power supply voltage VDD2 is supplied. In this case, the output resistance will be a value corresponding to the resistance values ​​of the parallel-connected resistors R11 and R12.

[0075] When the enable signal ENB is low, the adjustment code ADJB When the signal level becomes high, transistors Q12 and Q14 turn off, and the impedance adjustment circuit 16a is disconnected from the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12). In other words, in this case, the impedance adjustment circuit 16a becomes unselected (unused).

[0076] In the second embodiment, the SST driver 25, similar to the SST driver 25 in Figure 5, has its power supply voltage VDD2 variably controlled according to the adjustment code.

[0077] Thus, in the second embodiment, the impedance adjustment circuit 16a is provided which is not terminated at the ground voltage node but at the power supply voltage node, and the power supply voltage VDD2 of the SST driver 25 is variably adjusted according to the adjustment codes ADJ and ADJB. As a result, the common mode voltage can be increased as the adjustment code increases, and the common mode voltage specifications defined in the M-PHY standard can be met.

[0078] Furthermore, in the second embodiment, the power supply voltage VDD2 of the SST driver 25 is variably controlled according to the adjustment codes ADJ and ADJB. Therefore, even if the adjustment codes ADJ and ADJB are large, the output amplitude value of the serial signal output from the SST circuit 12 can be optimized. Thus, regardless of the adjustment codes ADJ and ADJB, the specifications for the common-mode voltage and the output amplitude value of the serial signal output from the SST circuit 12 as defined in the M-PHY standard can be met.

[0079] (Third embodiment) In the third embodiment, the impedance adjustment circuit 16 can be selectively selected by an adjustment code to be either VDD-terminated and GND-terminated, or GND-terminated.

[0080] Figure 15 is a circuit diagram showing an example of the internal configuration of one SST driver 25 and one impedance adjustment circuit 16b in the transmitting device 2 according to the third embodiment. The SST circuit 12 according to the third embodiment has a plurality of impedance adjustment circuits 16b and M SST drivers 25 having the same circuit configuration as in Figure 5. Figure 15 shows one impedance adjustment circuit 16b and one SST driver 25.

[0081] The impedance adjustment circuit 16b in Figure 15 has a circuit configuration that combines a part of the impedance adjustment circuit 16 in Figure 5 and the impedance adjustment circuit 16aa in Figure 13. Specifically, the impedance adjustment circuit 16b in Figure 15 has resistors R21, R22, and R23, each with one end connected to the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12), NMOS transistors Q21 and Q22 that are cascode-connected between the power supply voltage node and the other end of resistor R21, NMOS transistors Q23 and Q24 that are cascode-connected between the other end of resistor R22 and the ground voltage node, and NMOS transistors Q25 and Q26 that are cascode-connected between the power supply voltage node and the other end of resistor R23.

[0082] The gate of transistor Q23 is input with adjustment code ADJ1, and the gate of transistor Q24 is input with enable signal EN1. The gate of transistor Q21 is input with enable signal EN2B, the gate of transistor Q25 is input with enable signal EN3B, and the gates of transistors Q22 and Q26 are each input with adjustment code ADJ2B. Adjustment codes ADJ1 and ADJ2B are independent signals. Enable signals EN1, EN2B, and EN3B are also independent signals.

[0083] The circuit configuration of the SST driver 25 in Figure 15 is the same as that of the SST driver 25 in Figure 5. Although not shown in Figure 15, the input node SSTIN of the SST driver 25 is connected to the output node of the serial signal generation circuit 24, which has the same circuit configuration as in Figure 5, but the serial signal generation circuit 24 is not shown in Figure 15.

[0084] Figure 16 shows the enable signals EN1, EN2B, EN3B, and adjustment code ADJ1 input to the SST driver 25 and impedance adjustment circuit 16b in Figure 15. ADJ2B This diagram shows the correspondence between the operating state of the impedance adjustment circuit 16b and the actual state of the circuit. 'a' is, for example, any integer between 0 and 3.

[0085] The impedance adjustment circuit 16b is terminated to VDD when the enable signals EN1, EN2B, and EN3B are at a low level, and both adjustment codes ADJ1 and ADJ2B are at a low level. An output resistor corresponding to the resistance values ​​of the parallel-connected resistors R21 and R23 is connected between the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12) and the power supply voltage node.

[0086] The impedance adjustment circuit 16b is terminated to VDD and GND when the enable signal EN1 is high level, the enable signal EN2B is low level, and the enable signal EN3B is high level (or the enable signal EN1 is high level, the enable signal EN2B is high level, and the enable signal EN3B is low level), and the adjustment code ADJ1 is high level and the adjustment code ADJ2B is low level. An output resistor corresponding to the resistance value of resistor R21 (or R23) between the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12) and the power supply voltage node is connected, and an output resistor corresponding to the resistance value of resistor R22 between the output node nd of the SST driver 25 (common connection node n1 of the SST circuit 12) and the ground voltage node is connected.

[0087] The impedance adjustment circuit 16b is deselected (not used) when adjustment code ADJ1 is at a low level and adjustment code ADJ2B is at a high level. Furthermore, the impedance adjustment circuit 16b is deselected (not used) when the enable signal EN1 is at a low level and enable signals EN2B and EN3B are at high levels. Also, the impedance adjustment circuit 16b is deselected (not used) when enable signals EN2B and EN3B are at high levels and adjustment code ADJ1 is at a low level. Finally, the impedance adjustment circuit 16b is deselected (not used) when enable signal EN1 is at a low level and adjustment code ADJ2B is at a high level.

[0088] Figure 17 shows the correspondence between multiple impedance adjustment circuits 16b and each bit of the adjustment code ADJ according to the third embodiment. As shown in Figure 17, the output nodes nd of each of the M SST units 23 are all connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ1 <0> It is at a high level, and the adjustment code is ADJ2B <0> When the level is low, one impedance adjustment circuit Imp.adj <0> The output is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ1 <1> It is at a high level, and the adjustment code is ADJ2B <1> When the level is low, two impedance adjustment circuits Imp.adj <1> ~ <2> The output is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ1 <2> It is at a high level, and the adjustment code is ADJ2B <2> When the level is low, four impedance adjustment circuits Imp.adj <3> ~ <6> This is connected to the common connection node n1 of the SST circuit 12. Adjustment code ADJ1 <3> It is at a high level, and the adjustment code is ADJ2B <3> When the level is low, the 8 impedance adjustment circuits Imp.adj <7> ~ <14> This is connected to the common connection node n1 of the SST circuit 12.

[0089] Figure 18 is a circuit diagram showing an example of the internal configuration of one SST driver 25 and one impedance adjustment circuit 16c in a transmitter 2 according to one modified example of the third embodiment. Figure 18 shows one impedance adjustment circuit 16c and one SST driver 25 included in the SST circuit 12 according to one modified example. The circuit configuration of the impedance adjustment circuit 16c in Figure 18 has a circuit configuration similar to that of the impedance adjustment circuit 16b in Figure 15. The impedance adjustment circuit 16c in Figure 18 includes resistors R31, R32, R33, and R34, each having one end connected to the output node nd of the SST driver 25 (common connection node n1 of the SST circuit), PMOS transistors Q31 and Q32 cascode-connected between the power supply voltage node and the other end of resistor R31, NMOS transistors Q33 and Q34 cascode-connected between the other end of resistor R32 and the ground voltage node, PMOS transistors Q35 and Q36 cascode-connected between the power supply voltage node and the other end of resistor R33, and NMOS transistors Q37 and Q38 cascode-connected between the other end of resistor R34 and the ground voltage node.

[0090] Some of the signals input to the gates of transistors Q31 to Q38 differ between Figure 18 and Figure 15. In the impedance adjustment circuit 16c in Figure 18, the enable signal EN3B is input to the gate of transistor Q31, the adjustment code ADJ2B is input to the gate of transistor Q32, the adjustment code ADJ1 is input to the gate of transistor Q33, and the enable signal EN1 is input to the gate of transistor Q34. In addition, the enable signal EN4B is input to the gate of transistor Q35, the adjustment code ADJ2B is input to the gate of transistor Q36, the adjustment code ADJ1 is input to the gate of transistor Q37, and the enable signal EN2 is input to the gate of transistor Q38.

[0091] Figure 19 shows the enable signals EN1, EN2, EN3B, EN4B and the adjustment code ADJ1 input to the SST driver 25 and impedance adjustment circuit 16c in Figure 18. ADJ2B This figure shows the correspondence between bit values ​​(for example, a is 0 to 3) and the operating state of the impedance adjustment circuit 16c.

[0092] Enable signals EN1, EN2, EN3B, and EN4B are all at a high level, and adjustment code ADJ1 ADJ2B When all of these are at a high level, transistors Q33, Q34, Q37, and Q38 turn on, and transistors Q31, Q35, Q32, and Q36 turn off, so the impedance adjustment circuit 16c is terminated to GND.

[0093] Enable signals EN1, EN2, EN3B, and EN4B are all at a low level, and adjustment code ADJ1 ADJ2B When all of these are at a low level, transistors Q31, Q32, Q35, and Q36 are turned on, and transistors Q33, Q34, Q37, and Q38 are turned off, so the impedance adjustment circuit 16c is terminated with VDD.

[0094] Enable signals EN1 and EN4B are at a high level, enable signals EN2 and EN3B are at a low level, and adjustment code ADJ1 It is at a high level, and the adjustment code is ADJ2B When the current is at a low level, transistors Q31 to Q34 are all turned on, so the impedance adjustment circuit 16c is terminated on VDD and GND.

[0095] Enable signals EN1 and EN4B are at a low level, and enable signals EN2 and EN3B are at a high level, and adjustment code ADJ1 It is at a high level, and the adjustment code is ADJ2B When the current is at a low level, transistors Q35 to Q38 are all turned on, so the impedance adjustment circuit 16c is terminated with VDD and GND.

[0096] When the enable signals EN1, EN2, EN3B, 3N4B, and adjustment codes ADJ1, ADJ2B are of a logic other than those listed above, the impedance adjustment circuit 16c is deselected (not used).

[0097] Note that the output resistance when all transistors Q31-Q38 in the impedance adjustment circuit 16c are turned on will be different from the output resistance when only one set of transistors (Q31, Q32) or (Q35, Q36) is turned on, and only one set of transistors (Q33, Q34) or (Q37, Q38) is turned on. Therefore, enable signals EN1, EN2, EN3B, EN4B and adjustment code ADJ1 are used to prevent all transistors Q31-Q38 in the impedance adjustment circuit 16c from turning on. ADJ2B The logic of this is controlled.

[0098] Thus, in the third embodiment, enable signals EN1, EN2, EN3B, EN4B and adjustment code ADJ1 ADJ2B By switching the logic, the impedance adjustment circuit 16c can be either terminated with VDD and GND, or terminated with VDD (GND). Therefore, the receiving device 3 can be adjusted to the common-mode voltage that is easiest to receive.

[0099] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0100] [Note] [Item 1] A first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel or serial signal, A second circuit adjusts the output impedance of the output node of the first circuit, The system includes a third circuit that controls the power supply voltage of at least a portion of the circuit of the first circuit in accordance with the adjustment of the output impedance by the second circuit, Semiconductor equipment. [Item 2] The third circuit controls the power supply voltage of the circuit portion such that the output impedance value, the amplitude value of the second signal, and the common-mode voltage of the second signal satisfy predetermined standards. Semiconductor device as described in item 1. [Item 3] The aforementioned specified standard is M-PHY, which was developed by the MIPI (Mobile Industry Processor Interface) Alliance. Semiconductor device as described in item 2. [Item 4] The second circuit includes a circuit that terminates to a power supply voltage node or a ground voltage node. A semiconductor device as described in any one of items 1 through 3. [Item 5] The second circuit adjusts the output impedance between the output node of the first circuit and the power supply voltage node or the ground voltage node. Semiconductor device as described in item 4. [Item 6] The second circuit adjusts the output impedance based on the adjustment code, The third circuit controls the power supply voltage of the circuit portion based on the adjustment code. A semiconductor device as described in any one of items 1 through 5. [Item 7] The second circuit has a plurality of fourth circuits, each consisting of a common circuit. The second circuit controls, based on the adjustment code, whether or not to connect each of the output nodes of the plurality of fourth circuits to the output node of the first circuit. Semiconductor device as described in item 6. [Item 8] The adjustment code is a bit string signal containing multiple bits, A number of the fourth circuits selected by the value of each bit in the bit string signal are connected to the output node of the first circuit. Semiconductor device as described in item 7. [Item 9] Each of the plurality of fourth circuits switches, based on the corresponding bit of the adjustment code, whether to terminate at a power supply voltage node or a ground voltage node, or to disconnect from the output node of the second circuit. Semiconductor device as described in item 8. [Item 10] Each of the plurality of fourth circuits switches, based on the corresponding bit of the adjustment code, whether to terminate at a power supply voltage node or a ground voltage node, terminate at both a power supply voltage node and a ground voltage node, or disconnect from the output node of the second circuit. Semiconductor device as described in item 8. [Item 11] Each of the plurality of fourth circuits includes a resistor, a first transistor that turns on or off according to the corresponding bit of the adjustment code, and a second transistor that switches whether or not to enable the corresponding fourth circuit. A semiconductor device as described in any one of items 8 through 10. [Item 12] The first circuit comprises a plurality of fifth circuits to which the first signal is input, The second signal is output from a common connection node that connects each of the output nodes of the plurality of fifth circuits to each of the output nodes of the plurality of fourth circuits. A semiconductor device as described in any one of items 7 through 11. [Item 13] Each of the aforementioned plurality of fifth circuits is A sixth circuit that converts the aforementioned first signal into a third signal which is a serial signal, A seventh circuit having an input node connected to the output node of the sixth circuit and an output node connected to the common connection node, which outputs the second signal corresponding to the third signal, Semiconductor device as described in item 12. [Item 14] The third circuit controls the power supply voltage of the seventh circuit in accordance with the adjustment of the output impedance by the second circuit. Semiconductor device as described in item 13. [Item 15] The power supply voltage of the sixth circuit is at a fixed voltage level, regardless of the adjustment of the output impedance by the second circuit. Semiconductor device as described in item 14. [Item 16] The adjustment code input to each of the plurality of fourth circuits is a binary code or a thermometer code. A semiconductor device as described in any one of items 7 through 15. [Item 17] The first signal and the second signal are each differential signals. A semiconductor device as described in any one of items 1 through 16. [Item 18] A conversion circuit that outputs a first signal which is a parallel or serial signal, A semiconductor device according to any one of claims 1 to 17 that performs processing based on the first signal, comprising: Transmitter. [Item 19] The conversion circuit converts the fourth signal, which is a parallel signal of the first bit sequence, into the first signal, which is a parallel signal of the second bit sequence with fewer bits than the first bit sequence, and outputs it. The transmitting device described in item 18. [Item 20] The conversion circuit outputs the first signal which has undergone FFE (Feed Forward Equalizer) processing on the parallel signal of the first bit sequence. The transmitting device described in item 19. [Explanation of Symbols]

[0101] 1 Communication system, 2 Transmitter, 3 Receiver, 4 Differential transmission line, 11 PISO circuit, 12 SST circuit, 13 Clock generation circuit, 13a Impedance adjustment circuit, 13d Impedance adjustment circuit, 14 Power supply circuit, 15 Semiconductor device, 16 Impedance adjustment circuit, 16a Impedance adjustment circuit, 16b Impedance adjustment circuit, 16c Impedance adjustment circuit, 21 FFE processing unit, 22a Multiplexer, 22b Multiplexer, 23 SST unit, 24 Serial signal generation circuit, 25 SST driver, 26 Multiplexer, 27 Buffer circuit, 28 First inverter, 29 Second inverter, 30 First transfer gate, 31 Second transfer gate, 32 Third inverter, 33 Fourth inverter, 160 Impedance adjustment circuit, 200 Transmitter

Claims

1. A first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel or serial signal, A second circuit adjusts the output impedance of the output node of the first circuit, The system includes a third circuit that controls the power supply voltage of at least a portion of the first circuit in accordance with the adjustment of the output impedance by the second circuit, Semiconductor equipment.

2. The third circuit controls the power supply voltage of the circuit portion such that the output impedance value, the amplitude value of the second signal, and the common-mode voltage of the second signal satisfy predetermined standards. The semiconductor device according to claim 1.

3. The second circuit includes a circuit that terminates to a power supply voltage node or a ground voltage node. The semiconductor device according to claim 1.

4. The second circuit adjusts the output impedance based on the adjustment code, The third circuit controls the power supply voltage of the circuit portion based on the adjustment code. The semiconductor device according to claim 1.

5. The second circuit has a plurality of fourth circuits, each consisting of a common circuit. The second circuit controls, based on the adjustment code, whether or not to connect each of the output nodes of the plurality of fourth circuits to the output node of the first circuit. The semiconductor device according to claim 4.

6. Each of the plurality of fourth circuits includes a resistor, a first transistor that turns on or off according to the corresponding bit of the adjustment code, and a second transistor that switches whether or not to enable the corresponding fourth circuit. The semiconductor device according to claim 5.

7. The first circuit comprises a plurality of fifth circuits to which the first signal is input. The second signal is output from a common connection node that connects each of the output nodes of the plurality of fifth circuits to each of the output nodes of the plurality of fourth circuits. The semiconductor device according to claim 5.

8. A conversion circuit that outputs a first signal which is a parallel or serial signal, A semiconductor device according to any one of claims 1 to 7 that performs processing based on the first signal, comprising: Transmitter.

9. The conversion circuit converts the fourth signal, which is a parallel signal of the first bit sequence, into the first signal, which is a parallel signal of the second bit sequence having fewer bits than the first bit sequence, and outputs it. The transmitting device according to claim 8.

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