Semiconductor device, semiconductor memory device, and method for manufacturing a semiconductor device.

Abstract

The present invention provides a semiconductor device, a semiconductor memory device, and a method for manufacturing a semiconductor device that can suppress the decrease in the breakdown voltage of an insulating film. [Solution] The semiconductor device comprises an oxide semiconductor including an upper electrode, a lower electrode, a first part connected to the upper electrode, and a second part connected to the lower end of the first part and having a diameter larger than the diameter of the lower end of the first part, and connected to the lower electrode; a gate insulating film surrounding the side surface of the first part and having an outer diameter smaller than the diameter of the second part; a first insulating layer through which the first part passes; a gate electrode provided below the first insulating layer and through which the first part passes, the gate electrode facing the first part via the gate insulating film; and a second insulating layer provided below the gate electrode and having a connection portion between the first part and the second part.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor device, a semiconductor memory device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] Some semiconductor devices have an oxide semiconductor surrounded by an insulating film, with electrodes facing the oxide semiconductor via the insulating film. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication US2006 / 0128142 [Patent Document 2] U.S. Patent Application Publication US2023 / 0253463 [Patent Document 3] U.S. Patent Application Publication US2021 / 0057273 Specification [Patent Document 4] U.S. Patent Application Publication US2010 / 0102382 [Patent Document 5] U.S. Patent Application Publication US2012 / 0220079 Specification [Patent Document 6] U.S. Patent Application Publication US2024 / 0098981 [Patent Document 7] U.S. Patent No. 10347637 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the manufacturing process of semiconductor devices, damage to the insulating film can reduce its breakdown voltage.

[0005] The purpose of this disclosure is to provide a semiconductor device, a semiconductor memory device, and a method for manufacturing a semiconductor device that can suppress a decrease in the breakdown voltage of an insulating film. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises an oxide semiconductor including an upper electrode, a lower electrode, a first portion connected to the upper electrode, and a second portion connected to the lower end of the first portion and having a diameter larger than the diameter of the lower end of the first portion, and connected to the lower electrode; a gate insulating film surrounding the side surface of the first portion and having an outer diameter smaller than the diameter of the second portion; a first insulating layer through which the first portion passes; a gate electrode provided below the first insulating layer and through which the first portion passes, the gate electrode facing the first portion via the gate insulating film; and a second insulating layer provided below the gate electrode and having a connecting portion for the first and second portions.

[0007] The semiconductor device according to this disclosure comprises an upper electrode, an oxide semiconductor having an upper end and a lower end connected to the upper electrode and extending in the vertical direction, a gate insulating film provided on the side surface of the oxide semiconductor, a gate electrode facing the side surface of the oxide semiconductor via the gate insulating film, and a first layer provided below the gate electrode and connected to the gate insulating film, wherein the gate insulating film includes an extended insulating portion extending downward in the first layer.

[0008] The semiconductor memory device according to this disclosure comprises a semiconductor device and a capacitor electrically connected to the upper electrode through the oxide semiconductor, wherein the capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode.

[0009] A method for manufacturing a semiconductor device according to the present disclosure includes forming a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, exposing a first layer provided below the second insulating layer; forming a gate insulating film that covers the hole; forming a protective film that covers the gate insulating film; removing a portion of the protective film that covers the first layer; removing a portion of the gate insulating film that covers the first layer; removing the protective film; and forming a semiconductor inside the hole.

[0010] A method for manufacturing a semiconductor device according to the present disclosure includes forming a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, exposing a first layer provided below the second insulating layer; forming a sacrificial film to cover the hole; removing a portion of the sacrificial film covering the first layer to expose the upper surface of the first layer; forming a monolayer on the exposed upper surface of the first layer; removing the sacrificial film; forming a gate insulating film on the inner surface of the hole that is not covered by the monolayer; removing the monolayer; and forming a semiconductor inside the hole.

[0011] A method for manufacturing a semiconductor device according to the present disclosure includes forming a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, exposing a first layer provided below the second insulating layer; forming a gate insulating film that covers the hole; forming a sacrificial film that covers the gate insulating film below the hole; forming a monolayer in the hole that covers a portion of the gate insulating film not covered by the sacrificial film; removing the sacrificial film to expose a portion of the gate insulating film that was covered by the sacrificial film; removing a portion of the gate insulating film that covered the first layer in the hole to expose the first layer; removing the monolayer; and forming a semiconductor inside the hole. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram for explaining a circuit configuration example of a memory cell array according to the first embodiment. [Figure 2] This is a schematic cross-sectional view for explaining a structural example of a semiconductor memory device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane. [Figure 3] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 4] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 5] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 6] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 7] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 8] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the first embodiment. [Figure 9] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the first embodiment. [Figure 10] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the first embodiment. [Figure 11] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the first embodiment. [Figure 12] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the first embodiment. [Figure 13] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the first embodiment. [Figure 14] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the first embodiment. [Figure 15] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 16]This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 17] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 18] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 19] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 20] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the first embodiment. [Figure 21] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the sixth example of the first embodiment. [Figure 22] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the sixth example of the first embodiment. [Figure 23] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the seventh example of the first embodiment. [Figure 24] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the seventh example of the first embodiment. [Figure 25] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the eighth example of the first embodiment. [Figure 26] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the eighth example of the first embodiment. [Figure 27] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the eighth example of the first embodiment. [Figure 28] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the ninth example of the first embodiment. [Figure 29] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the ninth example of the first embodiment. [Figure 30] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the ninth example of the first embodiment. [Figure 31] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 32] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 33] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 34] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 35] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 36] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 10th example of the first embodiment. [Figure 37] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 11th example of the first embodiment. [Figure 38] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 11th example of the first embodiment. [Figure 39] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 11th example of the first embodiment. [Figure 40] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the twelfth example of the first embodiment. [Figure 41] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the twelfth example of the first embodiment. [Figure 42] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the twelfth example of the first embodiment. [Figure 43] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 13th example of the first embodiment. [Figure 44] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 13th example of the first embodiment. [Figure 45] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 13th example of the first embodiment. [Figure 46] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the 13th example of the first embodiment. [Figure 47] This is a schematic diagram showing the manufacturing process of a semiconductor device related to a comparative example. [Figure 48] This is a schematic diagram showing the manufacturing process of a semiconductor device related to a comparative example. [Figure 49]This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 50] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 51] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 52] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 53] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 54] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 55] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the first example of the second embodiment. [Figure 56] This figure shows an example of a process for selectively adsorbing SAM 151 onto the lower electrode 32 when the sacrificial gate insulating film 143 and the lower electrode 32 are exposed. [Figure 57] This figure shows another example of a process for selectively adsorbing SAM 151 onto the lower electrode 32 when the sacrificial gate insulating film 143 and the lower electrode 32 are exposed. [Figure 58] This diagram illustrates the effect of the extended insulating film 43a. [Figure 59] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 60] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 61] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 62] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 63] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 64]This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 65] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 66] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the second example of the second embodiment. [Figure 67] This figure shows an example of a process for selectively adsorbing SAM 155 onto the stopper film 601 when the sacrificial gate insulating film 143 and the stopper film 601 are exposed. [Figure 68] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 69] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 70] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 71] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 72] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 73] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 74] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 75] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the third example of the second embodiment. [Figure 76] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the second embodiment. [Figure 77] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the second embodiment. [Figure 78] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the second embodiment. [Figure 79] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fourth example of the second embodiment. [Figure 80]This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 81] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 82] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 83] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 84] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 85] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 86] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 87] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 88] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 89] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 90] This is a schematic diagram showing the manufacturing process of a semiconductor device according to the fifth example of the second embodiment. [Figure 91] This figure shows an example of a process for selectively removing SAM153 adsorbed on the sacrificial gate insulating film 143 when SAM153 is adsorbed on the sacrificial gate insulating film 143 and the stopper film 701. [Figure 92] This figure shows an example of a process for selectively adsorbing SAM154 onto the gate insulating film 43 when the gate insulating film 43 and stopper film 701 are exposed. [Figure 93] Figure 75 shows a cross-sectional view along the cutting line XCIII-XCIII. [Figure 94] This figure shows a modified example of the cross-section shown in Figure 93. [Modes for carrying out the invention]

[0013] This embodiment will now be described with reference to the attached drawings. To facilitate understanding of the explanation, the same reference numerals are used for identical components in each drawing whenever possible, and redundant explanations are omitted.

[0014] [First Embodiment] The configuration of the semiconductor memory device according to the first embodiment will now be described. Each drawing may show the X, Y, and Z axes. The X, Y, and Z axes form a three-dimensional Cartesian coordinate system in a right-handed system. Hereinafter, the direction of the arrow on the X axis may be called the X-axis+ direction, and the direction opposite to the arrow may be called the X-axis- direction, and the same applies to the other axes. The Z-axis+ direction and Z-axis- direction may also be called "up" and "down," respectively. Furthermore, the planes perpendicular to the X, Y, or Z axes may be called the YZ plane, ZX plane, or XY plane. The direction in the Z axis direction may also be called the "up and down direction." "Up," "down," and "up and down direction" are terms that indicate relative positional relationships within the drawings and do not define orientations based on the vertical direction.

[0015] Furthermore, unless otherwise specifically stated, the dimensions of the components shown in each drawing may differ from the actual dimensions in order to facilitate understanding of the explanation.

[0016] In this specification, “connection” includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0017] In this specification, "formed above" includes not only cases where it is formed in contact with what is above, but also cases where it is formed above through another object, unless otherwise specified. The same applies to cases such as "formed below."

[0018] The semiconductor memory device 101 according to the first embodiment is OS-RAM (Oxide Semiconductor-Random Access Memory) and includes a memory cell array.

[0019] As shown in Figure 1, the memory cell array includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0020] Figure 1 shows an example of multiple word lines WL, n Word line WL n+1 and word line WL n+2 This is shown (where n is a positive integer). Also, Figure 1 shows an example of a bit line BL. m , bit line BL m+1 and bit line BL m+2 This is shown (where m is a positive integer). Note that the number of memory cells MC is not limited to the number shown in Figure 1.

[0021] Multiple memory cells (MCs) are arranged, for example, in a matrix to form a memory cell array. A memory cell MC includes a memory transistor (MTR), which is a field-effect transistor (FET), and a memory capacitor (MCP).

[0022] A series of memory cells MC arranged along the row direction have a word line WL (e.g., word line WL) corresponding to the row to which they belong (e.g., row n). n A series of memory cells MCs arranged along the column direction are connected to the bit line BL (e.g., bit line BL) corresponding to the column to which they belong (e.g., the m+2th column). m+2 It connects to ).

[0023] More specifically, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs. Either the source or the drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0024] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to the other electrode of the source or drain of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power line (not shown) that supplies a specific potential.

[0025] The memory cell MC is configured to retain data by accumulating charge in the memory capacitor MCP through the current flowing through the corresponding bit line BL, which is achieved by switching the memory transistor MTR based on the potential of the corresponding word line WL.

[0026] As shown in Figure 2, the semiconductor memory device 101 comprises a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, and 63.

[0027] The capacitor 20 includes a conductor 21, an insulating film 22 (an example of a "dielectric film"), a conductor 23, a capacitor electrode 24 (an example of a "first capacitor electrode"), and a capacitor electrode 25 (an example of a "second capacitor electrode").

[0028] The semiconductor device 30 includes a field-effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 provided above the field-effect transistor 40, and a lower electrode 32 (an example of a "first layer") provided below the field-effect transistor 40.

[0029] The field-effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of a "gate electrode"), and an insulating layer 45. The field-effect transistor 40 corresponds to the memory transistor MTR of a memory cell MC (see Figure 1).

[0030] The oxide semiconductor layer 70 is formed within the insulating layer 45 and has an upper end 70a and a lower end 70b. The oxide semiconductor layer 70 is a columnar body that extends along the vertical direction. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0031] The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies act as donors. The oxide semiconductor layer 70 contains at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), iridium (Ir), ruthenium (Ru), and titanium (Ti), as well as oxygen.

[0032] In this embodiment, the oxide semiconductor layer 70 contains indium, zinc, and gallium as metallic elements. More specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, i.e., IGZO (InGaZnO). However, the oxide semiconductor layer 70 may be made of other types of oxide semiconductors.

[0033] The conductive layer 42 faces the oxide semiconductor layer 70 via a gate insulating film 43. More specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40 and surrounds the oxide semiconductor layer 70 via the gate insulating film 43 between its upper end 70a and lower end 70b. The conductive layer 42 contains, for example, tungsten (W).

[0034] The conductive layer 42 is made up of multiple electrodes that extend approximately parallel to the Y-axis and are repeatedly provided in the X-axis direction. These electrodes correspond to the word line WL (see Figure 1).

[0035] The gate insulating film 43 contains, for example, silicon and oxygen. Specifically, the gate insulating film 43 is silicon oxide. However, the gate insulating film 43 may be made of other materials, such as silicon nitride, or it may be formed as two layers of silicon oxide and silicon nitride. The gate insulating film 43 is formed to cover the entire circumference of the side surface of the oxide semiconductor layer 70.

[0036] The upper electrode 50 is formed in the Z-axis+ direction relative to the oxide semiconductor layer 70 and is connected to the upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0037] The metal film 50c contains tungsten. The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70 and contains a metal oxide. The metal oxide contains, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin oxide (ITO).

[0038] The barrier metal layer 50b contains titanium and nitrogen and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is formed of, for example, titanium nitride (TiN).

[0039] The lower electrode 32 is connected to the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 contains a metal oxide. Specifically, the lower electrode 32 contains, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin oxide (ITO).

[0040] Furthermore, the metal oxide layer 50a and the lower electrode 32 may not be limited to ITO, but may also contain at least one of the following elements: indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0041] Circuit 11 comprises peripheral circuits such as a decoder for selecting a predetermined memory cell MC from among multiple memory cells MC of the semiconductor memory device 101, i.e., capacitors 20 and field-effect transistors 40, a sense amplifier connected to the bit line BL, and a register composed of SRAM. Circuit 11 may include a CMOS circuit having field-effect transistors, specifically P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs), formed using a CMOS process.

[0042] The field-effect transistor of circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon substrate. Pch-FETs and Nch-FETs are so-called lateral field-effect transistors that have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have a channel for flowing carriers in the X-axis direction or Y-axis direction substantially parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a P-type to N-type conductivity. For convenience, Figure 2 shows an example of the field-effect transistor of circuit 11.

[0043] Capacitor 20 is a memory capacitor MCP included in the memory cell MC (see Figure 1). Figure 2 shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0044] In this embodiment, the capacitor 20 is provided above the semiconductor substrate 10. The capacitor electrode 24 of the capacitor 20 is connected to the conductor 21 and the lower electrode 32. The capacitor electrode 25 faces the capacitor electrode 24. The insulating film 22 is provided between the capacitor electrode 24 and the capacitor electrode 25.

[0045] Capacitor 20 is a three-dimensional capacitor such as a pillar-type capacitor. Note that other capacitors with a configuration capable of storing charge may also be used as the capacitor in this embodiment.

[0046] The conductor 21 abuts against the lower end face of the lower electrode 32 and has a shape that extends downward from that end. The capacitor electrode 24 is formed to cover the lower electrode 32 and the conductor 21. The insulating film 22 is formed to cover the capacitor electrode 24. The capacitor electrode 25 surrounds a portion of the lower part of the insulating film 22 and has a lower end that abuts against the upper end face of the conductor 23.

[0047] The conductor 21 may contain materials such as amorphous silicon. The insulating film 22 may contain materials such as hafnium oxide. The conductor 23 and the capacitor electrodes 24 and 25 may contain materials such as tungsten (W) and titanium nitride (TiN).

[0048] The conductor 33 includes wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 may include via wiring, which extends in the Z-axis direction, for example as shown in Figure 2, and has via wiring that connects the word line WL to the circuit 11 provided on the semiconductor substrate 10. The conductor 33 is made of, for example, copper.

[0049] The insulating layer 34 is provided between multiple capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0050] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0051] The semiconductor device 30 is located above the capacitor 20. The field-effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (see Figure 1).

[0052] In the semiconductor device 30, the field-effect transistor 40 is located above the lower electrode 32. More specifically, the oxide semiconductor layer 70 of the field-effect transistor 40 is positioned away from the semiconductor substrate 10, i.e., above, relative to the lower electrode 32.

[0053] The upper electrode 50 is located in a direction away from the semiconductor substrate 10, i.e., above, relative to the oxide semiconductor layer 70. With this configuration, the field-effect transistor 40 is a so-called vertical transistor having a channel that extends in the Z-axis direction (up and down direction) substantially perpendicular to the surface of the semiconductor substrate 10.

[0054] [Manufacturing method for semiconductor devices] The following describes a first example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the first example of the first embodiment).

[0055] (First Embodiment, First Example) Figures 3 to 8 show cross-sectional views of the semiconductor device 30 according to the first example of the first embodiment, as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0056] First, as shown in Figure 3, the insulating layer 45 includes insulating films 45a (an example of the "first insulating layer") and 45b (an example of the "second insulating layer"). The insulating films 45a and 45b and the conductive layer 42 are formed on the semiconductor substrate 10. The conductive layer 42 is provided below the insulating film 45a. The insulating film 45b is provided below the conductive layer 42.

[0057] By etching the insulating films 45a and 45b and the conductive layer 42, a transistor hole TH (an example of a "hole") is formed that penetrates the insulating films 45a and 45b and the conductive layer 42 in the vertical direction, exposing the lower electrode 32. In this example, the upper surface of the lower electrode 32 becomes the bottom of the transistor hole TH. Then, a gate insulating film 43 is formed to cover the transistor hole TH. Specifically, the gate insulating film 43 is formed, for example, by atomic layer deposition (ALD) so as to cover the upper surface of the insulating film 45a and the interior of the transistor hole TH.

[0058] Next, as shown in Figure 4, a gate protective film formation process is performed. In this example, a gate protective film 243 is formed to cover the gate insulating film 43. Specifically, the gate protective film 243 is formed by ALD so as to cover the upper surface of the gate insulating film 43. In this example, the gate protective film 243 is silicon nitride (SiN). The gate protective film 243 may also be titanium oxide (TiO), titanium nitride (TiN), aluminum oxide (Al2O3), gallium oxide (GaO), or zinc oxide (ZnO).

[0059] Next, as shown in Figure 5, the gate protective film is etched back. In this example, a portion of the gate protective film 243 covering the lower electrode 32 is removed by etching using gas ion collisions. Specifically, a portion of the gate insulating film 43 and a portion of the gate protective film 243 are removed by reactive ion etching (RIE). This exposes the upper surface of the insulating film 45a. Also, inside the transistor hole TH where the etching rate decreases, a portion of the gate protective film 243 covering the lower electrode 32 is removed, while a portion of the gate protective film 243 covering the lower electrode 32 remains, exposing the upper surface of the gate insulating film 43. Note that the gate protective film 243 covering the side of the transistor hole TH may be partially removed or damaged by RIE.

[0060] Next, as shown in Figure 6, a bottom removal process is performed. In this example, below the transistor hole TH, a portion of the gate insulating film 43 covering the lower electrode 32 is exposed from the gate protective film 243, and this portion is removed by wet etching or RIE. As a result, the upper surface of the lower electrode 32 is exposed at the bottom of the transistor hole TH. In the case of wet etching, a hydrofluoric acid solution (hereinafter sometimes referred to as HF solution) or a buffered hydrofluoric acid solution (hereinafter sometimes referred to as BHF solution) is used as the etching solution.

[0061] Next, as shown in Figure 7, a gate protective film removal process is performed. In this example, the gate protective film 243 is removed by wet etching. This exposes the gate insulating film 43 inside the transistor hole TH.

[0062] Next, as shown in Figure 8, an oxide semiconductor layer formation process is performed. In this example, an oxide semiconductor layer 70 is formed on the upper surface of the insulating film 45a and inside the transistor hole TH. The oxide semiconductor layer 70 is in contact with the upper surface of the lower electrode 32 exposed at the bottom of the transistor hole TH. As a result, the transistor hole TH is filled with the oxide semiconductor layer 70. Then, the oxide semiconductor layer 70 deposited on top of the insulating film 45a is chemically and mechanically polished, exposing the upper surface of the insulating film 45a. At this time, the upper surface 70a of the oxide semiconductor layer 70 is aligned with the upper surface of the insulating film 45a in the Z-axis direction. The conductive layer 42 surrounds the oxide semiconductor layer 70 via the gate insulating film 43.

[0063] The following describes a second example of the manufacturing method for the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the second example of the first embodiment).

[0064] (Example 2 of the first embodiment) Figures 9 and 10 show cross-sectional views of the semiconductor device 30 according to the second example of the first embodiment, as seen from the cross-section 70YZ which is parallel to the YZ plane and is contained within the transistor hole TH.

[0065] As shown in Figures 9 and 10, the second example of the first embodiment of the manufacturing method differs from the first example of the first embodiment of the manufacturing method shown in Figures 3 to 8 in that the bottom removal process takes longer.

[0066] As shown in Figure 9, in this example, the bottom removal process is performed by wet etching. Since the wet etching process time is longer than in the case shown in Figure 6, a portion of the lower electrode 32 is also removed by wet etching. For example, if the ITO contained in the lower electrode 32 is crystalline, the HF solution or BHF solution penetrates the particle interface, and the grain boundary expands in the lower electrode 32.

[0067] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 7, so a detailed explanation will be omitted.

[0068] Next, as shown in Figure 10, an oxide semiconductor layer formation process is performed. In this example, the oxide semiconductor layer 70 includes an extension 70e that extends downward from the upper end of the lower electrode 32. The extension 70e is formed at the expanded grain boundary in the lower electrode 32. The lower end 70b of the oxide semiconductor layer 70 is located inside the lower electrode 32. Multiple extensions 70e may be provided inside the lower electrode 32.

[0069] The following describes a third example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the third example of the first embodiment).

[0070] (Example 3 of the first embodiment) Figures 11 and 12 show cross-sectional views of the semiconductor device 30 according to the third example of the first embodiment, as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0071] As shown in Figures 11 and 12, the third example of the first embodiment of the manufacturing method differs from the second example of the first embodiment of the manufacturing method shown in Figures 9 and 10 in that the bottom removal process takes longer.

[0072] As shown in Figure 11, in this example, the wet etching process time is longer than in Figure 9, so the grain boundary extension at the lower electrode 32 extends further downward than in Figure 9. Also, since a portion of the lower part of the gate insulating film 43 is removed, the bottom of the transistor hole TH extends along the XY plane. Furthermore, the thickness of the gate protective film 243 is reduced by wet etching.

[0073] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 7, so a detailed explanation will be omitted.

[0074] Next, as shown in Figure 12, an oxide semiconductor layer formation process is performed. In this example, the oxide semiconductor layer 70 includes a first part 70f and a second part 70s.

[0075] The first part 70f is connected to the upper electrode 50 (see Figure 2). The gate insulating film 43 surrounds the side of the first part 70f. The conductive layer 42 faces the first part 70f through the gate insulating film 43. The first part 70f penetrates the insulating film 45a and the conductive layer 42.

[0076] The second part 70s is connected to the lower end of the first part 70f. The second part 70s has a diameter greater than the diameter of the lower end of the first part 70f. More specifically, when the second part 70s is viewed along the vertical direction, the maximum diameter of the second part 70s is greater than the diameter of the lower end of the first part 70f. The second part 70s is connected to the lower electrode 32. In this specification, "diameter" may mean the length in a direction intersecting the vertical direction (for example, the X-axis direction or the Y-axis direction).

[0077] The connection portion 70c between the first part 70f and the second part 70s is provided in the insulating film 45b. More specifically, the position of the connection portion 70c in the Z-axis direction is located between the position in the Z-axis direction of the upper end of the insulating film 45b and the position in the Z-axis direction of the lower end of the insulating film 45b.

[0078] The lower end of the gate insulating film 43 has an outer diameter less than or equal to the diameter of the second portion 70s of the oxide semiconductor layer 70. More specifically, when viewed along the vertical direction of the second portion 70s, the outer diameter of the lower end of the gate insulating film 43 is less than or equal to the maximum diameter of the second portion 70s.

[0079] The lower end 70b of the oxide semiconductor layer 70 is located lower inside the lower electrode 32 than in the case shown in Figure 9. Furthermore, since the oxide semiconductor layer 70 is formed at the bottom of the transistor hole TH which has widened along the XY plane, the contact area between the oxide semiconductor layer 70 and the lower electrode 32 is increased. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32.

[0080] The following describes a fourth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fourth example of the first embodiment).

[0081] (First Embodiment, Fourth Example) Figures 13 and 14 show cross-sectional views of the semiconductor device 30 according to the fourth example of the first embodiment, as seen from the cross-section 70YZ which is parallel to the YZ plane and is contained within the transistor hole TH.

[0082] As shown in Figures 13 and 14, the fourth example of the first embodiment of the manufacturing method differs from the third example of the first embodiment of the manufacturing method shown in Figures 11 and 12 in that the bottom removal process takes longer.

[0083] As shown in Figure 13, in this example, the wet etching process time is longer than in Figure 11, so the grain boundary expansion at the lower electrode 32 penetrates the lower electrode 32 along the vertical direction. Furthermore, a portion of the conductor 21 is also removed. In addition, the bottom of the transistor hole TH expands along the XY plane more than in Figure 11. Also, the thickness of the gate protective film 243 becomes thinner due to wet etching than in Figure 11.

[0084] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 7, so a detailed explanation will be omitted.

[0085] Next, as shown in Figure 14, an oxide semiconductor layer formation process is performed. In this example, the extension 70e of the oxide semiconductor layer 70 penetrates the lower electrode 32 along the vertical direction. The lower end 70b of the oxide semiconductor layer 70 is located below the lower electrode 32. Furthermore, since the oxide semiconductor layer 70 is formed at the bottom of the transistor hole TH which is widened along the XY plane, the contact area between the oxide semiconductor layer 70 and the lower electrode 32 is increased. This makes it possible to further reduce the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32.

[0086] The following describes a fifth example of the manufacturing method for the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fifth example of the first embodiment).

[0087] (Example 5 of the first embodiment) Figs. 15 to 20 show cross-sectional views of the semiconductor device 30 according to the fifth example of the first embodiment, taken in a cross-section 70YZ parallel to the YZ plane and including the transistor hole TH.

[0088] As shown in Figs. 15 to 20, the fifth example of the first embodiment of the manufacturing method is different from the first example of the first embodiment of the manufacturing method shown in Figs. 3 to 8 in that a stopper film 501 (an example of the "first layer" and the "first insulating film") is provided above the lower electrode 32.

[0089] The stopper film 501 is provided below the insulating film 45b. The stopper film 501 contains, for example, aluminum and oxygen. In this example, the stopper film 501 is an oxide of aluminum (AlO x )

[0090] Note that the stopper film 501 may be configured to contain at least one of the elements silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium, magnesium, zinc, gallium, tin, antimony, tellurium, lead, bismuth, thallium, scandium, titanium, molybdenum, and tungsten, and oxygen. The etching rate of the stopper film 501 is greater than the etching rate of the insulating film 45b.

[0091] The stopper film 501 suppresses damage to the ITO contained in the lower electrode 32 by a cleaning agent, for example, when removing residues inside the transistor hole TH by dry or wet means after the transistor hole TH is formed.

[0092] Also, the stopper film 501 suppresses the generation of whiskers such as tungsten by preventing the lower electrode 32 containing ITO from being exposed when, for example, the gate insulating film 43 is formed.

[0093] First, as shown in Figure 15, a transistor hole TH is formed. In this example, the upper surface of the stopper film 501 becomes the bottom of the transistor hole TH. Then, a gate insulating film 43 is formed, for example, by ALD, so as to cover the upper surface of the insulating film 45a and the inside of the transistor hole TH.

[0094] Next, as shown in Figure 16, a gate protection film formation process similar to the process shown in Figure 4 is performed.

[0095] Next, as shown in Figure 17, a gate protection film etch-back process similar to the process shown in Figure 5 is performed. In this example, since a stopper film 501 is provided, a portion of the lower part of the gate protection film 243 and a portion of the lower part of the gate insulating film 43 are removed by RIE so that the upper surface of the stopper film 501 is exposed.

[0096] Next, as shown in Figure 18, a bottom removal process similar to the process shown in Figure 6 is performed. In this example, a portion of the stopper film 501 is removed through the bottom of the transistor hole TH by wet etching using an HF solution or a BHF solution. As a result, a hole 501a that penetrates vertically is formed in the stopper film 501. The upper surface of the lower electrode 32 is exposed through the hole 501a.

[0097] Next, as shown in Figure 19, a gate protective film removal process similar to the process shown in Figure 7 is performed.

[0098] Next, as shown in Figure 20, an oxide semiconductor layer formation process similar to the process shown in Figure 8 is performed.

[0099] The following describes a sixth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the sixth example of the first embodiment).

[0100] (Example 6 of the first embodiment) Figures 21 and 22 show cross-sectional views of the semiconductor device 30 according to the sixth example of the first embodiment, as seen from the cross-section 70YZ which is parallel to the YZ plane and is contained within the transistor hole TH.

[0101] As shown in Figures 21 and 22, the sixth example of the first embodiment of the manufacturing method differs from the fifth example of the first embodiment of the manufacturing method shown in Figures 15 to 20 in that the bottom removal process takes longer.

[0102] As shown in Figure 21, in this example, the bottom removal process is performed by wet etching. Because the wet etching process time is longer than in the case shown in Figure 18, a portion of the lower electrode 32 is also removed. For example, if the lower electrode 32 is crystalline, the HF solution or BHF solution penetrates the particle interface, and the grain boundary expands at the lower electrode 32.

[0103] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 19, so a detailed explanation will be omitted.

[0104] Next, as shown in Figure 22, an oxide semiconductor layer formation process is performed. In this example, the lower end 70b of the oxide semiconductor layer 70 is located inside the lower electrode 32.

[0105] The following describes a seventh example of the manufacturing method for the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the seventh example of the first embodiment).

[0106] (Example 7 of the first embodiment) Figures 23 and 24 show cross-sectional views of the semiconductor device 30 according to the seventh example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0107] As shown in Figures 23 and 24, the seventh example of the first embodiment of the manufacturing method differs from the sixth example of the first embodiment of the manufacturing method shown in Figures 21 and 22 in that the bottom removal process takes longer.

[0108] As shown in Figure 23, in this example, the wet etching process time is longer than in Figure 21, so a portion of the lower part of the gate insulating film 43 is removed. The holes 501a in the stopper film 501 expand in the directions perpendicular to the vertical direction, i.e., in the X-axis and Y-axis directions. In addition, the grain boundary spread at the lower electrode 32 expands along the XY plane and extends downwards more than in Figure 21.

[0109] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 19, so a detailed explanation will be omitted.

[0110] Next, as shown in Figure 24, an oxide semiconductor layer formation process is performed. In this example, the lower end 70b of the oxide semiconductor layer 70 is located lower inside the lower electrode 32 than in the case shown in Figure 22. Furthermore, since the oxide semiconductor layer 70 is formed in the hole 501a which is enlarged in a direction perpendicular to the vertical direction, the contact area between the oxide semiconductor layer 70 and the lower electrode 32 is increased. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32.

[0111] The following describes an eighth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the eighth example of the first embodiment).

[0112] (Example 8 of the first embodiment) Figures 25 to 27 show cross-sectional views of the semiconductor device 30 according to the eighth example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0113] As shown in Figures 25 to 27, the seventh example of the first embodiment of the manufacturing method differs from the fifth example of the first embodiment of the manufacturing method shown in Figures 15 to 20 in that alkali treatment and diameter expansion treatment are added between the bottom removal treatment and the gate protective film removal treatment.

[0114] As shown in Figure 25, alkaline treatment is performed after the bottom removal process. In this example, a portion of the stopper film 501 is removed by wet etching using an alkaline chemical solution. As a result, the bottom of the transistor hole TH expands along the XY plane. The hole 501a of the stopper film 501 expands in a direction perpendicular to the vertical direction.

[0115] Next, as shown in Figure 26, a diameter expansion process is performed. In this example, a portion of the lower part of the gate insulating film 43, a portion of the stopper film 501, and a portion of the lower electrode 32 are removed by wet etching using an HF solution or a BHF solution. As a result, the bottom of the transistor hole TH expands along the XY plane. The holes 501a in the stopper film 501 expand in a direction perpendicular to the vertical direction. In addition, the HF solution or BHF solution penetrates the particle interface, and the grain boundary expands at the lower electrode 32.

[0116] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 19, so a detailed explanation will be omitted.

[0117] Next, as shown in Figure 27, an oxide semiconductor layer formation process is performed. In this example, the lower end 70b of the oxide semiconductor layer 70 is located inside the lower electrode 32.

[0118] The following describes a ninth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the ninth example of the first embodiment).

[0119] (First Embodiment, 9th Example) Figures 28 to 30 show cross-sectional views of the semiconductor device 30 according to the ninth example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0120] As shown in Figures 28 to 30, the ninth example of the first embodiment of the manufacturing method differs from the eighth example of the first embodiment of the manufacturing method shown in Figures 25 to 27 in that the alkali treatment and diameter expansion treatment times are longer.

[0121] As shown in Figure 28, an alkaline treatment is performed after the bottom removal process. In this example, since the alkaline treatment time is longer than in the case shown in Figure 25, the holes 501a of the stopper film 501 expand in a direction perpendicular to the vertical direction.

[0122] Next, as shown in Figure 29, a diameter expansion process is performed. In this example, since the processing time for the diameter expansion process is longer than in the case shown in Figure 26, a portion of the lower part of the gate insulating film 43 is removed more than in the case shown in Figure 26. The holes 501a of the stopper film 501 expand further in a direction perpendicular to the vertical direction. In addition, the spread of grain boundaries in the lower electrode 32 expands along the XY plane and extends downwards more than in the case shown in Figure 26.

[0123] The gate protective film removal process following the bottom removal process is the same as the process shown in Figure 19, so a detailed explanation will be omitted.

[0124] Next, as shown in Figure 30, an oxide semiconductor layer formation process is performed. In this example, the lower end 70b of the oxide semiconductor layer 70 is located lower inside the lower electrode 32 than in the case shown in Figure 27.

[0125] The following describes a tenth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the tenth example of the first embodiment).

[0126] (Example 10 of the first embodiment) Figures 31 to 36 show cross-sectional views of the semiconductor device 30 according to the 10th example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0127] As shown in Figures 31 to 36, the tenth example of the first embodiment of the manufacturing method differs from the fifth example of the first embodiment of the manufacturing method shown in Figures 15 to 20 in that a stopper film 601 (an example of the "first layer" and "first insulating film") is provided above the lower electrode 32 instead of the stopper film 501.

[0128] The stopper film 601 contains, for example, silicon and nitrogen. In this example, the stopper film 601 is silicon nitride (SiN). Alternatively, the stopper film 601 may contain silicon, carbon, and nitrogen, for example, SiCN. Furthermore, the stopper film 601 may contain silicon, oxygen, and nitrogen, for example, SiON.

[0129] First, as shown in Figure 31, transistor holes TH and gate insulating film 43 are formed in the same manner as shown in Figure 3.

[0130] Next, as shown in Figure 32, a gate protection film formation process similar to the process shown in Figure 4 is performed.

[0131] Next, as shown in Figure 33, a gate protection film etch-back process similar to the process shown in Figure 5 is performed. In this example, since a stopper film 601 is provided, a portion of the gate protection film 243 and a portion of the gate insulating film 43 are removed by RIE so that the upper surface of the stopper film 601 is exposed.

[0132] Next, as shown in Figure 34, a bottom removal process similar to the process shown in Figure 6 is performed. In this example, a portion of the stopper film 601 is removed through the bottom of the transistor hole TH by wet etching using an HF solution or a BHF solution, and a hole 601a is formed in the stopper film 601. In this example, the hole 601a does not penetrate in the vertical direction.

[0133] Next, as shown in Figure 35, a gate protective film peeling process similar to the process shown in Figure 7 is performed. In this example, since the gate protective film 243 and the stopper film 601 are made of SiN, the gate protective film 243 is peeled off, and the hole 601a of the stopper film 601 expands in a direction perpendicular to the vertical direction and penetrates in the vertical direction. As a result, the upper surface of the lower electrode 32 is exposed through the hole 601a.

[0134] Next, as shown in Figure 36, an oxide semiconductor layer formation process similar to the process shown in Figure 8 is performed.

[0135] The following describes an eleventh example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the eleventh example of the first embodiment).

[0136] (First Embodiment, 11th Example) Figures 37 to 39 show cross-sectional views of the semiconductor device 30 according to the 11th example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0137] As shown in Figures 37 to 39, the 11th example of the first embodiment of the manufacturing method differs from the 10th example of the first embodiment of the manufacturing method shown in Figures 34 to 36 in that the bottom removal process takes longer.

[0138] As shown in Figure 37, a bottom removal process similar to the process shown in Figure 34 is performed. In this example, since the wet etching process time is longer than in Figure 34, a portion of the lower part of the gate insulating film 43 is removed. The holes 601a in the stopper film 601 expand in a direction perpendicular to the vertical direction, and the bottom becomes deeper.

[0139] Next, as shown in Figure 38, a gate protective film removal process similar to the process shown in Figure 35 is performed. In this example, since the wet etching process time is longer than in the case shown in Figure 35, the holes 601a in the stopper film 601 expand in a direction perpendicular to the vertical direction and penetrate through in the vertical direction more than in the case shown in Figure 35.

[0140] Next, as shown in Figure 39, an oxide semiconductor layer formation process similar to the process shown in Figure 8 is performed.

[0141] The following describes a twelfth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the twelfth example of the first embodiment).

[0142] (First Embodiment, 12th Example) Figures 40 to 42 show cross-sectional views of the semiconductor device 30 according to the 12th example of the first embodiment, as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0143] As shown in Figures 40 to 42, the 12th example of the first embodiment of the manufacturing method differs from the 11th example of the first embodiment of the manufacturing method shown in Figures 37 to 39 in that the bottom removal process takes longer.

[0144] As shown in Figure 40, a bottom removal process similar to the process shown in Figure 37 is performed. In this example, since the wet etching process time is longer than in Figure 37, a portion of the lower part of the gate insulating film 43 is removed more than in Figure 37. The holes 601a in the stopper film 601 expand in diameter further in the direction perpendicular to the vertical direction, and the bottom becomes deeper.

[0145] Next, as shown in Figure 41, a gate protective film removal process similar to the process shown in Figure 38 is performed. In this example, since the wet etching process time is longer than in Figure 38, the holes 601a in the stopper film 601 expand in a direction perpendicular to the vertical direction and penetrate through in the vertical direction more than in Figure 38.

[0146] Next, as shown in Figure 42, an oxide semiconductor layer formation process similar to the process shown in Figure 8 is performed.

[0147] The following describes a thirteenth example of a method for manufacturing the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the thirteenth example of the first embodiment).

[0148] (First Embodiment, 13th Example) Figures 43 to 46 show cross-sectional views of the semiconductor device 30 according to the 13th example of the first embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0149] As shown in Figures 43 to 46, the 13th example of the first embodiment of the manufacturing method differs from the first example of the first embodiment of the manufacturing method shown in Figures 4, 6, 7, and 8 in that the gate protective film 243 is formed by plasma CVD (Chemical Vapor Deposition).

[0150] As shown in Figure 43, a gate protection film formation process is performed. In this example, a gate protection film 243 is formed by plasma CVD so as to cover the upper surface of the gate insulating film 43. In this example, the gate protection film 243 is made of SiN.

[0151] Unlike the ALD deposition shown in Figure 4, the thickness of the gate protection film 243 in the transistor hole TH may not be uniform in plasma CVD deposition. In this example, the thickness of the gate protection film 243 decreases as it approaches the bottom from the opening of the transistor hole TH. The position of the lower end of the gate protection film 243 in the Z-axis direction is below the conductive layer 42, but does not reach the bottom of the transistor hole TH. Therefore, the gate protection film 243 is not formed at the bottom of the transistor hole TH. Consequently, the gate protection film etch-back treatment is not performed.

[0152] Furthermore, the gate protection film 243 may be amorphous silicon, germanium, titanium oxide (TiO), titanium nitride (TiN), aluminum oxide (Al2O3), gallium oxide (GaO), zinc oxide (ZnO), or a carbon film.

[0153] Next, as shown in Figure 44, a bottom-removal process similar to the process shown in Figure 6 is performed.

[0154] Next, as shown in Figure 45, a gate protective film removal process similar to the process shown in Figure 7 is performed.

[0155] Next, as shown in Figure 46, an oxide semiconductor layer formation process similar to the process shown in Figure 8 is performed.

[0156] [assignment] The following describes a method for manufacturing a semiconductor device 30 according to a comparative example.

[0157] Figures 47 and 48 show cross-sectional views of a comparative example semiconductor device 30, viewed from a cross-section 70YZ parallel to the YZ plane and contained within the transistor hole TH.

[0158] As shown in Figures 47 and 48, in the comparative example of the manufacturing method, the gate protective film 243 is not formed.

[0159] Therefore, as shown in Figure 47, when the bottom-cutting process is performed after the gate insulating film 43 is formed in the transistor hole TH, ions colliding with the gate insulating film 43 due to RIE may enter the gate insulating film 43 as impurities. In addition, since the gate insulating film 43 is subjected to etching, the thickness of the gate insulating film 43 may decrease or scratches may be formed on the film.

[0160] Next, as shown in Figure 48, an oxide semiconductor layer formation process is performed. In the comparative example, when the semiconductor device 30 is operated for a long period of time, the electrical breakdown voltage of the gate insulating film 43 may decrease due to impurities in the gate insulating film 43 or physical damage such as thin film thickness or scratches.

[0161] [Effects of this embodiment on the problem] As shown in Figures 6, 18, and 34, during the bottom removal process, the gate insulating film 43 is physically protected by the gate protective film 243.

[0162] This prevents impurities from entering the gate insulating film 43 and prevents the gate insulating film 43 from being physically damaged, thereby suppressing a decrease in the breakdown voltage of the gate insulating film 43 and enabling the semiconductor device 30 to operate stably for a long period of time.

[0163] [Second Embodiment] A method for manufacturing the semiconductor device 30 according to the second embodiment will be described. In the second embodiment and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects and advantages due to similar configurations will not be mentioned sequentially for each embodiment.

[0164] The method for manufacturing the semiconductor device 30 according to the second embodiment differs from the method for manufacturing the semiconductor device 30 according to the first embodiment in that it selectively adsorbs a self-assembled monolayer (SAM) (an example of a "monolayer").

[0165] [Manufacturing method for semiconductor devices] The following describes a first example of a method for manufacturing the semiconductor device 30 according to the second embodiment (hereinafter sometimes referred to as the first example of the second embodiment).

[0166] (Second Embodiment, First Example) Figures 49 to 55 show cross-sectional views of the semiconductor device 30 according to the first example of the second embodiment, as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the transistor hole TH.

[0167] First, as shown in Figure 49, a transistor hole TH is formed. In this example, the upper surface of the lower electrode 32 becomes the bottom of the transistor hole TH. Then, a sacrificial gate insulating film 143 is formed, for example, by ALD, so as to cover the upper surface of the insulating film 45a and the interior of the transistor hole TH. The composition of the sacrificial gate insulating film 143 is, for example, the same as the composition of the gate insulating film 43. That is, the sacrificial gate insulating film 143 is silicon oxide. Note that the composition of the sacrificial gate insulating film 143 may differ from the composition of the gate insulating film 43.

[0168] Next, as shown in Figure 50, a dry etch back process is performed. In this example, a portion of the sacrificial gate insulating film 143 covering the lower electrode 32 is removed, exposing the upper surface of the lower electrode 32. Specifically, RIE removes a portion of the sacrificial gate insulating film 143 covering the lower electrode 32. This exposes the upper surface of the insulating film 45a. Also, the lower electrode 32 is exposed at the bottom of the transistor hole TH. Note that the sacrificial gate insulating film 143 may be subjected to impurities or physical damage due to RIE.

[0169] Next, as shown in Figure 51, SAM treatment is performed on the metal oxide. In this example, SAM 151 is formed on the upper surface of the exposed lower electrode 32. Specifically, at the bottom of the transistor hole TH, SAM 151 is selectively adsorbed onto the upper surface of the lower electrode 32 that is exposed from the sacrificial gate insulating film 143. SAM 151 does not adsorb in the area where the lower end of the sacrificial gate insulating film 143 and the lower electrode 32 are in contact (hereinafter sometimes referred to as the non-adsorbed area 181) due to a physical obstruction. Details of the process for selectively adsorbing SAM 151 onto the metal oxide will be described later.

[0170] Next, as shown in Figure 52, a wet etching process is performed. In this example, the sacrificial gate insulating film 143 is removed by wet etching using an HF solution or a BHF solution. At the bottom of the transistor hole TH, a portion of the lower electrode 32 covered by the SAM 151 is not removed.

[0171] On the other hand, the non-adsorbent portion 181 at the bottom of the transistor hole TH comes into contact with the HF solution or BHF solution after the sacrificial gate insulating film 143 is removed. As a result, a removal portion 182 is formed on the lower electrode 32, which includes a space extending downward from the non-adsorbent portion 181.

[0172] For example, if the ITO contained in the lower electrode 32 is crystalline, the removal portion 182 is an extended grain boundary in the lower electrode 32 and has a crack shape. If the ITO crystals are arranged in a pillar-like manner along a direction intersecting the vertical direction, dissolution reduces the size of each pillar-like crystal, and the gaps formed between the crystals become the removal portion 182. Also, for example, if the ITO contained in the lower electrode 32 is amorphous, the removal portion 182 becomes a rounded indentation.

[0173] Next, as shown in Figure 53, a gate insulating film formation process is performed. In this example, the gate insulating film 43 is formed on the inner surface of the transistor hole TH that is not covered by the SAM 151. Specifically, the gate insulating film 43 is formed, for example, by ALD, so as to cover the upper surface of the insulating film 45a, the interior of the transistor hole TH excluding the portion covered by the SAM 151, and the space included in the removal portion 182. The gate insulating film 43 is connected to the lower electrode 32. Hereinafter, the gate insulating film 43 formed in the space included in the removal portion 182 may be referred to as the extended insulating film 43a. The extended insulating film 43a extends downward at the lower electrode 32.

[0174] Next, as shown in Figure 54, a SAM removal treatment is performed. In this example, SAM151 is removed without etching using gas ion collisions. Specifically, SAM151 is oxidized by an ashing treatment in which the material is heated to about 200°C in an oxygen atmosphere. This removes SAM151. Alternatively, SAM151 may be removed by thermal decomposition through a heat treatment in which the material is heated to 400°C or higher in a nitrogen atmosphere. Alternatively, SAM151 may be removed by hydrolysis through treatment with a strongly acidic or strongly basic chemical solution.

[0175] Next, as shown in Figure 55, an oxide semiconductor layer formation process is performed. In this example, an oxide semiconductor layer 70 is formed on the upper surface of the gate insulating film 43 and on the lower electrode 32 exposed at the bottom of the transistor hole TH. The oxide semiconductor layer 70 is in contact with the upper surface of the lower electrode 32 exposed at the bottom of the transistor hole TH. As a result, the transistor hole TH is filled with the oxide semiconductor layer 70. Then, the gate insulating film 43 and the oxide semiconductor layer 70 deposited above the insulating film 45a are chemically and mechanically polished, exposing the upper surface of the insulating film 45a. At this time, the upper surface 70a of the oxide semiconductor layer 70 is aligned with the upper surface of the insulating film 45a in the Z-axis direction.

[0176] The following describes in detail the process for selectively adsorbing SAM151 onto metal oxides, as shown in Figure 51.

[0177] Figure 56 shows an example of a process for selectively adsorbing SAM 151 onto the lower electrode 32 when the sacrificial gate insulating film 143 and the lower electrode 32 are exposed.

[0178] As shown in Figure 56, first, SAM151 is supplied to the sacrificial gate insulating film 143 and the lower electrode 32. SAM151 may be a liquid or a gas. SAM151 is, for example, a phosphonic acid-based compound, a phosphate ester-based compound, or an amine-based compound.

[0179] Phosphonic acid compounds, for example, are those in which phosphonic acid is bonded to an alkyl group having 3 to 30 carbon atoms. However, the alkyl group is not limited to partially linear hydrocarbons; it may also have a structure in which it is partially substituted with other elements.

[0180] Phosphate ester compounds, for example, are those in which phosphate is bonded to an alkyl group having an ester bond and 3 to 30 carbon atoms. However, the alkyl group is not limited to partially linear hydrocarbons, and may also have a structure in which it is partially substituted with other elements.

[0181] Amine compounds are, for example, compounds having an alkyl group with 3 to 30 carbon atoms that has an amine bond. However, the alkyl group is not limited to partially linear hydrocarbons, and may have a structure in which it is partially substituted with other elements.

[0182] SAM151 selectively adheres to the lower electrode 32 without adsorbing to the sacrificial gate insulating film 143. As a result, the surface of the lower electrode 32 is not exposed.

[0183] Figure 57 shows another example of a process for selectively adsorbing SAM 151 onto the lower electrode 32 when the sacrificial gate insulating film 143 and the lower electrode 32 are exposed.

[0184] As shown in Figure 57, first, SAM152 is supplied to the sacrificial gate insulating film 143 and the lower electrode 32. SAM152 may be a liquid or a gas. SAM152 is, for example, an organosilane compound or an alcohol compound.

[0185] Organosilane compounds are, for example, compounds having an alkyl group with 3 to 30 carbon atoms and a Si-C bond. However, the alkyl group is not limited to partially linear hydrocarbons; it may also have a structure in which it is partially substituted with other elements.

[0186] Alcohol-based compounds are, for example, compounds having an alkyl group with 5 to 30 carbon atoms that contains an alcohol group. However, the alkyl group is not limited to partially linear hydrocarbons; it may also have a structure in which it is partially substituted with other elements.

[0187] SAM152 selectively adheres to the sacrificial gate insulating film 143 without adsorbing to the lower electrode 32. As a result, the surface of the sacrificial gate insulating film 143 is not exposed.

[0188] Next, SAM151 is supplied. In this example, SAM151 is, for example, a phosphonic acid compound, a phosphate ester compound, an amine compound, or an organosilane compound. Since the surface of the sacrificial gate insulating film 143 is not exposed, SAM151 selectively adsorbs onto the lower electrode 32. For example, the adsorption force of SAM152 to the sacrificial gate insulating film 143 is weaker than the adsorption force of SAM151 to the lower electrode 32.

[0189] Next, the temperature of the sacrificial gate insulating film 143 and the lower electrode 32 is increased by heat treatment. As a result, SAM 152, which has a weak adsorption force to the sacrificial gate insulating film 143, is removed from the surface of the sacrificial gate insulating film 143. On the other hand, SAM 151 remains on the surface of the lower electrode 32.

[0190] Figure 58 is a diagram illustrating the effect of the extended insulating film 43a. As shown in Figure 58, the extended insulating film 43a is formed on the lower electrode 32, extending downward from the lower end of a portion of the gate insulating film 43 that surrounds the oxide semiconductor layer 70 (see Figure 53).

[0191] Since the extended insulating film 43a is continuous with the gate insulating film 43 above the lower electrode 32, it divides the lower electrode 32 into the lower electrode 32i and the lower electrode 32o. Here, the extended insulating film 43a is not located between the oxide semiconductor layer 70 and the lower electrode 32i. On the other hand, the extended insulating film 43a is located between the oxide semiconductor layer 70 and the lower electrode 32o.

[0192] The carriers in IGZO contained in the oxide semiconductor layer 70 are oxygen vacancies (hereinafter sometimes referred to as Vo). The concentration of Vo in the oxide semiconductor layer 70 is approximately 10 17 ~10 18 atm / cm 3 On the other hand, the concentration of Vo in the ITO contained in the lower electrode 32 is approximately 10 19 ~10 21 atm / cm 3 That is the case.

[0193] Since a change in the concentration of Vo in the oxide semiconductor layer 70 alters the properties of the semiconductor device 30, we want to suppress the movement of Vo from the lower electrode 32 to the oxide semiconductor layer 70.

[0194] If the contact area between the oxide semiconductor layer 70 and the lower electrode 32 is reduced, the movement of Vo from the lower electrode 32 to the oxide semiconductor layer 70 can be suppressed. However, this increases the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32, which is undesirable.

[0195] In contrast, the semiconductor device 30 according to the first example of the second embodiment is configured to have an extended insulating film 43a, thereby suppressing the movement of Vo from the lower electrode 32o to the oxide semiconductor layer 70. This makes it possible to suppress changes in the characteristics of the semiconductor device 30.

[0196] Furthermore, by having the extended insulating film 43a extend downward from a lower end of a portion of the gate insulating film 43 surrounding the oxide semiconductor layer 70, the extended insulating film 43a can be provided without reducing the contact area between the oxide semiconductor layer 70 and the lower electrode 32. This makes it possible to suppress an increase in the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32.

[0197] The extended insulating film 43a is formed in the space included in the removal portion 182 that extends downward from the non-adsorption portion 181, which is the connection portion between the sacrificial gate insulating film 143 and the lower electrode 32. The gate insulating film 43 is provided in the position where the sacrificial gate insulating film 143 was provided. Therefore, even if the formation position of the transistor hole TH deviates from the design value, causing the formation position of the sacrificial gate insulating film 143 to deviate from the design value, the extended insulating film 43a and the gate insulating film 43 are formed with the same deviation, i.e., they are continuous, thus achieving the above effect.

[0198] The following describes a second example of a method for manufacturing the semiconductor device 30 according to the second embodiment (hereinafter sometimes referred to as the second example of the second embodiment).

[0199] (Example 2 of the first embodiment) Figures 59 to 66 show cross-sectional views of the semiconductor device 30 according to the second example of the second embodiment, as viewed from the cross-section 70YZ, which is parallel to the YZ plane and is included in the transistor hole TH.

[0200] As shown in Figures 59 to 66, the second example of the second embodiment of the manufacturing method differs from the first example of the second embodiment of the manufacturing method shown in Figures 49 to 55 in that a stopper membrane 501 is provided above the lower electrode 32.

[0201] First, as shown in Figure 59, a transistor hole TH is formed. In this example, the upper surface of the stopper film 501 becomes the bottom of the transistor hole TH. Then, a sacrificial gate insulating film 143 is formed, for example, by ALD, so as to cover the upper surface of the insulating film 45a and the interior of the transistor hole TH.

[0202] Next, as shown in Figure 60, a dry etch-back process similar to the process shown in Figure 50 is performed.

[0203] Next, as shown in Figure 61, the same SAM treatment as shown in Figure 51 is performed on the metal oxide.

[0204] Next, as shown in Figure 62, a wet etch-back process similar to the process shown in Figure 52 is performed.

[0205] Next, as shown in Figure 63, a gate insulating film formation process similar to the process shown in Figure 53 is performed.

[0206] Next, as shown in Figure 64, a SAM removal process similar to the process shown in Figure 54 is performed.

[0207] Next, as shown in Figure 65, an alkaline treatment using hot water is performed. In this example, a portion of the stopper film 501 is removed through the bottom of the transistor hole TH by wet etching using alkaline hot water. As a result, a hole 501a that penetrates vertically is formed in the stopper film 501. The upper surface of the lower electrode 32 is exposed through the hole 501a.

[0208] Next, as shown in FIG. 66, an oxide semiconductor layer formation process similar to the process shown in FIG. 55 is performed.

[0209] Note that a configuration in which a stopper film 601 is provided instead of the stopper film 501 may also be employed.

[0210] FIG. 67 is a diagram showing an example of a process of selectively adsorbing the SAM 155 to the stopper film 601 when the sacrificial gate insulating film 143 and the stopper film 601 are exposed.

[0211] As shown in FIG. 67, first, the SAM 155 is supplied to the sacrificial gate insulating film 143 and the stopper film 601. The SAM 155 may be a liquid or a gas. The SAM 155 is, for example, an alkyl bromide-based compound or an unsaturated hydrocarbon-based compound.

[0212] The alkyl bromide-based compound is, for example, Br-R. Here, R is a compound having an alkyl group with 5 to 30 carbon atoms, but the alkyl group is not limited to a linear hydrocarbon partially, and may have a structure partially substituted with other elements.

[0213] The unsaturated hydrocarbon-based compound is, for example, a compound having a C-C double bond or triple bond classified as an alkene or alkyne with 5 to 30 carbon atoms. The compound mainly consists of carbon and hydrogen, but may have an ether bond in addition to the C-C double bond or triple bond, or a part of hydrogen may be substituted with fluorine, chlorine, bromine or iodine.

[0214] The SAM 155 selectively adsorbs to the stopper film 601 without adsorbing to the sacrificial gate insulating film 143. As a result, the surface of the stopper film 601 is no longer exposed.

[0215] Hereinafter, a third example of a method for manufacturing the semiconductor device 30 according to the second embodiment (hereinafter, may be referred to as the third example of the second embodiment) will be described.

[0216] (Second Embodiment, Third Example) Figures 68 to 75 are cross-sections 70YZ parallel to the YZ plane, showing cross-sectional views of the semiconductor device 30 according to the third example of the second embodiment as seen in the cross-section 70YZ included in the transistor hole TH.

[0217] As shown in Figures 68 to 75, the third example of the second embodiment of the manufacturing method is different from the first example of the second embodiment of the manufacturing method shown in Figures 49 to 55 in that the sacrificial gate insulating film 143 is not replaced with the gate insulating film 43.

[0218] First, as shown in Figure 68, a transistor hole TH is formed. In this example, the upper surface of the lower electrode 32 becomes the bottom of the transistor hole TH. Then, for example, a gate insulating film 43b is formed by ALD so as to cover the upper surface of the insulating film 45a and the inside of the transistor hole TH. The gate insulating film 43b contains, for example, silicon and nitrogen. In this example, the gate insulating film 43b is SiN. Note that a stopper film 501, 601, or 701 may be provided between the lower electrode 32 and the insulating film 45b. In this case, the upper surface of the stopper film 501, 601, or 701 becomes the bottom of the transistor hole TH.

[0219] Next, as shown in Figure 69, a gate insulating film forming process is performed. In this example, a gate insulating film 43c is formed by ALD so as to cover the upper surface of the gate insulating film 43b. In this example, the gate insulating film 43c is SiO.

[0220] Next, as shown in Figure 70, a sacrificial film forming process is performed. In this example, a sacrificial film 80 is formed by ALD so as to cover the upper surface of the gate insulating film 43c and fill the transistor hole TH. In this example, the sacrificial film 80 is TiN. Note that the sacrificial film 80 may be zinc oxide (ZnO), aluminum oxide (Al2O3), IGZO, titanium nitride (TiN), molybdenum (Mo), or the like.[[ID=二十二]]

[0221] Next, as shown in Figure 71, a sacrificial film etch-back process is performed. In this example, a portion of the sacrificial film 80 is removed by wet etching. As a result, the sacrificial film 80 remains below the transistor hole TH. Then, the gate insulating film 43c is exposed on the side of the transistor hole TH.

[0222] Next, as shown in Figure 72, SAM treatment is performed on silicon oxide. In this example, SAM 153 is selectively adsorbed onto the exposed surface of the gate insulating film 43c above the gate insulating film 43c and inside the transistor hole TH. SAM 153 is not adsorbed onto the sacrificial film 80 located below the transistor hole TH. SAM 153 is, for example, an organosilane compound or an alcohol compound.

[0223] Next, as shown in Figure 73, a bottom removal process is performed. In this example, the sacrificial film 80 remaining below the transistor hole TH is removed by wet etching using heated hydrogen peroxide (H2O2), ozone, a solution in which carbon dioxide is dissolved with ozone (hereinafter sometimes referred to as O3W), or a solution in which an acidic chemical is added to O3W, such as ozone-added hydrochloric acid or a diluted HF (dolute hydrogen fluoride) solution (hereinafter sometimes referred to as DHF solution). Then, a portion of the gate insulating film 43c and a portion of the gate insulating film 43b covering the bottom of the transistor hole TH, which are exposed by the removal of the sacrificial film 80, are removed. As a result, the upper surface of the lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0224] Next, as shown in Figure 74, a SAM removal process is performed. In this example, SAM153 is oxidized by ashing or oxidation using oxygen. This removes SAM153.

[0225] Next, as shown in Figure 75, an oxide semiconductor layer formation process similar to the process shown in Figure 66 is performed. In this example, voids 70i are formed inside the oxide semiconductor layer 70 where the oxide semiconductor layer 70 is not filled.

[0226] The following describes a fourth example of a method for manufacturing the semiconductor device 30 according to the second embodiment (hereinafter sometimes referred to as the fourth example of the second embodiment).

[0227] (Second Embodiment, Fourth Example) Figures 76 to 79 show cross-sectional views of the semiconductor device 30 according to the fourth example of the second embodiment, as seen from the cross-section 70YZ which is parallel to the YZ plane and is included in the transistor hole TH.

[0228] As shown in Figures 76 to 79, the fourth example of the second embodiment of the manufacturing method differs from the third example of the second embodiment of the manufacturing method shown in Figures 68 to 75 in that the method of forming the sacrificial film is different.

[0229] First, although not shown in the diagram, the gate insulating film 43b (see Figure 68) and the gate insulating film 43c (see Figure 69) are formed.

[0230] Next, as shown in Figure 76, SAM treatment is performed on silicon oxide. In this example, SAM153a is selectively adsorbed onto the exposed surface of the gate insulating film 43c above the gate insulating film 43c and inside the transistor hole TH. SAM153a is, for example, an organosilane compound or an alcohol compound. In this example, the composition of SAM153a is the same as the composition of SAM153 shown in Figure 72.

[0231] Next, as shown in Figure 77, a precursor coating process is performed. In this example, the precursor 81 is coated into the interior of the transistor hole TH by the sol-gel method. The precursor 81 is, for example, an alcohol solution containing an organometallic compound. Specifically, the precursor 81 is a methanol or ethanol solution containing zinc acetate, or an aqueous solution thereof.

[0232] Next, as shown in FIG. 78, a SAM removal process and a solvent removal process are performed. In this example, by heating the SAM 153 and the precursor 81 to 200° C. or higher, the alcohol solution contained in the SAM 153 and the precursor 81 is removed. Then, the organometallic compound contained in the precursor 81 changes into a sacrificial film 82. The sacrificial film 82 is, for example, a metal oxide or hydroxide.

[0233] Next, as shown in FIG. 79, a SAM treatment for silicon oxide similar to the treatment shown in FIG. 72 is performed. In this example, the SAM 153 is selectively adsorbed on the exposed surface of the gate insulating film 43c above the gate insulating film 43c and inside the transistor hole TH. The sacrificial film 82 located below the transistor hole TH does not adsorb the SAM 153.

[0234] Next, although not shown, a bottom removal process (see FIG. 73), a SAM removal process (see FIG. 74), and an oxide semiconductor layer formation process (see FIG. 75) are performed.

[0235] Hereinafter, a fifth example of the manufacturing method of the semiconductor device 30 according to the second embodiment (hereinafter sometimes referred to as the second embodiment fifth example) will be described.

[0236] (First Embodiment Fifth Example) FIGS. 80 to 90 are cross-sections 70YZ parallel to the YZ plane, showing cross-sectional views of the semiconductor device 30 according to the fifth example of the second embodiment as seen in the cross-section 70YZ included in the transistor hole TH.

[0237] As shown in FIGS. 80 to 90, the fifth example of the manufacturing method according to the second embodiment is different from the second example of the manufacturing method shown in FIGS. 59 to 66 in that a stopper film 701 (an example of a "first layer" and a "first insulating film") is provided above the lower electrode 32 instead of the stopper film 501.

[0238] The stopper film 701 contains, for example, silicon and oxygen. In this example, the stopper film 701 is silicon oxide (SiO). The stopper film 701 is, for example, a thermal oxide film.

[0239] First, as shown in Figure 80, a transistor hole TH is formed. In this example, the upper surface of the stopper film 701 becomes the bottom of the transistor hole TH. Then, a sacrificial gate insulating film 143 is formed, for example, by ALD, so as to cover the upper surface of the insulating film 45a and the interior of the transistor hole TH.

[0240] Next, as shown in Figure 81, a dry etch-back process similar to the process shown in Figure 50 is performed.

[0241] Next, as shown in Figure 82, SAM treatment is performed on silicon oxide. In this example, SAM 153 is selectively adsorbed onto the upper surface of the insulating film 45a and onto the exposed sacrificial gate insulating film 143 and stopper film 701 inside the transistor hole TH.

[0242] Next, as shown in Figure 83, a first selective SAM removal process is performed. In this example, the SAM 153 adsorbed on the upper surface of the insulating film 45a and the sacrificial gate insulating film 143 is removed. On the other hand, the SAM 153 adsorbed on the stopper film 701 remains. Details of the first selective SAM removal process will be described later.

[0243] Next, as shown in Figure 84, a wet etch-back process similar to the process shown in Figure 52 is performed.

[0244] Next, as shown in Figure 85, a gate insulating film formation process similar to the process shown in Figure 53 is performed.

[0245] Next, as shown in Figure 86, SAM treatment is performed on silicon oxide. In this example, SAM 154 is selectively adsorbed onto the exposed surface of the gate insulating film 43 above the gate insulating film 43 and inside the transistor hole TH. SAM 154 does not adsorb onto the bottom of the transistor hole TH where SAM 153 is adsorbed.

[0246] Next, as shown in Figure 87, a second selective SAM removal process is performed. In this example, the SAM 153 adsorbed on the stopper film 701 at the bottom of the transistor hole TH is removed. On the other hand, the SAM 153 adsorbed on the gate insulating film 43 remains. Details of the second selective SAM removal process will be described later.

[0247] Next, as shown in Figure 88, a bottom removal process is performed. In this example, wet etching using a BHF solution or a DHF solution removes a portion of the gate insulating film 43 that is not selectively adsorbed by SAM154, and a portion of the stopper film 701 that is exposed at the bottom of the transistor hole TH. As a result, a hole 701a that penetrates vertically is formed in the stopper film 701. The upper surface of the lower electrode 32 is exposed through the hole 701a.

[0248] Next, as shown in Figure 89, a SAM removal process similar to the process shown in Figure 54 is performed.

[0249] Next, as shown in Figure 90, an oxide semiconductor layer formation process similar to the process shown in Figure 55 is performed.

[0250] The details of the first selective SAM removal process, shown in Figure 83, will be explained below.

[0251] Figure 91 shows an example of a process for selectively removing SAM 153 adsorbed on the sacrificial gate insulating film 143 when SAM 153 is adsorbed on the sacrificial gate insulating film 143 and the stopper film 701.

[0252] As shown in Figure 91, the sacrificial gate insulating film 143 and the stopper film 701 are initially exposed. As mentioned above, the sacrificial gate insulating film 143 and the stopper film 701 are silicon oxide.

[0253] On the other hand, the film quality of the sacrificial gate insulating film 143 and the stopper film 701 is different. In detail, the sacrificial gate insulating film 143 is formed by ALD. The sacrificial gate insulating film 143 may contain organic matter derived from the source gas used in ALD.

[0254] The stopper film 701 is a thermal oxide film formed by heating silicon in an oxygen atmosphere. In the stopper film 701, oxygen atoms and silicon atoms are strongly chemically bonded. For this reason, SAM 153 is more easily detached from the sacrificial gate insulating film 143 than the stopper film 701.

[0255] Next, SAM153 is supplied. SAM153 adheres to the respective surfaces of the sacrificial gate insulating film 143 and the stopper film 701. As described above, the adsorption force of SAM153 to the sacrificial gate insulating film 143 is weaker than the adsorption force of SAM153 to the stopper film 701.

[0256] Next, the SAM 153 adsorbed on the sacrificial gate insulating film 143 is removed by heat treatment or chemical treatment because its adsorption force is weak. On the other hand, the SAM 153 adsorbed on the stopper film 701 remains because its adsorption force is strong.

[0257] The details of the second selective SAM removal process, shown in Figure 87, will be explained below.

[0258] Figure 92 shows an example of a process for selectively adsorbing SAM154 onto the gate insulating film 43 when the gate insulating film 43 and stopper film 701 are exposed.

[0259] As shown in Figure 92, first, when SAM153 is adsorbed onto the stopper film 701, SAM154 is supplied to the gate insulating film 43 and the stopper film 701. SAM154 may be a liquid or a gas.

[0260] SAM154 is, for example, an organosilane or alcohol compound, similar to SAM153. SAM153 and SAM154 differ in at least one of the functional groups and alkyl groups that bind to the adsorbed film. Specifically, the alkyl groups differ between SAM153 and SAM154 in at least one of the number of carbon atoms, the number of carbon atoms, and the branching structure.

[0261] Since the surface of the gate insulating film 43 is not exposed, the SAM 154 selectively adsorbs onto the stopper film 701. For example, the adsorption force of the SAM 153 onto the stopper film 701 is weaker than the adsorption force of the SAM 154 onto the gate insulating film 43.

[0262] This can be achieved by adjusting at least one of the alkyl group and functional group of SAM154.

[0263] Next, the SAM153 adsorbed on the stopper film 701 is removed by heat treatment or chemical treatment because its adsorption force is weak. On the other hand, the SAM154 adsorbed on the gate insulating film 43 remains because its adsorption force is strong.

[0264] (Cross-section of semiconductor device 30) Figure 93 is a cross-sectional view taken along the cutting line XCIII-XCIII shown in Figure 75. As shown in Figure 93, the cross-section of the oxide semiconductor layer 70 is approximately circular. The gate insulating film 43c surrounds the oxide semiconductor layer 70. The gate insulating film 43b surrounds the gate insulating film 43c. The cross-sections of the gate insulating films 43b and 43c are ring-shaped.

[0265] The cross-section of the oxide semiconductor layer 70 may be oval or rectangular. Furthermore, a gate insulating film 43 may be provided instead of gate insulating films 43b and 43c. Also, the cross-section shown in Figure 75 is not limited to the cross-section of the semiconductor device 30 according to the third example of the second embodiment shown in Figure 75, but may be the cross-section of the semiconductor device 30 according to other embodiments.

[0266] Figure 94 shows a modified example of the cross-section shown in Figure 93. As shown in Figure 94, the cross-section of the oxide semiconductor layer 70 is substantially rectangular (see, for example, Patent Document 7).

[0267] The gate insulating film 43c is provided in the Y-axis + direction and Y-axis - direction of the oxide semiconductor layer 70, but not in the X-axis + direction and X-axis - direction of the oxide semiconductor layer 70. In other words, the gate insulating film 43c does not surround the oxide semiconductor layer 70, but rather sandwiches the oxide semiconductor layer 70.

[0268] The gate insulating film 43b is provided such that the gate insulating film 43c is located between the gate insulating film 43b and the oxide semiconductor layer 70. More specifically, in the Y-axis+ direction of the oxide semiconductor layer 70, the gate insulating films 43c and 43b are provided in this order toward the Y-axis+ direction. In the Y-axis- direction of the oxide semiconductor layer 70, the gate insulating films 43c and 43b are provided in this order toward the Y-axis- direction.

[0269] The planes of the oxide semiconductor layer 70 in the X+ direction and the X- direction do not contact either of the gate insulating films 43c and 43b, but contact the insulating film 45b.

[0270] In addition, in the conductive layer 42, the gate insulating films 43b and 43c may surround the oxide semiconductor layer 70.

[0271] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of Symbols]

[0272] 10… Semiconductor substrates 11... Circuit 20…Capacitor 21... Conductor 22…Insulating film 23... Conductor 24, 25... Capacitor electrodes 30... Semiconductor equipment 32...Lower electrode 33... Conductor 34, 35... Insulating layer 40…Field-effect transistor 42...Conductive layer 43, 43b, 43c… Gate insulating film 43a...Extended insulating film 45…Insulating layer 45a, 45b… Insulating film 50…Top electrode 50a... Metal oxide layer 50b... Barrier metal layer 50c…Metal film 70…Oxide semiconductor layer 70a…Top end 70b…lower end 70f…Part 1 70s…Part 2 70c...connection part 70e...extension part 70i...Void 80... Sacrificial membrane 81… Precursor 82... Sacrificial membrane 101... Semiconductor memory 143… Sacrificial gate insulating film 151, 152, 153, 153a, 154, 155…SAM 181…Non-adsorption part 182...Removal part 243... Gate protective film 501, 601, 701... Stopper membrane 501a, 601a, 701a...hole

Claims

1. Upper electrode and Lower electrode and An oxide semiconductor comprising: a first part connected to the upper electrode; and a second part connected to the lower end of the first part, having a diameter larger than the diameter of the lower end of the first part, and connected to the lower electrode; A gate insulating film surrounding the side surface of the first part, The first part penetrates a first insulating layer, A gate electrode provided below the first insulating layer, through which the first portion penetrates, and the gate electrode facing the first portion via the gate insulating film, A second insulating layer is provided below the gate electrode and is provided with a connection portion between the first and second parts, Semiconductor equipment.

2. The oxide semiconductor includes a plurality of extensions extending downward from the upper end of the lower electrode, The semiconductor device according to claim 1.

3. The extension portion penetrates the lower electrode, The semiconductor device according to claim 2.

4. The lower end of the gate insulating film has an outer diameter less than or equal to the diameter of the second part. The semiconductor device according to claim 1.

5. The aforementioned semiconductor device is The first insulating film is further provided below the second insulating layer, The second part penetrates the first insulating film and reaches the lower electrode, The semiconductor device according to claim 1.

6. Upper electrode and An oxide semiconductor having an upper end and a lower end connected to the upper electrode, and extending in the vertical direction, A gate insulating film provided on the side surface of the oxide semiconductor, A gate electrode facing the side surface of the oxide semiconductor via the gate insulating film, It comprises a first layer provided below the gate electrode and connected to the gate insulating film, The gate insulating film includes an extended insulating portion that extends downward in the first layer. Semiconductor equipment.

7. The first layer is a lower electrode connected to the lower end of the oxide semiconductor. The semiconductor device according to claim 6.

8. The aforementioned semiconductor device is The oxide semiconductor further comprises a lower electrode connected to the lower end, The first layer is provided above the lower electrode and is an insulating layer through which the oxide semiconductor penetrates. The semiconductor device according to claim 6.

9. The semiconductor device according to claim 1 or 6, A capacitor electrically connected to the upper electrode through the oxide semiconductor, The capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. Semiconductor memory device.

10. To form a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, and exposes the first layer provided below the second insulating layer, To form a gate insulating film covering the aforementioned hole, To form a protective film that covers the gate insulating film, Removing a portion of the protective film covering the first layer, Removing a portion of the gate insulating film covering the first layer, Removing the aforementioned protective film, This includes forming a semiconductor inside the aforementioned hole. A method for manufacturing a semiconductor device.

11. Removing a portion of the protective film covering the first layer is performed by etching using gas ion collisions. A method for manufacturing a semiconductor device according to claim 10.

12. Removing a portion of the gate insulating film covering the first layer is performed by wet etching. A method for manufacturing a semiconductor device according to claim 10.

13. The removal of the protective film is performed by wet etching. A method for manufacturing a semiconductor device according to claim 10.

14. To form a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, and exposes the first layer provided below the second insulating layer, To form a sacrificial film that covers the aforementioned pore, Removing a portion of the sacrificial film covering the first layer, exposing the upper surface of the first layer, Forming a monolayer on the upper surface of the exposed first layer, Removing the aforementioned sacrificial film, A gate insulating film is formed on the inner surface of the hole that is not covered by the monolayer, Removing the aforementioned monolayer, This includes forming a semiconductor inside the aforementioned hole. A method for manufacturing a semiconductor device.

15. If the first layer contains a metal or metal oxide, the monolayer is a phosphonic acid compound, a phosphate ester compound, an amine compound, or an organosilane compound. The method for manufacturing a semiconductor device according to claim 14.

16. The monolayer, when the first layer contains silicon and nitrogen, is an alkyl bromide compound or an unsaturated hydrocarbon compound. The method for manufacturing a semiconductor device according to claim 14.

17. The monolayer is an organosilane compound when the first layer contains silicon and oxygen. The method for manufacturing a semiconductor device according to claim 14.

18. The removal of the aforementioned monolayer is performed without etching using gas ion collisions. The method for manufacturing a semiconductor device according to claim 14.

19. To form a hole that penetrates a first insulating layer, a gate electrode provided below the first insulating layer, and a second insulating layer provided below the gate electrode, and exposes the first layer provided below the second insulating layer, To form a gate insulating film covering the aforementioned hole, A sacrificial film is formed below the hole to cover the gate insulating film, In the aforementioned pore, a monolayer is formed to cover a portion of the gate insulating film that is not covered by the sacrificial film, The sacrificial film is removed, and a portion of the gate insulating film that was covered by the sacrificial film is exposed. In the aforementioned hole, a portion of the gate insulating film covering the first layer is removed, exposing the first layer. Removing the aforementioned monolayer, This includes forming a semiconductor inside the aforementioned hole. A method for manufacturing a semiconductor device.

20. The aforementioned semiconductor is an oxide semiconductor. A method for manufacturing a semiconductor device according to claim 10, 14, or 19.

21. The first layer is a first insulating film provided below the lower electrode or the second insulating layer. A method for manufacturing a semiconductor device according to claim 10, 14, or 19.

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