Dummy pattern design apparatus and dummy pattern design method

Abstract

The present invention provides a dummy pattern design apparatus and a dummy pattern design method that can suppress the increase in resistance value due to wire breakage. [Solution] The dummy pattern design apparatus 1 includes a generation unit 10, which generates a second figure D2 by subtracting a via placement area width h from one end and the other end of a first figure D1 extending in one direction, which is a dummy pattern generation pattern; generates a first via placement area VP1 by subtracting the second figure D2 from the first figure D1; generates a third figure D3 by subtracting a predetermined value a from one end and the other end of the second figure D2; generates a fourth figure D4 by subtracting a via placement area width h from one end and the other end of the third figure D3; generates a second via placement area VP2 by subtracting the fourth figure D4 from the third figure D3; and places vias VA in the first via placement area VP1 and the second via placement area VP2.

Description

[Technical Field]

[0001] This disclosure relates to a dummy pattern design apparatus and a dummy pattern design method. [Background technology]

[0002] Patent documents 1 to 3 describe methods for designing dummy patterns. The dummy pattern design method of Patent Document 1 generates a dummy pattern such that a first wiring layer having a wiring pattern including a pattern extending in one direction and a second wiring layer having a wiring pattern arranged in the stacking direction relative to the first wiring layer are connected via vias. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-114295 [Patent Document 2] Japanese Patent Publication No. 2013-239063 [Patent Document 3] Japanese Patent Publication No. 2012-048702 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] As shown in the dummy pattern design method of Patent Document 1, by forming the pattern in two layers stacked in the stacking direction, the parasitic wiring resistance between vias can be reduced by half. However, if a break occurs in even one place between vias due to electromigration or the like, the resistance will revert to the value when only one layer of wiring was used. If breaks occur in both the upper and lower wiring layers, the conductivity will be interrupted and the device will become inoperable.

[0005] This disclosure is made to solve these problems and aims to provide a dummy pattern design apparatus and a dummy pattern design method that can suppress the increase in resistance value due to wire breakage. [Means for solving the problem]

[0006] Therefore, the present disclosure provides a dummy pattern design apparatus comprising a generation unit, wherein the generation unit generates a second figure by subtracting the via placement area width in one direction from one end of a first figure extending in one direction and the other end in the opposite direction to the first end of the first figure which is a dummy pattern generation pattern, generates a plurality of first via placement areas by subtracting the second figure from the first figure, generates a third figure by subtracting a predetermined value from one end and the other end of the second figure, generates a fourth figure by subtracting the via placement area width from one end and the other end of the third figure, generates a plurality of second via placement areas by subtracting the fourth figure from the third figure, and places vias in the first via placement area and the second via placement area.

[0007] Furthermore, this disclosure provides a dummy pattern design method which involves generating a second figure by subtracting the via placement area width in one direction from one end of a first figure extending in one direction and the other end in the opposite direction of the first figure, which is a dummy pattern generation pattern; generating a plurality of first via placement areas by subtracting the second figure from the first figure; generating a third figure by subtracting a predetermined value from one end and the other end of the second figure; generating a fourth figure by subtracting the via placement area width from one end and the other end of the third figure; generating a plurality of second via placement areas by subtracting the fourth figure from the third figure; and placing vias in the first via placement area and the second via placement area. [Effects of the Invention]

[0008] This disclosure provides a dummy pattern design apparatus and a dummy pattern design method that can suppress the increase in resistance value due to wire breakage. [Brief explanation of the drawing]

[0009] [Figure 1] It is a block diagram illustrating a dummy pattern design device according to Embodiment 1. [Figure 2] It is a plan view illustrating a dummy pattern generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 3] It is a side view illustrating a dummy pattern generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 4] It is a plan view illustrating a dummy pattern generated by a generation unit in a dummy pattern design device according to a comparative example. [Figure 5] It is a side view illustrating a dummy pattern generated by a generation unit in a dummy pattern design device according to a comparative example. [Figure 6] It is a side view illustrating a case where there is a disconnection point in dummy wiring formed by a dummy pattern generated by a generation unit in a dummy pattern design device according to a comparative example. [Figure 7] It is a side view illustrating a case where there is a disconnection point in dummy wiring formed by a dummy pattern generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 8] It is a diagram illustrating resistance values of a dummy wiring layer formed by a dummy pattern generated by a generation unit and a wiring layer formed by a wiring pattern in the dummy pattern design device according to Embodiment 1. [Figure 9] It is a flowchart diagram illustrating a dummy pattern design method using the dummy pattern design device according to Embodiment 1. [Figure 10] It is a plan view illustrating a first figure generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 11] It is a plan view illustrating a second figure generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 12] It is a plan view illustrating a plurality of first via arrangement regions generated by a generation unit in the dummy pattern design device according to Embodiment 1. [Figure 13]In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating vias arranged in the first via arrangement region. [Figure 14] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating the third figure generated by the generation unit. [Figure 15] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating the fourth figure generated by the generation unit. [Figure 16] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating a plurality of second via arrangement regions generated by the generation unit. [Figure 17] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating vias arranged in the second via arrangement region. [Figure 18] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating the fifth figure generated by the generation unit. [Figure 19] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating the third via arrangement region generated by the generation unit. [Figure 20] In the dummy pattern design device according to Embodiment 1, it is a plan view illustrating vias arranged in the third via arrangement region.

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same or corresponding elements are denoted by the same reference numerals, and redundant descriptions are omitted as necessary for clarity of explanation. Also, some reference numerals are omitted so that the drawings do not become complicated.

[0011] <Embodiment 1> A dummy pattern design apparatus according to Embodiment 1 will be described. Figure 1 is a block diagram illustrating a dummy pattern design apparatus 1 according to Embodiment 1. As shown in Figure 1, the dummy pattern design apparatus 1 includes a generation unit 10. The generation unit 10 has a first generation unit 11, a second generation unit 12, a third generation unit 13, and a determination unit 14. The dummy pattern design apparatus 1 may further include a control unit 20, a storage unit 30, and a communication unit 40. The control unit 20 has a processing unit 21, a ROM (Read Only Memory) 22, and a RAM (Random Access Memory) 23. The dummy pattern design apparatus 1 includes, for example, an information processing device such as a PC (Personal Computer), a server, or a tablet.

[0012] The processing unit 21 includes a processor and executes programs stored in the storage unit 30, ROM 22, and storage medium, etc., by calling them into the work memory area on the RAM 23. The processing unit 21 also drives and controls each component connected via the bus 29.

[0013] ROM22 stores control programs and various parameters for controlling the dummy pattern design device 1. RAM23 temporarily holds loaded programs and various data, and also provides a work area used by the control unit 20 for various processing. The dummy pattern design device 1 includes the above-described generation unit 10 as a functional block realized by a program processed by the processing unit 21. For convenience, these configurations are shown as being connected to communicate as appropriate via bus 29.

[0014] The memory unit 30 is, for example, a storage device such as a hard disk drive, a solid-state drive, or flash memory. The memory unit 30 may store programs executed by the control unit 20, data necessary for program execution, an operating system, etc. These programs, etc., are read by the control unit 20 as needed, transferred to the RAM 23, and then read by the processing unit 21 for execution. The programs may be stored in either the ROM 22 or the memory unit 30. The ROM 22 and the memory unit 30 may be integrated. The memory unit 30 may also store design data such as wiring patterns and dummy patterns.

[0015] The communication unit 40 controls communication with the network NW, etc. The bus 29 is a path that mediates the exchange of control signals, data signals, etc. between each unit.

[0016] The generation unit 10, which includes the first generation unit 11, the second generation unit 12, and the third generation unit 13, generates a dummy pattern DP1 including a via wiring area VP by a dummy pattern design method described later. The determination unit 14 determines whether to continue generating the dummy pattern DP1 under predetermined conditions.

[0017] Figure 2 is a plan view illustrating a dummy pattern DP1 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 3 is a side view illustrating a dummy pattern DP1 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. As shown in Figures 2 and 3, the dummy pattern DP1 is arranged to be stacked on the wiring pattern WP. The dummy pattern DP1 and the wiring pattern WP have portions that extend in one direction. The portion of the dummy pattern DP1 that extends in one direction and the portion of the wiring pattern WP that extends in one direction are stacked on top of each other.

[0018] Here, for the sake of explaining the dummy pattern DP1, the XYZ Cartesian coordinate system is introduced. The X-axis direction is the direction in which the dummy pattern DP1 extends. Therefore, one side of this direction is the +X-axis direction, and the other side is the -X-axis direction. Two mutually orthogonal directions perpendicular to the X-axis direction are the Y-axis direction and the Z-axis direction. For example, the Z-axis direction is the direction in which the dummy pattern DP1 and the wiring pattern WP are stacked. The direction from the wiring pattern WP to the dummy pattern DP1 is the +Z-axis direction, and the direction from the dummy pattern DP1 to the wiring pattern WP is the -Z-axis direction. The +Z-axis direction is sometimes called "up," and the -Z-axis direction is sometimes called "down." Note that "up" and "down" are for the sake of explaining the dummy pattern DP1 and do not indicate the actual direction in which the dummy pattern DP1 is placed.

[0019] The dummy pattern DP1 has multiple via placement areas VP. The multiple via placement areas VP are spaced apart in the X-axis direction. The dummy pattern DP1 may have portions in which the via placement areas VP are spaced equally apart. Multiple vias VA are placed in the via placement areas VP. A via electrode EP is placed in each via VA. The vias VA and via electrodes EP extend in the Z-axis direction. The via electrodes EP connect the dummy wiring layer formed by the dummy pattern DP and the wiring layer formed by the wiring pattern WP.

[0020] In this way, by connecting the dummy wiring layer formed by the dummy pattern DP1 and the wiring layer formed by the wiring pattern WP with via electrodes EP, the resistance value from one end of the wiring layer to the other can be reduced as a parasitic resistance value. For example, the resistance value from one end of the wiring layer to the other can be reduced to half of the parasitic resistance value.

[0021] Figure 4 is a plan view illustrating a dummy pattern DP101 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to the comparative example. Figure 5 is a side view illustrating a dummy pattern DP101 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to the comparative example. As shown in Figures 4 and 5, the generation unit 10 may generate the dummy pattern DP101. The dummy pattern DP101 has via placement areas VP at both ends in the X-axis direction. The via electrodes EP in the via placement areas VP at both ends connect the dummy wiring by the dummy pattern DP101 to the wiring layer by the wiring pattern WP.

[0022] In the comparative example, as in Embodiment 1, the dummy wiring layer formed by the dummy pattern DP101 and the wiring layer formed by the wiring pattern WP are connected by via electrodes EP, thereby reducing the resistance value from one end of the wiring layer to the other as a parasitic resistance value. For example, the resistance value from one end of the wiring layer to the other can be reduced to half of the parasitic resistance value.

[0023] Figure 6 is a side view illustrating a case in the dummy pattern design apparatus 1 of the comparative example where there is a break point BP in the dummy wiring generated by the generation unit 10 using the dummy pattern DP101. As shown in Figure 6, a break point BP occurs in the dummy wiring using the dummy pattern DP101 of the comparative example. For example, if a break point BP occurs in the dummy wiring using the dummy pattern DP101 due to electromigration or the like, the resistance value of the dummy wiring layer and the wiring layer from one end to the other increases. Specifically, the parasitic resistance value, which was 1 / 2 when the dummy wiring layer and wiring layer were stacked, becomes the resistance value of only the original wiring layer. The entire section between the via placement area VP located at one end of the wiring layer and the via placement area VP located at the other end becomes high resistance. If a break point BP occurs in the upper and lower dummy wiring layers and wiring layers, the conductivity is interrupted and the device becomes inoperable.

[0024] Figure 7 is a side view illustrating a case in the dummy pattern design apparatus 1 according to Embodiment 1 where there is a break point BP in the dummy wiring generated by the generation unit 10 using the dummy pattern DP1. As shown in Figure 7, a break point BP occurs in the dummy wiring using the dummy pattern DP1 of this embodiment. For example, due to electromigration or the like, one break point BP occurs in the dummy wiring using the dummy pattern DP1. However, in this embodiment, even if a break point BP occurs in the dummy wiring using the dummy pattern DP1, the parasitic resistance value increases only in the section between the via placement area VP that encloses the break point BP due to the influence of the break point BP. In this embodiment, by increasing such a partial parasitic resistance value, the increase in the overall parasitic resistance value from one end to the other of the wiring layer can be kept to a minimum. Furthermore, even if a break point BP occurs in the section between separate via placement areas VP in the upper and lower layers, conductivity is maintained as a wiring layer. This prevents failure of semiconductor devices, etc., due to break points BP, improves reliability, and extends the lifespan.

[0025] Furthermore, in this embodiment, via placement areas VP can be placed in all areas of the overlapping wiring pattern WP. In this case, the increase in parasitic resistance can be minimized regardless of where a break point BP occurs.

[0026] Next, in this embodiment, an example of the change in parasitic resistance when a break point BP occurs will be described. Figure 8 is a diagram illustrating the resistance values ​​of the dummy wiring layer by the dummy pattern DP1 and the wiring layer by the wiring pattern WP generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. As shown in Figure 8, for example, in a two-layer stacked dummy wiring layer and wiring layer, if a break point BP occurs in the dummy wiring by the dummy pattern DP1, the resistance value of only one wiring layer between the via placement area VP that sandwiches the break point BP will double.

[0027] For example, let the sheet resistance ρ of the wiring layer be ρ = 0.07 Ω / □, the wiring width W of the wiring layer be W = 20 μm, the wiring length L from one end to the other of the wiring layer be L = 1000 μm, and the wiring length L from one end to the other of the dummy wiring layer be L = 1000 μm. The resistance value R1 of one wiring layer is R1 = ρ × L / W. Therefore, the resistance value R1 is 3.5 Ω. The resistance value R2 for the dummy wiring layer when there is no break point BP and for the case of two layers of wiring layers stacked together is calculated using parallel resistance calculation, and is R2 = 1.75 Ω.

[0028] Let F = 50 μm be the distance between adjacent via regions VP in a region where multiple via regions VP are arranged at equal intervals. Connect the dummy wiring layer and the wiring layer with via electrodes EP of via VA. For simplicity, ignore the resistance of the via electrodes EP. Then the resistance value RF of the distance F is RF = 0.0875 Ω.

[0029] In this case, if a break point BP occurs between via regions VP, the resistance between the via regions VP surrounding this break point BP doubles. Therefore, it increases by 0.0875Ω to 0.175Ω. For a total length of 1000μm of wiring, this becomes 1.75Ω + 0.0875Ω = 1.8375Ω. Thus, the wiring resistance increases by 5%.

[0030] Assuming that a 5% increase in resistance is within the acceptable range for the characteristics of the circuit, for a 1000 μm wiring, this would result in 20 intervals of 50 μm spacing. The spacing F can be set to (1 / 20) the wiring length L of the wiring layer.

[0031] Even when wiring layers are stacked in triple, quadruple, ..., n layers, the resistance value of one section of wiring layer can be calculated in the same way as above using the parallel calculation method for resistance values.

[0032] The resistance value of one interval is equal to the total resistance value divided by the number of divisions. 1 / number of divisions is the ratio m to the total resistance value. If a break point BP occurs in one section, the total resistance value increases by m × 100% relative to the original total resistance value. If the tolerance for the resistance value of the wiring layer is m × 100% using the series calculation method of resistance values, then by setting the interval F = m × L or less, the effect of the resistance increase due to the break point BP can be kept within the tolerance range. Thus, in this embodiment, the interval F between via placement areas VP can be adjusted based on the tolerance for the resistance value of the wiring layer.

[0033] Next, the dummy pattern design method will be described. The dummy pattern forming method of this embodiment is carried out using the dummy pattern design apparatus 1.

[0034] Figure 9 is a flowchart illustrating a dummy pattern design method using the dummy pattern design apparatus 1 according to Embodiment 1. Figure 10 is a plan view illustrating a first figure D1 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 11 is a plan view illustrating a second figure D2 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 12 is a plan view illustrating a plurality of first via placement areas VP1 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 13 is a plan view illustrating vias VA placed in the first via placement area VP1 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 14 is a plan view illustrating a third figure D3 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1.

[0035] As shown in step S11 of Figure 9, the generation unit 10 sets n=1 and m=1. n and m are natural numbers. n represents n in the nth figure, and m represents m in the mth via arrangement region VP.

[0036] As shown in step S12 of Figure 9 and in Figure 10, the generation unit 10 acquires the first figure D1. The generation unit 10 may generate the first figure D1, or it may acquire the first figure D1 from the storage unit 30. The first figure D1 extends in the X-axis direction. The generation of the first via placement area VP1 will be described later.

[0037] In step S13, the determination unit 14 determines whether the width of the first figure D1 satisfies the following equation (1). Here, the determination unit 14 determines that the width of the first figure D1 in the X-axis direction is x n Let = x1. The determination unit 14 determines that h is the width of the via placement area VP in the X-axis direction. The determination unit 14 determines that a is a predetermined value in the X-axis direction. The predetermined value a is, for example, the distance between adjacent via placement areas VP in a portion where multiple via placement areas VP are arranged at equal intervals. The predetermined value a is set based on the current density of the current flowing through the wiring or the material of the wiring.

[0038] 2a + 2h ≤ x n (1)

[0039] Here, the determination unit 14 may determine a predetermined value a. The determination unit 14 may acquire the sheet resistance of the wiring layer, the wiring width, the wiring length, and the number of wiring layers. The determination unit 14 may calculate the number of divisions such that the resistance value does not exceed a predetermined resistance value when there is a predetermined number of disconnections BP. The determination unit 14 may determine a predetermined value a based on the wiring length and the number of divisions. The predetermined number of disconnections and the predetermined resistance value may be arbitrarily set by the user. Furthermore, the determination unit 14 may determine a predetermined value a based on the current density of the current flowing through the wiring layer. More specifically, the higher the current density, the smaller the predetermined value a may be determined by the determination unit 14. The determination unit 14 may determine a predetermined value a based on the material of the wiring layer. The predetermined value a may be arbitrarily set by the user.

[0040] For example, if the break points BP are set to 3 locations and the increase in the resistance value of the wiring layer is within 10%, the number of divisions can be calculated, and the interval F and a predetermined value a can be determined. Also, as the current density increases, electromigration becomes more likely, so the probability of breakage increases. Therefore, in such cases, increasing the number of divisions can reduce the risk of complete breakage in the same section of the stacked wiring layer or an increase in the resistance value of the wiring layer.

[0041] In this manner, the determination unit 14 sets a predetermined value a so as not to exceed a predetermined resistance value when a predetermined number of disconnections BP occur in at least one of the dummy wiring layer and the wiring layer formed by connecting the dummy wiring layer and the wiring layer stacked on the dummy pattern with via electrodes EP located in the via placement region VP of the laminate.

[0042] If the determination unit 14 determines that equation (1) for the width x1 of the first figure D1 is satisfied (YES), the process proceeds to step S14. If the determination unit 14 determines that equation (1) for the width x1 of the first figure D1 is not satisfied (NO), the process proceeds to step S19.

[0043] In step S14, as shown in Figure 11, the generation unit 10 generates a second figure D2 by subtracting the via placement area width h from the +X-axis side end and the -X-axis side end of the first figure D1, which is a dummy pattern generation pattern and extends in the X-axis direction. Specifically, the first generation unit 11 of the generation unit 10 generates the second figure D2 by subtracting the via placement area width h from the +X-axis side end and the -X-axis side end of the first figure D1.

[0044] Here, subtracting the via area width h from the +X-axis end of the first figure D1 means deleting the via area width h from the +X-axis end of the first figure D1 toward the -X-axis side, and moving the +X-axis end of the first figure D1 toward the -X-axis side by h, thereby shortening the length of the first figure D1 in the X-axis direction. Similarly, subtracting the via area width h from the -X-axis end of the first figure D1 means deleting the via area width h from the -X-axis end of the first figure D1 toward the +X-axis side, and moving the -X-axis end of the first figure D1 toward the +X-axis side by h, thereby shortening the length of the first figure D1 in the X-axis direction. The same applies to the nth figure Dn. n represents a natural number.

[0045] In step S15, as shown in Figure 12, the generation unit 10 generates a plurality of first via placement regions VP1 by subtracting the second figure D2 from the first figure D1. Specifically, the second generation unit 12 of the generation unit 10 generates a plurality of first via placement regions VP1 by subtracting the second figure D2 from the first figure D1.

[0046] Here, subtracting the second figure D2 from the first figure D1 means removing the overlapping portion between the first figure D1 and the second figure D2 from the first figure D1. The same applies to the nth figure Dn and the (n+1)th figure D(n+1).

[0047] In step S16, as shown in Figure 13, the generation unit 10 places via VA in the first via placement area VP1. Specifically, the second generation unit 12 of the generation unit 10 places via VA in the first via placement area VP1.

[0048] In step S17, as shown in Figure 14, the generation unit 10 generates the third figure D3 by subtracting a predetermined value a from the +X-axis side end and the -X-axis side end of the second figure D2. Specifically, the third generation unit 13 of the generation unit 10 generates the third figure D3 by subtracting a predetermined value a from the +X-axis side end and the -X-axis side end of the second figure D2. a represents a positive value.

[0049] Here, subtracting a predetermined value a from the +X-axis end of the second figure D2 means deleting a predetermined value a from the +X-axis end of the second figure D2 toward the -X-axis, and moving the +X-axis end of the second figure D2 toward the -X-axis by a, thereby shortening the length of the second figure D2 in the X-axis direction. Similarly, subtracting a predetermined value a from the -X-axis end of the second figure D2 means deleting a predetermined value a from the -X-axis end of the second figure D2 toward the +X-axis, and moving the -X-axis end of the second figure D2 toward the +X-axis by a, thereby shortening the length of the second figure D2 in the X-axis direction. The same applies to the nth figure Dn.

[0050] In step S18, the generation unit 10 sets n=n+2 and m=m+1 so that the determination unit 14 can perform the determination in step S13. As a result, in step S13, the determination unit 14 determines the width x of the third figure D3. n Determine if =x3 satisfies equation (1). Here, x3 represents the width of the third figure D3 in the X-axis direction. h and a are the same as described above.

[0051] In step S13, if the determination unit 14 determines that equation (1) for the width x 3 of the third figure D3 is satisfied (YES), the process proceeds to step S14. In step S13, if the determination unit 14 determines that equation (1) for the width x 3 of the third figure D3 is not satisfied (NO), the process proceeds to step S19. The following describes the case where the determination unit 14 determines that equation (1) for the width of the third figure D3 is satisfied (YES).

[0052] Figure 15 is a plan view illustrating a fourth figure D4 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 16 is a plan view illustrating a plurality of second via placement areas VP2 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 17 is a plan view illustrating vias VA placed in the second via placement areas in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 18 is a plan view illustrating a fifth figure generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 19 is a plan view illustrating a third via placement area VP3 generated by the generation unit 10 in the dummy pattern design apparatus 1 according to Embodiment 1. Figure 20 is a plan view illustrating vias VA placed in the third via placement area VP3 in the dummy pattern design apparatus 1 according to Embodiment 1.

[0053] In step S14, as shown in Figure 15, the generation unit 10 generates the fourth figure D4 by subtracting the via placement area width h from the +X-axis side end and the -X-axis side end of the third figure D3. Specifically, the first generation unit 11 of the generation unit 10 generates the fourth figure D4 by subtracting the via placement area width h from both ends of the third figure D3.

[0054] In step S15, as shown in Figure 16, the generation unit 10 generates multiple second via placement areas VP2 by subtracting the fourth figure D4 from the third figure D3. Specifically, the second generation unit 12 of the generation unit 10 generates multiple second via placement areas VP2 by subtracting the fourth figure D4 from the third figure D3.

[0055] In step S16, as shown in Figure 17, the generation unit 10 places via VA in the second via placement area VP2. Specifically, the second generation unit 12 of the generation unit 10 places via VA in the second via placement area VP2.

[0056] In step S17, as shown in Figure 18, the generation unit 10 generates the fifth figure D5 by subtracting a predetermined value a from the +X-axis side end and the -X-axis side end of the fourth figure D4. Specifically, the third generation unit 13 of the generation unit 10 generates the fifth figure D5 by subtracting a predetermined value a from the +X-axis side end and the -X-axis side end of the fourth figure D4.

[0057] In step S18, the generation unit 10 sets n=n+2 and m=m+1 so that the determination unit 14 can perform the determination in step S13. As a result, in step S13, the determination unit 14 determines the width x of the fifth figure D5. n Determine if =x5 satisfies equation (1). Here, x5 represents the width of the fifth figure D5 in the X-axis direction. h and a are the same as described above.

[0058] In step S13, if the determination unit 14 determines that equation (1) for the width x 5 of the fifth figure D5 is satisfied (YES), the process proceeds to step S14. In step S13, if the determination unit 14 determines that equation (1) for the width x 5 of the fifth figure D5 is not satisfied (NO), the process proceeds to step S19. The following describes the case where the determination unit 14 determines that equation (1) for the width x 5 of the fifth figure D5 is not satisfied (NO).

[0059] In step S19, the determination unit 14 of the generation unit 10 determines whether the width x5 of the fifth figure D5 satisfies the following equation (2). Here, the determination unit 14 determines the width x in the X-axis direction of the fifth figure D5 n Let = x5. h and a are the same as described above.

[0060] h≦x n <2a+2h (2)

[0061] The determination unit 14 determines x on the right side nFor 2a + 2h, it has already been determined in step S13. Therefore, the determination unit 14 determines h ≤ x5 on the left side. When the determination unit 14 determines that the formula (2) for the width x5 of the fifth figure D5 is satisfied (YES), the process proceeds to step S20. When the determination unit 14 determines that the formula (2) for the width x5 of the fifth figure D5 is not satisfied (NO), that is, when it is determined that x5 < h (NO), the generation unit 10 ends the process without generating the third via arrangement region.

[0062] In step S20, as shown in FIG. 19, the generation unit 10 generates a third via arrangement region VP3 at the center of the fifth figure D5. Specifically, the second generation unit 12 of the generation unit 10 generates a third via arrangement region VP3 at the center of the fifth figure D5.

[0063] In step S21, as shown in FIG. 20, the generation unit 10 arranges a via VA in the third via arrangement region VP3. Specifically, the second generation unit 12 of the generation unit 10 arranges a via VA in the third via arrangement region VP3. Then, the process ends. In this way, a dummy pattern DP1 as shown in FIGS. 2 and 3 can be generated.

[0064] Next, the effects of this embodiment will be described. In this embodiment, the generation unit 10 subtracts the via arrangement region width h from both ends of the first figure D1 to generate the second figure D2, subtracts the second figure D2 from the first figure D1 to generate a plurality of first via arrangement regions VP1, and subtracts a predetermined value a from both ends of the second figure D2 to generate the third figure D3. The generation unit 10 repeats such processing until the nth via arrangement region VP cannot be arranged. Thereby, a plurality of via arrangement regions VP can be arranged at a constant interval F having a predetermined value a.

[0065] Thus, in this embodiment, by simply determining a certain value a, it is possible to arrange the via placement regions VP evenly on the left and right without performing calculations such as measuring the total length of the wiring layer and arranging it evenly. Therefore, it is possible to generate a plurality of via placement regions VP that connect the dummy pattern DP1 that becomes the dummy wiring layer and the wiring pattern WP that becomes the wiring layer. However, it may be unevenly spaced only in one part at the center of the wiring layer.

[0066] In this embodiment, even if a disconnection point BP occurs in the dummy wiring by the dummy pattern DP1, it is possible to limit the increase in the resistance value only to the section between the via placement regions VP sandwiching the disconnection point BP, and suppress the increase in the overall resistance value. Further, in this embodiment, even when a disconnection point BP occurs in the section between different via placement regions VP in the upper and lower layers including the dummy wiring layer and the wiring layer, it is possible to maintain the conduction as the wiring layer. Thereby, it is possible to prevent defects such as semiconductor devices due to the disconnection point BP, improve reliability, and achieve a longer lifespan.

[0067] Also, in this embodiment, when the generation unit 10 generates the (n + 1)-th figure, the determination unit 14 determines that 2a + 2h ≤ x n And when the determination unit determines that 2a + 2h ≤ x n the generation unit 10 forms the (n + 1)-th figure. Therefore, the via placement regions VP can be arranged at equal intervals.

[0068] Furthermore, in this embodiment, when the generation unit 10 determines that h ≤ x n < 2a + 2h, it generates the m-th via placement region at the center of the n-th figure, and when it determines that x n < h, it ends the process without generating the m-th via placement region. Thereby, the generation unit 10 can generate the maximum possible via placement regions VP within the range allowed by the n-th figure.

[0069] The predetermined value 'a' is set based on the current density of the current flowing through the wiring layer or the material of the wiring. This allows the spacing F between via placement areas VP to be set according to the specifications of the wiring layer, thereby improving design flexibility.

[0070] This disclosure is not limited to the description of Embodiment 1 above, and can be modified as appropriate without departing from the spirit of the invention. For example, any combination of the configurations of Embodiment 1 and the Comparative Examples is also within the scope of the technical concept of this embodiment. Furthermore, the dummy pattern design method and the dummy pattern design program that causes a computer to execute the dummy pattern design method, as shown below, are also within the scope of the technical concept of this embodiment.

[0071] (Note A1) A second figure is generated by subtracting the via placement area width in one direction from one end in that direction and the other end in the opposite direction of the first figure, which is a dummy pattern generation pattern and extends in one direction. Multiple first via placement regions are generated by subtracting the second figure from the first figure. A third figure is generated by subtracting predetermined values ​​from one end and the other end of the second figure. A fourth figure is generated by subtracting the via arrangement area width from one end and the other end of the third figure. Subtracting the fourth figure from the third figure generates multiple second via placement regions. Vias are placed in the first via placement area and the second via placement area. Dummy pattern design method. (Appendix A2) Let the via arrangement area width be h, the predetermined value be a, and the width of the third figure in one direction be x3. Then, determine that 2a + 2h ≤ x3. When we determine that 2a + 2h ≤ x3, The fourth figure is generated, The second via placement region is generated, Subtract a predetermined value from the one - side end and the other - side end of the fourth figure to generate a fifth figure. The dummy pattern design method according to Supplementary Note A1. (Supplementary Note A3) Let the width of the via arrangement area be h, the predetermined value be a, and the width of the n - th figure be x n When n and m are integers, determine h ≤ x n <2a + 2h, h ≤ x n When it is determined that h ≤ x <2a + 2h, generate the m - th via arrangement area at the center of the n - th figure. x n When it is determined that x <h, end the process without generating the m - th via arrangement area. The dummy pattern design method according to Supplementary Note A1. (Supplementary Note A4) The predetermined value is set based on the current density of the current flowing through the wiring layer or the material of the wiring layer. The dummy pattern design method according to Supplementary Note A1. (Supplementary Note A5) When a predetermined number of disconnection points occur in at least one of the dummy wiring layer and the wiring layer in the laminate formed by connecting the dummy wiring layer formed by the dummy pattern and the wiring layer formed by the wiring pattern laminated on the dummy pattern with via electrodes arranged in the via arrangement area, set the predetermined value so that the resistance value of the laminate does not exceed a predetermined resistance value. The dummy pattern design method according to Supplementary Note A1. (Supplementary Note B1) Subtract the width of the via arrangement area in one direction from the one - side end and the other - side end in the one direction of the first figure, which is a pattern for generating a dummy pattern, to generate a second figure. Subtract the second figure from the first figure to generate a plurality of first via arrangement areas. Subtract a predetermined value from the one - side end and the other - side end of the second figure to generate a third figure. Subtract the width of the via arrangement area from the one-side end and the other-side end of the third figure to generate a fourth figure. Subtract the fourth figure from the third figure to generate a plurality of second via arrangement areas. Place vias in the first via arrangement area and the second via arrangement area. A dummy pattern design program that causes a computer to execute the above. (Appendix B2) When the width of the via arrangement area is h, the predetermined value is a, and the width of the third figure in the one direction is x3, determine that 2a + 2h ≤ x3. When it is determined that 2a + 2h ≤ x3 Generate the fourth figure. Generate the second via arrangement area. Subtract the predetermined value from the one-side end and the other-side end of the fourth figure to generate a fifth figure. The dummy pattern design program according to Appendix B1 that causes a computer to execute the above. (Appendix B3) When the width of the via arrangement area is h, the predetermined value is a, the width of the nth figure is x n and n and m are integers, determine that h ≤ x n < 2a + 2h. h ≤ x n < 2a + 2h, generate a the mth via arrangement area at the center of the nth figure. x n < h, end the process without generating the mth via arrangement area. The dummy pattern design program according to Appendix B1 that causes a computer to execute the above. (Appendix B4) The predetermined value is set based on the current density of the current flowing through the wiring layer or the material of the wiring layer. The dummy pattern design program according to Appendix B1. (Appendix B5) When a predetermined number of disconnections occur in at least one of the dummy wiring layer and the wiring layer formed by connecting the dummy wiring layer formed by the dummy pattern and the wiring layer formed by the wiring pattern stacked on the dummy pattern with via electrodes placed in the via placement area, the predetermined value is set so that the resistance value of the laminate does not exceed a predetermined resistance value. A dummy pattern design program described in Appendix B1 that causes a computer to perform the following actions.

[0072] Furthermore, the dummy pattern design program described above, when loaded into a computer, includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals. [Explanation of symbols]

[0073] 1. Dummy pattern design device 10 Generation part 11 1st generation part 12 Second generation part 13 Third generation part 14 Judgment section 20 Control Unit 21 Processing Unit 22 ROM 23 RAM 29 bus 30 Storage section 40 Communications Department BP break point D1, D2, D3, D4, D5 shapes DP1, DP101 dummy patterns EP via electrode F interval VA Beer VP, VP1, VP2, VP3 via placement area WP wiring pattern

Claims

1. A dummy pattern design apparatus equipped with a generation unit, The generating unit is A second figure is generated by subtracting the via placement area width in one direction from one end in that direction and the other end in the opposite direction of the first figure, which is a dummy pattern generation pattern and extends in one direction. Multiple first via placement regions are generated by subtracting the second figure from the first figure. A third figure is generated by subtracting predetermined values ​​from one end and the other end of the second figure. A fourth figure is generated by subtracting the via arrangement area width from one end and the other end of the third figure. Subtracting the fourth figure from the third figure generates a plurality of second via placement regions. Vias are placed in the first via placement area and the second via placement area. Dummy pattern design device.

2. Let h be the width of the via placement area, a be the predetermined value, and x be the width of the nth figure. ｎ Let n and m be integers, The generating unit is h ≤ x ｎ If it is determined that <2a + 2h, a via placement region of the mth figure is generated at the center of the nth figure, x ｎ If it is determined that <h>, the process will terminate without generating the via placement area m. The dummy pattern design apparatus according to claim 1.

3. It has a determination unit, The determination unit sets the predetermined value based on the current density of the current flowing through the wiring layer or the material of the wiring layer. The dummy pattern design apparatus according to claim 1.

4. It has a determination unit, The determination unit sets a predetermined value so that the resistance value of the laminate does not exceed a predetermined resistance value when a predetermined number of disconnections occur in at least one of the dummy wiring layer and the wiring layer formed by connecting the dummy wiring layer formed by the dummy pattern and the wiring layer formed by the wiring pattern stacked on the dummy pattern with via electrodes placed in the via arrangement area. The dummy pattern design apparatus according to claim 1.

5. A second figure is generated by subtracting the via placement area width in one direction from one end in that direction and the other end in the opposite direction of the first figure, which is a dummy pattern generation pattern and extends in one direction. Multiple first via placement regions are generated by subtracting the second figure from the first figure. A third figure is generated by subtracting predetermined values ​​from one end and the other end of the second figure. A fourth figure is generated by subtracting the via arrangement area width from one end and the other end of the third figure. Subtracting the fourth figure from the third figure generates a plurality of second via placement regions. Vias are placed in the first via placement area and the second via placement area. Dummy pattern design method.

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