Loop device

Abstract

To provide a circuit device, etc., that can shift the level of a signal using a latch circuit. [Solution] The circuit device 100 includes a latch circuit 130-1 that latches an input signal SIN1, a signal output circuit 150 that outputs a latch signal LLAT and a power control signal LCNT based on a control signal CNT, a latch control circuit 120 that outputs a latch control signal LTCT to the latch circuit 130-1 based on the latch signal LLAT, and a power switching circuit 110 that supplies a first power supply voltage V1 or a second power supply voltage V2 different from the first power supply voltage V1 to the power line LQ of the latch circuit 130-1 and the latch control circuit 120 based on the power control signal LCNT. When the control signal CNT changes from inactive to active, the signal output circuit 150 changes the latch signal LLAT from inactive to active, and then outputs a power control signal LCNT indicating a switch from the first power supply voltage V1 to the second power supply voltage V2.

Description

Technical Field

[0001] The present invention relates to a circuit device and the like.

Background Art

[0002] Patent Document 1 discloses a level conversion circuit. The level conversion circuit includes a pair of load transistors with their gates and drains cross-connected, and a pair of drive transistors that pull down or pull up each load transistor according to an input signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is necessary to increase the current capacity ratio of the drive transistor with respect to the load transistor in the level shifter. For this reason, there is a problem that an influence is caused by using a level shifter in a signal path. For example, when level shifters are provided in a large number of signal paths, the circuit area increases, or problems such as signal delay due to imbalance between signal rise and fall occur.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device including a latch circuit for latching an input signal, a signal output circuit that outputs a latch signal and a power control signal based on a control signal, a latch control circuit that outputs a latch control signal to the latch circuit based on the latch signal, and a power switching circuit that supplies a first power supply voltage or a second power supply voltage different from the first power supply voltage to the power lines of the latch circuit and the latch control circuit based on the power supply control signal, wherein the signal output circuit outputs a power control signal indicating a switch from the first power supply voltage to the second power supply voltage after the latch signal has been activated from inactive to active when the control signal has been activated from inactive to active. [Brief explanation of the drawing]

[0006] [Figure 1] An example of a circuit device configuration. [Figure 2] An example of a latch circuit configuration. [Figure 3] An example of a timing chart illustrating the operation of a circuit device. [Figure 4] Detailed configuration example of a circuit device. [Figure 5] A table showing the operating modes of the memory circuit. [Figure 6] First detailed configuration example of a word line control circuit. [Figure 7] An example configuration of a power supply switching circuit in the first detailed configuration example of a word line control circuit. [Figure 8] An example of the configuration of a latch control circuit in the first detailed configuration example of a word line control circuit. [Figure 9] An example of the latch circuit configuration in the first detailed configuration example of a word line control circuit. [Figure 10] A timing chart example illustrating the operation of the first detailed configuration example of a word line control circuit. [Figure 11] A second detailed configuration example of a word line control circuit. [Figure 12] An example configuration of a power supply switching circuit in the second detailed configuration example of a word line control circuit. [Figure 13] An example of the configuration of a latch control circuit in the second detailed configuration example of a word line control circuit. [Figure 14] Configuration example of the latch circuit in the second detailed configuration example of the word line control circuit. [Figure 15] Example of a timing chart for explaining the operation of the second detailed configuration example of the word line control circuit. [Figure 16] Third detailed configuration example of the word line control circuit. [Figure 17] Configuration example of the signal output circuit in the third detailed configuration example of the word line control circuit. [Figure 18] Configuration example of the latch control circuit in the third detailed configuration example of the word line control circuit. [Figure 19] Configuration example of the latch circuit in the third detailed configuration example of the word line control circuit. [Figure 20] Example of a timing chart for explaining the operation of the third detailed configuration example of the word line control circuit. [Figure 21] Configuration example of the latch control circuit in the fourth detailed configuration example of the word line control circuit. [Figure 22] Detailed configuration example of the clocked inverter. [Figure 23] Example of simulation waveforms when the P-type MOS transistor cannot maintain OFF when the power supply control signal changes from low level to high level in the write mode. [Figure 24] Example of simulation waveforms when the P-type MOS transistor can maintain OFF when the power supply control signal changes from low level to high level in the write mode. [Figure 25] Example of simulation waveforms when the N-type MOS transistor cannot maintain OFF when the power supply control signal changes from low level to high level in the erase mode. [Figure 26] Example of simulation waveforms when the N-type MOS transistor can maintain OFF when the power supply control signal changes from low level to high level in the erase mode. [Figure 27] First comparative example of this embodiment. [Figure 28] Circuit configuration example and signal waveform example when level shifting is performed using a latch circuit. [Figure 29] Another first configuration example of the latch circuit. [Figure 30] Another second configuration example of the latch circuit. [Figure 31] The first comparative example of the present embodiment.

Modes for Carrying Out the Invention

[0007] Hereinafter, preferred embodiments of the present disclosure will be described in detail. Note that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements.

[0008] 1. Configuration example FIG. 1 is a configuration example of the circuit device 100. The circuit device 100 includes a power supply switching circuit 110, a latch control circuit 120, latch circuits 130-1 to 130-n, a signal output circuit 150, and a control circuit 190. n is an integer of 1 or more. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0009] The control circuit 190 outputs a control signal CNT for controlling the power supply switching circuit 110 and the latch circuits 130-1 to 130-n, and input signals SIN1 to SINn of the latch circuits 130-1 to 130-n. The control circuit 190 is constituted by a logic circuit that processes digital signals.

[0010] The signal output circuit 150 outputs a power supply control signal LCNT for controlling the power supply switching circuit 110 and a latch signal LLAT for controlling the latch circuits 130-1 to 130-n based on the control signal CNT. The signal output circuit 150 is constituted by a logic circuit that processes digital signals.

[0011] The power switching circuit 110 switches the voltage VQ of the power line LQ to either the first power supply voltage V1 or the second power supply voltage V2 based on the power control signal LCNT. The voltage value of the second power supply voltage V2 is different from the voltage value of the first power supply voltage V1. The power line LQ is a line that supplies power to the latch control circuit 120 and the latch circuits 130-1 to 130-n. The power switching circuit 110 level-shifts the power control signal LCNT to a signal of the voltage level of the power line LQ, and outputs a power control feedback signal SW to the signal output circuit 150 based on the level-shifted signal.

[0012] The latch control circuit 120 outputs a latch control signal LTCT based on the latch signal LLAT. The latch circuit 130-1 latches the input signal SIN1 based on the latch control signal LTCT and outputs the latched signal as the output signal SQ1. Similarly, the latch circuits 130-2 to 130-n latch the input signals SIN2 to SINn based on the latch control signal LTCT and output the latched signals as the output signals SQ2 to SQn. The latch control circuit 120 level-shifts the latch signal LLAT to a signal of the voltage level of the power line LQ, and outputs a latch control feedback signal LT to the signal output circuit 150 based on the level-shifted signal.

[0013] The signal output circuit 150 controls the transition timing of the power control signal LCNT based on the control signal CNT and the latch control feedback signal LT, and controls the transition timing of the latch signal LLAT based on the control signal CNT and the power control feedback signal SW.

[0014] The control circuit 190 and the signal output circuit 150 operate using a predetermined power supply. Here, it is assumed that the control circuit 190 and the signal output circuit 150 are supplied with a first power supply voltage V1. When the first power supply voltage V1 is a high-potential power supply voltage, the control circuit 190 outputs input signals SIN1 to SINn that set the first power supply voltage V1 to a high level. At this time, if the voltage VQ is the second power supply voltage V2, the latch circuits 130-1 to 130-n output output signals SQ1 to SQn that set the second power supply voltage V2 to a high level. That is, the high level of the signal is level-shifted from the first power supply voltage V1 to the second power supply voltage V2. When the first power supply voltage V1 is a low-potential power supply voltage, the control circuit 190 outputs input signals SIN1 to SINn that set the first power supply voltage V1 to a low level. In this case, if the voltage VQ is the second power supply voltage V2, the latch circuits 130-1 to 130-n output output signals SQ1 to SQn that set the second power supply voltage V2 to a low level. That is, the low level of the signal is level-shifted from the first power supply voltage V1 to the second power supply voltage V2.

[0015] Conventionally, such level shifting was achieved by inserting a level shifter into the signal path. In this embodiment, by switching the power supply voltage of the latch control circuit 120 and the latch circuits 130-1 to 130-n by the control described later in Figure 3, it is possible to perform level shifting using the latch circuits 130-1 to 130-n without using a level shifter. As a result, it is no longer necessary to insert a level shifter into each signal path, and various effects such as a reduction in layout area or a reduction in signal delay can be obtained.

[0016] In Figure 1, an example is shown where the input signals SIN1 to SINn output by the control circuit 190 are directly input to the latch circuits 130-1 to 130-n. However, it is sufficient that the latch circuits 130-1 to 130-n receive signals equivalent to the input signals SIN1 to SINn output by the control circuit 190. For example, as shown in Figure 6 later, the signal output circuit 150 may include a logic circuit inserted between the control circuit 190 and the latch circuits 130-1 to 130-n.

[0017] Figure 2 shows an example configuration of latch circuit 130-1. Latch circuit 130-1 includes an input control circuit 132 and a holding circuit 134. Latch circuits 130-2 to 130-n have a similar configuration.

[0018] The active state of the latch signal LLAT and the latch control signal LTCT represents a logic level indicating signal retention, while the inactive state represents a logic level indicating non-retention of the signal, i.e., signal passage. When the latch control signal LTCT is inactive, the input control circuit 132 passes the input signal SIN1 to the holding circuit 134, and the holding circuit 134 passes the input signal without retention and outputs it as the output signal SQ1. When the latch control signal LTCT is active, the input control circuit 132 blocks the input signal SIN1 and does not input it to the holding circuit 134, and the holding circuit 134 retains the signal that was input before the latch control signal LTCT changed from inactive to active and outputs it as the output signal SQ1.

[0019] The voltage VQ of the power line LQ is supplied as the power supply voltage to at least the holding circuit 134. If the input control circuit 132 uses a circuit that requires a power supply, such as a clocked inverter, then the voltage VQ is further supplied to the input control circuit 132 from the power line LQ.

[0020] Figure 3 is an example timing chart illustrating the operation of the circuit device 100. Inactivity of the power control signal LCNT signifies the selection of the first power supply voltage V1, while activity signifies the selection of the second power supply voltage V2. The control signal CNT, power control signal LCNT, and latch signal LLAT are assumed to be highly active. While Figure 3 uses the operation of latch circuit 130-1 as an example, the operation of latch circuits 130-2 to 130-n is similar.

[0021] The control circuit 190 updates the input signal SIN1 at predetermined timings. Figure 3 shows an example in which the control circuit 190 updates the input signal SIN1 at predetermined intervals. The input signals SIN1 in each period are denoted as SIN1a and SIN1b. Each of SIN1a and SIN1b is either a low level or a high level.

[0022] The control circuit 190 updates the input signal SIN1 to SIN1a, and then sets the control signal CNT from a low level to a high level. The signal output circuit 150, upon receiving that the control signal CNT has changed from a low level to a high level, sets the latch signal LLAT from a low level to a high level. The latch control circuit 120 causes the latch circuit 130-1 to latch SIN1a and sets the latch control feedback signal LT from a low level to a high level. The signal output circuit 150, upon receiving that the latch control feedback signal LT has changed from a low level to a high level, sets the power control signal LCNT from a low level to a high level. The power switching circuit 110 switches the voltage VQ of the power line LQ from the first power supply voltage V1 to the second power supply voltage V2 and sets the power control feedback signal SW from a low level to a high level. With the latch circuit 130-1 holding SIN1a, the voltage VQ of the power line LQ switches from the first power supply voltage V1 to the second power supply voltage V2, and the output signal SQ1 of the latch circuit 130 is level shifted.

[0023] Next, the control circuit 190 changes the control signal CNT from a high level to a low level. The signal output circuit 150, upon receiving that the control signal CNT has changed from a high level to a low level, changes the power control signal LCNT from a high level to a low level. The power switching circuit 110 switches the voltage VQ of the power line LQ from the second power supply voltage V2 to the first power supply voltage V1, and also changes the power control feedback signal SW from a high level to a low level. With the latch circuit 130-1 holding SIN1a, the voltage VQ of the power line LQ switches from the second power supply voltage V2 to the first power supply voltage V1, and the output signal SQ1 of the latch circuit 130 returns to an un-level-shifted state. The signal output circuit 150, upon receiving that the power control feedback signal SW has changed from a high level to a low level, changes the latch signal LLAT from a high level to a low level. The latch control circuit 120 allows SIN1a to pass through the latch circuit 130-1, and also changes the latch control feedback signal LT from a high level to a low level. Next, the control circuit 190 updates the input signal SIN1 to SIN1b. The circuit device 100 then repeats the same operation.

[0024] In this way, with the latch circuit 130-1 holding the input signal SIN1, the power supply switching circuit 110 switches the voltage VQ of the power line LQ. This makes it possible to shift the level using the latch circuit 130-1 without using a level shifter.

[0025] In this embodiment, the circuit device 100 includes a latch circuit (e.g., 130-1), a signal output circuit 150, a latch control circuit 120, and a power supply switching circuit 110. The latch circuit 130-1 latches the input signal SIN1. The signal output circuit 150 outputs a latch signal LLAT and a power supply control signal LCNT based on a control signal CNT. The latch control circuit 120 outputs a latch control signal LTCT to the latch circuit 130-1 based on the latch signal LLAT. The power supply switching circuit 110 supplies a first power supply voltage V1, or a second power supply voltage V2 different from the first power supply voltage V1, to the power supply line LQ of the latch circuit 130-1 and the latch control circuit 120 based on the power supply control signal LCNT. When the control signal CNT changes from inactive to active, the signal output circuit 150 changes the latch signal LLAT from inactive to active, and then outputs a power supply control signal LCNT indicating a switch from the first power supply voltage V1 to the second power supply voltage V2.

[0026] According to this embodiment, after the latch circuit 130-1 latches the input signal SIN1, the power supply switching circuit 110 switches the voltage VQ of the power line LQ of the latch control circuit 120 and the latch circuit 130-1 from the first power supply voltage V1 to the second power supply voltage V2. When the power supply voltage is switched in a stable state in which the latch circuit 130-1 has latched the signal, the output level of the latch circuit 130-1 changes from the first power supply voltage V1 to the second power supply voltage V2. This makes it possible to level shift the signal using the latch circuit 130-1 without using a level shifter. Various effects can be obtained by eliminating the need to insert a level shifter in each signal path. For example, in the case of many signal paths, such as the word line control signal of the memory circuit described later, a latch circuit can be provided in each signal path instead of a level shifter, thus reducing the layout area. Alternatively, since the imbalance between falling and falling edges of the signal is small in the latch circuit, unlike in a level shifter, signal delay can be reduced.

[0027] In this embodiment, when the signal output circuit 150 changes the latch signal LLAT from inactive to active, the latch control circuit 120 outputs a latch control signal LTCT based on the first power supply voltage V1. Also, the latch circuit 130-1 latches the input signal SIN1 and outputs an output signal SQ1 based on the first power supply voltage V1. When the latch circuit 130-1 holds the latched input signal SIN1, the signal output circuit 150 outputs a power control signal LCNT indicating a switch from the first power supply voltage V1 to the second power supply voltage V2. Also, the power switching circuit 110 switches the voltage VQ of the power line LQ from the first power supply voltage V1 to the second power supply voltage V2. Furthermore, the latch control circuit 120 outputs a latch control signal LTCT based on the second power supply voltage V2, and the latch circuit 130-1 outputs an output signal SQ1 based on the second power supply voltage V2.

[0028] According to this embodiment, the signal output circuit 150 controls the signal so that the latch circuit 130-1 latches the input signal SIN1, and then the power supply switching circuit 110 switches the voltage VQ of the power line LQ. As a result, as described above, the latch circuit 130-1 can level shift the signal without using a level shifter.

[0029] In this embodiment, the latch circuit 130-1 includes an input control circuit 132 to which the input signal SIN1 is input, and a holding circuit 134 connected to the input control circuit 132. When the latch control signal LTCT is inactive, the input control circuit 132 inputs the input signal SIN1 to the holding circuit 134. When the latch control signal LTCT is active, the input control circuit 132 blocks the input of the input signal SIN1 to the holding circuit 134.

[0030] According to this embodiment, based on the signal control of the signal output circuit 150 described above, when the input control circuit 132 is blocking the input signal SIN1, the power supply switching circuit 110 switches the voltage VQ of the power line LQ of the latch control circuit 120 and latch circuit 130-1 from the first power supply voltage V1 to the second power supply voltage V2. As a result, the power supply voltage is switched while latch circuit 130-1 is unaffected by changes in the input signal SIN1, so the output level of latch circuit 130-1 is appropriately level-shifted.

[0031] In this embodiment, the holding circuit 134 allows the input signal SIN1 input from the input control circuit 132 to pass through when the latch control signal LTCT is inactive. When the latch control signal LTCT is active, the holding circuit 134 holds the input signal SIN1 that was input when the latch control signal LTCT was inactive.

[0032] According to this embodiment, based on the signal control of the signal output circuit 150 described above, when the input control circuit 132 blocks the input signal SIN1 and the holding circuit 134 holds the signal, the power supply switching circuit 110 switches the voltage VQ of the power line LQ of the latch control circuit 120 and latch circuit 130-1 from the first power supply voltage V1 to the second power supply voltage V2. As a result, the power supply voltage is switched while the latch circuit 130-1 is not affected by changes in the input signal SIN1 and is in a stable state with the latch circuit 130-1 latching the signal, so the output level of the latch circuit 130-1 is appropriately level-shifted.

[0033] In this embodiment, when the control signal CNT changes from active to inactive, the signal output circuit 150 outputs a power control signal LCNT indicating a switch from the second power supply voltage V2 to the first power supply voltage V1, and then changes the latch signal LLAT from active to inactive.

[0034] In this embodiment, when the signal output circuit 150 outputs a power control signal LCNT indicating a switch from the second power supply voltage V2 to the first power supply voltage V1, the latch circuit 130-1 holds the latched input signal SIN1. Also, the power switching circuit 110 switches the voltage VQ of the power line LQ from the second power supply voltage V2 to the first power supply voltage V1. When the power switching circuit 110 is supplying the first power supply voltage V1 to the power line LQ, the signal output circuit 150 changes the latch signal LLAT from active to inactive, and the latch circuit 130-1 changes from a state where it latches the input signal SIN1 to a state where it allows it to pass through.

[0035] According to these embodiments, the power supply voltage does not switch when the latch circuit 130-1 is allowing a signal to pass through, and the power supply voltage switches when the latch circuit 130-1 is in a stable state where it has latched a signal.

[0036] In this embodiment, the circuit device 100 also includes a control circuit 190 that outputs a control signal CNT.

[0037] According to this embodiment, the signal output circuit 150 can control the power control signal LCNT and the latch signal LLAT based on the control signal CNT from the control circuit 190.

[0038] 2. Detailed Configuration Example The following describes an example in which the circuit device 100 shown in Figure 1 is used for word line control of a memory circuit. However, the circuit device 100 shown in Figure 1 can be used for various applications that involve shifting signal levels between circuits with different power supplies.

[0039] Figure 4 shows a detailed configuration example of the circuit device 100. The circuit device 100 includes a control circuit 190, a word line control circuit 192, and a memory circuit 194.

[0040] The control circuit 190 outputs a write control signal PGM, an erase control signal ERS, and word line control signals DEC1 to DECn. The write control signal PGM or the erase control signal ERS corresponds to the control signal CNT in Figure 1, and the word line control signals DEC1 to DECn correspond to the input signals SIN1 to SINn in Figure 1.

[0041] The word line control circuit 192 corresponds to the power switching circuit 110, latch control circuit 120, latch circuits 130-1 to 130-n, and signal output circuit 150 in Figure 1. The word line control circuit 192 outputs word line selection signals WL1 to WLn, which correspond to the output signals SQ1 to SQn in Figure 1. A detailed configuration example of the word line control circuit 192 will be described later in Figure 6, etc.

[0042] The memory circuit 194 is a memory circuit in which a word line is selected by word line selection signals WL1 to WLn. The memory circuit 194 is a non-volatile memory that can be electrically written to and erased, such as an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0043] Figure 5 is a table showing the operating modes of the memory circuit 194. In standby mode, all word lines are unselected, and their word line selection signal is the ground voltage GND. In read mode, the word line selection signal for selected word lines is the power supply voltage VDD, and the word line selection signal for unselected word lines is the ground voltage GND. The power supply voltage VDD and ground voltage GND are at the same potential as, for example, the power supply voltage and ground voltage of the control circuit 190. In write mode, the word line control signal for selected word lines is the write voltage VPP, which is higher than the power supply voltage VDD, and the word line selection signal for unselected word lines is the ground voltage GND. In erase mode, the word line selection signal for selected word lines is the negative erase voltage VNN, which is lower than the ground voltage GND, and the word line selection signal for unselected word lines is the power supply voltage VDD.

[0044] Figure 6 shows a first detailed configuration example of the word line control circuit 192. This configuration example relates to data writing control to the memory circuit 194. In this configuration example, the write control signal PGM corresponds to the control signal CNT. The power supply control feedback signal SWP corresponds to the power supply control feedback signal SW. The word line control signals DEC1 to DECn correspond to the input signals SIN1 to SINn, and the word line selection signals WL1 to WLn correspond to the output signals SQ1 to SQn. The power supply voltage VDD corresponds to the first power supply voltage V1, the write voltage VPP corresponds to the second power supply voltage V2, and the voltage VPW of the power supply line LPW corresponds to the voltage VQ of the power supply line LQ.

[0045] The word line control circuit 192 includes a power switching circuit 110, a latch control circuit 120, latch circuits 130-1 to 130-n, and a signal output circuit 150. The signal output circuit 150 is constructed from circuit elements of a low-voltage (LV) process. The power switching circuit 110, the latch control circuit 120, and the latch circuits 130-1 to 130-n are constructed from circuit elements of a high-voltage (HV) process.

[0046] The signal output circuit 150 is a circuit that performs preprocessing on signals from the control circuit 190. The signal output circuit 150 includes NAND gates 10, 80-1 to 80-n, a NOR gate 30, and inverter gates 11, 31, 81-1 to 81-n.

[0047] The NAND circuit 10 receives the write control signal PGM and the latch control feedback signal LT, and outputs the negative logical AND of the write control signal PGM and the latch control feedback signal LT as the signal LXPGM. The inverter circuit 11 receives the signal LXPGM and outputs the signal LPGM, which is the inverted logic of the signal LXPGM. The high level of signals LPGM and LXPGM corresponds to the power supply voltage VDD, and the low level corresponds to the ground voltage GND. Signals LPGM and LXPGM correspond to the power supply control signal LCNT in Figure 1, and hereafter, signals LPGM and LXPGM will be referred to as power supply control signals.

[0048] The NOR circuit 30 receives the write control signal PGM and the power control feedback signal SWP, and outputs the signal LXLAT as the negated logical OR of the write control signal PGM and the power control feedback signal SWP. The inverter circuit 31 receives the signal LXLAT and outputs a latch signal LLAT, which is the inverted logic of the signal LXLAT. The high level of the latch signal LLAT and the signal LXLAT is the power supply voltage VDD, and the low level is the ground voltage GND. Hereafter, the signal LXLAT will also be referred to as a latch signal.

[0049] NAND gate 80-1 and inverter gate 81-1 receive the word line control signal DEC1 and output the signal LWL1. Similarly, NAND gates 80-2 to 80-n and inverter gates 81-2 to 81-n receive the word line control signals DEC2 to DECn and output the signals LWL2 to LWLn. NAND gates 80-1 to 80-n correspond to, for example, a decoder that decodes the word line address signal, or the final stage of a decoder. The high level of signals LWL1 to LWLn is the power supply voltage VDD, and the low level is the ground voltage GND. Hereafter, signals LWL1 to LWLn will also be referred to as word line control signals or input signals.

[0050] The power switching circuit 110 switches the voltage VVPW of the power line LPW to the power supply voltage VDD or the write voltage VPP according to the logic levels of the power control signals LPGM and LXPGM. The power switching circuit 110 level-shifts the power control signals LPGM and LXPGM to signals of the voltage level of the power line LPW, and outputs a power control feedback signal SWP based on the level-shifted signal.

[0051] The latch control circuit 120 and latch circuits 130-1 to 130-n are supplied with the voltage VPW of the power line LPW as the high-potential side power supply voltage, and the ground voltage GND as the low-potential side power supply voltage.

[0052] The latch control circuit 120 outputs latch control signals HLAT and HXLAT based on latch signals LLAT and LXLAT. HLAT is based on the same logic as LLAT, and HXLAT is based on the same logic as LXLAT. The high level of the latch control signals HLAT and HXLAT corresponds to the voltage VPW of the power line LPW, and the low level corresponds to the ground voltage GND. The latch control circuit 120 level-shifts the latch signal LLAT to a signal at the voltage level of the power line LPW, and outputs a latch control feedback signal LT based on the level-shifted signal.

[0053] Latch circuit 130-1 allows or latches word line control signal LWL1 depending on the logic level of latch control signals HLAT and HXLAT, and outputs the allowed or latched signal as word line selection signal WL1. Similarly, latch circuits 130-2 to 130-n allow or latch word line control signals LWL2 to LWLn depending on the logic level of latch control signals HLAT and HXLAT, and outputs the allowed or latched signals as word line selection signals WL2 to WLn. The high level of word line selection signals WL1 to WLn corresponds to the voltage VPW of the power line LPW, and the low level corresponds to the ground voltage GND.

[0054] Figure 7 shows an example configuration of the power supply switching circuit 110 in the first detailed configuration example of the word line control circuit 192. The power supply switching circuit 110 includes a level shifter 111, inverter circuits 12, 13, and 14, and P-type MOS transistors MP8 and MP9.

[0055] The level shifter 111 and inverter circuits 12 and 13 are supplied with a writing voltage VPP as the high-potential side power supply voltage and a ground voltage GND as the low-potential side power supply voltage. The level shifter 111 includes P-type MOS transistors MP0 and MP1 and N-type MOS transistors MN0 and MN1. The P-type MOS transistors MP0 and MP1 are load transistors, and their gates and drains are cross-connected to each other. The N-type MOS transistor MN0 is the drive transistor for the P-type MOS transistor MP0, and a power control signal LXPGM is input to its gate. The N-type MOS transistor MN1 is the drive transistor for the P-type MOS transistor MP1, and a power control signal LPGM is input to its gate. The level shifter 111 outputs output signals from the drains of the P-type MOS transistor MP1 and the N-type MOS transistor MN1. The inverter circuit 12 logically inverts the output signal of the level shifter 111. The inverter circuit 13 logically inverts the output signal of the inverter circuit 12.

[0056] The source of the P-type MOS transistor MP8 is connected to the node with the power supply voltage VDD, and its drain is connected to the power line LPW. The output signal of inverter circuit 12 is input to the gate of the P-type MOS transistor MP8. The source of the P-type MOS transistor MP9 is connected to the node with the write voltage VPP, and its drain is connected to the power line LPW. The output signal of inverter circuit 13 is input to the gate of the P-type MOS transistor MP9. When the power control signal LPGM is low level, the P-type MOS transistor MP8 is on and the P-type MOS transistor MP9 is off. This connects the node with the power supply voltage VDD to the power line LPW via the P-type MOS transistor MP8. When the power control signal LPGM is high level, the P-type MOS transistor MP8 is off and the P-type MOS transistor MP9 is on. This connects the node with the write voltage VPP to the power line LPW via the P-type MOS transistor MP9.

[0057] The inverter circuit 14 is supplied with the power supply voltage VDD as the high-potential side power supply voltage and the ground voltage GND as the low-potential side power supply voltage. The inverter circuit 14 logically inverts the output signal of the inverter circuit 13 and outputs the result as a power control feedback signal SWP.

[0058] Figure 8 shows an example configuration of the latch control circuit 120 in a first detailed configuration example of the word line control circuit 192. The latch control circuit 120 includes a level shifter 121 and inverter circuits 50, 51, and 52.

[0059] The level shifter 121 and inverter circuits 50 and 51 are supplied with the voltage VPW of the power line LPW as the high-potential side power supply voltage and the ground voltage GND as the low-potential side power supply voltage. The level shifter 121 includes P-type MOS transistors MP2 and MP3 and N-type MOS transistors MN2 and MN3. The P-type MOS transistors MP2 and MP3 are load transistors, and their gates and drains are cross-connected to each other. The N-type MOS transistor MN2 is the driving transistor for the P-type MOS transistor MP2, and a latch signal LXLAT is input to its gate. The N-type MOS transistor MN3 is the driving transistor for the P-type MOS transistor MP3, and a latch signal LLAT is input to its gate. The level shifter 121 outputs output signals from the drains of the P-type MOS transistor MP3 and the N-type MOS transistor MN3. The inverter circuit 50 logically inverts the output signals of the level shifter 121 and outputs the result as a latch control signal HLAT. The inverter circuit 51 logically inverts the output signal of the inverter circuit 50 and outputs the result as a latch control signal HXLAT.

[0060] The inverter circuit 52 is supplied with the power supply voltage VDD as the high-potential side power supply voltage and the ground voltage GND as the low-potential side power supply voltage. The inverter circuit 52 logically inverts the output signal of the inverter circuit 51 and outputs the result as a latch control feedback signal LT.

[0061] Figure 9 shows an example configuration of latch circuit 130-1 in the first detailed configuration example of the word line control circuit 192. Latch circuit 130 includes clocked inverter circuits 82 and 84, and inverter circuits 83, 85, and 86. Latch circuits 130-2 to 130-n have a similar configuration. Clocked inverter circuit 82 corresponds to the input control circuit 132 in Figure 2, and clocked inverter circuit 84 and inverter circuits 83, 85, and 86 correspond to the holding circuit 134 in Figure 2. Note that inverter circuits 85 and 86 may be omitted.

[0062] The clocked inverter circuits 82 and 84 and inverter circuits 83, 85, and 86 are supplied with the voltage VPW of the power line LPW as the high-potential power supply voltage and the ground voltage GND as the low-potential power supply voltage. The clocked inverter circuits 82 and inverter circuits 83, 85, and 86 are connected in series between the input node and the output node of the latch circuit 130-1, in that order. The input node of inverter circuit 83 is node L1 and the output node is node L2. The input node of clocked inverter circuit 84 is connected to node L2 and the output node is connected to node L1. The latch control signals HLAT and HXLAT are input to the clocked inverter circuits 82 and 84, and the passing and blocking of the signal are controlled by these latch control signals HLAT and HXLAT. When the latch control signal HLAT is at a low level, the clocked inverter circuit 82 allows the signal to pass through and the clocked inverter circuit 84 blocks the signal. As a result, the latch circuit 130-1 allows the word line control signal LWL1 to pass through. When the latch control signal HLAT is at a high level, the clocked inverter circuit 82 blocks the signal, and the clocked inverter circuit 84 allows the signal to pass through. As a result, the latch circuit 130-1 latches the word line control signal LWL1.

[0063] Figure 10 is an example timing chart illustrating the operation of the first detailed configuration example of the word line control circuit 192. While Figure 10 uses the operation of latch circuit 130-1 as an example, the operation of latch circuits 130-2 to 130-n is similar.

[0064] The control circuit 190 updates the word line control signal DEC1 at a predetermined interval. As a result, the word line control signal LWL1 input to the latch circuit 130-1 is updated at a predetermined interval. The control circuit 190 outputs a low-level write control signal PGM before and after the timing of updating the word line control signal DEC1. As a result, the power supply switching circuit 110 selects the power supply voltage VDD as the voltage VPW of the power supply line LPW.

[0065] After updating the word line control signal DEC1, the control circuit 190 sets the write control signal PGM from low to high. Since the power control feedback signal SWP and the latch control feedback signal LT are low, the power control signal LPGM remains low, and the latch signal LLAT goes from low to high. In response, the latch control circuit 120 sets the latch control signal HLAT from low to high and the latch control signal HXLAT from high to low. The high levels of the latch control signals HLAT and HXLAT correspond to the power supply voltage VDD.

[0066] In response to the transitions of the latch control signals HLAT and HXLAT, the latch circuit 130-1 switches from a state that allows the word line control signal LWL1 to pass through to a state that holds it. When the word line control signal LWL1 is low level, the latch circuit 130-1 outputs a word line selection signal WL1 with ground voltage GND, and when the word line control signal LWL1 is high level, it outputs a word line selection signal WL1 with power supply voltage VDD.

[0067] When the latch control signal HXLAT changes from a high level to a low level, the latch control feedback signal LT changes from a low level to a high level. Since the write control signal PGM is at a high level, the power control signal LPGM changes from a low level to a high level. As a result, the power switching circuit 110 switches the voltage VPW of the power line LPW from the power supply voltage VDD to the write voltage VPP. In response, the latch control signal HLAT changes from the power supply voltage VDD to the write voltage VPP. If the word line selection signal WL1 is at a high level, it changes from the power supply voltage VDD to the write voltage VPP. As shown by the dotted arrow, the sequence is guaranteed that the latch circuit 130-1 latches the input signal SIN1, and then the power supply voltage of the latch circuit 130-1 switches to the write voltage VPP.

[0068] Next, the control circuit 190 changes the write control signal PGM from a high level to a low level. This causes the power control signal LPGM to change from a high level to a low level. The power switching circuit 110 switches the voltage VVPW of the power line LPW from the write voltage VPP to the power supply voltage VDD. In response, the latch control signal HLAT changes from the write voltage VPP to the power supply voltage VDD. If the word line selection signal WL1 is high level, it changes from the write voltage VPP to the power supply voltage VDD.

[0069] When the voltage VPW switches to the power supply voltage VDD, meaning the gate signal of the P-type MOS transistor MP9 changes from low to high, the power supply control feedback signal SWP changes from high to low. Since the write control signal PGM is low, the latch signal LLAT changes from high to low. In response, the latch control circuit 120 changes the latch control signal HLAT from high to low and the latch control signal HXLAT from low to high.

[0070] Following the transitions of the latch control signals HLAT and HXLAT, the latch circuit 130-1 switches from a state of holding the word line control signal LWL1 to a state of allowing it to pass through. As shown by the dotted arrow, the sequence is guaranteed that the power supply voltage of the latch circuit 130-1 switches to the power supply voltage VDD, and then the latch circuit 130-1 enters a state of allowing the input signal SIN1 to pass through. Next, the control circuit 190 updates the word line control signal DEC1. Thereafter, the word line control circuit 192 repeats the same operation.

[0071] Figure 11 shows a second detailed configuration example of the word line control circuit 192. The following explanation will primarily focus on the differences from the first detailed configuration example, omitting explanations of parts similar to the first detailed configuration example as appropriate. This configuration example relates to the data erase control of the memory circuit 194. In this configuration example, the erase control signal ERS corresponds to the control signal CNT. The power supply control feedback signal XSWN corresponds to the power supply control feedback signal SW. Furthermore, the ground voltage GND corresponds to the first power supply voltage V1, the erase voltage VNN corresponds to the second power supply voltage V2, and the voltage VNW of the power line LNW corresponds to the voltage VQ of the power line LQ.

[0072] The signal output circuit 150 includes NAND circuits 20, 80-1 to 80-n, a NOR circuit 32, and inverter circuits 21, 25, 31, 81-1 to 81-n.

[0073] The NAND gate 20 receives the erase control signal ERS and the latch control feedback signal LT, and outputs the signal LXERS as the negative logical AND of the erase control signal ERS and the latch control feedback signal LT. The inverter gate 21 receives the signal LXERS and outputs the signal LERS, which is the inverted logic of the signal LXERS. The high level of signals LXERS and LERS corresponds to the power supply voltage VDD, and the low level corresponds to the ground voltage GND. Signals LERS and LXERS correspond to the power supply control signal LCNT in Figure 1, and hereafter, signals LERS and LXERS will be referred to as power supply control signals.

[0074] The inverter circuit 25 inverts the logic of the power control feedback signal XSWN and outputs the signal SWN. Hereafter, the signal SWN will also be referred to as the power control feedback signal. The NOR circuit 32 receives the erase control signal ERS and the power control feedback signal SWN and outputs the negated logical OR of the erase control signal ERS and the power control feedback signal SWN as the signal LXLAT. The inverter circuit 31 receives the signal LXLAT and outputs the latch signal LLAT, which is the inverted logic of the signal LXLAT. The high level of the latch signal LLAT and the signal LXLAT is the power supply voltage VDD, and the low level is the ground voltage GND. Hereafter, the signal LXLAT will also be referred to as the latch signal.

[0075] The power switching circuit 110 switches the voltage VNW of the power line LNW to the ground voltage GND or the erase voltage VNN according to the logic levels of the power control signals LERS and LXERS. The power switching circuit 110 level-shifts the power control signals LERS and LXERS to the voltage level signals of the power line LNW, and outputs a power control feedback signal XSWN based on the level-shifted signal.

[0076] The latch control circuit 120 and latch circuits 130-1 to 130-n are supplied with the power supply voltage VDD as the high-potential side power supply voltage and the voltage VNW of the power line LNW as the low-potential side power supply voltage. That is, the high level of the latch control signals HLAT, HXLAT and word line selection signals WL1 to WLn is the power supply voltage VDD, and the low level is the voltage VNW of the power line LNW. The latch control circuit 120 level-shifts the latch signal LLAT to a signal of the voltage level of the power line LNW, and outputs a latch control feedback signal LT based on the level-shifted signal.

[0077] Figure 12 shows an example configuration of the power supply switching circuit 110 in a second detailed configuration example of the word line control circuit 192. The power supply switching circuit 110 includes a level shifter 112, inverter circuits 22, 23, and 24, and N-type MOS transistors MN8 and MN9.

[0078] The level shifter 112 and inverter circuits 22 and 23 are supplied with a power supply voltage VDD as the high-potential side power supply voltage and an erase voltage VNN as the low-potential side power supply voltage. The level shifter 112 includes P-type MOS transistors MP4 and MP5 and N-type MOS transistors MN4 and MN5. The N-type MOS transistors MN4 and MN5 are load transistors, and their gates and drains are cross-connected to each other. The P-type MOS transistor MP4 is the driving transistor for the N-type MOS transistor MN4, and a power control signal LERS is input to its gate. The P-type MOS transistor MP5 is the driving transistor for the N-type MOS transistor MN5, and a power control signal LXERS is input to its gate. The level shifter 112 outputs an output signal ERLSQ from the drains of the P-type MOS transistor MP5 and the N-type MOS transistor MN5. The inverter circuit 22 logic inverts the output signal ERLSQ of the level shifter 112. The inverter circuit 23 logically inverts the output signal of the inverter circuit 22.

[0079] The source of the N-type MOS transistor MN8 is connected to the node with ground voltage GND, and its drain is connected to the power line LNW. The output signal of inverter circuit 22 is input to the gate of the N-type MOS transistor MN8. The source of the N-type MOS transistor MN9 is connected to the node with erase voltage VNN, and its drain is connected to the power line LNW. The output signal of inverter circuit 23 is input to the gate of the N-type MOS transistor MN9. When the power control signal LERS is low level, the N-type MOS transistor MN8 is on and the N-type MOS transistor MN9 is off. This connects the node with ground voltage GND and the power line LNW via the N-type MOS transistor MN8. When the power control signal LERS is high level, the N-type MOS transistor MN8 is off and the N-type MOS transistor MN9 is on. This connects the node with erase voltage VNN and the power line LNW via the N-type MOS transistor MN9.

[0080] The inverter circuit 24 is supplied with the power supply voltage VDD as the high-potential power supply voltage and the ground voltage GND as the low-potential power supply voltage. The inverter circuit 24 logically inverts the output signal of the inverter circuit 23 and outputs the result as the power control feedback signal XSWN.

[0081] Figure 13 shows an example configuration of the latch control circuit 120 in a second detailed configuration example of the word line control circuit 192. The latch control circuit 120 includes a level shifter 122 and inverter circuits 50, 51, and 52.

[0082] The level shifter 122 and inverter circuits 50 and 51 are supplied with a power supply voltage VDD as the high-potential side power supply voltage and with the voltage VNW of the power line LNW as the low-potential side power supply voltage. The level shifter 122 includes P-type MOS transistors MP6 and MP7 and N-type MOS transistors MN6 and MN7. The N-type MOS transistors MN6 and MN7 are load transistors, and their gates and drains are cross-connected to each other. The P-type MOS transistor MP6 is the driving transistor for the N-type MOS transistor MN6, and a latch signal LXLAT is input to its gate. The P-type MOS transistor MP7 is the driving transistor for the N-type MOS transistor MN7, and a latch signal LLAT is input to its gate. The level shifter 122 outputs output signals from the drains of the P-type MOS transistor MP7 and the N-type MOS transistor MN7.

[0083] Figure 14 shows an example configuration of latch circuit 130-1 in a second detailed configuration example of the word line control circuit 192. Latch circuits 130-2 to 130-n have a similar configuration.

[0084] The clocked inverter circuits 82 and 84 and the inverter circuits 83, 85, and 86 are supplied with the power supply voltage VDD as the high-potential side power supply voltage and the voltage VNW of the power line LNW as the low-potential side power supply voltage. The clocked inverter circuit 82 and the inverter circuits 85 and 86 are connected in series between the input node and the output node of the latch circuit 130-1, in that order. Node L1, which is the input node of inverter circuit 83, is connected to the output node of clocked inverter circuit 82 and the input node of inverter circuit 85. In this example, the word line selection signal WL1 is the logic inversion signal of the word line control signal LWL1.

[0085] Figure 15 is an example timing chart illustrating the operation of the second detailed configuration example of the word line control circuit 192. While Figure 15 uses the operation of latch circuit 130-1 as an example, the operation of latch circuits 130-2 to 130-n is similar.

[0086] The control circuit 190 outputs a low-level erase control signal ERS before and after updating the word line control signal DEC1. As a result, the power supply switching circuit 110 selects the ground voltage GND as the voltage VNW of the power line LNW.

[0087] After updating the word line control signal DEC1, the control circuit 190 sets the erase control signal ERS from low to high. Since the power control feedback signal SWN and the latch control feedback signal LT are low, the power control signal LERS remains low, and the latch signal LLAT goes from low to high. In response, the latch control circuit 120 sets the latch control signal HLAT from low to high and the latch control signal HXLAT from high to low. The low level of the latch control signals HLAT and HXLAT is the ground voltage GND.

[0088] In response to the transitions of the latch control signals HLAT and HXLAT, the latch circuit 130-1 switches from a state that allows the word line control signal LWL1 to pass through to a state that holds it. When the word line control signal LWL1 is high level, the latch circuit 130-1 outputs a word line selection signal WL1 with the ground voltage GND, and when the word line control signal LWL1 is low level, it outputs a word line selection signal WL1 with the power supply voltage VDD.

[0089] When the latch control signal HXLAT changes from a high level to a low level, the latch control feedback signal LT changes from a low level to a high level. Since the erase control signal ERS is at a high level, the power supply control signal LERS changes from a low level to a high level. As a result, the power supply switching circuit 110 switches the voltage VNW of the power supply line LNW from the ground voltage GND to the erase voltage VNN. In response, the latch control signal HXLAT changes from the ground voltage GND to the erase voltage VNN. If the word line selection signal WL1 is at a low level, it changes from the ground voltage GND to the erase voltage VNN. As shown by the dotted arrow, the sequence is guaranteed that the latch circuit 130-1 latches the input signal SIN1, and then the low-potential side power supply voltage of the latch circuit 130-1 switches to the erase voltage VNN.

[0090] Next, the control circuit 190 changes the erase control signal ERS from a high level to a low level. This causes the power control signal LERS to change from a high level to a low level. The power switching circuit 110 switches the voltage VNW of the power line LNW from the erase voltage VNN to the ground voltage GND. In response, the latch control signal HXLAT changes from the erase voltage VNN to the ground voltage GND. If the word line selection signal WL1 is at a low level, it changes from the erase voltage VNN to the ground voltage GND.

[0091] When the voltage VNW switches to the ground voltage GND, meaning the gate signal of the N-type MOS transistor MN9 changes from high to low, the power supply control feedback signal SWN changes from high to low. Since the erase control signal ERS is low, the latch signal LLAT changes from high to low. In response, the latch control circuit 120 changes the latch control signal HLAT from high to low and the latch control signal HXLAT from low to high.

[0092] Following the transitions of the latch control signals HLAT and HXLAT, the latch circuit 130-1 switches from a state of holding the word line control signal LWL1 to a state of allowing it to pass through. As shown by the dotted arrow, the sequence is guaranteed that the low-potential side power supply voltage of the latch circuit 130-1 switches to the ground voltage GND, and then the latch circuit 130-1 enters a state of allowing the input signal SIN1 to pass through. Next, the control circuit 190 updates the word line control signal DEC1. Thereafter, the word line control circuit 192 repeats the same operation.

[0093] Figure 16 shows a third detailed configuration example of the word line control circuit 192. The following explanation will primarily focus on the differences from the first or second detailed configuration example, while explanations of parts similar to the first or second detailed configuration example will be omitted as appropriate. This configuration example is for a case where both data writing control and data erasure control of the memory circuit 194 are performed.

[0094] The power switching circuit 110 switches the voltage VVPW of the power line LPW to the power supply voltage VDD or the write voltage VPP according to the logic level of the power control signals LPGM and LXPGM. The power switching circuit 110 level-shifts the power control signals LPGM and LXPGM to the voltage level of the power line LPW and outputs a power control feedback signal SWP based on the level-shifted signal. The power switching circuit 110 also switches the voltage VNW of the power line LNW to the ground voltage GND or the erase voltage VNN according to the logic level of the power control signals LERS and LXERS. The power switching circuit 110 level-shifts the power control signals LERS and LXERS to the voltage level of the power line LNW and outputs a power control feedback signal XSWN based on the level-shifted signal.

[0095] The latch control circuit 120 is supplied with the power supply voltage VDD and the voltage VPW of the power line LPW as the high-potential side power supply voltage, and the voltage VNW of the power line LNW as the low-potential side power supply voltage.

[0096] The latch control circuit 120 outputs latch control signals HLAT and HXLAT based on the latch signals LLAT and LXLAT. The latch control circuit 120 also outputs erase latch control signals HERS and HXERS based on the logic level of the power control signal LERS. Specifically, the power switching circuit 110 includes the level shifter 112 shown in Figure 12, and the latch control circuit 120 outputs latch control signals HLAT and HXLAT based on the output signal ERLSQ of the level shifter 112. HERS has the same logic as LERS, and HXERS is the inverse logic of LERS. The high levels of the latch control signals HLAT and HXLAT and the erase latch control signals HERS and HXERS correspond to the voltage VPW of the power line LPW, and the low levels correspond to the voltage VNW of the power line LNW.

[0097] Latch circuit 130-1 allows or latches word line control signal LWL1 depending on the logic level of the latch control signals HLAT and HXLAT, and outputs the allowed or latched signal as word line selection signal WL1. Similarly, latch circuits 130-2 to 130-n allow or latch word line control signals LWL2 to LWLn depending on the logic level of the latch control signals HLAT and HXLAT, and outputs the allowed or latched signals as word line selection signals WL2 to WLn. In addition, latch circuits 130-1 to 130-n switch circuit connections depending on the logic level of the erase latch control signals HERS and HXERS. The high level of word line selection signals WL1 to WLn corresponds to the voltage VPW of the power line LPW, and the low level corresponds to the voltage VNW of the power line LNW.

[0098] The power switching circuit 110 in the third detailed configuration example of the word line control circuit 192 includes both the first detailed configuration example in Figure 7 and the second detailed configuration example in Figure 12.

[0099] Figure 17 shows an example configuration of the signal output circuit 150 in a third detailed configuration example of the word line control circuit 192. The signal output circuit 150 includes NAND circuits 10, 20, 80-1 to 80-n, NOR circuits 30, 32, 47, and inverter circuits 11, 21, 25, 48, 81-1 to 81-n.

[0100] The NOR circuit 47 receives the output signals from the NOR circuit 30 and the NOR circuit 32, and outputs the negated OR of the output signals from the NOR circuit 30 and the NOR circuit 32 as a latch signal LLAT. The inverter circuit 48 receives the latch signal LLAT and outputs a latch signal LXLAT, which is the inverted logic of the latch signal LLAT.

[0101] Figure 18 shows an example configuration of the latch control circuit 120 in a third detailed configuration example of the word line control circuit 192. The latch control circuit 120 includes level shifters 121 and 122, and inverter circuits 50, 51, 52, 60, and 61.

[0102] The level shifter 122 is supplied with the power supply voltage VDD as the high-potential side power supply voltage, and the voltage VNW of the power line LNW as the low-potential side power supply voltage. The level shifter 121 and inverter circuits 50, 51, 60, and 61 are supplied with the voltage VPW of the power line LPW as the high-potential side power supply voltage, and the voltage VNW of the power line LNW as the low-potential side power supply voltage.

[0103] In level shifter 122, the latch signal LXLAT is input to the gate of P-type MOS transistor MP6, and the latch signal LLAT is input to the gate of P-type MOS transistor MP7. In level shifter 121, signals are input to the gate of N-type MOS transistor MN2 from the drains of P-type MOS transistor MP7 and N-type MOS transistor MN7 in level shifter 122. Signals are input to the gate of N-type MOS transistor MN3 from the drains of P-type MOS transistor MP6 and N-type MOS transistor MN6 in level shifter 122. Level shifter 121 outputs output signals from the drains of P-type MOS transistor MP3 and N-type MOS transistor MN3. Inverter circuit 50 logically inverts the output signal of level shifter 121 and outputs the result as a latch control signal HLAT. Inverter circuit 51 logically inverts the output signal of inverter circuit 50 and outputs the result as a latch control signal HXLAT.

[0104] Inverter circuit 60 logically inverts the output signal ERLSQ of the level shifter 112 of the power switching circuit 110 and outputs the result as an erase latch control signal HXERS. Inverter circuit 61 logically inverts the output signal of inverter circuit 60 and outputs the result as an erase latch control signal HERS.

[0105] Figure 19 shows an example configuration of latch circuit 130-1 in the third detailed configuration example of the word line control circuit 192. Latch circuit 130 includes clocked inverter circuits 82 and 84, inverter circuits 83, 85 and 86, and transfer gates TG10 and TG11. Latch circuits 130-2 to 130-n have a similar configuration.

[0106] The clocked inverter circuits 82 and 84 and the inverter circuits 83, 85, and 86 are supplied with the voltage VPW from power line LPW as the high-potential power supply voltage and the voltage VNW from power line LNW as the low-potential power supply voltage. The clocked inverter circuit 82, inverter circuit 83, transfer gate TG10, and inverter circuits 85 and 86 are connected in series between the input node and output node of latch circuit 130-1, in that order. The transfer gate TG11 is connected between node L1, which is the input node of inverter circuit 83, and the input node of inverter circuit 85.

[0107] Transfer gate TG10 includes a parallel-connected P-type MOS transistor MP10 and an N-type MOS transistor MN10. Transfer gate TG11 includes a parallel-connected P-type MOS transistor MP11 and an N-type MOS transistor MN11. The gates of the P-type MOS transistor MP10 and the N-type MOS transistor MN11 are input to the erase latch control signal HERS. The gates of the N-type MOS transistor MN10 and the P-type MOS transistor MP11 are input to the erase latch control signal HXERS. When the erase latch control signal HERS is low level, transfer gate TG10 is on and transfer gate TG11 is off. This corresponds to the connection shown in the first detailed configuration example in Figure 9. When the erase latch control signal HERS is high level, transfer gate TG10 is off and transfer gate TG11 is on. This corresponds to the connection shown in the second detailed configuration example in Figure 14.

[0108] Figure 20 is an example timing chart illustrating the operation of the third detailed configuration example of the word line control circuit 192. While Figure 20 uses the operation of latch circuit 130-1 as an example, the operation of latch circuits 130-2 to 130-n is similar.

[0109] In the example shown in Figure 20, the control circuit 190 updates the word line control signal DEC1, then performs the data write control described in the first detailed configuration example in Figure 10, and then updates the word line control signal DEC1 again, followed by the data erase control described in the second detailed configuration example in Figure 15. However, data writing and data erasure do not need to be performed consecutively. The data erase control is basically the same as in the second detailed configuration example in Figure 15, but the switching by transfer gates TG10 and TG11 is different. That is, when the control circuit 190 changes the erase control signal ERS from a low level to a high level, transfer gate TG10 changes from on to off, and transfer gate TG11 changes from off to on. This inverts the logic of the word line selection signal WL1. When the control circuit 190 changes the erase control signal ERS from a high level to a low level, transfer gate TG10 changes from off to on, and transfer gate TG11 changes from on to off. This cancels the logic inversion of the word line selection signal WL1.

[0110] The fourth detailed configuration example of the word line control circuit 192 is basically the same as the third detailed configuration example, but the configuration of the latch control circuit 120 is different. Figure 21 shows an example of the configuration of the latch control circuit 120 in the fourth detailed configuration example of the word line control circuit 192. In the fourth detailed configuration example, the latch control circuit 120 includes an inverter circuit 49 instead of the level shifters 121 and 122 of the latch control circuit 120 in the third detailed configuration example of the latch control circuit 120 in Figure 18.

[0111] The inverter circuit 49 is supplied with the power supply voltage VDD as the high-potential side power supply voltage, and the voltage VNW of the power line LNW as the low-potential side power supply voltage. The inverter circuit 49 is input with the latch signal LLAT from the signal output circuit 150. That is, the inverter circuit 48 of the signal output circuit 150 in the third detailed configuration example of Figure 17 is omitted.

[0112] As shown in Figure 20, when the latch signal LLAT (≒LT) is at a low level, the voltage VPW of the power line LPW is the power supply voltage VDD, and the voltage VNW of the power line LNW is the ground voltage GND. In this case, the signal is transmitted in the latch control circuit 120 without level shifting, so there is no need to consider level shifting. As shown in Figure 20, when the latch signal LLAT (≒LT) is at a high level, the voltage VPW of the power line LPW or the voltage VNW of the power line LNW switches. In this case, since the latch signal LLAT is at a high level, the inverter circuit 49 outputs a low level, and the inverter circuit 49 does not output a high level. Therefore, it is only necessary to consider level shifting when the inverter circuit 49 outputs a low level. Level shifting is performed when the inverter circuit 49 outputs the voltage VNW of the power line LNW as a low level, and the inverter circuit 50 receives this and outputs the voltage VPW of the power line LPW as a high level.

[0113] In each embodiment described above, the drive time constant of the power switch and the drive time constant of the latch control signal are set to be approximately the same. For example, in Figure 10, when the voltage VPW changes from VDD to VPP, the high-level latch control signal HLAT changes from VDD to VPP. The time constants of these changes are approximately the same. Also, in Figure 15, when the voltage VNW changes from GND to VNN, the low-level latch control signal HXLAT changes from GND to VNN. The time constants of these changes are approximately the same. In this way, even if the power switching circuit 110 switches the power supply voltage, the logic of the signal latched by the latch circuit 130-1 can be maintained. Details will be explained below. The same applies to latch circuits 130-2 to 130-n.

[0114] The drive time constant is determined by the ratio of the node's load capacitance to the current capability of the transistor driving that node. That is, by adjusting this ratio, the drive time constant of the power switch and the drive time constant of the latch control signal can be set to be approximately the same. For example, in the first detailed configuration example, the drive time constant of the power switch is determined by the ratio of the load capacitance of the power line LPW in Figure 7 to the current capability of the P-type MOS transistor MP9. Also, the drive time constant of the latch control signal HLAT in Figure 8 is determined by the ratio of the load capacitance of the signal line of the latch control signal HLAT to the current capability of the transistor in the inverter circuit 50. Each ratio is set so that these drive time constants are approximately the same.

[0115] Figure 22 shows a detailed configuration example of the clocked inverter circuit 82. The clocked inverter circuit 82 includes P-type MOS transistors MP80 and MP81, and N-type MOS transistors MN81 and MN80. These transistors are connected in series between the power line LPW and the power line LNW, in that order. The gates of the P-type MOS transistor MP80 and the N-type MOS transistor MN80 are input to the word line control signal LWL1. The gate of the P-type MOS transistor MP81 is input to the latch control signal HLAT. The gate of the N-type MOS transistor MN81 is input to the latch control signal HXLAT. When the latch control signal HLAT is inactive, i.e., low level, the clocked inverter circuit 82 is in an enabled state, allowing the signal to pass through. When the latch control signal HLAT is active, i.e., high level, the clocked inverter circuit 82 is in a disabled state, blocking the signal.

[0116] When the power supply switching circuit 110 switches the power supply voltage, the latch control signal HLAT is at a high level and the latch control signal HXLAT is at a low level, so the P-type MOS transistor MP81 and the N-type MOS transistor MN81 are off. However, there is a possibility that the above transistors may not remain off when the power supply is switched. Below, we will compare the cases in which the above transistors cannot remain off and in which they can, using simulation waveforms.

[0117] Figure 23 shows an example of a simulated waveform when the P-type MOS transistor MP81 cannot remain off when the power control signal LPGM changes from a low level to a high level in write mode. Consider the case where the word line control signal LWL1 is high level, i.e., the power supply voltage VDD. When the power control signal LPGM is low level, node L1 is low level, i.e., the ground voltage GND, and node L2 is high level, i.e., the power supply voltage VDD.

[0118] When the power control signal LPGM changes from a low level to a high level, the power switching circuit 110 switches the voltage VPW from the power supply voltage VDD to the write voltage VPP. Consequently, the voltage of the latch control signal HLAT changes from the power supply voltage VDD to the write voltage VPP. If the drive time constant of the latch control signal HLAT is greater than the drive time constant of the voltage VPW, the difference between the voltage VPW and the voltage of the latch control signal HLAT becomes greater than the threshold voltage of the P-type MOS transistor MP81 as the voltage VPW rises to the write voltage VPP. As a result, the P-type MOS transistor MP81 is temporarily turned on. Also, the word line control signal LWL1 is the power supply voltage VDD, and as the voltage VPW rises to the write voltage VPP, the P-type MOS transistor MP80 is turned on. This causes the voltage VPW to be output to node L1, and node L1 changes from the ground voltage GND to the write voltage VPP. In other words, node L1, which was at a low level, changes to a high level, and node L2, which was at a high level, changes to a low level, and the latch circuit 130-1 can no longer maintain logic.

[0119] Figure 24 shows an example of a simulated waveform when the P-type MOS transistor MP81 can remain off when the power control signal LPGM changes from a low level to a high level in write mode. Consider the case where the word line control signal LWL1 is at a high level, i.e., the power supply voltage VDD.

[0120] If the drive time constant of the latch control signal HLAT is approximately the same as the drive time constant of the voltage VPW, then as the voltage VPW rises to the write voltage VPP, the difference between the voltage VPW and the voltage of the latch control signal HLAT remains smaller than the threshold voltage of the P-type MOS transistor MP81. Therefore, the P-type MOS transistor MP81 remains off. This maintains the disconnection between the power line LPW and node L1, and keeps node L1 at the ground voltage GND. That is, node L1 is kept at a low level and node L2 is kept at a high level, so the latch circuit 130-1 can maintain logic. The slight rise in the voltage of node L1 when the voltage VPW rises is due to the voltage drop caused by the current flowing through the power line LNW, or due to capacitive coupling between the power line LPW and node L1.

[0121] Figure 25 shows an example of a simulated waveform when the N-type MOS transistor MN81 cannot remain off when the power control signal LERS changes from a low level to a high level in erase mode. Consider the case where the word line control signal LWL1 is low level, i.e., ground voltage GND. When the power control signal LERS is low level, node L1 is high level, i.e., power supply voltage VDD, and node L2 is low level, i.e., ground voltage GND.

[0122] When the power control signal LERS changes from a low level to a high level, the power switching circuit 110 switches the voltage VNW from the ground voltage GND to the erase voltage VNN. Consequently, the voltage of the latch control signal HXLAT changes from the ground voltage GND to the erase voltage VNN. If the drive time constant of the latch control signal HXLAT is greater than the drive time constant of the voltage VNW, the difference between the voltage VNW and the voltage of the latch control signal HXLAT becomes greater than the threshold voltage of the N-type MOS transistor MN81 as the voltage VNW decreases to the erase voltage VNN. Therefore, the N-type MOS transistor MN81 is temporarily turned on. Also, the word line control signal LWL1 is the ground voltage GND, and as the voltage VNW decreases to the erase voltage VNN, the N-type MOS transistor MN80 is turned on. As a result, the voltage VNW is output to node L1, and node L1 changes from the power supply voltage VDD to the erase voltage VNN. In other words, node L1, which was at a high level, changes to a low level, and node L2, which was at a low level, changes to a high level, causing the latch circuit 130-1 to lose its ability to maintain logic.

[0123] Figure 26 shows an example of a simulated waveform when the N-type MOS transistor MN81 can remain off when the power control signal LERS changes from a low level to a high level in erase mode. Consider the case where the word line control signal LWL1 is at a low level, i.e., the ground voltage GND.

[0124] If the drive time constant of the latch control signal HXLAT is approximately the same as the drive time constant of the voltage VNW, then as the voltage VNW decreases to the erase voltage VNN, the difference between the voltage VNW and the voltage of the latch control signal HXLAT remains smaller than the threshold voltage of the N-type MOS transistor MN81. Therefore, the N-type MOS transistor MN81 remains off. This maintains the disconnection between the power line LNW and node L1, and node L1 remains at the power supply voltage VDD. That is, node L1 is maintained at a high level and node L2 is maintained at a low level, so the latch circuit 130-1 can maintain logic. The slight decrease in the voltage of node L1 when the voltage VNW decreases is due to the voltage drop caused by the current flowing through the power line LPW, or due to capacitive coupling between the power line LNW and node L1.

[0125] Figure 27 shows a first comparative example of this embodiment. Figure 27 shows an example of a circuit configuration and signal waveform when level shifting is performed using a level shifter, rather than a level shift using a latch circuit as in this embodiment. The low level of the input signal IN is the ground voltage GND, and the high level is the power supply voltage VDD. The low level of the output signal OUT is the voltage VNW, and the high level is the voltage VPW. In the signal waveform example, VPW=VDD and VNW=GND.

[0126] In a level shifter, the size of the drive transistor must be larger than the size of the load transistor. Therefore, compared to a latch circuit, which does not require unbalanced transistor sizes, a level shifter requires a larger layout area. If a level shifter like the one shown in Figure 27 is provided for each signal path of the word line control signals LWL1 to LWLn, a large number of level shifters will be required, increasing the layout area of ​​the circuit device 100.

[0127] Furthermore, due to the relatively small size of the load transistor, the rising and falling edges of the signals become unbalanced, leading to a problem of delayed signal transmission. Specifically, as shown in the example signal waveform in Figure 27, the rising edges of signals V1a, V2a, V3a, and OUT are slow in the example circuit configuration. This causes a delay in signal transmission. In memory read mode, VPW=VDD and VNW=GND, so signal level shifting is not necessary, and considering the read speed, faster signal transmission is desirable. However, even in read mode, the word line control signal passes through the level shifter, so the read speed becomes slow due to the delays mentioned above.

[0128] Furthermore, when a level shifter transitions the logic of a signal, a current flows through it that pulls up or down the load transistor using the drive transistor. For example, when many word line control signals change simultaneously, such as in erase mode, a large current flows, resulting in a significant impact. For instance, this can limit the amount of data that can be erased at once, or restrict testing.

[0129] Furthermore, when using a level shifter, the signal is simply level-shifted and passed through, so the output signal OUT reacts sensitively to noise in the input signal IN.

[0130] Figure 28 shows an example of a circuit configuration and signal waveform when level shifting is performed using a latch circuit as in this embodiment.

[0131] In a latch circuit, the driving capabilities of the P-type MOS transistor and the N-type MOS transistor are balanced. Therefore, compared to a level shifter, which requires an imbalance in the driving capabilities of the load transistor and the drive transistor, a latch circuit can require less layout area. When there are many signal paths, such as word line control signals LWL1 to LWLn, a latch circuit can save more layout area than a level shifter.

[0132] Furthermore, because the driving capabilities of the P-type MOS transistors and N-type MOS transistors are balanced, the rising and falling edges of the signals are balanced, resulting in less signal transmission delay. Specifically, as shown in the signal waveform example in Figure 28, the rising and falling edges of signal V1b and the rising and falling edges of the output signal OUT in the circuit configuration example are balanced without delay. In the memory read mode, since VPW=VDD and VNW=GND, signal level shifting is not necessary, and the latch circuit simply passes the signal through, but because the signal delay is small, the read speed becomes fast.

[0133] Furthermore, in a latch circuit, no pull-up or pull-down current flows, unlike in a level shifter; only the node's charging and discharging current flows. Therefore, even when many word line control signals change simultaneously, such as in erase mode, there is no influence from the current. For example, there are no limitations on the amount of data that can be erased at once, or on testing.

[0134] Furthermore, the latch circuit latches the signal in write mode or erase mode, so the output signal OUT remains stable even with respect to noise in the input signal IN.

[0135] Figure 29 shows another configuration example of latch circuit 130-1. Latch circuit 130-1 includes inverter circuits 83, 87, and 88, and transfer gates TGA and TGB. The configurations of latch circuits 130-2 to 130-n are similar.

[0136] Compared to Figure 9, the clocked inverter circuit 82 is replaced with an inverter circuit 87 and a transfer gate TGA, and the clocked inverter circuit 84 is replaced with an inverter circuit 88 and a transfer gate TGB. The clocked inverter circuit 82 in Figure 9 is constructed using a high-voltage process, while the inverter circuit 87 in Figure 29 is constructed using a low-voltage process, and the transfer gate TGA is constructed using a high-voltage process. The voltage VPW or VNW switches when the transfer gate TGA is off. By using a low-voltage process for the inverter circuit 87, the layout area can be reduced.

[0137] Note that the latch circuit 130-1 in Figure 29 may further include inverter circuits 85 and 86 as shown in Figure 9, or transfer gates TG10 and TG11 as shown in Figure 19.

[0138] Figure 30 shows a second alternative configuration of latch circuit 130-1. Latch circuit 130-1 includes a NAND gate 80-1, an inverter circuit 83, a transfer gate TGA, and a clocked inverter circuit 84. The configurations of latch circuits 130-2 to 130-n are similar.

[0139] Compared to Figure 9, the clocked inverter circuit 82 is replaced with a NAND circuit 80-1 and a transfer gate TGA. The NAND circuit 80-1 is constructed using a low-voltage process. Since the inverter circuit after the NAND circuit 80-1 can be omitted, the layout area can be reduced.

[0140] Note that the latch circuit 130-1 in Figure 30 may further include inverter circuits 85 and 86 as shown in Figure 9, or transfer gates TG10 and TG11 as shown in Figure 19.

[0141] Figure 31 shows a second comparative example of this embodiment. Figure 31 shows an example of a circuit configuration in which the feedback signal is returned in the signal output circuit 150, rather than the configuration in this embodiment in which the feedback signal is returned from the power switching circuit 110 and latch control circuit 120, and an example of the signal waveform.

[0142] As shown in the circuit configuration example, the delay circuit Delay1 generates a latch control feedback signal from a signal equivalent to the latch signal LLAT, and the delay circuit Delay2 generates a power control feedback signal from the power control signal LXPGM. Therefore, as shown in the signal waveform example, after the latch signal LLAT goes from a low level to a high level, and after the delay time by the delay circuit Delay1, the power control signal LPGM goes from a low level to a high level. After the power control signal LPGM goes from a high level to a low level, and after the delay time by the delay circuit Delay2, the latch signal LLAT goes from a high level to a low level.

[0143] As explained in Figures 7 and 8, there is a level shifter 111 after the power control signal LPGM, and a level shifter 121 after the latch signal LLAT. Therefore, the time from when the power control signal LPGM transitions until the power supply actually switches, and the time from when the latch signal LLAT transitions until the state of the latch circuit switches, are affected by the delay of each level shifter, or by the imbalance between falling and falling edges. In order to ensure that the power supply switches while the latch circuit 130 is latched the signal, it is necessary to make the delay time of the delay circuits Delay1 and Delay2 large enough to obtain a sufficient margin against the above effects. For this reason, the signal delay becomes large in this comparative example.

[0144] In this embodiment, since feedback signals are returned from the power switching circuit 110 and the latch control circuit 120, the order of signal transitions is not affected by the level shifter, and it is naturally guaranteed that the power switch will occur with the latch circuit 130 latching the signal. As a result, there is no need to provide delay circuits Delay1 and Delay2, and the signal delay is smaller compared to the comparative example.

[0145] In this embodiment, as explained in Figure 6, the signal output circuit 150 outputs a power supply control signal LPGM based on the logical AND of a control signal (write control signal PGM) and a latch control feedback signal LT based on a latch control signal HXLAT. The signal output circuit 150 outputs a latch signal LLAT based on the logical OR of a control signal (write control signal PGM) and a power supply control feedback signal SWP based on a power supply control signal LPGM. Furthermore, as explained in Figure 11, the signal output circuit 150 outputs a power supply control signal LERS based on the logical AND of a control signal (erase control signal ERS) and a latch control feedback signal LT based on a latch control signal HXLAT. The signal output circuit 150 outputs a latch signal LLAT based on the logical OR of a control signal (erase control signal ERS) and a power supply control feedback signal SWN based on a power supply control signal LERS.

[0146] In this embodiment, when the control signals (PGM, ERS) become inactive or active, the latch signal LLAT, based on logical OR, changes from inactive to active. This allows the latch circuit 130-1 to latch the input signal SIN1 before the power supply switching circuit 110 switches the power supply. Also, when the control signals (PGM, ERS) change from active to inactive, the power control signals (LPGM, LERS), based on logical AND, change from active to inactive. This allows the power supply switching circuit 110 to switch the power supply before the latch circuit 130-1 releases the signal hold.

[0147] As explained in Figure 7, the power switching circuit 110 includes a level shifter 111 that level-shifts the power control signal LPGM to a voltage level signal of the power line LPW. Based on the output signal of the level shifter 111, the power switching circuit 110 switches the voltage VPW supplied to the power line LPW to either the first power supply voltage (power supply voltage VDD) or the second power supply voltage (writing voltage VPP), and outputs a power control feedback signal SWP. Also, as explained in Figure 12, the power switching circuit 110 includes a level shifter 112 that level-shifts the power control signal LERS to a voltage level signal of the power line LNW. Based on the output signal of the level shifter 112, the power switching circuit 110 switches the voltage VNW supplied to the power line LNW to either the first power supply voltage (ground voltage GND) or the second power supply voltage (erasure voltage VNN), and outputs a power control feedback signal XSWN.

[0148] According to this embodiment, power control feedback signals (SWP, XSWN) are output based on the output signals of the level shifters (111, 112). The signal output circuit 150 performs signal control based on these power control feedback signals (SWP, XSWN). As a result, as explained in Figure 31, it is no longer necessary to consider the delay of the level shifters (111, 112) in signal control, and the signal delay can be reduced compared to the comparative example in Figure 31. Furthermore, since the power switching circuit 110 is provided in common for multiple latch circuits 130-1 to 130-n, the number of level shifters is smaller compared to the case where a level shifter is provided for each signal path.

[0149] As explained in Figure 8, etc., the latch control circuit 120 includes a level shifter 121 that level shifts the latch signal LLAT to a signal of the voltage level of the power line LPW. Based on the output signal of the level shifter 121, the latch control circuit 120 outputs latch control signals HLAT and HXLAT, as well as a latch control feedback signal LT. Furthermore, as explained in Figure 13, etc., the latch control circuit 120 includes a level shifter 122 that level shifts the latch signal LLAT to a signal of the voltage level of the power line LNW. Based on the output signal of the level shifter 122, the latch control circuit 120 outputs latch control signals HLAT and HXLAT, as well as a latch control feedback signal LT.

[0150] According to this embodiment, a latch control feedback signal LT is output based on the output signals of the level shifters (121, 122). The signal output circuit 150 performs signal control based on this latch control feedback signal LT. As a result, as explained in Figure 31, it is no longer necessary to consider the delay of the level shifters (121, 122) in signal control, and the signal delay can be reduced compared to the comparative example in Figure 31. Furthermore, since the latch control circuit 120 is provided in common for multiple latch circuits 130-1 to 130-n, the number of level shifters is smaller compared to the case where a level shifter is provided for each signal path.

[0151] As explained in Figures 22 to 24, the power switching circuit 110 switches the voltage VPW of the power line LPW from the first power supply voltage (power supply voltage VDD) to the second power supply voltage (writing voltage VPP). At this time, the latch control circuit 120 outputs a latch control signal HLAT where the difference between the voltage VPW of the power line LPW and the voltage of the latch control signal HLAT is smaller than the threshold value of the cutoff transistor (P-type MOS transistor MP81 of the clocked inverter circuit 82) of the input control circuit 132. Also, as explained in Figures 22, 25, and 26, the power switching circuit 110 switches the voltage VNW of the power line LNW from the first power supply voltage (ground voltage GND) to the second power supply voltage (erasure voltage VNN). At this time, the latch control circuit 120 outputs a latch control signal HXLAT where the difference between the voltage VNW of the power line LNW and the voltage of the latch control signal HXLAT is smaller than the threshold value of the cutoff transistor (N-type MOS transistor MN81 of the clocked inverter circuit 82) of the input control circuit 132.

[0152] According to this embodiment, as explained in Figures 22 to 26, when the power supply switching circuit 110 switches the voltage of the power line, the logic level of the signal output by the input control circuit 132 does not change, so the logic level of the signal held by the holding circuit 134 is maintained. As a result, the logic level of the signal latched by the latch circuit 130 is maintained, while the voltage level of that signal changes from the first power supply voltage to the second power supply voltage. This realizes a level shift by the latch circuit 130-1.

[0153] In this embodiment, the circuit device 100 also includes a memory circuit 194. The input signal is a word line control signal (LWL1, etc.) of the memory circuit 194. The word line of the memory circuit 194 is controlled based on the output signal (WL1, etc.) of the latch circuit.

[0154] According to this embodiment, the word line control signal can be level-shifted using a latch circuit instead of a level shifter. This provides the various effects described in Figures 27 and 28.

[0155] In this embodiment, the first power supply voltage may be the power supply voltage VDD used for reading from the memory circuit 194. The second power supply voltage may be a voltage higher than the power supply voltage VDD and may be the write voltage VPP used for writing to the memory circuit 194.

[0156] In this embodiment, the circuit device 100 also includes a control circuit 190 that outputs a control signal (write control signal PGM). The control circuit 190 activates the control signal (PGM) from inactive when writing to the memory circuit 194, and maintains the control signal (PGM) inactive when reading from the memory circuit 194.

[0157] In this embodiment, the first power supply voltage may be the ground voltage GND used for reading from the memory circuit 194. The second power supply voltage may be a voltage lower than the ground voltage GND and may be the erase voltage VNN used for erasing from the memory circuit 194.

[0158] According to these embodiments, in the write mode or erase mode of the memory circuit 194, the word line control signal can be level-shifted to the write voltage VPP or the erase voltage VNN.

[0159] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of power switching circuits, latch control circuits, latch circuits, control circuits, signal output circuits, memory circuits, word line control circuits, and circuit devices are not limited to those described in this embodiment, and various modifications are possible. [Explanation of Symbols]

[0160] 100...Circuit device, 110...Power switching circuit, 111,112...Level shifter, 120...Latch control circuit, 121,122...Level shifter, 130-1~130-n...Latch circuit, 132...Input control circuit, 134...Holding circuit, 150...Signal output circuit, 190...Control circuit, 192...Word line control circuit, 194...Memory circuit, CNT...Control signal, DEC1~DECn,LWL1~LWLn...Word line control signal, ERS...Erase control signal, GND...Ground voltage, LLAT,LXLAT...Latch signal, LPGM,LXP GM, LERS, LXERS… Power control signals, LT… Latch control feedback signals, LQ, LPW, LNW… Power lines, LTCT, HLAT, HXLAT… Latch control signals, PGM… Write control signals, SIN1~SINn… Input signals, SQ1~SQn… Output signals, SW, SWP, SWN, XSWN… Power control feedback signals, V1… First power supply voltage, V2… Second power supply voltage, VDD… Power supply voltage, VNN… Erase voltage, VPP… Write voltage, VQ, VNW, VPW… Power line voltages, WL1~WLn… Word line selection signals

Claims

1. A latch circuit that latches the input signal, A signal output circuit that outputs a latch signal and a power control signal based on a control signal, A latch control circuit that outputs a latch control signal to the latch circuit based on the latch signal, A power switching circuit that supplies a first power supply voltage, or a second power supply voltage different from the first power supply voltage, to the latch circuit and the power supply line of the latch control circuit based on the power supply control signal, Includes, The signal output circuit is characterized in that, when the control signal changes from inactive to active, it first activates the latch signal, and then outputs the power control signal indicating a switch from the first power supply voltage to the second power supply voltage.

2. In the circuit device described in claim 1, When the signal output circuit changes the latch signal from inactive to active, the latch control circuit outputs the latch control signal based on the first power supply voltage, the latch circuit latches the input signal and outputs an output signal based on the first power supply voltage. A circuit device characterized in that, when the latch circuit holds the latched input signal, the signal output circuit outputs the power control signal indicating a switch from the first power supply voltage to the second power supply voltage, the power switching circuit switches the voltage of the power line from the first power supply voltage to the second power supply voltage, the latch control circuit outputs the latch control signal based on the second power supply voltage, and the latch circuit outputs the output signal based on the second power supply voltage.

3. In the circuit device described in claim 1, The aforementioned signal output circuit is Based on the logical AND of the control signal and the latch control feedback signal based on the latch control signal, the power control signal is output. A circuit device characterized by outputting the latch signal based on the logical OR of the control signal and the power control feedback signal based on the power control signal.

4. In the circuit device described in claim 3, The aforementioned power supply switching circuit is Includes a level shifter that level shifts the power control signal to a voltage level signal of the power line, A circuit device characterized by switching the voltage supplied to the power line to the first power supply voltage or the second power supply voltage based on the output signal of the level shifter, and outputting the power control feedback signal.

5. In the circuit device described in claim 3, The latch control circuit is Includes a level shifter that level shifts the latch signal to a voltage level signal of the power line, A circuit device characterized by outputting the latch control signal and the latch control feedback signal based on the output signal of the level shifter.

6. In the circuit device described in claim 1, The latch circuit is An input control circuit to which the aforementioned input signal is input, A holding circuit connected to the input control circuit, Includes, The aforementioned input control circuit is When the latch control signal is inactive, the input signal is input to the holding circuit. A circuit device characterized in that when the latch control signal is active, the input of the input signal to the holding circuit is blocked.

7. In the circuit device described in claim 6, The holding circuit is When the latch control signal is inactive, the input signal input from the input control circuit is allowed to pass through. A circuit device characterized in that when the latch control signal is active, it holds the input signal that was input when the latch control signal was inactive.

8. In the circuit device described in claim 6, When the power switching circuit switches the voltage of the power line from the first power supply voltage to the second power supply voltage, The latch control circuit is characterized in that it outputs a latch control signal in which the difference between the voltage of the power line and the voltage of the latch control signal is smaller than the threshold value of the cutoff transistor of the input control circuit.

9. In the circuit device described in claim 1, The signal output circuit is characterized in that, when the control signal changes from active to inactive, it outputs a power control signal indicating a switch from the second power supply voltage to the first power supply voltage, and then changes the latch signal from active to inactive.

10. In the circuit device described in claim 9, When the signal output circuit outputs the power control signal indicating a switch from the second power supply voltage to the first power supply voltage, the latch circuit holds the latched input signal, and the power switching circuit switches the voltage of the power line from the second power supply voltage to the first power supply voltage. A circuit device characterized in that, when the power switching circuit supplies the first power supply voltage to the power line, the signal output circuit changes the latch signal from active to inactive, and the latch circuit changes from a state in which it latches the input signal to a state in which it allows the signal to pass through.

11. In the circuit device described in claim 1, A circuit device characterized by including a control circuit that outputs the aforementioned control signal.

12. In the circuit device described in claim 1, Includes memory circuitry, The input signal is the word line control signal of the memory circuit. The memory circuit is characterized in that the word line is controlled based on the output signal of the latch circuit.

13. In the circuit device described in claim 12, The first power supply voltage is the power supply voltage used for reading the memory circuit, The circuit device is characterized in that the second power supply voltage is a voltage higher than the power supply voltage and is a writing voltage used for writing to the memory circuit.

14. In the circuit device described in claim 13, Includes a control circuit that outputs the aforementioned control signal, The aforementioned control circuit is When writing to the memory circuit, the control signal is changed from inactive to active. A circuit device characterized by keeping the control signal inactive when reading from the memory circuit.

15. In the circuit device described in claim 12, The first power supply voltage is the ground voltage used for reading the memory circuit. The circuit device is characterized in that the second power supply voltage is a voltage lower than the ground voltage and is an erase voltage used to erase the memory circuit.

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