Technology for glass-penetrating vias with caps

Abstract

The present invention provides an apparatus and method for reducing the occurrence of cracks in a glass core due to differences in thermal expansion with through vias. [Solution] In the integrated circuit component 100, the substrate core 202 has a defined hole in it, and vias 208 for transporting power or data signals through the substrate core are positioned within the hole. The vias are formed using a bottom-up plating process, and the vias are not fixed to the side walls 216 of the hole in the substrate core. Therefore, the vias can move relative to the substrate core, thereby reducing cracking of the core during thermal cycling. To reduce cracking in the build-up layer 206 on the core 202, the vias have via caps 210 that can reduce stress in the build-up layer.

Description

Background Art

[0001] Glass cores for circuit boards and other electronic components are becoming increasingly common. To transport power and data signals through the glass core, through-glass vias (TGVs) can be formed in the glass core. The vias can be made of copper or other conductive materials. However, the coefficients of thermal expansion (CTEs) of the glass core and the vias can be mismatched, thereby causing stress when subjected to thermal cycling. In some cases, the stress can cause cracks in the glass core.

Brief Description of the Drawings

[0002] [Figure 1] An isometric view of one embodiment of a system having an integrated circuit component on a circuit board having a substrate core.

[0003] [Figure 2] A cross-sectional view of one embodiment of the system of FIG. 1.

[0004] [Figure 3] A cross-sectional view of one embodiment of the system of FIG. 1.

[0005] [Figure 4] A cross-sectional view of one embodiment of the system of FIG. 1.

[0006] [Figure 5] A cross-sectional view of one embodiment of the system of FIG. 1.

[0007] [Figure 6] A flowchart of one embodiment of a method of creating one embodiment of the system of FIG. 1.

[0008] [Figure 7]This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0009] [Figure 8] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0010] [Figure 9] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0011] [Figure 10] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0012] [Figure 11] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0013] [Figure 12] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0014] [Figure 13] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0015] [Figure 14] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 6.

[0016] [Figure 15] This is a flowchart of one embodiment of a method for creating one embodiment of the system shown in Figure 1.

[0017] [Figure 16] This is a cross-sectional view of one embodiment of a glass core at one stage of the flowchart in Figure 15.

[0018] [Figure 17] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 15.

[0019] [Figure 18] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 15.

[0020] [Figure 19] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 15.

[0021] [Figure 20] It is a flowchart of an embodiment of a method for creating an embodiment of the system of FIG. 1.

[0022] [Figure 21] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 20.

[0023] [Figure 22] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 20.

[0024] [Figure 23] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 2 (should be FIG. 20 here).

[0025] [Figure 24] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 20.

[0026] [Figure 25] It is a cross-sectional view of an embodiment of a glass core at one stage of the flowchart of FIG. 20.

[0027] [Figure 26] Note: There seems to be a typo in the original text where it says "図2" in ID=39, which should probably be "図20" to be consistent with the other references to FIG. 20. The translation has been adjusted accordingly.This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 20.

[0028] [Figure 27] This is a cross-sectional view of one embodiment of the glass core at one stage of the flowchart in Figure 20.

[0029] [Figure 28] This is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0030] [Figure 29] This is a side cross-sectional view of an integrated circuit device that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0031] [Figure 30A] This is a perspective view of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 30B] This is a perspective view of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 30C] This is a perspective view of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 30D] This is a perspective view of exemplary planar, gate-all-around, and stacked gate-all-around transistors.

[0032] [Figure 31] This is a side cross-sectional view of an integrated circuit device assembly which may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0033] [Figure 32] This is an exemplary block diagram of an electrical device which may include a microelectronic assembly according to any of the embodiments disclosed herein. [Modes for carrying out the invention]

[0034] In various embodiments disclosed herein, an integrated circuit component has a circuit board on which a semiconductor die is disposed on its surface. The circuit board has a substrate core in which vias are defined. In exemplary embodiments, the vias are not fixed to the sidewalls, thereby reducing cracking of the core due to thermal cycling and mismatch in thermal expansion coefficients between the via material and the core material. The vias also include caps or pads, which can also reduce cracking of the dielectric layer constructed on the substrate core.

[0035] As used herein, the phrase “communicatively coupled” refers to the ability of a component to transmit or receive signals from another component. The signals may be of any type, such as input signals, output signals, or power signals. A component may transmit or receive signals from another component to which it is communicatively coupled via a wired or wireless medium (e.g., conductive traces, conductive contacts, or air). Examples of communicatively coupled components include integrated circuit dies located within the same package that communicate via embedded bridges within the package substrate, and integrated circuit components mounted on a printed circuit board that transmit or receive signals from other integrated circuit components or electronic devices mounted on a printed circuit board.

[0036] The following description includes specific details, but embodiments of the technology described herein can be practiced without these specific details. Known circuits, structures, and technologies are not shown in detail to avoid obscuring the understanding of this specification. Phrases such as “one embodiment,” “various embodiments,” and “several embodiments” may include features, structures, or characteristics, but not all embodiments necessarily include specific features, structures, or characteristics.

[0037] Some embodiments may have some or all of the features described in other embodiments, or may not have any of these features. “First,” “Second,” “Third,” etc., describe common objects and indicate that different examples of similar objects are being referred to. Such adjectives do not indicate that the objects described in this way must be in a given order, sequence, or any other arbitrary manner, temporally or spatially. “Connected” may indicate that elements are in direct physical or electrical contact, and “coupled” may indicate that elements cooperate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, terms such as “equipped,” “included,” and “having” as used for embodiments of this disclosure are synonyms. Terms modified with the word “substantially” include arrangements, orientations, spacings, or positions that are slightly different in meaning from the unmodified terms. For example, the central axis of a magnetic plug substantially coaxial with a through-hole may be offset by a few degrees from the central axis of the through-hole. In another example, substrate assembly features such as through-widths, which are described as substantially having the listed dimensions, may vary within a few percent of the listed dimensions.

[0038] In the examples shown and further described below, it should be understood that the figures may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, while certain figures show transistor designs having source / drain regions, electrodes, etc., with orthogonal (e.g., vertical) boundaries, it should be understood that embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., orthogonality of + / - 5 or 10 degrees) due to the fabrication method used to create such devices or for other reasons.

[0039] Drawings are referenced here, but they are not necessarily drawn to scale, and similar or identical reference numerals may be used to designate the same or similar parts in different drawings. The use of similar or identical reference numerals in different drawings does not mean that all drawings containing similar or identical reference numerals constitute a single or identical embodiment. Similar numerals with different letter suffixes may represent different instances of similar components. Drawings generally illustrate, as examples, various embodiments discussed in this document, without limitation.

[0040] In the following description, specific numerical details are included for illustrative purposes to provide these understandings. However, it will be apparent that these novel embodiments can be practiced without these specific details. In other examples, known structures and devices are shown in block diagrams to facilitate these descriptions. All modifications, equivalents, and alternatives within the scope of the claims are intended to be covered.

[0041] As used herein, the term “located” in the context of a first layer or component located on a second layer or component means that the first layer or component is physically attached directly to the second layer or component (without any layers or components between the first and second layers or components), or that one or more layers or components interpose to the second layer or component.

[0042] As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there are no layers or components between the indicated adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0043] Referring here to Figures 1 and 2, in one embodiment, the integrated circuit component 100 includes a circuit board 102 on which one or more dies 104 are mounted. Figure 1 shows an isometric view of the integrated circuit component 100, and Figure 2 shows a cross-sectional view of the integrated circuit component 100. As shown in Figure 1, dies 104, such as a processor die 104, may be located on the top surface 108 of the circuit board 102. In exemplary embodiments, additional components, such as other semiconductor dies 106 (e.g., memory dies, other processor dies, etc.), are also located on the top surface 108 of the circuit board 102.

[0044] Where used herein, terms such as “top side” and “bottom side” are arbitrary designations used for clarity and should be understood as not indicating a specific orientation required for manufacture or use. In the exemplary embodiments described, the dies 104 and 106 are positioned on the “top” side of the circuit board 102, but in some embodiments, these components may be positioned on the “bottom” side of the circuit board 102.

[0045] The circuit board 102 includes a substrate core 202, a lower build-up layer 204, and an upper build-up layer 206. Holes or cavities are defined in the substrate core 202, extending from the top surface 226 to the bottom surface 230 of the substrate core 202. Vias 208 are placed in the holes. As will be discussed in more detail below, in exemplary embodiments, the vias 208 are manufactured in such a manner that they are not fixed to the sidewalls 216 of the holes. As a result, there may be gaps 212 between the vias 208 and the sidewalls 216 of the holes. The gaps 212 may be, for example, 5 to 200 nanometers, and the average gap 212 may be, for example, 10 to 150 nanometers. Naturally, as shown in the inset of Figure 2, there may be several contact points 214 over a relatively small area between the vias 208 and the sidewalls 216. However, the majority of the surface area of ​​the vias 208 does not contact the sidewalls 216. For example, a cross-section taken perpendicular to via 208 may show that via 208 does not touch the sidewall 216 at all in that cross-section. Generally, less than half of the surface area of ​​via 208 (e.g., 50% to 1% or even less) will be in contact with the sidewall 216. Because via 208 is not fixed to the sidewall 216, when the integrated circuit component 100 undergoes thermal cycling, via 208 can expand and contract due to elastic deformation independently of the substrate core 202, thereby reducing cracking in the substrate core 202. However, since via 208 can still expand more than the substrate core 202, it puts stress on the dielectric build-up layers 204 and 206. In particular, the stress may be greatest at the point where via 208, the substrate core 202, and the build-up layers 204 and 206 meet (without via cap 210).

[0046] To reduce stress in the build-up layers 204, 206, via caps 210 are formed on one or both ends of the vias 208. The via caps 210 may also be referred to as pads or via pads. The via caps 210 can reduce stress in the build-up layers 204, 206. In some embodiments, the via caps 210 may be fixed to a portion of the substrate core 202, such as the top surface 226 of the substrate core 202. In other embodiments, the via caps 210 may not be fixed to any portion of the substrate core 202. Different manufacturing methods that may result in fixed or unfixed via caps 210 are described in further detail below.

[0047] In an exemplary embodiment, the circuit board 102 is a multilayer circuit board 102 having build-up layers 204 and 206 above and below the substrate core 202. The build-up layers 204 and 206 may each have any preferred number of layers, such as 1 to 10 layers. In another embodiment, the circuit board 102 may be a single-layer circuit board 102. In an exemplary embodiment, the substrate core 202 is an inorganic core, such as a glass core. The glass core may be silicon oxide glass. In another embodiment, the glass core may be made of any preferred material, such as crystalline, amorphous, or crystalline, for example, fused silicon, borosilicate, sapphire, yttrium aluminum garnet, etc. The glass core may be, for example, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica. The glass core may contain one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The glass core may contain silicon and oxygen, as well as one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The glass core may contain at least 20-40 weight percent silicon, at least 20-40 weight percent oxygen, and at least 5 weight percent aluminum. For example, some embodiments of the glass core may contain, for example, at least 20-23 weight percent silicon and at least 20-26 weight percent oxygen. In other embodiments, the substrate core 202 may be an organic core, such as a fibrous glass substrate made of glass fibers and resin, such as FR-4.

[0048] The thickness of the circuit board 102 may be any suitable thickness, such as 100 micrometers to 5 millimeters. The thickness of the substrate core 202 may be any suitable thickness, such as 50 micrometers to 2 millimeters. The circuit board 102 may have any suitable length and width, such as 1 to 500 millimeters. Although shown as rectangular, the circuit board 102 may have any suitable shape and should be understood to have protrusions, notches, etc., for accommodating, mating with, or touching other components of the device. In exemplary embodiments, the circuit board 102 is planar. In other embodiments, the circuit board 102 may be unplanar.

[0049] In an exemplary embodiment, die 104 may be a processor die, and the other die 106 may be a memory die communicatively coupled to the processor die 104. In other embodiments, die 104 and / or die 106 may be any suitable die, such as one or more processor dies, memory dies, a central processing unit (CPU), a graphics processing unit (GPU), any other suitable processing unit (xPU), an accelerator circuit, a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). Dies 104 and 106 may be connected to contact pads or vias 220 on the circuit board 102 through conductive contacts 222, such as solder balls.

[0050] Vias 208 in the core 202 can transport power and / or data signals through the substrate core 202. In an exemplary embodiment, vias 208 are made of copper. In other embodiments, vias 208 may be made of any suitable conductive material, such as tungsten, polysilicon, etc. The core 202 may have any suitable number of vias 208 extending through it, such as 1 to 10,000 vias 208. Vias 208 may have any suitable diameter, such as 10 to 500 micrometers. Vias 208 may be connected to other traces 218, vias 220, etc. on the build-up layers 204, 206 to connect to various components on the top or bottom surface of the circuit board 102. Traces 218 and vias 220 may be made of any suitable conductive material, such as copper or aluminum.

[0051] The build-up layers 204 and 206 may be made of any suitable material or a combination of materials, for example, any suitable dielectric capable of supporting traces 218, vias 220, etc. In exemplary embodiments, the build-up layers 204 and 206 may be made of a resin material filled with a filler such as Ajinomoto build-up film (ABF).

[0052] A wide range of variations of the vias 208 and via caps 210 described above can also be considered. For example, in one embodiment, the via cap 302 may be countersinked within the core 202, as shown in Figure 3. The countersinked via cap 302 may further improve stress reduction. In the embodiment shown in Figure 2, the via 208 has a via cap 210 only at the upper end of the via 208 at the interface with the upper build-up layer 206. Additionally or alternatively, in some embodiments, the via 208 may have a via cap 210 at the bottom end of the via at the interface with the bottom build-up layer 206, as shown in Figure 4. In some embodiments, a liner 502 may be present between the via 208 and the core 202, as shown in Figure 5. The liner 502 may be any suitable material, such as a polymer. The via cap 210 may have any suitable dimensions, such as a diameter of 20 to 1,000 micrometers and a thickness of 5 to 35 micrometers.

[0053] Referring here to Figure 6, a flowchart of Method 600 for creating an integrated circuit component 100 is shown in one embodiment. Method 600 may be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of Method 600. Such machines may include, for example, memory, processors, data storage, etc. The memory and / or data storage may store instructions that cause the machine to perform some or all of the steps of Method 600 when performed by the machine. Method 600 may use any preferred set of techniques used in semiconductor processing or circuit board processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, selective laser etching, thermal treatment, flip chip, layer transfer, magnetron sputter deposition, pulsed laser deposition, laser processing, laser-induced deep etching, 3D photolithography, screen printing, inkjet printing, etc. It should be understood that Method 600 is merely one embodiment of a method for creating one embodiment of the system, and other methods may be used to create any preferred embodiment of the system. In some embodiments, the steps of Method 600 may be performed in a different order than that shown in the flowchart.

[0054] Method 600 begins in block 602, where the substrate core 202 is prepared by, for example, dicing, polishing, etc. In block 604, holes 702 or cavities are formed in the substrate core, as shown in Figure 7. In exemplary embodiments, laser-induced deep etching (LIDE) is used to form the holes 702. In other embodiments, other techniques, such as laser drilling, mechanical drilling, etching, etc., may be used. In some embodiments, the liner may be positioned within the holes 702 so that the liner is positioned around the outer periphery of the cavity.

[0055] In block 606, as shown in Figure 8, a seed layer 802, such as a copper seed layer, may be formed on the upper surface of the core 202. In an exemplary embodiment, the copper seed layer 802 is formed using electroless plating. In other embodiments, the copper seed layer 802 may be formed in a different manner, such as by lamination on a copper sheet. The seed layer 802 may have any preferred thickness, such as 0.1 to 5 micrometers.

[0056] In block 608, as shown in Figure 9, the photoresist 902 is patterned onto the copper seed layer 802 to define the position of the via cap 210. In block 610, as shown in Figure 10, additional material is electroplated onto the seed layer 802 to form the via cap 210. In block 612, as shown in Figure 11, the photoresist 902 is removed. In block 614, the substrate core 202 is inverted.

[0057] In block 616, as shown in Figure 12, glass through vias 208 are formed using a bottom-up plating process. In exemplary embodiments, it should be understood that the electroplating technique used to form the vias 208 deposits additional material (e.g., copper) only on existing layers of that material. Thus, although the vias 208 develop from the via cap 210 through a hole defined within the substrate core 202, the vias 208 are not fixed to the substrate core 202.

[0058] In block 618, in some embodiments, a via cap 210 is formed on top of the via 208, as shown in Figure 13. In other embodiments, the via cap 210 is not formed on top of the via 208.

[0059] In block 620, the seed layer 802 is removed, as shown in Figure 14. In an exemplary embodiment, it should be understood that fragments of the seed layer 1402 remain beneath the via cap 210. Since these fragments of the seed layer 1402 are fixed to the surface of the substrate core 202, the via cap 210 and via 208 are fixed to the surface of the substrate core 202. In microscopic images obtained using TEM or SEM, it should be understood that there may be an observable interface between the seed layer 1402 and the via cap 210. For example, the particle structure in the seed layer 1402 may differ from that of the via cap 210.

[0060] After the vias 208 are formed and the seed layer 802 is removed, further processing may be carried out. For example, build-up layers 204 and 206 may be constructed on the substrate core 202, and one or more dies 104 and 106 may be mounted on the substrate, thereby completing the integrated circuit component 100 as shown in Figure 2.

[0061] Referring here to Figure 15, a flowchart of Method 1500 for creating an integrated circuit component 100 is shown in one embodiment. Method 1500 may be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of Method 1500. Such machines may include, for example, memory, processors, data storage, etc. The memory and / or data storage may store instructions that cause the machine to perform some or all of the steps of Method 1500 when performed by the machine. Method 1500 may use any preferred set of techniques used in semiconductor processing or circuit board processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, selective laser etching, thermal treatment, flip chip, layer transfer, magnetron sputter deposition, pulsed laser deposition, laser processing, laser-induced deep etching, 3D photolithography, screen printing, inkjet printing, etc. It should be understood that Method 1500 is merely one embodiment of a method for creating one embodiment of the system, and other methods may be used to create any preferred embodiment of the system. In some embodiments, the steps of Method 1500 may be performed in a different order than that shown in the flowchart.

[0062] Method 1500 begins in block 1502, where the substrate core 202 is prepared by, for example, dicing, polishing, etc. In block 1504, holes 702 or cavities are formed in the substrate core, as shown in Figure 16. In an exemplary embodiment, laser-induced deep etching (LIDE) is used to form the holes 702. In other embodiments, other techniques, such as laser drilling, mechanical drilling, etching, etc., may be used.

[0063] In block 1506, as shown in Figure 17, a photoresist 1702 is patterned on the substrate core 202 and the positions of the via caps 210 are defined. In block 1508, as shown in Figure 18, the substrate core 202 is mounted on the carrier 1802 and inverted. The carrier 1802 may be, for example, silicon or other substrates, glass substrates, tape materials, and / or similar. In an exemplary embodiment, the carrier 1802 has a release film 1804 on the surface of the carrier 1802 and a seed layer formed on the release film 1804.

[0064] In block 1510, as shown in Figure 19, additional material is electroplated onto the seed layer 802 to form via caps 210 and vias 208. Similar to method 600, in exemplary embodiments, the electroplating technique used to form the vias 208 and via caps 210 deposits the additional material (e.g., copper) only on existing layers of that material. Thus, although the vias 208 and via caps 210 develop from the seed layer 1806 through holes defined within the substrate core 202, the vias 208 and via caps 210 are not fixed to the substrate core 202.

[0065] In block 1512, in some embodiments, a via cap 210 is formed on top of the via 208. In other embodiments, the via cap 210 is not formed on top of the via 208.

[0066] In block 1514, the carrier 1802 is removed. To this end, in an exemplary embodiment, the release film 1804 is removed by shining a laser through the carrier 1802 to excise or otherwise remove the release film 1804. In block 1516, the seed layer 1806 and the photoresist 1702 are etched off. Next, additional processing may be used to form build-up layers 204, 206 and mount the dies 104, 106 on the circuit board 102.

[0067] Referring here to Figure 20, a flowchart of Method 2000 for creating an integrated circuit component 100 is shown in one embodiment. Method 2000 may be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of Method 2000. Such machines may include, for example, memory, processors, data storage, etc. The memory and / or data storage may store instructions that cause the machine to perform some or all of the steps of Method 2000 when performed by the machine. Method 2000 may use any preferred set of techniques used in semiconductor processing or circuit board processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, selective laser etching, thermal treatment, flip chip, layer transfer, magnetron sputter deposition, pulsed laser deposition, laser processing, laser-induced deep etching, 3D photolithography, screen printing, inkjet printing, etc. It should be understood that Method 2000 is merely one embodiment of a method for creating one embodiment of the system, and other methods may be used to create any preferred embodiment of the system. In some embodiments, the steps of Method 2000 may be performed in a different order than that shown in the flowchart.

[0068] Method 2000 begins in block 2002, where the substrate core 202 is prepared by, for example, dicing, polishing, etc. In block 2004, holes 702 or cavities are formed in the substrate core, as shown in Figure 21. In an exemplary embodiment, laser-induced deep etching (LIDE) is used to form the holes 702. In other embodiments, other techniques, such as laser drilling, mechanical drilling, etching, etc., may be used.

[0069] In block 2006, as shown in Figure 22, hole 2202 is countersink-machined within the substrate core 202 around hole 702. In exemplary embodiments, laser-induced deep etching (LIDE) is used to form hole 2202. In other embodiments, other techniques, such as laser drilling, mechanical drilling, etching, etc., may be used.

[0070] In block 2008, as shown in Figure 23, a seed layer 802, such as a copper seed layer, may be formed on the upper surface of the core 202. In an exemplary embodiment, the copper seed layer 802 is formed using electroless plating. In other embodiments, the copper seed layer 802 may be formed in a different manner, such as by lamination on a copper sheet.

[0071] In block 2010, as shown in Figure 24, an additional material is electroplated onto the seed layer 802 to form a via cap 210. In block 2012, as shown in Figure 25, the substrate core 202 is inverted.

[0072] In block 2014, vias 208 are formed using a bottom-up plating process, as shown in Figure 26. As previously discussed, in the exemplary embodiment, the electroplating technique used to form vias 208 deposits additional material (e.g., copper) only on existing layers of that material. Thus, although vias 208 develop from via caps 210 through holes defined within the substrate core 202, vias 208 are not fixed to the substrate core 202. However, in the exemplary embodiment, via caps 210 are fixed to the seed layer 802, including within countersink holes.

[0073] In block 2016, in some embodiments, a via cap 210 is formed on top of the via 208. In other embodiments, the via cap 210 is not formed on top of the via 208.

[0074] In block 2018, the seed layer 802 is removed, as shown in Figure 27. In an exemplary embodiment, as shown in Figure 27, a portion of the via cap 210 may be removed until the via cap 210 is coplanar with the substrate core 202. In other embodiments, the via cap 210 may extend beyond the plane defined by the surface of the substrate core, even if the via cap 210 is countersink-machined.

[0075] After the vias 208 are formed and the seed layer 802 is removed, further processing may be carried out. For example, build-up layers 204 and 206 may be constructed on the substrate core 202, and one or more dies 104 and 106 may be mounted on the substrate, thereby completing the integrated circuit component 100 as shown in Figure 2.

[0076] It should be understood that the integrated circuit component 100 and other integrated circuit components described herein may have additional components not shown, such as additional semiconductor dies, active components, passive components, thermal management components, such as integrated heat spreaders and heat sinks. In some embodiments, vias 208 may be embedded in the circuit board 102 below the die 104 in the integrated circuit component 100, as shown in some figures above. In other embodiments, vias 208 may be embedded in any suitable circuit board 102, such as a motherboard, daughterboard, riser board, distribution board, mezzanine board, auxiliary board, and / or similar.

[0077] Figure 28 is a top view of a wafer 2800 and a die 2802 that may be included in any of the integrated circuit components 100 disclosed herein (e.g., as one of any of dies 104, 106). The wafer 2800 may be constructed of semiconductor material and may include one or more dies 2802 having integrated circuit structures formed on the surface of the wafer 2800. Each die 2802 may be an iterative unit of an integrated circuit product containing any preferred integrated circuit. After the fabrication of the semiconductor product is complete, the wafer 2800 may undergo a fragmentation process in which the dies 2802 are separated from each other to provide separate “chips” of the integrated circuit product. The die 2802 may be any of the dies 104, 106 disclosed herein. The die 2802 may include one or more transistors (e.g., part of transistor 2940 in Figure 29 discussed below), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 2800 or die 2802 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2802. For example, a memory array formed by multiple memory devices may be formed on the same die 2802 as a processor unit (e.g., processor unit 3202 in Figure 32) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.Various integrated circuit components 100 disclosed herein may be manufactured using die-to-wafer assembly technology, in which several dies 104, 106 are mounted on a wafer 2800 containing the other of the dies 104, 106, and the wafer 2800 is subsequently sliced ​​into individual pieces.

[0078] Figure 29 is a side cross-sectional view of an integrated circuit device 2900 that may be included in any of the integrated circuit components 100 disclosed herein (for example, in either die 104 or 106). One or more of the integrated circuit devices 2900 may be included in one or more dies 2802 (Figure 28). The integrated circuit device 2900 may be formed on a die substrate 2902 (for example, wafer 2800 in Figure 28) and may be included in a die (for example, die 2802 in Figure 28). The die substrate 2902 may be a semiconductor substrate constructed of a semiconductor material system including, for example, a system (or a combination of both) of n-type or p-type material. The die substrate 2902 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 2902 may be formed using alternative materials, which may or may not be combined with silicon, including, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 2902. Only a few examples of materials from which the die substrate 2902 may be formed are described here, but any material that can function as the basis for the integrated circuit device 2900 may be used. The die substrate 2902 may be part of a flaked die (e.g., die 2802 in Figure 28) or a wafer (e.g., wafer 2800 in Figure 28).

[0079] The integrated circuit device 2900 may include one or more device layers 2904 disposed on the die substrate 2902. The device layer 2904 may include features of one or more transistors 2940 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 2902. The transistor 2940 may include, for example, one or more source and / or drain (S / D) regions 2920, a gate 2922 that controls the flow of current between the S / D regions 2920, and one or more S / D contacts 2924 that route electrical signals to and from the S / D regions 2920. The transistor 2940 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 2940 is not limited to the type and configuration depicted in Figure 29 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbons, nanosheets, or nanowire transistors.

[0080] Figures 30A to 30D are simplified perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors shown in Figures 30A to 30D are formed on a substrate 3016 having a surface 3008. An insulating region 3014 separates the source and drain regions of the transistor from other transistors and from the bulk region 3018 of the substrate 3016.

[0081] Figure 30A is a perspective view of an exemplary planar transistor 3000, which includes a gate 3002 that controls the flow of current between a source region 3004 and a drain region 3006. The transistor 3000 is planar in that the source region 3004 and the drain region 3006 are planar with respect to the surface 3008 of the substrate.

[0082] Figure 30B is a perspective view of an exemplary FinFET transistor 3020, which includes a gate 3022 that controls the flow of current between the source region 3024 and the drain region 3026. Transistor 3020 is non-planar in that the source region 3024 and the drain region 3026 include “fins” that extend upward from the surface 3008 of the substrate. Transistor 3020 can be considered a tri-gate transistor because the gate 3022 surrounds three sides of the semiconductor fin that extends from the source region 3024 to the drain region 3026. Figure 30B shows one S / D fin extending through the gate 3022, but multiple S / D fins can extend through the gate of a FinFET transistor.

[0083] Figure 30C is a perspective view of a gate-all-around (GAA) transistor 3040, which includes a gate 3042 that controls the flow of current between the source region 3044 and the drain region 3046. Transistor 3040 is non-planar in that the source region 3044 and the drain region 3046 are raised above the surface 3008 of the substrate.

[0084] Figure 30D is a perspective view of a GAA transistor 3060, which includes a gate 3062 that controls the flow of current between multiple raised source regions 3064 and multiple raised drain regions 3066. Transistor 3060 is a stacked GAA transistor because the gate controls the current between multiple raised S / D regions stacked on top of each other. Transistors 3040 and 3060 are considered gate-all-around transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Transistors 3040 and 3060 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors, depending on the width (e.g., the widths of transistors 3048 and 3068, respectively, of the semiconductor portion extending through the gate).

[0085] Returning to Figure 29, the transistor 2940 may include a gate 2922 formed by at least two layers, a gate dielectric, and a gate electrode. The gate dielectric layer may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0086] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and zinc lead niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric layer to improve its quality.

[0087] The gate electrode may be formed on a gate dielectric, and the gate electrode may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2940 is to be a p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, one or more of which are work function metal layers, and at least one of which is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers.

[0088] For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0089] In some embodiments, when viewed as a cross-section of the transistor 2940 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 2902 and two sidewall portions substantially perpendicular to the top surface of the die substrate 2902. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 2902 and not including any sidewall portions substantially perpendicular to the top surface of the die substrate 2902. In other embodiments, the gate electrode may consist of a combination of U-shaped and non-U-shaped planar structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on the top surface of one or more planar non-U-shaped layers.

[0090] In some embodiments, pairs of sidewall spacers may be formed on opposing faces of a gate stack so as to surround the gate stack. These sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Several processes for forming sidewall spacers are known in the art and generally include deposition and etching steps. In some embodiments, multiple spacer pairs may be used. For example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of a gate stack.

[0091] The S / D region 2920 may be formed within the die substrate 2902 adjacent to the gate 2922 of individual transistors 2940. The S / D region 2920 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 2902 to form the S / D region 2920. An annealing process to activate the dopants and further diffuse them into the die substrate 2902 may follow the ion implantation process. In the latter process, the die substrate 2902 may first be etched to form a recess at the location of the S / D region 2920. Next, an epitaxial growth process may be performed to fill the recess with the material used to manufacture the S / D region 2920. In some packaging configurations, the S / D region 2920 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 2920 is formed using one or more alternating semiconductor materials, such as germanium or materials or alloys of groups III to V. In further embodiments, one or more layers of metals and / or metallic alloys may be used to form the S / D region 2920.

[0092] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and from devices on device layer 2904 (e.g., transistor 2940) through one or more interconnect layers (shown as interconnect layers 2906-2910 in Figure 29). For example, conductive features of device layer 2904 (e.g., gate 2922 and S / D contact 2924) can be electrically coupled to interconnect structures 2928 of interconnect layers 2906-2910. One or more interconnect layers 2906-2910 can form a metallization stack (also referred to as the "ILD stack") 2919 of the integrated circuit device 2900.

[0093] The interconnect structure 2928 may be arranged within interconnect layers 2906-2910 to route electrical signals according to a variety of designs, and in particular, the arrangement is not limited to the specific configuration of the interconnect structure 2928 depicted in Figure 29. Although a specific number of interconnect layers 2906-2910 are depicted in Figure 29, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those depicted.

[0094] In some embodiments, the interconnect structure 2928 may include lines 2928a and / or vias 2928b filled with a conductive material such as metal. Lines 2928a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 2902 on which the device layer 2904 is formed. For example, lines 2928a may route electrical signals in the direction inward and outward of a page, and / or across a page. Vias 2928b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 2902 on which the device layer 2904 is formed. In some embodiments, vias 2928b may electrically couple lines 2928a of different interconnect layers 2906-2910 together.

[0095] As shown in Figure 29, interconnect layers 2906-2910 may include dielectric material 2926 disposed between interconnect structures 2928. In some embodiments, the dielectric material 2926 disposed between interconnect structures 2928 in different interconnect layers 2906-2910 may have different compositions. In other embodiments, the composition of the dielectric material 2926 between different interconnect layers 2906-2910 may be the same. Device layer 2904 may include dielectric material 2926 disposed between the transistor 2940 and the bottom layer of the metallization stack. The dielectric material 2926 contained in device layer 2904 may have a different composition from the dielectric material 2926 contained in interconnect layers 2906-2910. In other embodiments, the composition of the dielectric material 2926 in device layer 2904 may be the same as the dielectric material 2926 contained in any one of interconnect layers 2906-2910.

[0096] A first interconnect layer 2906 (referred to as metal 1 or "M1") may be formed directly on the device layer 2904. As shown, in some embodiments, the first interconnect layer 2906 may include lines 2928a and / or vias 2928b. Lines 2928a of the first interconnect layer 2906 may be coupled to contacts of the device layer 2904 (e.g., S / D contacts 2924). Vias 2928b of the first interconnect layer 2906 may be coupled to lines 2928a of the second interconnect layer 2908.

[0097] A second interconnect layer 2908 (referred to as metal 2 or "M2") may be formed directly above the first interconnect layer 2906. In some embodiments, the second interconnect layer 2908 may include vias 2928b for connecting lines 2928a-2928b of the second interconnect layer 2908 to line 2928a of the third interconnect layer 2910. Although lines 2928a and vias 2928b are structurally depicted using lines within individual interconnect layers for clarity, lines 2928a and vias 2928b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0098] A third interconnect layer 2910 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed in succession on the second interconnect layer 2908 according to similar techniques and configurations described in relation to the second interconnect layer 2908 or the first interconnect layer 2906. In some embodiments, interconnect layers that are "higher" (i.e., further from the device layer 2904) in the metallization stack 2919 within the integrated circuit device 2900 may be thicker than interconnect layers that are lower in the metallization stack 2919, and lines 2928a and vias 2928b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0099] The integrated circuit device 2900 may include a solder resist material 2934 (e.g., polyimide or a similar material) and one or more conductive contacts 2936 formed on interconnect layers 2906-2910. In Figure 29, the conductive contacts 2936 are shown to take the form of bonding pads. The conductive contacts 2936 may be electrically coupled to an interconnect structure 2928 and configured to route electrical signals from transistors 2940 to an external device. For example, solder bonding may be formed on one or more conductive contacts 2936 to mechanically and / or electrically couple an integrated circuit die containing the integrated circuit device 2900 to another component (e.g., a printed circuit board). The integrated circuit device 2900 may include additional or alternating structures for routing electrical signals from interconnect layers 2906-2910. For example, the conductive contacts 2936 may include other similar features (e.g., posts) for routing electrical signals to an external component. The conductive contacts 2936 may, as appropriate, function as conductive contacts 222.

[0100] In some embodiments where the integrated circuit device 2900 is a double-sided die, the integrated circuit device 2900 may include another metallization stack (not shown) on the opposite side of the device layer 2904. This metallization stack may include multiple interconnect layers to provide conductive paths (including, for example, conductive lines and vias) between the device layer 2904 and the additional conductive contacts (not shown) on the opposite side of the conductive contact 2936 of the integrated circuit device 2900, as discussed above with reference to interconnect layers 2906-2910. These additional conductive contacts may, as appropriate, function as conductive contacts 222.

[0101] In other embodiments where the integrated circuit device 2900 is a double-sided die, the integrated circuit device 2900 may include one or more through-silicon vias (TSVs) through the die substrate 2902. These TSVs may contact the device layer 2904 and may provide a conductive path between the device layer 2904 and additional conductive contacts (not shown) on the side of the integrated circuit device 2900 opposite to the conductive contact 2936. These additional conductive contacts may optionally function as conductive contacts 222. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 2900 opposite to the conductive contact 2936 to the transistor 2940 and any other components integrated into the die, and the metallization stack 2919 may be used to route I / O signals from the conductive contact 2936 to the transistor 2940 and any other components integrated into the die.

[0102] In individual stacked devices, multiple integrated circuit devices 2900 may be stacked using one or more TSVs that provide connections between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and TSVs in the HBM die may provide connections between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may have fine-pitched solder bumps (microbumps).

[0103] Figure 31 is a side cross-sectional view of an integrated circuit device assembly 3100 which may include any of the integrated circuit components 100 disclosed herein. In some embodiments, the integrated circuit device assembly 3100 may be an integrated circuit component 100. The integrated circuit device assembly 3100 includes several components arranged on a circuit board 3102 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 3100 includes components arranged on a first surface 3140 of the circuit board 3102 and an opposing second surface 3142 of the circuit board 3102. Generally, components may be arranged on one or both surfaces 3140 and 3142. Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly 3100 may take any preferred form of an integrated circuit component 100 disclosed herein.

[0104] In some embodiments, the circuit board 3102 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer has a conductive trace. One or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 3102. In other embodiments, the circuit board 3102 may be a non-PCB substrate. In some embodiments, the circuit board 3102 may be, for example, circuit board 102. The integrated circuit device assembly 3100 shown in Figure 31 includes a package-on-interposer structure 3136 coupled to a first surface 3140 of the circuit board 3102 by a coupling component 3116. The coupling component 3116 may electrically and mechanically couple the package-on-interposer structure 3136 to the circuit board 3102 and may include solder balls (as shown in Figure 31), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female sockets, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The coupling component 3116 may, as appropriate, function as a coupling component shown or described for any of the board assemblies or board assembly components described herein.

[0105] The package-on-interposer structure 3136 may include an integrated circuit component 3120 coupled to an interposer 3104 by a coupling component 3118. The coupling component 3118 can take any preferred form for the application, such as the form discussed above with reference to the coupling component 3116. Although a single integrated circuit component 3120 is shown in Figure 31, multiple integrated circuit components may be coupled to the interposer 3104. In fact, additional interposers may be coupled to the interposer 3104. The interposer 3104 may provide an intervening substrate used to bridge the circuit board 3102 and the integrated circuit component 3120.

[0106] The integrated circuit component 3120 may be a packaged or unpackaged integrated circuit product comprising one or more integrated circuit dies (e.g., die 2802 in Figure 28, integrated circuit device 2900 in Figure 29) and / or one or more other suitable components. The packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, and the integrated circuit dies and package substrate are enclosed in a casing material such as metal, plastic, glass, or ceramic. In an example of an unpackaged integrated circuit component 3120, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly mounted to the interposer 3104. The integrated circuit component 3120 may comprise one or more computing system components, such as one or more processor units (e.g., a system-on-a-chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor, an I / O controller, memory, or a network interface controller). In some embodiments, the integrated circuit component 3120 may comprise one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0107] In embodiments where the integrated circuit component 3120 comprises multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit components). The multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0108] In addition to comprising one or more processor units, the integrated circuit component 3120 may comprise additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor units, or on one or more integrated circuit dies separate from the integrated circuit die comprising the processor units. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments in which the integrated circuit component comprises multiple integrated circuit dies, interconnection between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., Intel® embedded multi-die interconnect bridge (EMIB)), or a combination thereof.

[0109] Generally, the interposer 3104 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 3104 may couple an integrated circuit component 3120 to a set of ball grid array (BGA) conductive contacts of a coupling component 3116 for coupling to a circuit board 3102. In the embodiment shown in Figure 31, the integrated circuit component 3120 and the circuit board 3102 are mounted on opposing sides of the interposer 3104. In other embodiments, the integrated circuit component 3120 and the circuit board 3102 may be mounted on the same side of the interposer 3104. In some embodiments, three or more components may be interconnected by the interposer 3104.

[0110] In some embodiments, the interposer 3104 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 3104 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, an epoxy resin containing an inorganic filler, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 3104 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 3104 may include a metal interconnect 3108 and vias including, but not limited to, through-hole vias 3110-1 (extending from the first surface 3150 of the interposer 3104 to the second surface 3154 of the interposer 3104), blind vias 3110-2 (extending from the first or second surface 3150 or 3154 of the interposer 3104 to the internal metal layer), and embedded vias 3110-3 (connecting the internal metal layer).

[0111] In some embodiments, the interposer 3104 may comprise a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections from a first face of the silicon interposer to an opposing second face of the silicon interposer. In some embodiments, the interposer 3104 comprising a silicon interposer may further comprise one or more routing layers for routing connections from the first face of the interposer 3104 to an opposing second face of the interposer 3104.

[0112] The interposer 3104 may further include embedded devices 3114, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. Multiple more complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 3104. The package-on-interposer structure 3136 may take any form of package-on-interposer structure known in the art.

[0113] The integrated circuit device assembly 3100 may include an integrated circuit component 3124 coupled to the first surface 3140 of the circuit board 3102 by a coupling component 3122. The coupling component 3122 may take any form of the embodiments discussed above with reference to the coupling component 3116, and the integrated circuit component 3124 may take any form of the embodiments discussed above with reference to the integrated circuit component 3120.

[0114] The integrated circuit device assembly 3100 shown in Figure 31 includes a package-on-package structure 3134 coupled to a second surface 3142 of a circuit board 3102 by a coupling component 3128. The package-on-package structure 3134 may include integrated circuit components 3126 and 3132, coupled together by a coupling component 3130 such that integrated circuit component 3126 is positioned between the circuit board 3102 and integrated circuit component 3132. The coupling components 3128 and 3130 may take any form of the embodiment of the coupling component 3116 discussed above, and the integrated circuit components 3126 and 3132 may take any form of the embodiment of the integrated circuit component 3120 discussed above. The package-on-package structure 3134 may be configured according to any package-on-package structure known in the art.

[0115] Figure 32 is a block diagram of an exemplary electrical device 3200, which may include one or more of the integrated circuit components 100 disclosed herein. For example, any preferred components of the electrical device 3200 may include one or more of the integrated circuit device assembly 3100, integrated circuit component 3120, integrated circuit device 2900, or integrated circuit die 2802 disclosed herein, which may be arranged in any of the integrated circuit components 100 disclosed herein. Although several components are shown in Figure 32 as being included in the electrical device 3200, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the electrical device 3200 may be mounted on one or more motherboard mainboards or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die.

[0116] Additionally, in various embodiments, the electrical device 3200 does not have to include one or more of the components shown in Figure 32, but it may include interface circuits for coupling one or more components. For example, the electrical device 3200 does not have to include the display device 3206, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 3206 can be coupled. In another set of examples, the electrical device 3200 does not have to include the audio input device 3224 or the audio output device 3208, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 3224 or the audio output device 3208 can be coupled.

[0117] The electrical device 3200 may include one or more processor units 3202 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 3202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit may be referred to as XPU (or xPU).

[0118] The electrical device 3200 may include a memory 3204 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or a hard drive. In some embodiments, the memory 3204 may include memory located on the same integrated circuit die as the processor unit 3202. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0119] In some embodiments, the electrical device 3200 may comprise one or more processor units 3202 that are heterogeneous or asymmetrical with other processor units 3202 in the electrical device 3200. There may be a variety of differences between the processing units 3202 in the system in terms of a spectrum of advantages metrics, including architecture, microarchitecture, thermal characteristics, and power consumption characteristics. These differences may effectively manifest themselves as asymmetrical and heterogeneous between the processor units 3202 in the electrical device 3200.

[0120] In some embodiments, the electrical device 3200 may include a communication component 3212 (e.g., one or more communication components). For example, the communication component 3212 may manage wireless communication for data transfer to and from the electrical device 3200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data by the use of modulated electromagnetic radiation over a non-solid medium. The term “wireless” does not imply that the associated device does not include any wires, although in some embodiments this may not be the case.

[0121] The communication component 3212 may implement any of several wireless standards or protocols, including, but are not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects, including any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP® 2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed compliance and interoperability tests for the IEEE 802.16 standard. The communication component 3212 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 3212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 3212 may operate in accordance with Code Division Multiplexing (CDMA), Time Division Multiplexing (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and their derivatives, as well as any other radio protocol designated as 3G, 4G, 5G and beyond. In other embodiments, the communication component 3212 may operate in accordance with a plurality of other radio protocols.The electrical device 3200 may include an antenna 3222 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM wireless transmissions).

[0122] In some embodiments, the communication component 3212 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet® standard). As noted above, the communication component 3212 may include multiple communication components. For example, a first communication component 3212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth®, and a second communication component 3212 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 3212 may be dedicated to wireless communications, and the second communication component 3212 may be dedicated to wired communications.

[0123] The electrical device 3200 may include a battery / power supply circuit 3214. The battery / power supply circuit 3214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 3200 to an energy source separate from the electrical device 3200 (e.g., AC line power).

[0124] The electrical device 3200 may include a display device 3206 (or the corresponding interface circuit discussed above). The display device 3206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0125] The electrical device 3200 may include an audio output device 3208 (or the corresponding interface circuit discussed above). The audio output device 3208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or in-ear monitor.

[0126] The electrical device 3200 may include an audio input device 3224 (or a corresponding interface circuit as discussed above). The audio input device 3224 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI (musical instrument digital interface) output). The electrical device 3200 may include a Global Navigation Satellite System (GNSS) device 3218 (or a corresponding interface circuit as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 3218 may communicate with a satellite-based system and determine the geographic location of the electrical device 3200 based on information received from one or more GNSS satellites, as is known in the art.

[0127] The electrical device 3200 may include other output devices 3210 (or corresponding interface circuits as discussed above). Examples of other output devices 3210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0128] The electrical device 3200 may include other input devices 3220 (or corresponding interface circuits discussed above). Examples of other input devices 3220 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., planar or stereoscopic cameras), cursor control devices such as trackballs, trackpads, touchpads, keyboards, and mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoelectric fingertip plethysmography) sensors, electrocutaneous reaction sensors, any other sensors, or radio frequency identification (RFID) readers.

[0129] The electrical device 3200 may have any desired shape factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs®), ultramobile personal computers, portable gaming consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or thread computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary gaming consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems that are part of vehicles, smart appliances, consumer electronics or equipment, or manufacturing facilities). In some embodiments, the electrical device 3200 may be any other electronic device that processes data. In some embodiments, the electrical device 3200 may comprise several separate physical components. Given the range of devices that the electrical device 3200 may present as in various embodiments, in some embodiments, the electrical device 3200 may be referred to as a computing device or computing system. [Examples]

[0130] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more, and any combination of, the examples described below.

[0131] Embodiment 1 includes a substrate core, the substrate core having a top side and a bottom side, wherein a plurality of cavities are defined within the substrate core, each of the plurality of cavities extending from the bottom side to the top side; a plurality of vias extending through the plurality of cavities defined in the substrate core, wherein each of the plurality of vias is not fixed to the sidewall of the corresponding cavity of the plurality of cavities; and a plurality of via caps, wherein each of the plurality of via caps is located at one end of each of the plurality of vias.

[0132] Example 2 includes the subject matter of Example 1, wherein the plurality of via caps are countersinked on the substrate core such that at least a portion of each individual via cap of the plurality of via caps extends below the plane defined by the upper side of the substrate core.

[0133] Example 3 includes the subject matter of either Example 1 or 2, wherein the plurality of via caps are coplanar with the substrate core such that no portion of any individual via cap of the plurality of via caps extends above the plane defined by the upper side of the substrate core.

[0134] Example 4 includes the subject matter of any of Examples 1 to 3, wherein each of the plurality of via caps is fixed to the upper surface side of the substrate core.

[0135] Example 5 includes the subject matter of any of Examples 1 to 4, wherein each individual via cap of the plurality of via caps has a seed layer of a first granular structure and an electroplated layer of a second granular structure different from the first granular structure.

[0136] Example 6 includes the subject matter of any of Examples 1 to 5, wherein there is a gap of at least 10 nanometers between at least some of the individual vias of the plurality of vias and between the side walls of the corresponding cavities of the plurality of cavities.

[0137] Example 7 includes the subject matter of any of Examples 1 to 6, wherein the individual via caps of the plurality of via caps are not fixed to the substrate core.

[0138] Example 8 includes the subject matter of any of Examples 1 to 7, wherein the cross section of each individual via of the plurality of vias, taken perpendicular to the individual via, does not contact the side wall of the corresponding cavity of the plurality of cavities.

[0139] Example 9 includes the subject matter of any of Examples 1 to 8, wherein for each of the plurality of cavities, a liner is arranged around the outer circumference of the corresponding cavity, and the side walls of the plurality of cavities are the side walls of the corresponding liner.

[0140] Example 10 includes the subject matter of any of Examples 1 to 9, and further includes a plurality of build-up layers adjacent to the top and bottom surfaces; and one or more semiconductor dies mounted on the build-up layers among the plurality of build-up layers.

[0141] Embodiment 11 includes an apparatus comprising: a substrate core, the substrate core having an upper side and a bottom side, wherein a plurality of cavities are defined within the substrate core extending from the bottom side to the upper side; a plurality of vias extending through the plurality of cavities defined in the substrate core, wherein there is a gap of at least 10 nanometers between at least a portion of the individual vias of the plurality of vias and the sidewalls of the corresponding cavities of the plurality of cavities; and a plurality of via caps, wherein the individual via caps of the plurality of via caps are located at one end of the individual vias of the plurality of vias.

[0142] Example 12 includes the subject matter of Example 11, wherein the individual vias of the plurality of vias are not fixed to the sidewalls of the corresponding cavities of the plurality of cavities.

[0143] Example 13 includes the subject matter of either Example 11 or 12, wherein the plurality of via caps are countersinked on the substrate core such that at least a portion of each individual via cap of the plurality of via caps extends below the plane defined by the upper side of the substrate core.

[0144] Example 14 incorporates the subject matter of any of Examples 11 to 13, wherein the plurality of via caps are coplanar with the substrate core such that no portion of any individual via cap of the plurality of via caps extends above the plane defined by the upper side of the substrate core.

[0145] Example 15 includes the subject matter of any of Examples 11 to 14, wherein each of the multiple via caps is fixed to the upper side of the substrate core.

[0146] Example 16 includes the subject matter of any of Examples 11 to 15, wherein each individual via cap of the plurality of via caps has a seed layer of a first granular structure and an electroplated layer of a second granular structure different from the first granular structure.

[0147] Example 17 includes the subject matter of any of Examples 11 to 16, wherein the individual via caps of the plurality of via caps are not fixed to the substrate core.

[0148] Example 18 includes the subject matter of any of Examples 11 to 17, wherein the cross section of each individual via of the plurality of vias, taken perpendicular to the individual via, does not contact the side wall of the corresponding cavity of the plurality of cavities.

[0149] Example 19 incorporates the subject matter of any of Examples 11 to 18, wherein for each of the plurality of cavities, a liner is arranged around the outer circumference of the corresponding cavity, and the side walls of the plurality of cavities are the side walls of the corresponding liner.

[0150] Example 20 incorporates the subject matter of any of Examples 11 to 19, wherein less than half of the surface area of ​​each individual via of the plurality of vias is in contact with the side wall of the corresponding cavity of the plurality of cavities.

[0151] Example 21 includes the subject matter of any of Examples 11 to 20, and further includes a plurality of build-up layers adjacent to the top and bottom surfaces; and one or more semiconductor dies mounted on the build-up layers among the plurality of build-up layers.

[0152] Example 22 includes a method comprising the steps of creating a plurality of holes in a glass core; and creating a plurality of vias having via caps in the plurality of holes using a bottom-up plating process.

[0153] Example 23 includes the subject matter of Example 22, wherein the steps of creating the plurality of vias having via caps in the plurality of holes include: forming a seed layer on the glass core; patterning a photoresist on the seed layer; electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and electroplating the plurality of vias on the via caps.

[0154] Example 24 includes the subject matter of either Example 22 or 23, wherein the steps of creating the plurality of vias having via caps in the plurality of holes include: patterning a photoresist on the glass core; bonding a carrier on the glass core, the carrier including a seed layer; electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and electroplating the plurality of vias on the via caps.

[0155] Example 25 includes the subject matter of any of Examples 22 to 24, wherein the step of creating the plurality of vias having via caps in the plurality of holes includes: creating a plurality of countersink holes around the plurality of holes in the glass core; forming a seed layer on the glass core; patterning a photoresist on the seed layer; electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and electroplating the plurality of vias on the via caps. [Other adjacent items] [Item 1] A substrate core, the substrate core having an upper side and a lower side, wherein a plurality of cavities are defined within the substrate core, and each of the plurality of cavities extends from the lower side to the upper side; A plurality of vias extending through the plurality of cavities defined in the substrate core, wherein each via of the plurality of vias is not fixed to the sidewall of the corresponding cavity of the plurality of cavities; and Multiple beer caps, where each individual beer cap of the multiple beer caps is positioned at one end of each individual beer of the multiple beers. A device equipped with the following features. [Item 2] The apparatus according to item 1, wherein the plurality of via caps are countersinked on the substrate core such that at least a portion of each individual via cap of the plurality of via caps extends below the plane defined by the upper side of the substrate core. [Item 3] The apparatus according to item 2, wherein the plurality of via caps are coplanar with the substrate core such that no portion of any individual via cap of the plurality of via caps extends above the plane defined by the upper side of the substrate core. [Item 4] The apparatus according to item 1, wherein each of the plurality of via caps is fixed to the upper surface side of the substrate core. [Item 5] The apparatus according to item 4, wherein each of the plurality of via caps has a seed layer having a first granular structure and an electroplating layer having a second granular structure different from the first granular structure. [Item 6] The apparatus according to item 1, wherein there is a gap of at least 10 nanometers between at least some of the individual vias of the plurality of vias and between the side walls of the corresponding cavities of the plurality of cavities. [Item 7] The apparatus according to item 1, wherein the cross-section of each of the plurality of vias, taken perpendicular to the individual via, does not contact the side wall of the corresponding cavity of the plurality of cavities. [Item 8] Multiple build-up layers adjacent to the upper and lower surfaces; and One or more semiconductor dies mounted on the build-up layer of the aforementioned multiple build-up layers The apparatus described in item 1, further comprising the above. [Item 9] A substrate core, the substrate core having an upper side and a lower side, wherein a plurality of cavities are defined within the substrate core, extending from the lower side to the upper side; A plurality of vias extending through the plurality of cavities defined in the substrate core, wherein there is a gap of at least 10 nanometers between at least a portion of each of the plurality of vias and the sidewalls of the corresponding cavities of the plurality of cavities; and Multiple beer caps, where each individual beer cap of the multiple beer caps is positioned at one end of each individual beer of the multiple beers. A device equipped with the following features. [Item 10] The apparatus according to item 9, wherein the individual vias of the plurality of vias are not fixed to the side walls of the corresponding cavities of the plurality of cavities. [Item 11] The apparatus according to item 9, wherein the plurality of via caps are countersinked on the substrate core such that at least a portion of each individual via cap of the plurality of via caps extends below the plane defined by the upper side of the substrate core. [Item 12] The apparatus according to item 9, wherein each of the plurality of via caps is fixed to the upper surface side of the substrate core. [Item 13] The apparatus according to item 12, wherein each of the plurality of via caps has a seed layer of a first granular structure and an electroplating layer of a second granular structure different from the first granular structure. [Item 14] The apparatus according to item 9, wherein the individual via caps of the plurality of via caps are not fixed to the substrate core. [Item 15] The apparatus according to item 9, wherein for each of the plurality of cavities, a liner is arranged around the outer circumference of the corresponding cavity, and the side walls of the plurality of cavities are the side walls of the corresponding liner. [Item 16] The apparatus according to item 9, wherein less than half of the surface area of ​​each individual via of the plurality of vias is in contact with the side wall of the corresponding cavity of the plurality of cavities. [Item 17] Multiple build-up layers adjacent to the upper and lower surfaces; and One or more semiconductor dies mounted on the build-up layer of the aforementioned multiple build-up layers The apparatus described in item 9, further comprising the above. [Item 18] The step of creating multiple holes in the glass core; and A step of creating multiple vias having via caps in the multiple holes using a bottom-up plating process. A method that includes [a certain feature]. [Item 19] The step of creating the plurality of vias, each having a via cap in the plurality of holes, is: A step of forming a seed layer on the glass core; The step of patterning a photoresist on the seed layer; A step of electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and Steps to electroplat the plurality of vias on the via cap. The method described in item 18, which has the following characteristics. [Item 20] The step of creating the plurality of vias, each having a via cap in the plurality of holes, is: The step of patterning a photoresist on the glass core; The step of bonding carriers onto the glass core, where the carriers include a seed layer; A step of electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and Steps to electroplat the plurality of vias on the via cap. The method described in item 18, which has the following characteristics.

Claims

1. A substrate core, the substrate core having an upper side and a lower side, wherein a plurality of cavities are defined within the substrate core, and each of the plurality of cavities extends from the lower side to the upper side; A plurality of vias extending through the plurality of cavities defined in the substrate core, wherein each via of the plurality of vias is not fixed to the sidewall of the corresponding cavity of the plurality of cavities; and Multiple beer caps, where each individual beer cap of the multiple beer caps is positioned at one end of each individual beer of the multiple beers. A device equipped with the following features.

2. The apparatus according to claim 1, wherein at least a portion of each of the plurality of via caps is countersinked on the substrate core such that the plurality of via caps extend below the plane defined by the upper surface of the substrate core.

3. The apparatus according to claim 2, wherein the plurality of via caps are coplanar with the substrate core such that no portion of any individual via cap of the plurality of via caps extends above the plane defined by the upper surface of the substrate core.

4. The apparatus according to claim 1, wherein each of the plurality of via caps is fixed to the upper surface side of the substrate core.

5. The apparatus according to claim 4, wherein each of the plurality of via caps has a seed layer having a first granular structure and an electroplating layer having a second granular structure different from the first granular structure.

6. The apparatus according to any one of claims 1 to 5, wherein a gap of at least 10 nanometers exists between at least a portion of the individual vias of the plurality of vias and between the side walls of the corresponding cavities of the plurality of cavities.

7. The apparatus according to claim 1, wherein the individual via caps of the plurality of via caps are not fixed to the substrate core.

8. The apparatus according to any one of claims 1 to 5, wherein the cross-section of each of the plurality of vias, taken perpendicular to the individual via, does not contact the side wall of the corresponding cavity of the plurality of cavities.

9. The apparatus according to any one of claims 1 to 5, wherein for each of the plurality of cavities, a liner is arranged around the outer circumference of the corresponding cavity, and the side walls of the plurality of cavities are the side walls of the corresponding liner.

10. Multiple build-up layers adjacent to the upper and lower surfaces; and One or more semiconductor dies mounted on the build-up layer among the multiple build-up layers The apparatus according to any one of claims 1 to 5, further comprising:

11. A substrate core, the substrate core having an upper side and a lower side, wherein a plurality of cavities are defined within the substrate core, extending from the lower side to the upper side; A plurality of vias extending through the plurality of cavities defined in the substrate core, wherein there is a gap of at least 10 nanometers between at least a portion of each of the plurality of vias and the sidewalls of the corresponding cavities of the plurality of cavities; and Multiple beer caps, where each individual beer cap of the multiple beer caps is positioned at one end of each individual beer of the multiple beers. A device equipped with the following features.

12. The apparatus according to claim 11, wherein each of the plurality of vias is not fixed to the side wall of the corresponding cavity of the plurality of cavities.

13. The apparatus according to claim 11, wherein at least a portion of each of the plurality of via caps is countersinked on the substrate core such that the plurality of via caps extend below the plane defined by the upper side of the substrate core.

14. The apparatus according to claim 13, wherein the plurality of via caps are coplanar with the substrate core such that no portion of any individual via cap of the plurality of via caps extends above the plane defined by the upper surface of the substrate core.

15. The apparatus according to claim 11, wherein each of the plurality of via caps is fixed to the upper surface side of the substrate core.

16. The apparatus according to claim 15, wherein each of the plurality of via caps has a seed layer having a first granular structure and an electroplating layer having a second granular structure different from the first granular structure.

17. The apparatus according to claim 11, wherein the individual via caps of the plurality of via caps are not fixed to the substrate core.

18. The apparatus according to any one of claims 11 to 17, wherein the cross-section of each of the plurality of vias, taken perpendicular to the individual via, does not contact the side wall of the corresponding cavity of the plurality of cavities.

19. The apparatus according to any one of claims 11 to 17, wherein for each of the plurality of cavities, a liner is arranged around the outer circumference of the corresponding cavity, and the side walls of the plurality of cavities are the side walls of the corresponding liner.

20. The apparatus according to any one of claims 11 to 17, wherein less than half of the surface area of ​​each individual via of the plurality of vias is in contact with the side wall of the corresponding cavity of the plurality of cavities.

21. Multiple build-up layers adjacent to the upper and lower surfaces; and One or more semiconductor dies mounted on the build-up layer among the multiple build-up layers The apparatus according to any one of claims 11 to 17, further comprising the above.

22. The step of creating multiple holes in the glass core; and A step of creating multiple vias having via caps in the multiple holes using a bottom-up plating process. A method that includes [a certain feature].

23. The step of creating the plurality of vias, each having a via cap in the plurality of holes, is: A step of forming a seed layer on the glass core; The step of patterning a photoresist on the seed layer; A step of electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and Steps to electroplat the plurality of vias on the via cap. The method according to claim 22, having the following characteristics.

24. The step of creating the plurality of vias, each having a via cap in the plurality of holes, is: The step of patterning a photoresist on the glass core; The step of bonding carriers onto the glass core, where the carriers include a seed layer; A step of electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and Steps to electroplat the plurality of vias on the via cap. The method according to claim 22, having the following characteristics.

25. The step of creating the plurality of vias, each having a via cap in the plurality of holes, is: A step of creating a plurality of countersink holes around the plurality of holes in the glass core; A step of forming a seed layer on the glass core; The step of patterning a photoresist on the seed layer; A step of electroplating the via caps of the plurality of vias on the seed layer in the region defined by the photoresist; and Steps to electroplat the plurality of vias on the via cap. The method according to claim 22, having the following characteristics.

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