Magnetoresistive element, magnetic memory, and method for controlling magnetic memory

Abstract

The objective is to provide a magnetoresistive element, a magnetic memory, and a control method for the magnetic memory, in which writing is controlled by a new method. [Solution] This magnetoresistive element comprises a spin-orbit torque wiring, a laminate, and a transistor. The laminate comprises a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first and second ferromagnetic layers. The transistor has a first terminal, a second terminal, and a third terminal. The first terminal is electrically connected to a first contact of the spin-orbit torque wiring. The second terminal is electrically connected to a second contact of the spin-orbit torque wiring. The laminate is in contact with the spin-orbit torque wiring between the first and second contacts of the current path along the spin-orbit torque wiring.

Description

[Technical Field]

[0001] This disclosure relates to a magnetoresistive element, a magnetic memory, and a method for controlling a magnetic memory. [Background technology]

[0002] Giant magnetoresistance (GMR) elements, which consist of a multilayer film of a ferromagnetic layer and a non-magnetic layer, and tunnel magnetoresistance (TMR) elements, which use an insulating layer (tunnel barrier layer, barrier layer) in the non-magnetic layer, are known as magnetoresistive elements. Magnetoresistive elements can be applied to magnetic sensors, high-frequency components, magnetic heads, and non-volatile random-access memory (MRAM).

[0003] MRAM is a memory element that integrates magnetoresistive elements. MRAM reads and writes data by utilizing the property that the resistance of the magnetoresistive elements changes when the direction of magnetization of the two ferromagnetic layers flanking the non-magnetic layer in the magnetoresistive element changes. For example, there are proposed designs that control the direction of magnetization of the ferromagnetic layers using the magnetic field generated by an electric current, and designs that control the direction of magnetization of the ferromagnetic layers using the spin transfer torque (STT) generated by passing an electric current in the stacking direction of the magnetoresistive elements.

[0004] When using STT to rewrite the magnetization direction of a ferromagnetic layer, current is passed in the direction of stacking of the magnetoresistive elements. The writing current can cause degradation of the characteristics of the magnetoresistive elements.

[0005] In recent years, attention has been focused on methods that do not require current to flow in the stacking direction of magnetoresistive elements during writing (for example, Patent Documents 1 and 2). One such method is a writing method that utilizes spin-orbit torque (SOT). SOT is induced by a spin current generated by spin-orbit interaction or by the Rashba effect at the interface of dissimilar materials. The current required to induce SOT in a magnetoresistive element flows in a direction intersecting the stacking direction of the magnetoresistive elements. In other words, it is not necessary to flow current in the stacking direction of the magnetoresistive elements, and this is expected to extend the lifespan of the magnetoresistive elements. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2019-33166 [Patent Document 2] Japanese Patent Publication No. 2019-54154 [Overview of the project] [Problems that the invention aims to solve]

[0007] Magnetic memory has multiple magnetoresistive elements. To increase the storage capacity per unit volume of magnetic memory, it is necessary to increase the number of magnetoresistive elements arranged within a given area. Magnetic memory with a large number of magnetoresistive elements arranged within a given area has superior integration performance, while magnetic memory with a small number of magnetoresistive elements arranged within a given area has inferior integration performance.

[0008] The size of the selector (e.g., a transistor) that controls the operation of a magnetoresistive element is larger than the size of the magnetoresistive element itself. In particular, the write control selector, which is responsible for writing data to the magnetoresistive element, needs to control large voltages or currents and is therefore large in size. There is a need for a new write control method that can reduce the size of the write control selector that is placed within the integrated region.

[0009] This disclosure is made in view of the above circumstances and aims to provide a magnetoresistive element, a magnetic memory, and a method for controlling a magnetic memory that can control data writing in a new manner. [Means for solving the problem]

[0010] This disclosure provides the following means to solve the above problems.

[0011] The magnetoresistive effect element according to the first aspect includes a spin-orbit torque wiring, a laminate, and a transistor. The laminate includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The transistor has a first terminal, a second terminal, and a third terminal. The first terminal is electrically connected to a first contact of the spin-orbit torque wiring. The second terminal is electrically connected to a second contact of the spin-orbit torque wiring. The laminate is in contact with the spin-orbit torque wiring between the first contact and the second contact of the current path along the spin-orbit torque wiring.

Advantages of the Invention

[0012] The magnetoresistive effect element, the magnetic memory, and the control method of the magnetic memory according to the present disclosure control data writing in a new manner.

Brief Description of the Drawings

[0013] [Figure 1] It is a block diagram of a magnetic memory according to the first embodiment. [Figure 2] It is a circuit diagram of a magnetic memory according to the first embodiment. [Figure 3] It is a cross-sectional view near one unit of a magnetic memory according to the first embodiment. [Figure 4] It is a cross-sectional view of a magnetoresistive effect element according to the first embodiment. [Figure 5] It is a plan view of a magnetoresistive effect element according to the first embodiment. [Figure 6] It is a schematic diagram for explaining a first example of a write control method of a magnetic memory according to the first embodiment. [Figure 7] It is a schematic diagram for explaining a second example of a write control method of a magnetic memory according to the first embodiment. [Figure 8] It is a schematic diagram for explaining a read control method of a magnetic memory according to the first embodiment. [Figure 9] It is a circuit diagram of a magnetic memory according to the first modification of the first embodiment. [Figure 10] It is a cross-sectional view of the vicinity of one unit of the magnetic memory according to the second embodiment. [Figure 11] It is a cross-sectional view of the vicinity of one unit of the magnetic memory according to the third embodiment. [Figure 12] It is a cross-sectional view of the vicinity of one unit of the magnetic memory according to the first modification of the third embodiment. [Figure 13] It is a cross-sectional view of the vicinity of one unit of the magnetic memory according to the fourth embodiment. [Figure 14] It is a cross-sectional view of the vicinity of one unit of the magnetic memory according to the first modification of the fourth embodiment. [Figure 15] It is a circuit diagram of the magnetic memory according to the fifth embodiment. [Figure 16] It is a circuit diagram of the magnetic memory according to the sixth embodiment. [Figure 17] It is a circuit diagram of the magnetic memory according to the seventh embodiment. [Figure 18] It is a circuit diagram of the magnetic memory according to the eighth embodiment.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, the present embodiment will be described in detail with appropriate reference to the drawings. The drawings used in the following description may show the characteristic parts enlarged for convenience to make the characteristics easier to understand, and the dimensional ratios of each component may be different from the actual ones. The materials, dimensions, etc. exemplified in the following description are examples, and the present disclosure is not limited to them, and it can be appropriately changed and implemented within the scope where the effects of the present disclosure are achieved.

[0015] First, let's define the directions. One direction on one side of the substrate 90 (see Figure 3), described later, is defined as the x-direction, and the direction perpendicular to the x-direction is defined as the y-direction. The x-direction is, for example, the longitudinal direction of the spin-orbit torque wiring. The z-direction is the direction perpendicular to both the x-direction and the y-direction. The z-direction is an example of the stacking direction in which each layer is stacked. Hereafter, the +z direction may be expressed as "up" and the -z direction as "down". Up and down do not necessarily coincide with the direction in which gravity acts.

[0016] In this specification, "extending in the x-direction" means, for example, that the dimension in the x-direction is greater than the smallest dimension among the dimensions in the x, y, and z directions. The same applies to extensions in other directions. Furthermore, in this specification, "connection" is not limited to cases where two layers are directly connected. For example, "connection" is not limited to cases where two layers are directly in contact with each other, but also includes cases where two layers are indirectly connected with another layer in between.

[0017] "First Embodiment" Figure 1 is a block diagram of a magnetic memory 100 according to the first embodiment. The magnetic memory 100 has an integrated region A1 and a peripheral region A2.

[0018] Integrated region A1 is a region where multiple magnetoresistive elements are integrated. Integrated region A1 stores data using multiple magnetoresistive elements.

[0019] The peripheral region A2 is a region that controls data writing to and reading from the integrated region A1. Peripheral region A2 includes, for example, a writing circuit B1 and a reading circuit B2. Figure 1 shows an example where peripheral region A2 is outside the integrated region A1, but peripheral region A2 may be on a different layer in the z direction from the integrated region A1.

[0020] The writing circuit B1 controls the writing of data to magnetoresistive elements within the integrated region A1. The writing circuit B1 includes, for example, a power supply, a control device, a processor, and memory. The power supply generates a potential difference for applying writing current to the magnetoresistive elements. The control device controls which magnetoresistive elements receive the writing current. The control device is operated by a processor, which operates based on an operating program stored in memory. The processor is, for example, a CPU (Central Processing Unit).

[0021] The read circuit B2 controls the reading of data from magnetoresistive elements within the integrated region A1. The read circuit B2 includes, for example, a power supply, a control device, a processor, and memory. The power supply generates a potential difference for applying read current to the magnetoresistive elements. The control device controls which magnetoresistive elements receive the read current. The control device is operated by a processor, which operates based on an operating program stored in memory. The processor and memory may be located in both the write circuit B1 and the read circuit B2, or they may be shared between the write circuit B1 and the read circuit B2.

[0022] Figure 2 is a circuit diagram of a magnetic memory 100 according to the first embodiment. The magnetic memory 100 includes a plurality of magnetoresistive elements 10, a plurality of write control selectors 20, a plurality of read control selectors 30, a plurality of main write lines W1, a plurality of sub-write lines W2, a plurality of read lines R, a plurality of first gate lines G1, a plurality of second gate lines G2, and a plurality of common lines C. The magnetic memory 100 is, for example, a magnetic array in which the magnetoresistive elements 10 are arranged in an array.

[0023] Multiple magnetoresistive elements 10 are divided into multiple units U. Each unit U is connected to one main writing line W1 and one common line C. Within each unit U are multiple magnetoresistive elements 10. The multiple magnetoresistive elements 10 are arranged within the integration region A1 shown in Figure 1. The specific structure of the magnetoresistive elements 10 will be described later.

[0024] Each of the multiple write control selectors 20 is located between the first terminal UA of each unit U and the main write line W1. The write control selector 20 is a control element that controls the write current flowing through the unit U. The write control selector 20 is an example of a first write control selector and a second write control selector.

[0025] The write control selector 20 is, for example, a transistor, an element that utilizes a phase change in the crystal layer such as an ovonic threshold switch (OTS), an element that utilizes a change in band structure such as a metal-insulator transition (MIT) switch, an element that utilizes a breakdown voltage such as a Zener diode and an avalanche diode, or an element whose conductivity changes with a change in atomic position. Figure 1 illustrates the case where the write control selector 20 is a three-terminal transistor. The write control selector 20 belongs to the write circuit B1 in peripheral region A2 shown in Figure 1, for example.

[0026] Each of the multiple first gate lines G1 is connected to the gate of the write control selector 20. The first gate lines G1 may be connected to multiple write control selectors 20. Multiple write control selectors 20 connected to the same first gate line G1 are connected to different main write lines W1. Each of the multiple first gate lines G1 is a wire connecting the write circuit B1 in the peripheral region A2 to the integrated region A1. When a voltage is applied to the write control selector 20 via the first gate line G1, a write current flows to the unit U connected to the write control selector 20.

[0027] Each of the multiple main writing lines W1 is a wire for carrying writing current. Each of the multiple main writing lines W1 is connected to a unit U via a writing control selector 20. Multiple units U may be connected to each of the main writing lines W1. The number of units U connected to a main writing line W1 is not limited. One of the multiple units U connected to the same main writing line W1 will be referred to as the first unit U1, and another as the second unit U2. The main writing line W1 belongs to the writing circuit B1 in peripheral area A2 shown in Figure 1, for example. The main writing line W1 is connected to the power supply in the writing circuit B1, for example.

[0028] Each of the multiple sub-writing lines W2 is connected to the gate of a transistor in the magnetoresistive element 10. Each of the multiple sub-writing lines W2 may be connected to multiple magnetoresistive elements 10. Multiple magnetoresistive elements 10 connected to the same sub-writing line W2 belong to different units U. The multiple sub-writing lines W2 are wirings that connect the writing circuit B1 in the peripheral region A2 to the integrated region A1. The multiple sub-writing lines W2 are connected, for example, to a power supply in the writing circuit B1.

[0029] Each of the multiple read lines R is a wire for carrying read current. Each of the multiple read lines R is connected to one of the multiple read control selectors 30. Each of the multiple read lines R is connected to one of the magnetoresistive elements 10 via the read control selector 30. Each of the multiple read lines R may be connected to multiple magnetoresistive elements 10. Multiple magnetoresistive elements 10 connected to the same read line R belong to different units U. The multiple read lines R are wires that connect the read circuit B2 in the peripheral region A2 to the integrated region A1. The multiple read lines R are connected to, for example, the power supply in the read circuit B2.

[0030] Each of the multiple read control selectors 30 is connected to one of the magnetoresistive elements 10. The read control selector 30 is a control element that controls the read current flowing to the magnetoresistive element 10. There is a one-to-one correspondence between the read control selector 30 and the magnetoresistive element 10. The read control selector 30 is an example of a first read control selector and a second read control selector. The read control selector 30 can be the same as the write control selector 20. Figure 1 illustrates the case where the read control selector 30 is a three-terminal transistor. The read control selector 30 is arranged, for example, in the integrated region A1 shown in Figure 1. Since the read current for reading data from the magnetoresistive element 10 is smaller than the write current for writing data to the magnetoresistive element 10, the read control selector 30 is smaller in size than the write control selector 20.

[0031] Each of the multiple second gate lines G2 is connected to the gate of the read control selector 30. The second gate lines G2 may be connected to multiple read control selectors 30. Each of the multiple second gate lines G2 is a wire connecting the read circuit B2 in the peripheral region A2 to the integrated region A1. When a voltage is applied to the read control selector 30 via the second gate lines G2, a read current flows through the magnetoresistive element 10 connected to the read control selector 30.

[0032] Each of the multiple common wires C is connected to the second terminal UB of one of the units U. The second terminal UB is the end of the unit U opposite to the first terminal UA. The magnetoresistive elements belonging to the unit U are connected in series between the first terminal UA and the second terminal UB. Each of the multiple common wires C may be connected to multiple units U. For example, multiple units U connected to a certain main writing line W1 are all connected to a single common wire C. For example, the first unit U1 and the second unit U2 may be connected to the same common wire C. Each of the multiple common wires C is a wire for carrying write current and read current. Each of the multiple common wires C is used during both writing and reading. The first common wire and the second common wire are examples of common wires.

[0033] Figure 3 is a cross-sectional view of the vicinity of one unit U of the magnetic memory 100 according to the first embodiment. Figure 3 is a cross-section of the spin orbit torque wiring 12 of the magnetoresistive element 10, cut by the xz plane passing through the center of the width in the y direction.

[0034] The magnetic memory 100 has a substrate 90 and a laminated structure 91. The substrate 90 is a support for the laminated structure 91. The substrate 90 is, for example, a semiconductor substrate. A transistor 13 of the magnetoresistive effect element 10 is formed on a part of the substrate 90.

[0035] The stacked structure 91 has multiple magnetoresistive elements 10, multiple write control selectors 20, multiple read control selectors 30, multiple main write lines W1, multiple sub-write lines W2, multiple read lines R, multiple first gate lines G1, multiple second gate lines G2, and multiple common lines C.

[0036] Magnetoresistive elements 10 belonging to the same unit U are connected in series, for example, via wiring 41. Wiring 41 is a conductor extending in the xy plane. Magnetoresistive elements 10 are connected in series between the first end UA and the second end UB of unit U. The second end UB is connected to the common wire C, for example, via wiring 41.

[0037] The write control selector 20 is connected to the first end UA of unit U via wiring 41 and via wiring 43. Via wiring 43 is a conductor extending in the z direction. The write control selector 20 belongs to peripheral region A2.

[0038] The write control selector 20 includes, for example, a first active region 201, a second active region 202, a gate insulating layer 203, and a gate electrode 204.

[0039] The first active region 201 and the second active region 202 are semiconductors into which carriers are injected. The first active region 201 and the second active region 202 are the source and drain of the transistor. Which of the first active region 201 and the second active region 202 is the source or drain depends on the direction of current flow. The first active region 201 is connected to the main writing line W1 via via wiring 42. Via wiring 42 is a conductor extending in the z direction. The second active region 202 is connected to unit U via via wiring 43 and wiring 41. The gate insulating layer 203 is an insulator. The gate electrode 204 is connected to the first gate line G1. The gate electrode 204 is a conductor.

[0040] The channel length L1 of the write control selector 20 is wider than the channel length L2 of the transistor 13 that constitutes the magnetoresistive element 10. Furthermore, the area of ​​the write control selector 20 is wider than the area of ​​the transistor 13 that constitutes the magnetoresistive element 10. This is because the write control selector 20 controls the write current flowing through unit U, requiring transistors with high voltage resistance. Additionally, the channel width in the Y direction of the write control selector 20 is wider than the channel width in the Y direction of the transistor 13 that constitutes the magnetoresistive element 10. Because the write control selector 20 has a wider channel width than the transistor 13, it can handle larger currents.

[0041] The readout control selector 30 is not shown in Figure 3 and is located at a different position on the page. The readout line R and the readout control selector 30 are not shown in Figure 3 and are connected to electrode E1. The second gate line G2 is not shown in Figure 3 and is located at a different position on the page.

[0042] The elements and wiring within the laminated structure 91 are surrounded by an insulator 92. The insulator 92 is an insulating layer that insulates the spaces between wiring and elements in the multilayer wiring. The insulator 92 is made of, for example, silicon oxide (SiO2). x ), silicon nitride (SiN x ), silicon carbide (SiC), chromium nitride (CrN), silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al2O3), zirconium oxide (ZrO3) x Examples include magnesium oxide (MgO), aluminum nitride (AlN), etc.

[0043] Figure 4 is a cross-sectional view of the vicinity of the magnetoresistive element 10 according to the first embodiment. Figure 5 is a plan view of the magnetoresistive element 10 according to the first embodiment. In Figure 5, the insulator 92 is not shown.

[0044] The magnetoresistive element 10 comprises a laminate 11, spin-orbit torque wiring 12, a transistor 13, via wiring 14, and via wiring 15.

[0045] The laminate 11 is in contact with the spin-orbit torque wiring 12 between the first contact P1 and the second contact P2 of the current path along the spin-orbit torque wiring 12. The laminate 11 is, for example, laminated on the spin-orbit torque wiring 12.

[0046] The resistance of the laminate 11 in the z direction changes as spin is injected into the laminate 11 from the spin-orbit torque wiring 12. The magnetoresistive element 10 is a magnetic element that utilizes spin-orbit torque (SOT), and is sometimes called a spin-orbit torque type magnetoresistive element, spin-injection type magnetoresistive element, or spin-current magnetoresistive element.

[0047] The laminate 11 is sandwiched in the z-direction between the spin-orbit torque wiring 12 and the electrode E1. The laminate 11 is connected to the readout control selector 30 via the electrode E1.

[0048] The laminate 11 is columnar. The shape of the laminate 11 in plan view from the z direction is, for example, circular, elliptical, or quadrilateral. The sides of the laminate 11 are, for example, inclined with respect to the z direction.

[0049] The laminate 11 includes, for example, a first ferromagnetic layer 1, a second ferromagnetic layer 2, and a non-magnetic layer 3. The first ferromagnetic layer 1 is, for example, in contact with a spin-orbit torque wiring 12 and is laminated on the spin-orbit torque wiring 12. Spins are injected into the first ferromagnetic layer 1 from the spin-orbit torque wiring 12. If spins generated in the spin-orbit torque wiring 12 can be injected into the first ferromagnetic layer 1, other layers may be present between the first ferromagnetic layer 1 and the spin-orbit torque wiring 12. The magnetization of the first ferromagnetic layer 1 changes its orientation direction due to the spin-orbit torque (SOT) caused by the injected spins. The first ferromagnetic layer 1 and the second ferromagnetic layer 2 are sandwiched in the z direction by the non-magnetic layer 3.

[0050] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 each have magnetization. The magnetization M2 of the second ferromagnetic layer 2 is less likely to change orientation direction than the magnetization M1 of the first ferromagnetic layer 1 when a predetermined external force is applied. In the figure, the orientation directions of magnetization M1 and magnetization M2 are shown by arrows. The first ferromagnetic layer 1 is called the magnetization free layer, and the second ferromagnetic layer 2 is sometimes called the magnetization fixed layer or magnetization reference layer. In the laminate 11 shown in Figure 4, the magnetization fixed layer is on the side away from the substrate 90, and is called a top-pin structure. The laminate 11 may also be a bottom-pin structure in contact with the lower surface of the spin-orbit torque wiring 12. The resistance value of the laminate 11 changes according to the difference in the relative angle of magnetization between the first ferromagnetic layer 1 and the second ferromagnetic layer 2, which sandwich the non-magnetic layer 3.

[0051] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 contain a ferromagnetic material. The ferromagnetic material is, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing one or more of these metals and at least one element of B, C, and N, etc. The ferromagnetic material is, for example, Co-Fe, Co-Fe-B, Ni-Fe, Co-Ho alloy, Sm-Fe alloy, Fe-Pt alloy, Co-Pt alloy, CoCrPt alloy.

[0052] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 may contain a Heusler alloy. The Heusler alloy contains an intermetallic compound having a chemical composition of XYZ or X2YZ. X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group in the periodic table, Y is a transition metal of the Mn, V, Cr, or Ti group or an element species of X, and Z is a typical element from Group III to Group V. The Heusler alloy is, for example, Co2FeSi, Co2FeGe, Co2FeGa, Co2MnSi, Co2Mn 1-a Fe a Al b Si 1-b , Co2FeGe 1-c Ga c etc. The Heusler alloy has a high spin polarization rate.

[0053] The non-magnetic layer 3 contains a non-magnetic material. When the non-magnetic layer 3 is an insulator (when it is a tunnel barrier layer), as its material, for example, Al2O3, SiO2, MgO, MgAl2O4, etc. can be used. In addition to these, materials in which part of Al, Si, and Mg are replaced by Zn, Be, etc. can also be used. Among these, MgO and MgAl2O4 are materials capable of realizing coherent tunneling, so spin can be efficiently injected. When the non-magnetic layer 3 is a metal, as its material, Cu, Au, Ag, etc. can be used. Furthermore, when the non-magnetic layer 3 is a semiconductor, as its material, Si, Ge, CuInSe2, CuGaSe2, Cu(In,Ga)Se2, etc. can be used.

[0054] The laminate 11 may have layers other than the first ferromagnetic layer 1, the second ferromagnetic layer 2, and the non-magnetic layer 3. For example, there may be an underlayer between the spin-orbit torque wiring 12 and the first ferromagnetic layer 1. The underlayer enhances the crystallinity of each layer constituting the laminate 11. Alternatively, for example, there may be a cap layer on the uppermost surface of the laminate 11.

[0055] The laminate 11 may also have a ferromagnetic layer on the side of the second ferromagnetic layer 2 opposite to the non-magnetic layer 3, via a spacer layer. The second ferromagnetic layer 2, the spacer layer, and the ferromagnetic layer form a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure consists of two magnetic layers flanking a non-magnetic layer. The antiferromagnetic coupling between the second ferromagnetic layer 2 and the ferromagnetic layer increases the coercivity of the second ferromagnetic layer 2 compared to the case without a ferromagnetic layer. The ferromagnetic layer is, for example, IrMn, PtMn, etc. The spacer layer includes, for example, at least one selected from the group consisting of Ru, Ir, and Rh.

[0056] The spin-orbit torque wiring 12 is in contact with the laminate 11. Spin-orbit torque wiring 12 belonging to the same unit U are connected in series, for example, via wiring 41.

[0057] The spin-orbit torque wiring 12 is, for example, wiring whose length in the x-direction is longer than that in the y-direction when viewed from the z-direction. The planar shape of the spin-orbit torque wiring 12 is not limited to a rectangle, but may also be U-shaped or V-shaped. The writing current flows along the spin-orbit torque wiring 12.

[0058] The spin-orbit torque wiring 12 generates a spin current through the spin Hall effect when an electric current flows, injecting spin into the first ferromagnetic layer 1. The spin-orbit torque wiring 12 applies a spin-orbit torque (SOT) to the magnetization of the first ferromagnetic layer 1 sufficient to reverse its magnetization. The spin Hall effect is a phenomenon in which, when an electric current flows, a spin current is induced in a direction perpendicular to the direction of the current flow, based on spin-orbit interaction. The spin Hall effect is similar to the ordinary Hall effect in that the direction of motion (movement) of moving charges (electrons) is bent. In the ordinary Hall effect, the direction of motion of charged particles moving in a magnetic field is bent by the Lorentz force. In contrast, in the spin Hall effect, the direction of spin movement is bent simply by the movement of electrons (simply by the flow of electric current), even without a magnetic field.

[0059] For example, when current flows through the spin-orbit torque wiring 12, the first spin, which is oriented in one direction, and the second spin, which is oriented in the opposite direction to the first spin, are each bent in a direction perpendicular to the direction of the current flow by the spin Hall effect. For example, when current flows in the +x direction, the first spin, which is oriented in the -y direction, is bent in the +z direction, and the second spin, which is oriented in the +y direction, is bent in the -z direction. Also, for example, when current flows in the -x direction, the first spin, which is oriented in the -y direction, is bent in the -z direction, and the second spin, which is oriented in the +y direction, is bent in the +z direction.

[0060] In non-magnetic materials (materials that are not ferromagnetic), the number of electrons in the first spin and the number of electrons in the second spin, which are generated by the spin Hall effect, are equal. That is, the number of electrons in the first spin moving in the +z direction is equal to the number of electrons in the second spin moving in the -z direction. The first and second spins flow in a direction that eliminates the uneven distribution of spins. In the movement of the first and second spins in the z direction, the flow of charge cancels each other out, so the amount of current is zero. A spin current that does not produce an electric current is specifically called a pure spin current.

[0061] The flow of electrons in the first spin is J ↑ , the flow of electrons with second spin is J ↓ , spin current J S Expressed as, JS =J ↑ -J ↓ It is defined as: Spin current J S This occurs in the z-direction.

[0062] The first ferromagnetic layer 1 receives either a first or second spin from the spin-orbit torque wiring 12. The choice of which spin to inject into the first ferromagnetic layer 1 can be selected by changing the direction of the current flowing through the spin-orbit torque wiring 12.

[0063] The spin-orbit torque wiring 12 includes one of the following: a metal, alloy, intermetallic compound, metal boride, metal carbide, metal silide, metal phosphide, or metal nitride, which has the function of generating a spin current.

[0064] The spin-orbit torque wiring 12 includes, for example, any of the materials selected from the group consisting of heavy metals with an atomic number of 39 or higher, metal oxides, metal nitrides, metal oxynitrides, and topological insulators. The spin-orbit torque wiring 12 may also include a magnetic material.

[0065] The spin-orbit torque wiring 12 contains, for example, a non-magnetic heavy metal as its main component. A heavy metal refers to a metal with a specific gravity greater than or equal to yttrium (Y). A non-magnetic heavy metal is, for example, a non-magnetic metal with a large atomic number of 39 or higher that has d or f electrons in its outermost shell. Non-magnetic heavy metals exhibit stronger spin-orbit interaction than other metals. The spin Hall effect arises from the spin-orbit interaction, causing spin to become unevenly distributed within the spin-orbit torque wiring 12, resulting in a spin current J S This makes it more likely to occur.

[0066] Transistor 13 is connected to spin-orbit torque wiring 12 via via wirings 14 and 15.

[0067] The transistor 13 includes, for example, a first active region 131, a second active region 132, a gate insulating layer 133, and a gate electrode 134. A known three-terminal transistor can be used for the transistor 13.

[0068] The first active region 131 and the second active region 132 are semiconductors into which carriers are injected. The first active region 131 and the second active region 132 act as the source and drain of transistor 13. Which of the first active region 131 or the second active region 132 acts as the source or drain depends on the direction of current flow.

[0069] The first active region 131 is electrically connected to the first contact P1 of the spin-orbit torque wiring 12. The first active region 131 is connected to the first contact P1, for example, via wiring 14. The first active region 131 is an example of a first terminal.

[0070] The second active region 132 is electrically connected to the second contact P2 of the spin-orbit torque wiring 12. The second active region 132 is connected to the second contact P2, for example, via wiring 15. The second active region 132 is an example of a second terminal.

[0071] The gate insulating layer 133 is an insulator that insulates the channel from the gate electrode 134.

[0072] The gate electrode 134 is a conductor. The gate electrode 134 is connected to the sub-writing line W2. The gate electrode 134 is an example of a third terminal. When a voltage is applied from the sub-writing line W2 to the gate electrode 134, a current path is formed in the channel between the first active region 131 and the second active region 132.

[0073] Via wiring 14 and via wiring 15 are wirings that extend in the z direction. Via wiring 14 and via wiring 15 are examples of conductive layers. Via wiring 14 and via wiring 15 are made of materials with excellent conductivity. Via wiring 14 and via wiring 15 are, for example, Al, Cu, W, and Cr.

[0074] Next, a method for manufacturing the magnetic memory 100 will be described. The magnetic memory 100 is formed by a layer stacking process and a processing process in which a portion of each layer is processed into a predetermined shape. For the layer stacking, sputtering, chemical vapor deposition (CVD), electron beam deposition (EB deposition), atomic laser deposition, etc., can be used. For the processing of each layer, photolithography, etc., can be used.

[0075] First, the transistor 13, write control selector 20, and read control selector 30 are formed on the circuit board 90. Alternatively, a circuit board 90 with the transistor 13, write control selector 20, and read control selector 30 already formed may be purchased.

[0076] Next, an insulator 92 is formed on the substrate 90. Via wirings 14, 15, 42, and 43 can be formed by creating openings in the insulator 92 and filling the openings with conductive material. The main writing line W1, sub-writing line W2, reading line R, common line C, first gate line G1, second gate line G2, and wiring 41 are formed by creating grooves in the insulator 92 and filling the grooves with conductive material.

[0077] The spin-orbit torque wiring 12 can be fabricated by sputtering a conductive layer connecting the via wiring 14 and via wiring 15, and then processing the conductive layer into a predetermined shape. The laminate 11 can be fabricated by depositing each layer on the spin-orbit torque wiring 12, and then processing the deposited layers into a predetermined shape. The magnetic memory 100 according to the first embodiment can be fabricated using this procedure.

[0078] Next, a control method for the magnetic memory 100 according to the first embodiment will be described. The magnetic memory 100 has write operations and read operations. First, a control method for the write operation of the magnetic memory will be described.

[0079] The data is stored as the resistance value of the laminate 11 of the magnetoresistive element 10. The resistance value of the laminate 11 of the magnetoresistive element 10 differs depending on whether the magnetizations M1 and M2 are parallel or antiparallel. For example, by setting the case where magnetizations M1 and M2 are parallel to "0" and the case where magnetizations M1 and M2 are antiparallel to "1", each magnetoresistive element 10 stores binary data. It is up to the user to decide which state to set as "0" and which as "1".

[0080] Figure 6 is a schematic diagram illustrating a first example of a write control method for the magnetic memory 100 according to the first embodiment. In Figure 6, the direction of the magnetization M1 of the first ferromagnetic layer 1 is indicated by an arrow.

[0081] First, a unit U containing the magnetoresistive element 10 to be written to is selected. The writing circuit B1 selects the unit U. Next, the write control selector 20 connected to the selected unit U is turned ON. Turning the write control selector 20 ON means applying a voltage to the gate electrode 204 of the write control selector 20 via the first gate line G1, causing current to flow in the channel between the first active region 201 and the second active region 202. By turning the write control selector 20 ON, a write current can flow between the main writing line W1 and the common line C. Although not shown in the diagram, the read control selector 30 connected to the selected unit U is turned OFF. By turning the read control selector 30 OFF, the write current flowing through the read control selector 30 can be suppressed.

[0082] In the first example of the writing method, when writing data to a predetermined magnetoresistive element 10 in unit U, the first step S1 and the second step S2 are performed.

[0083] In the first step S1, a first write current Iw1 is passed from the first terminal UA to the second terminal UB of unit U. The first write current Iw1 is a current with a current density greater than the reversal current density required to reverse the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10. In the first step S1, all transistors 13 of the magnetoresistive element 10 included in unit U are turned OFF. That is, no voltage is applied to the gate electrode 134 of transistor 13 via the sub-write line W2, and almost no current flows in the channel between the first active region 131 and the second active region 132.

[0084] Because transistor 13 is OFF, the first writing current Iw1 flows along the spin-orbit torque wiring 12 in each of the magnetoresistive elements 10. As the first writing current Iw1 flows along the spin-orbit torque wiring 12, spin is injected from the spin-orbit torque wiring 12 toward the first ferromagnetic layer 1. The magnetization M1 of the first ferromagnetic layer 1 is oriented in a predetermined direction as a result of the spin injection.

[0085] The magnetization M1 of the first ferromagnetic layer 1 in unit U is all oriented in the same direction. Regardless of the orientation of the magnetization M1 of the first ferromagnetic layer 1 in unit U before the first step S1, the first step S1 can cause the magnetization M1 of the first ferromagnetic layer 1 in unit U to be oriented in the same direction. The magnetoresistive elements 10 in unit U are all in a state of "1" or "0". Whether it is "1" or "0" depends on the initial setting. Performing the first step S1 resets the data stored in the magnetoresistive elements 10 in unit U.

[0086] Next, in the second step S2, a second writing current Iw2 is flowed from the second end UB of unit U towards the first end UA. The second writing current Iw2 is a current with a current density greater than the reversal current density required to reverse the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10. The second writing current Iw2 flows in the opposite direction to the first writing current Iw1.

[0087] In the second step S2, some of the transistors 13 of the magnetoresistive element 10 included in unit U are turned ON, and the rest are turned OFF. From the state reset in the first step S1, the transistors 13 of the magnetoresistive element 10 that reverse the direction of magnetization of the first ferromagnetic layer 1 are turned OFF, and the transistors 13 of the magnetoresistive element 10 that do not reverse the direction of magnetization of the first ferromagnetic layer 1 are turned ON.

[0088] In the magnetoresistive element 10 with transistor 13 turned OFF, the second writing current Iw2 flows along the spin-orbit torque wiring 12. As the second writing current Iw2 flows along the spin-orbit torque wiring 12, spin is injected from the spin-orbit torque wiring 12 toward the first ferromagnetic layer 1. The magnetization M1 of the first ferromagnetic layer 1 is reversed by the injection of spin.

[0089] In the magnetoresistive element 10 with transistor 13 ON, a portion of the second writing current Iw2 is diverted from the spin-orbit torque wiring 12 and flows through the channel of transistor 13. Because a portion of the second writing current Iw2 is diverted to the transistor 13 side, the current density of the current flowing through the spin-orbit torque wiring 12 becomes smaller than the reversal current density. When the current density of the current flowing through the spin-orbit torque wiring 12 is smaller than the reversal current density, sufficient torque cannot be applied to the magnetization M1 of the first ferromagnetic layer 1, and the magnetization M1 of the first ferromagnetic layer 1 does not reverse.

[0090] In the first example of the writing method, the first step aligns the direction of the magnetization M1 of the first ferromagnetic layer 1, and then the second step reverses the direction of the magnetization M1 of some of the first ferromagnetic layer 1. By performing the first and second steps, data is written to the magnetoresistive element 10 in the unit U.

[0091] Figure 7 is a schematic diagram illustrating a second example of a writing control method for the magnetic memory 100 according to the first embodiment. In Figure 7, the direction of the magnetization M1 of the first ferromagnetic layer 1 is indicated by an arrow.

[0092] In the second example, the process is the same as in the first example: a unit U containing the magnetoresistive element 10 to be written to is selected, the write control selector 20 connected to the selected unit U is turned ON, and the read control selector 30 connected to the selected unit U is turned OFF.

[0093] In the second example, when writing data to a predetermined magnetoresistive element 10 within unit U, the first step S1' and the second step S2' are performed.

[0094] In the first step S1', a first write current Iw1 is passed from the first terminal UA to the second terminal UB of the unit U. The first write current Iw1 is a current with a current density greater than the reversal current density required to reverse the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10. In the first step S1', the transistor 13 of a predetermined magnetoresistive element 10 among the magnetoresistive elements 10 included in the unit U is turned ON, and the transistors 13 of the remaining magnetoresistive elements 10 are turned OFF.

[0095] In the magnetoresistive element 10 with transistor 13 ON, a portion of the first writing current Iw1 is diverted from the spin-orbit torque wiring 12 and flows through the channel of transistor 13. Since the current density of the current flowing through the spin-orbit torque wiring 12 is smaller than the reversal current density, the magnetization M1 of the first ferromagnetic layer 1 does not reverse. In other words, the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10 with transistor 13 ON maintains its state before writing. The direction in which these magnetizations M1 are oriented is unknown unless the previous state is referred to.

[0096] In the magnetoresistive element 10 with transistor 13 OFF, the first writing current Iw1 flows along the spin-orbit torque wiring 12. As the first writing current Iw1 flows along the spin-orbit torque wiring 12, spin is injected from the spin-orbit torque wiring 12 toward the first ferromagnetic layer 1. The magnetization M1 of the first ferromagnetic layer 1 is oriented in a predetermined direction as a result of the spin injection. As the magnetization M1 of the first ferromagnetic layer 1 is oriented in a predetermined direction, data is written to the magnetoresistive element 10 with transistor 13 OFF.

[0097] Next, in the second step S2', a second write current Iw2 is flowed from the second end UB of unit U to the first end UA. The second write current Iw2 is a current with a current density greater than the reversal current density required to reverse the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10. The second write current Iw2 flows in the opposite direction to the first write current Iw1.

[0098] In the second step S2', the ON and OFF relationship of transistor 13 is reversed compared to the first step S1'. That is, transistor 13 that was OFF in the first step S1' is turned ON, and transistor 13 that was ON in the first step S1' is turned OFF.

[0099] In the second step S2', the magnetoresistive element 10 with transistor 13 ON is the magnetoresistive element on which data was written in the first step S1'. In the magnetoresistive element 10 with transistor 13 ON, a portion of the second writing current Iw2 is diverted from the spin-orbit torque wiring 12 and flows through the channel of transistor 13. Since the current density of the current flowing through the spin-orbit torque wiring 12 is smaller than the reversal current density, the magnetization M1 of the first ferromagnetic layer 1 does not reverse. In other words, the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10 with transistor 13 ON maintains the state of the first step S1'.

[0100] In the magnetoresistive element 10 with transistor 13 OFF, the second writing current Iw2 flows along the spin-orbit torque wiring 12. As the second writing current Iw2 flows along the spin-orbit torque wiring 12, spin is injected from the spin-orbit torque wiring 12 toward the first ferromagnetic layer 1. The magnetization M1 of the first ferromagnetic layer 1 is oriented in a predetermined direction as a result of the spin injection. As the magnetization M1 of the first ferromagnetic layer 1 is oriented in a predetermined direction, data is written to the magnetoresistive element 10 with transistor 13 OFF.

[0101] Since the first writing current Iw1 and the second writing current Iw2 flow in opposite directions, the direction of the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10 on which data is written in the second step S2' is opposite to the direction of the magnetization M1 of the first ferromagnetic layer 1 of the magnetoresistive element 10 on which data is written in the first step S1'. The writing method of the second example allows data to be written to all magnetoresistive elements 10 in the unit U by performing the first step S1' and the second step S2'.

[0102] Next, a method for controlling the read operation of the magnetic memory will be described. Figure 8 is a schematic diagram illustrating the read control method of the magnetic memory 100 according to the first embodiment.

[0103] First, the magnetoresistive element 10 to be read is selected. The selection of the magnetoresistive element 10 is performed by the read circuit B2. Next, the read control selector 30 connected to the selected magnetoresistive element 10 is turned ON. Turning the read control selector 30 ON means applying a voltage to the gate electrode of the read control selector 30 via the second gate line G2, causing current to flow through the read control selector 30. By turning the read control selector 30 ON, a read current Ir can be passed between the read line R and the common line C. At this time, the read control selector 30 and write control selector 20 that are not selected are turned OFF.

[0104] When a readout current Ir flows in the stacking direction of the laminate 11, the resistance of the laminate 11 can be determined by Ohm's law. The resistance value of the laminate 11 differs depending on whether the magnetization M1 of the first ferromagnetic layer 1 and the magnetization M2 of the second ferromagnetic layer 2 are parallel or antiparallel. Therefore, the data stored in the magnetoresistive element 10 can be read out from the resistance value of the laminate 11 or from the potential difference between the readout line R and the common line C.

[0105] When reading data from the magnetic memory 100, it is preferable to turn ON the transistor 13 of one or more magnetoresistive elements 10 located between the magnetoresistive element 10 to be read and the common line C, among the multiple magnetoresistive elements 10 in the unit U to which the magnetoresistive element 10 to be read belongs.

[0106] During the readout operation, the high-resistance spin-orbit torque wiring 12 acts as parasitic resistance. When transistor 13 is turned ON, a portion of the readout current Ir flowing through the spin-orbit torque wiring 12 is diverted to transistor 13. By diverting a portion of the readout current Ir to transistor 13, the parasitic resistance during readout can be reduced.

[0107] Furthermore, among the multiple magnetoresistive elements 10 within the unit U to which the magnetoresistive element 10 to be read belongs, the transistors 13 of the magnetoresistive element 10 to be read and the magnetoresistive element 10 located on the main writing line W1 side of the magnetoresistive element 10 to be read may be either ON or OFF.

[0108] In the magnetic memory 100 according to the first embodiment, the amount of writing current flowing through the spin-orbit torque wiring 12 can be switched ON or OFF by the ON or OFF of the transistor 13. In the magnetic memory 100 according to the first embodiment, data writing can be controlled by switching the ON or OFF of the transistor 13, and the writing method of the magnetic memory 100 is novel. In the magnetic memory 100 according to the first embodiment, even when magnetoresistive elements 10 are arranged in series, the data of each magnetoresistive element 10 can be rewritten individually.

[0109] Furthermore, the magnetic memory 100 according to the first embodiment has excellent integration performance. The write control selector 20 is larger in size than the transistor 13 and read control selector 30 of the magnetoresistive element 10 because it controls a large potential difference. In the magnetic memory 100 according to the first embodiment, this write control selector 20 is placed in the peripheral region A2, which has little impact on integration performance, while the smaller transistor 13 and read control selector 30 are placed within the integration region A1. Because the size of the transistor 13 placed within the integration region A1 is small, the magnetic memory 100 according to the first embodiment has high integration performance.

[0110] The above describes an example of a magnetic memory 100 according to the first embodiment, but additions, omissions, substitutions, and other modifications to the configuration are possible without departing from the spirit of this disclosure.

[0111] For example, Figure 9 is a circuit diagram of a magnetic memory 100' according to a first modification of the first embodiment. The magnetic memory 100' differs from the magnetic memory 100 in that the connection state of the common line C is different. In the magnetic memory 100', components similar to those in the magnetic memory 100 are given the same reference numerals and their description is omitted.

[0112] The magnetic memory 100' according to the first modified example differs from the magnetic memory 100 in that multiple units U connected to a certain main writing line W1 are connected to different common lines C. For example, a first unit U1 and a second unit U2 connected to the same main writing line W1 are connected to different common lines C. The common line C connected to the first unit U1 is referred to as the first common line C1, and the common line C connected to the second unit U2 is referred to as the second common line C2. The first common line C1 is connected to the second end of the first unit U1, and the second common line C2 is connected to the second end of the second unit U2.

[0113] The write control selector 20 connected to the first unit U1 is referred to as the first write control selector 21, and the write control selector 20 connected to the second unit U2 is referred to as the second write control selector 22. When writing data to the magnetoresistive element 10 of the first unit U1, the first write control selector 21 is turned ON and a write current is passed between the main write line W1 and the first common line C1. When writing data to the magnetoresistive element 10 of the second unit U2, the second write control selector 22 is turned ON and a write current is passed between the main write line W1 and the second common line C2.

[0114] The read control selector 30 connected to the first unit U1 is referred to as the first read control selector 31, and the read control selector 30 connected to the second unit U2 is referred to as the second read control selector 32. When reading data from the magnetoresistive element 10 of the first unit U1, the first read control selector 31 is turned ON and a read current is passed between the read line R and the first common line C1. When reading data from the magnetoresistive element 10 of the second unit U2, the second read control selector 32 is turned ON and a read current is passed between the read line R and the second common line C2.

[0115] The magnetic memory 100' according to the first modification is similar to the magnetic memory 100, differing only in the wiring connection. The magnetic memory 100' can suppress erroneous writing by having multiple common lines C connected to a single main writing line W1.

[0116] "Second Embodiment" Figure 10 is a cross-sectional view of the vicinity of one unit U of the magnetic memory 101 according to the second embodiment. Components in the magnetic memory 101 that are the same as those in the magnetic memory 100 are denoted by the same reference numerals and their descriptions are omitted.

[0117] The block diagram and circuit diagram of magnetic memory 101 are the same as those of magnetic memory 100. The same circuit structure as magnetic memory 100' can be applied to magnetic memory 101.

[0118] The magnetic memory 101 differs from the magnetic memory 100 according to the first embodiment in that the spin-orbit torque wiring 12' of magnetoresistive elements 10 belonging to the same unit U is connected and integrated. The spin-orbit torque wiring 12' extends across multiple magnetoresistive elements 10 belonging to the same unit U. The spin-orbit torque wiring 12' is the same as the spin-orbit torque wiring 12, except that it is shared by multiple magnetoresistive elements 10. The control method for the magnetic memory 101 is the same as that for the magnetic memory 100.

[0119] The magnetic memory 101 according to the second embodiment provides the same effects as the magnetic memory 100 according to the first embodiment. The magnetic memory 101 is easy to manufacture because the spin-orbit torque wiring 12' is integrated. In addition, the magnetic memory 101 has excellent integration performance because the distance between the magnetoresistive elements 10 can be narrowed.

[0120] "Third Embodiment" Figure 11 is a cross-sectional view of the vicinity of one unit U of the magnetic memory 102 according to the third embodiment. Components in the magnetic memory 102 that are the same as those in the magnetic memory 100 are denoted by the same reference numerals and their descriptions are omitted.

[0121] The block diagram and circuit diagram of magnetic memory 102 are the same as those of magnetic memory 100. The same circuit structure as that of magnetic memory 100' can be applied to magnetic memory 102.

[0122] The magnetic memory 102 differs from the magnetic memory 100 in that adjacent magnetoresistive elements 10 belonging to the same unit U share a via wiring 16 that connects the spin-orbit torque wiring 12 and the transistor 13.

[0123] For example, one of the magnetoresistive elements 10 belonging to the same unit U is referred to as the first magnetoresistive element 10A, and the magnetoresistive element 10 adjacent to the first magnetoresistive element 10A is referred to as the second magnetoresistive element 10B. The via wiring connecting the second active region 132 of the first magnetoresistive element 10A and the second contact of the spin-orbit torque wiring 12, and the via wiring connecting the first active region 131 of the second magnetoresistive element 10B and the first contact of the spin-orbit torque wiring 12 are integrated to form a via wiring 16. The control method for the magnetic memory 102 is the same as that for the magnetic memory 100.

[0124] The magnetic memory 102 according to the third embodiment provides the same effects as the magnetic memory 100 according to the first embodiment. In the magnetic memory 102, the via wiring of adjacent magnetoresistive elements 10 is integrated into a via wiring 16, which allows the distance between magnetoresistive elements 10 to be reduced. The magnetic memory 102 according to the third embodiment has excellent integration performance.

[0125] In the magnetic memory 102 according to the third embodiment, additions, omissions, substitutions, and other modifications to the configuration are possible without departing from the spirit of this disclosure.

[0126] For example, Figure 12 is a cross-sectional view of the vicinity of one unit U of a magnetic memory 102' according to a first modified example of the third embodiment. In the magnetic memory 102', the spin-orbit torque wiring 12' is shared by a plurality of magnetoresistive elements 10. The magnetic memory 102' incorporates the characteristic configuration of the magnetic memory 101 according to the second embodiment into the magnetic memory 102. The magnetic memory 102' provides the same effects as the magnetic memory 102.

[0127] "Fourth Embodiment" Figure 13 is a cross-sectional view of the vicinity of one unit U of the magnetic memory 103 according to the fourth embodiment. Components in the magnetic memory 103 that are the same as those in the magnetic memory 100 are denoted by the same reference numerals and their descriptions are omitted.

[0128] The block diagram and circuit diagram of magnetic memory 103 are the same as those of magnetic memory 100. The same circuit structure as that of magnetic memory 100' can be applied to magnetic memory 103.

[0129] The magnetic memory 103 differs from the magnetic memory 100 in that adjacent magnetoresistive elements 10 belonging to the same unit U share via wiring 16 and the active region 135 of transistor 13'.

[0130] Similar to the magnetic memory 103 according to the third embodiment, the via wiring connecting the second active region 132 of the first magnetoresistive element 10A and the second contact of the spin-orbit torque wiring 12, and the via wiring connecting the first active region 131 of the second magnetoresistive element 10B and the first contact of the spin-orbit torque wiring 12 are integrated to form a via wiring 16.

[0131] Furthermore, in the magnetic memory 103, the second active region 132 of the first magnetoresistive element 10A and the first active region 131 of the second magnetoresistive element 10B are integrated to form an active region 135. The active region 135 serves as both the second active region 132 of the first magnetoresistive element 10A and the first active region 131 of the second magnetoresistive element 10B. The control method for the magnetic memory 103 is the same as that for the magnetic memory 100.

[0132] The magnetic memory 103 according to the fourth embodiment provides the same effects as the magnetic memory 100 according to the first embodiment. Since the via wiring 16 and active region 135 of adjacent magnetoresistive elements 10 are integrated in the magnetic memory 103, the distance between magnetoresistive elements 10 can be reduced. The magnetic memory 103 according to the fourth embodiment has excellent integration performance.

[0133] In the magnetic memory 103 according to the fourth embodiment, additions, omissions, substitutions, and other modifications to the configuration are possible without departing from the spirit of the present disclosure.

[0134] For example, Figure 14 is a cross-sectional view of the vicinity of one unit U of a magnetic memory 103' according to a first modified example of the fourth embodiment. In the magnetic memory 103', the spin-orbit torque wiring 12' is shared by a plurality of magnetoresistive elements 10. The magnetic memory 103' incorporates the characteristic configuration of the magnetic memory 101 according to the second embodiment into the magnetic memory 103. The magnetic memory 103' provides the same effects as the magnetic memory 103.

[0135] "Fifth Embodiment" Figure 15 is a circuit diagram of the magnetic memory 104 according to the fifth embodiment. Components in the magnetic memory 104 that are the same as those in the magnetic memory 100 are denoted by the same reference numerals and their descriptions are omitted.

[0136] The magnetic memory 104 differs from the magnetic memory 100 in that the write control selector 20 is replaced by a write control selector 25. The write control selector 25 is located between the first terminal UA of unit U and the main write line W1. The write control selector 25 has multiple selectors 25A and 25B in a parallel relationship between the main write line W1 and unit U. Figure 15 shows an example where the write control selector 25 consists of two selectors 25A and 25B, but the number of selectors within the write control selector 25 is not limited. The same elements as those used in the write control selector 20 can be used for selectors 25A and 25B.

[0137] The write control selector 25 controls the write current flowing to unit U using multiple selectors 25A and 25B. Except for controlling the write current with multiple selectors 25A and 25B, the control method for the magnetic memory 104 is the same as that for the magnetic memory 100.

[0138] The sizes of selectors 25A and 25B are smaller than the size of the write control selector 20. Size refers to, for example, channel width and area. Since selectors 25A and 25B control the write current flowing to unit U using multiple selectors 25A and 25B, the size of each selector 25A and 25B can be reduced. For example, the size of selectors 25A and 25B may be equivalent to the size of the transistor 13 of the magnetoresistive element 10.

[0139] The magnetic memory 104 according to the fifth embodiment provides the same effects as the magnetic memory 100 according to the first embodiment. The magnetic memory 104 has smaller selectors 25A and 25B that constitute the write control selector 25. The magnetic memory 104 is easy to manufacture because, for example, there is no need to manufacture the transistor 13 and selectors 25A and 25B separately when fabricating them on the substrate 90.

[0140] Furthermore, in the magnetic memory 104 according to the fifth embodiment, magnetoresistive elements 10 within the same unit U may share a spin-orbit torque wiring 12', or adjacent magnetoresistive elements 10 may share a via wiring 16 or an active region 135.

[0141] "Sixth Embodiment" Figure 16 is a circuit diagram of the magnetic memory 105 according to the sixth embodiment. Components in the magnetic memory 105 that are the same as those in the magnetic memory 100' are denoted by the same reference numerals and their descriptions are omitted.

[0142] Magnetic memory 105 differs from magnetic memory 100' in that the write control selector 20 is replaced by a write control selector 26. The write control selector 26 is a two-terminal selector. The write control selector 26 is, for example, an element whose resistance changes depending on the potential difference across its terminals. The write control selector 26 is, for example, an element that utilizes a phase change in a crystal layer, such as an ovonic threshold switch (OTS), an element that utilizes a change in band structure, such as a metal-insulator transition (MIT) switch, an element that utilizes a breakdown voltage, such as a Zener diode and an avalanche diode, or an element whose conductivity changes with a change in atomic position.

[0143] Units U connected to the same main writing line W1 are connected to different common lines C. For example, the first unit U1 is connected to the first common line C1, and the second unit U2 is connected to the second common line C2. Because the units U connected to the same main writing line W1 are connected to different common lines C, the potential difference applied to each write control selector 26 can be freely designed. If the potential difference applied to each write control selector 26 can be freely designed, then each write control selector 26 can be switched ON or OFF.

[0144] The magnetic memory 105 according to the sixth embodiment provides the same effects as the magnetic memory 100' according to the first embodiment. The magnetic memory 105 has a two-terminal write control selector 26 and can be manufactured with fewer manufacturing steps.

[0145] Furthermore, in the magnetic memory 105 according to the sixth embodiment, magnetoresistive elements 10 within the same unit U may share a spin-orbit torque wiring 12', or adjacent magnetoresistive elements 10 may share a via wiring 16 or an active region 135.

[0146] "Seventh Embodiment" Figure 17 is a circuit diagram of the magnetic memory 106 according to the seventh embodiment. Components in the magnetic memory 106 that are the same as those in the magnetic memory 100' are denoted by the same reference numerals and their descriptions are omitted.

[0147] Magnetic memory 106 differs from magnetic memory 100' in that the read control selector 30 is replaced by a read control selector 36. The read control selector 36 is a two-terminal selector. The read control selector 36 is, for example, an element whose resistance changes depending on the potential difference across its terminals. The read control selector 36 can use the same element as the write control selector 26 described above.

[0148] Magnetoresistive elements 10 connected to the same readout line R are connected to different common lines C. Because the magnetoresistive elements 10 connected to the same readout line R are connected to different common lines C, the potential difference applied to each readout control selector 36 can be freely designed. Being able to freely design the potential difference applied to each readout control selector 36 allows for switching each readout control selector 36 ON or OFF.

[0149] The magnetic memory 106 according to the seventh embodiment provides the same effects as the magnetic memory 100' according to the first embodiment. The magnetic memory 106 has a two-terminal read control selector 36 and can be manufactured with fewer manufacturing steps.

[0150] Furthermore, in the magnetic memory 106 according to the seventh embodiment, magnetoresistive elements 10 within the same unit U may share a spin-orbit torque wiring 12', or adjacent magnetoresistive elements 10 may share a via wiring 16 or an active region 135.

[0151] "Eighth Embodiment" Figure 18 is a circuit diagram of the magnetic memory 107 according to the eighth embodiment. Components in the magnetic memory 107 that are the same as those in magnetic memories 105 and 106 are denoted by the same reference numerals and their descriptions are omitted.

[0152] Magnetic memory 107 differs from magnetic memory 100' in that the write control selector 20 becomes a write control selector 26, and the read control selector 30 becomes a read control selector 36. Magnetic memory 107 combines the characteristic configurations of magnetic memory 105 and magnetic memory 106.

[0153] The magnetic memory 107 according to the eighth embodiment provides the same effects as the magnetic memory 105 according to the sixth embodiment and the magnetic memory 106 according to the seventh embodiment.

[0154] Furthermore, in the magnetic memory 107 according to the eighth embodiment, magnetoresistive elements 10 within the same unit U may share a spin-orbit torque wiring 12', or adjacent magnetoresistive elements 10 may share a via wiring 16 or an active region 135.

[0155] While preferred embodiments of the present disclosure have been illustrated based on several examples and modifications, the disclosure is not limited to these embodiments. For example, characteristic configurations in each embodiment and modification may be applied to other embodiments and modifications. [Explanation of Symbols]

[0156] 1 First ferromagnetic layer 2 Second ferromagnetic layer 3 Non-magnetic layer 10 Magnetoresistive element 10A First magnetoresistive element 10B Second magnetoresistance element 11 Laminate 12, 12' Spin-orbit torque wiring 13, 13' transistor Via wiring 14, 15, 16, 42, 43 20, 25, 26 Write control selector 21. First Write Control Selector 22 Second write control selector 25A, 25B Selector 30, 36 Read control selector 31. First Read Control Selector 32 Second Read Control Selector 41 Wiring 90 circuit boards 91 Laminated Structure 92 Insulator 100, 100', 101, 102, 102', 103, 103', 104, 105, 106, 107 Magnetic memory 131, 201 1st active region 132, 202 2nd active region 133, 203 Gate insulating layer 134, 204 gates 135 Active region A1 Integration Area A2 Peripheral area B1 Programming Circuit B2 Readout Circuit C Common Line C1 First Common Line C2 Second Common Line E1 electrode G1 Gate 1 Line G2 Gate 2 Line Ir Readout Current Iw1 First write current Iw2 Second write current M1, M2 magnetization P1 First contact point P2 2nd contact R readout line S1, S1' 1st process S2, S2' 2nd process U Unit U1 Unit 1 U2 Unit 2 UA 1st end UB 2nd end W1 Main writing line W2 Sub-Write Line

Claims

1. Spin orbit torque wiring, Laminate and Equipped with a transistor, The laminate comprises a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The transistor has a first terminal, a second terminal, and a third terminal. The first terminal is electrically connected to the first contact of the spin orbit torque wiring, The second terminal is electrically connected to the second contact of the spin-orbit torque wiring. The laminate is a magnetoresistive element that is in contact with the spin-orbit torque wiring between the first contact and the second contact of the current path along the spin-orbit torque wiring.

2. Having the first unit, The first unit has a plurality of magnetoresistive elements, Each of the plurality of magnetoresistive elements of the first unit is a magnetoresistive element according to claim 1, In the first unit, the spin-orbit torque wiring of each of the plurality of magnetoresistive elements is connected in series, forming a magnetic memory.

3. The magnetic memory according to claim 2, wherein in the first unit, the spin-orbit torque wiring of each of the plurality of magnetoresistive elements is connected to each other and integrated.

4. The first unit comprises a first magnetoresistive element and a second magnetoresistive element. The magnetic memory according to claim 2, wherein a via connection between the second terminal and the second contact of the first magnetoresistive element and a via connection between the first terminal and the first contact of the second magnetoresistive element are integrated.

5. The first unit comprises a first magnetoresistive element and a second magnetoresistive element. The magnetic memory according to claim 2, wherein the second terminal of the first magnetoresistive element and the first terminal of the second magnetoresistive element are integrated.

6. It further comprises a main writing line, a first writing control selector, multiple sub-writing lines, and a first common line. The first write control selector is located between the first end of the first unit and the main write line. Each of the plurality of sub-writing lines is connected to the third terminal of one of the plurality of magnetoresistive elements, The magnetic memory according to claim 2, wherein the first common line is connected to the second end of the first unit.

7. The first write control selector has a plurality of selectors, The magnetic memory according to claim 6, wherein the plurality of selectors are in a parallel relationship between the first writing line and the first unit.

8. It further comprises a second unit, a second write control selector, and a second common line. Both the first write control selector and the second write control selector are two-terminal selectors. The second unit has a plurality of magnetoresistive elements, Each of the plurality of magnetoresistive elements of the second unit is the same as the magnetoresistive element of the first unit, In the second unit, the spin-orbit torque wiring of each of the plurality of magnetoresistive elements is connected in series. The second write control selector is located between the first end of the second unit and the main write line. The magnetic memory according to claim 6, wherein the second common line is connected to the second end of the second unit.

9. Further equipped with a first gate line, Each of the first write control selectors is a three-terminal transistor, The magnetic memory according to claim 6, wherein the first gate line is connected to the gate of the first write control selector.

10. The magnetic memory according to claim 9, wherein the transistor constituting the first write control selector has a wider channel width than the transistors constituting each of the plurality of magnetoresistive elements.

11. The magnetic memory according to claim 9, wherein the transistor constituting the first write control selector has a larger area than the transistors constituting each of the plurality of magnetoresistive elements.

12. It further comprises multiple read lines, multiple first read control selectors, and a first common line, Each of the multiple first read control selectors is connected to the laminate of any of the multiple magnetoresistive elements in the first unit, Each of the plurality of read lines is connected to one of the plurality of first read control selectors, The magnetic memory according to claim 2, wherein the first common line is connected to the second end of the first unit.

13. It further comprises a second unit, a plurality of second read control selectors, and a second common line. The plurality of first read control selectors and the plurality of second read control selectors are all two-terminal selectors. The second unit has a plurality of magnetoresistive elements, Each of the plurality of magnetoresistive elements of the second unit is the same as the magnetoresistive element of the first unit, In the second unit, the spin-orbit torque wiring of each of the plurality of magnetoresistive elements is connected in series. Each of the multiple second read control selectors is connected to the laminate of any of the multiple magnetoresistive elements in the second unit, Each of the plurality of read lines is also connected to one of the plurality of second read control selectors. The magnetic memory according to claim 12, wherein the second common line is connected to the second end of the second unit.

14. Furthermore, a second gate line is provided. Each of the aforementioned plurality of first read control selectors is a three-terminal transistor, The magnetic memory according to claim 12, wherein the second gate line is connected to each gate of the plurality of first read control selectors.

15. A method for controlling a magnetic memory according to claim 2, A control method for a magnetic memory, comprising: a first step of passing a first write current from the first end to the second end of the first unit when writing data to the plurality of magnetoresistive elements of the first unit; and a second step of passing a second write current from the second end to the first end of the first unit.

16. In the first step, all of the transistors of the plurality of magnetoresistive elements of the first unit are turned OFF. The method for controlling a magnetic memory according to claim 15, wherein in the second step, only the transistor of a predetermined magnetoresistive element among the plurality of magnetoresistive elements of the first unit is turned ON.

17. In the first step, the transistor of a predetermined magnetoresistive element among the plurality of magnetoresistive elements is turned ON, and the transistors of the remaining magnetoresistive elements are turned OFF. The magnetic memory control method according to claim 15, wherein in the second step, the ON and OFF states of the transistor are reversed compared to the first step.

18. A method for controlling a magnetic memory according to claim 2, A method for controlling a magnetic memory, which involves turning on the transistors of one or more magnetoresistive elements located between the magnetoresistive element to be read from and the first common line connected to the second end of the first unit when reading data from any of the plurality of magnetoresistive elements of the first unit.

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