Method for manufacturing element chips and method for manufacturing assembled bodies

Abstract

Obtain a device chip suitable for direct bonding. [Solution] The method for manufacturing an element chip comprises: a preparation step of preparing a substrate 1 having a first layer 2 which is a semiconductor layer and a second layer 3 which includes an insulator, and having a divided region that defines a plurality of element regions; a first protective layer formation step of forming a first protective layer having a first opening that exposes the divided region on the upper surface of the second layer 3; a first groove formation step of forming a first groove by etching in the second layer 3 exposed to the first opening; a second protective layer formation step of forming a second protective layer 6 on the surface of the second layer 3; a laser grooving step of forming a second groove 7 that reaches the first layer 2 inside the first groove in the divided region by irradiating it with laser light; and a dicing step of dividing the substrate 1 at the second groove 7 to form a plurality of element chips, each having an element region and a recess at its outer edge.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing an element chip and a method for manufacturing a joined body.

Background Art

[0002] Conventionally, a technique for manufacturing a plurality of element chips by plasma dicing a substrate has been known (for example, Patent Document 1). The method for manufacturing an element chip of Patent Document 1 includes a step of preparing a substrate including a plurality of element regions and a dividing region that defines the element regions, a step of forming a mask layer on the upper surface of the substrate, a step of removing the mask layer corresponding to the dividing region by irradiation with laser light, and a step of obtaining a plurality of element chips corresponding to the element regions by exposing the dividing region of the substrate to plasma.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, development of a so-called direct bonding technique for directly bonding the surfaces of each element chip to each other or the surfaces of an element chip and a substrate to each other has been promoted. Direct bonding is advantageous in that the bonding distance can be shortened, while the surface of an element chip or the like is required to be highly flat. In such a situation, one of the objects of the present disclosure is to obtain an element chip suitable for direct bonding.

Means for Solving the Problems

[0005] One aspect of this disclosure relates to a method for manufacturing an element chip. The manufacturing method comprises a preparation step of preparing a substrate having a plurality of element regions and divided regions defining the element regions, the first main surface of the substrate having a first main surface and a second main surface, the first layer being a semiconductor layer, and the second layer being formed on the first main surface side of the first layer and including an insulator, the substrate having a plurality of element regions and divided regions defining the element regions, the planarization step of flattening the upper surface of the second layer by polishing the first main surface side of the substrate, the first protective layer forming step of forming a first protective layer having a first opening that exposes the divided regions on the upper surface of the second layer, the first groove forming step of forming a first groove having a first groove width in the divided region by etching a part of the second layer exposed in the first opening, and the substrate The method comprises: a support step of supporting the second main surface with a support member; a second protective layer formation step of forming a second protective layer on the surface of the second layer; a laser grooving step of irradiating the inside of the first groove with laser light from the first main surface side in the divided region to form a second groove inside the first groove that penetrates the second protective layer and the second layer and reaches the first layer, and has a second groove width smaller than the first groove width; and a dicing step of dividing the substrate at the second groove while the second main surface is supported by the support member to form a plurality of element chips, each having the element region and a recess at the outer edge on the first main surface side.

[0006] Another aspect of this disclosure relates to a method for manufacturing a bonded body. The manufacturing method comprises an element chip preparation step for preparing an element chip, a second substrate preparation step for preparing a second substrate, and a bonding step for bonding the element chip to the second substrate, wherein the element chip preparation step includes a preparation step for preparing a first substrate having a first main surface and a second main surface, a first layer which is a semiconductor layer, and a second layer which is formed on the first main surface side of the first layer and includes an insulator, and the first substrate having a plurality of element regions and a dividing region which defines the element regions, a planarization step for planarizing the upper surface of the second layer by polishing the first main surface side of the first substrate, a first protective layer forming step for forming a first protective layer having a first opening that exposes the dividing region on the upper surface of the second layer, and etching a part of the second layer exposed in the first opening so that the dividing region has a first groove width The bonding process includes: a first groove forming step of forming a groove; a support step of supporting the second main surface of the first substrate with a support member; a second protective layer forming step of forming a second protective layer on the surface of the second layer; a laser grooving step of irradiating the inside of the first groove with laser light from the first main surface side in the divided region to form a second groove inside the first groove that penetrates the second protective layer and the second layer and reaches the first layer, and has a second groove width smaller than the first groove width; and a dicing step of dividing the first substrate at the second groove while the second main surface is supported by the support member to form a plurality of element chips, each having an element region and a recess at the outer edge on the first main surface side, wherein in the bonding step, the first main surface side of the element chip is brought into close contact with the second substrate and bonded. [Effects of the Invention]

[0007] According to this disclosure, it is possible to obtain an element chip suitable for direct bonding. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view illustrating the preparation steps of Embodiment 1, and shows an example of a first substrate. [Figure 2]This is a cross-sectional view illustrating the planarization process of Embodiment 1, in which the upper surface of the second layer is flattened. [Figure 3] This is a cross-sectional view illustrating the first protective layer formation process of Embodiment 1, in which the first protective layer is formed on the upper surface of the second layer. [Figure 4] This is a cross-sectional view illustrating the first groove formation process of Embodiment 1, in which the first groove is formed in the divided region. [Figure 5] This is a cross-sectional view illustrating the first protective layer removal process of Embodiment 1, where the first protective layer has been removed. [Figure 6] This is a cross-sectional view illustrating the thinning process of Embodiment 1, in which the first substrate has been thinned. [Figure 7] This is a cross-sectional view illustrating the support process of Embodiment 1, in which the first substrate is supported by a support member. [Figure 8] This is a cross-sectional view illustrating the second protective layer formation process of Embodiment 1, in which the second protective layer is formed on the surface of the second layer. [Figure 9] This is a cross-sectional view illustrating the laser grooving process of Embodiment 1, in which a second groove is formed inside the first groove. [Figure 10] This is a cross-sectional view illustrating the dicing process of Embodiment 1, showing a plurality of element chips. [Figure 11] This is a cross-sectional view illustrating the second protective layer removal process of Embodiment 1, where the second protective layer has been removed. [Figure 12] This is a cross-sectional view illustrating the second substrate preparation process and bonding process of Embodiment 1, showing how the element chip is bonded to the second substrate. [Figure 13] This is a schematic diagram showing an example of a plasma processing device. [Figure 14] This is a cross-sectional view illustrating the first protective layer formation process of Embodiment 2, in which the first protective layer is formed on the upper surface of the second layer. [Figure 15] This is a cross-sectional view illustrating the first groove formation process of Embodiment 2, in which the first groove is formed in the divided region. [Figure 16] A cross-sectional view for explaining the first protective layer removal step of Embodiment 2, in which the first protective layer has been removed. [Figure 17] A cross-sectional view for explaining the planarization step of Embodiment 2, in which the upper surface of the second layer has been planarized. [Figure 18] A cross-sectional view for explaining the preparation step of Embodiment 6, showing another example of the first substrate. [Figure 19] A cross-sectional view for explaining the first groove formation step of Embodiment 6, in which the first groove is formed in the division region. [Figure 20] A cross-sectional view showing a plurality of element chips obtained in Embodiment 6.

Embodiments for Carrying Out the Invention

[0009] Examples of embodiments of a method for manufacturing an element chip and a method for manufacturing a bonded body according to the present disclosure will be described below with reference to examples. However, the present disclosure is not limited to the examples described below. In the following description, specific numerical values and materials may be exemplified, but other numerical values and materials may be applied as long as the effects of the present disclosure can be obtained.

[0010] (Method for Manufacturing Element Chip) The method for manufacturing an element chip according to the present disclosure is a method of obtaining a plurality of element chips by singulating a substrate. The method for manufacturing an element chip according to the present disclosure includes a preparation step, a planarization step, a first protective layer formation step, a first groove formation step, a support step, a second protective layer formation step, a laser grooving step, and a dicing step. Note that the execution order of each step is not limited by the described order. However, usually, the second groove formation step is performed after the first groove formation step, the laser grooving step is performed after the second protective layer formation step, and the dicing step is performed after the laser grooving step.

[0011] In the preparation process, a substrate having a first main surface and a second main surface is prepared, the substrate including a first layer which is a semiconductor layer, and a second layer formed on the first main surface side of the first layer and containing an insulator. The substrate includes a plurality of element regions and division regions that define the element regions. The first layer and the second layer may be adjacent to each other. The semiconductor material included in the first layer is not particularly limited, and may be, for example, Si, SiC, GaN, or GaAs. The second layer may include an insulating film such as SiO2, SiN, SiCN, and metals such as Cu, Al. The shape of each element region is not particularly limited, and may be, for example, rectangular, polygonal, or circular. The width of the division region is also not particularly limited and may be appropriately set according to the purpose. The thickness of the second layer may be, for example, 3 μm or more and 20 μm or less, or may be 8 μm or more and 18 μm or less.

[0012] In the planarization process, the upper surface of the second layer is planarized by polishing the first main surface side of the substrate. In the planarization process, for example, the upper surface of the second layer may be planarized by chemical mechanical polishing (CMP). The upper surface (or the outermost surface) of the second layer may include SiO2, SiON (silicon oxynitride), or SiCN (silicon carbonitride).

[0013] In the first protective layer formation process, a first protective layer having a first opening that exposes the division region is formed on the upper surface of the second layer. The first protective layer may include a water-soluble or water-insoluble resin material. Examples of the water-insoluble resin material can include, for example, a photoresist material. The first protective layer may or may not be removed before the second protective layer formation process. The first protective layer is preferably formed of a photoresist. Also, the cross-sectional shape of the edge of the first opening of the first protective layer may be a forward taper shape or a round shape.

[0014] In the first groove formation step, a first groove having a first groove width is formed in the divided region by etching a portion of the second layer exposed to the first opening. The etching method is not particularly limited, and for example, plasma etching or sputter etching can be used. The etching may be performed under conditions in which no protrusions (or burrs) are substantially formed on the opening edge of the first groove. The first groove width may be substantially the same as the opening width of the first opening. The depth of the first groove may be, for example, 0.2 μm or more and 2 μm or less. Furthermore, by making the cross-sectional shape of the edge of the first opening of the first protective layer a forward tapered shape or a rounded shape in the first protective layer formation step, it is possible to make it less likely for protrusions (or burrs) to be formed on the opening edge of the first groove when sputter etching is performed in the first groove formation step.

[0015] In the support process, the second main surface of the substrate is supported by a support member. The support member may have an annular frame and a retaining sheet attached to the frame to which the substrate is attached.

[0016] In the second protective layer formation step, a second protective layer is formed on the surface of the second layer on which the first groove is formed. The second protective layer may contain a water-soluble or water-insoluble resin material. Examples of water-insoluble resin materials include photoresist materials. In particular, it is preferable that the second protective layer be formed of a water-soluble resin. The "surface" of the second layer includes the top surface of the second layer, the bottom surface of the first groove, and the side walls. Furthermore, if the first protective layer remains on the top surface of the second layer, forming the second protective layer on the surface of the second layer includes forming the second protective layer on the surface of the first protective layer. The second protective layer may be formed using a spin coater or a spray coater. When a spin coater is used to form the second protective layer, it is preferable that the depth of the first groove formed in the first groove formation step is 2 μm or less in order to ensure good coverage of the second protective layer on the surface of the second layer.

[0017] In the laser grooving process, in the divided region, laser light is irradiated from the first main surface side to the inside of the first groove to remove the second protective layer and the remainder of the second layer, thereby forming a second groove inside the first groove that penetrates the second protective layer and the second layer, reaches the first layer, and has a second groove width smaller than the first groove width. A step corresponding to the first groove is formed between the second groove thus formed and the upper surface of the second layer. Due to this step, a recess described later may be formed in the dicing process. The laser light may be an ultrashort pulse laser light on the picosecond or femtosecond order, but from the viewpoint of manufacturing cost, a short pulse laser light on the nanoscale is preferred. The laser light is absorbed by the second protective layer and the second layer, but does not necessarily have to be absorbed by the first layer.

[0018] In the dicing process, with the second main surface supported by a support member, the substrate is divided at the second groove to form multiple element chips, each having an element region and a recess on the outer edge on the first main surface side. In the element chips obtained in this way, minute protrusions having a size of tens to hundreds of nanometers may be formed on their edges, more specifically on the edges of the bottom surface of the recesses. Conventionally, such minute protrusions would be a factor that hinders direct bonding, but in this disclosure, because they are formed on the edges of the bottom surface of the recesses, they do not protrude above the upper surface of the second layer and do not hinder direct bonding. For this reason, the depth of the first groove formed in the first groove formation process is preferably 0.2 μm or more.

[0019] The planarization step may be performed before the first protective layer formation step. In this case, the upper surface of the second layer can be planarized more easily than when the planarization step is performed after the first protective layer formation step or the subsequent first groove formation step.

[0020] The flattening step may be performed after the first groove formation step. In this case, even if minute protrusions are formed on the opening edge of the first groove during the first groove formation step, these minute protrusions can be removed during the subsequent flattening step.

[0021] The method for manufacturing the element chip may further include a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate after the first groove forming step. In the support step, the second main surface of the thinned substrate may be supported by a support member.

[0022] The preparation step may include a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate. In this case, the thickness of the substrate after thinning is preferably 300 μm or more.

[0023] The method for manufacturing the element chip may further include a thinning step after the planarization step, in which the substrate is thinned by grinding the second main surface side of the substrate. In the support step, the second main surface of the thinned substrate may be supported by a support member. The thinning step may be performed after the planarization step and before the first protective layer formation step.

[0024] The second layer in the divided region may include a metal pattern exposed on the surface. The etching of the second layer in the first groove formation step may include sputter etching that etches the insulator and the metal pattern. In the thickness direction of the substrate, the maximum distance between the bottom surface of the first groove and the second main surface may be smaller than the distance between the top surface of the second layer in the element region and the second main surface. This relationship between the magnitudes of the distances helps to prevent minute protrusions from directly interfering with bonding, even if minute protrusions are formed on the edges of the bottom surface of the recesses during the laser grooving step. The metal pattern may be a Test Element Group (TEG). The maximum distance between the bottom surface of the first groove and the second main surface may also be the distance between the surface of the metal pattern after sputter etching and the second main surface.

[0025] The dicing process may include a plasma dicing process in which the substrate is divided by exposing the second groove to plasma and etching the first layer. This plasma etching may be performed using at least the second protective layer as a mask. A Bosch process may be used for etching the first layer.

[0026] The dicing process may include a laser irradiation process in which the substrate is divided by irradiating the second groove with laser light.

[0027] The dicing process may include a blade dicing step in which the substrate is divided in the second groove using a blade thinner than the width of the second groove.

[0028] (Method of manufacturing the joint) The method for manufacturing a bonded body according to this disclosure is a method for manufacturing a bonded body by bonding element chips obtained by separating a substrate into individual pieces to a second substrate. The method for manufacturing a bonded body according to this disclosure comprises an element chip preparation step, a second substrate preparation step, and a bonding step.

[0029] The element chip preparation process includes a preparation step, a planarization step, a first protective layer formation step, a first groove formation step, a support step, a second protective layer formation step, a laser grooving step, and a dicing step, similar to the method for manufacturing an element chip according to this disclosure. Each step may be performed in the same manner as each step in the method for manufacturing an element chip according to this disclosure, with "substrate" replaced by "first substrate". The surface of the element chip may be subjected to a hydrophilization treatment using plasma surface activation followed by water washing.

[0030] In the second substrate preparation step, the second substrate is prepared. The surface of the second substrate may include regions composed of SiO2, SiON, or SiCN, and regions composed of metals such as Cu or Al. The surface of the second substrate may be subjected to a hydrophilization treatment using plasma surface activation followed by water washing.

[0031] In the bonding process, the element chip is bonded to the second substrate. In the bonding process, the first main surface side of the element chip is brought into close contact with the second substrate for bonding. The bonding process may be performed by direct bonding (for example, hybrid bonding). Since there are no minute protrusions on the first main surface of the element chip, the bonding can be performed well.

[0032] As described above, according to this disclosure, an element chip suitable for direct bonding can be obtained by forming the first groove and the second groove. Furthermore, according to this disclosure, it is possible to manufacture a bonded body comprising such an element chip by direct bonding.

[0033] Hereinafter, an example of a method for manufacturing an element chip and a bonded assembly according to this disclosure will be specifically described with reference to the drawings. The steps for the method for manufacturing an element chip and a bonded assembly described below can be applied to the steps described above. The steps for the method for manufacturing an element chip and a bonded assembly described below can be modified based on the above description. Furthermore, the matters described below may be applied to the above embodiments. Among the steps for manufacturing an element chip and a bonded assembly described below, steps that are not essential to the method for manufacturing an element chip and a bonded assembly according to this disclosure may be omitted. Note that the figures shown below are schematic and do not accurately reflect the actual shape and number of components.

[0034] Embodiment 1 Embodiment 1 of this disclosure will now be described. The method for manufacturing a bonded body of this embodiment is a method for manufacturing a bonded body by bonding element chips obtained by separating a first substrate into individual pieces to a second substrate. The method for manufacturing a bonded body comprises an element chip preparation step of preparing element chips 10, a second substrate preparation step of preparing a second substrate 50, and a bonding step of bonding element chips 10 to the second substrate 50.

[0035] The element chip preparation process is a process that corresponds to the method for manufacturing an element chip according to the present disclosure, and comprises a preparation step, a planarization step, a first protective layer formation step, a first groove formation step, a first protective layer removal step, a thinning step, a support step, a second protective layer formation step, a laser grooving step, a dicing step, and a second protective layer removal step.

[0036] In the preparation step, as shown in Figure 1, a first substrate 1 is prepared, which has a first main surface 1a and a second main surface 1b, and comprises a first layer 2 which is a semiconductor layer, and a second layer 3 formed on the first main surface 1a side of the first layer 2 and containing an insulator. The first substrate 1 comprises a plurality of device regions EA and dividing regions DA that define the device regions EA. In this embodiment, the upper surface (outermost surface) of the second layer 3 contains SiO2, but is not limited to this. At least one metal electrode 3a is disposed on the second layer 3 corresponding to the device region EA. At least one metal electrode 3b is disposed on the second layer 3 corresponding to the dividing region DA. For example, a part of the metal electrode 3a corresponding to the device region EA protrudes from the upper surface of the second layer 3.

[0037] In the planarization process, as shown in Figure 2, the upper surface of the second layer 3 is planarized by polishing the first main surface 1a side of the first substrate 1. In this embodiment, the upper surface of the second layer 3 is planarized by CMP, but it is not limited to this. In this embodiment, the planarization process is performed before the first protective layer formation process.

[0038] In the first protective layer formation step, as shown in Figure 3, a first protective layer 4 having a first opening 4a that exposes the divided region DA is formed on the upper surface of the flattened second layer 3. Such a first protective layer 4 having a first opening 4a can be formed, for example, by forming a protective layer over the entire upper surface of the second layer 3 and then removing the portion of the protective layer corresponding to the divided region DA. The first protective layer 4 in this embodiment includes, but is not limited to, a photoresist.

[0039] In the first groove formation step, as shown in Figure 4, a portion of the second layer 3 exposed to the first opening 4a is etched to form a first groove 5 having a first groove width W1 in the divided region DA. This etching may be performed using plasma etching.

[0040] In the first protective layer removal step, the first protective layer 4 is removed as shown in Figure 5. As described above, the first protective layer 4 in this embodiment contains, for example, a photoresist, and can therefore be removed by cleaning with an organic solvent or ashing with oxygen plasma. Alternatively, the first protective layer 4 may not be removed at this stage, and the second protective layer 6 may be formed on the first protective layer 4 in the subsequent second protective layer formation step.

[0041] In the thinning process, as shown in Figure 6, the first substrate 1 is thinned by grinding the second main surface 1b side of the first substrate 1. For example, a back grinder can be used for this grinding. In this embodiment, the thinning process is performed after the first groove formation process.

[0042] In the support process, as shown in Figure 7, the second main surface 1b of the thinned first substrate 1 is supported by a support member 20 (for example, a resin holding sheet).

[0043] In the second protective layer formation step, as shown in Figure 8, a second protective layer 6 is formed on the surface of the second layer 3. The second protective layer 6 in this embodiment contains, but is not limited to, a water-soluble resin.

[0044] In the laser grooving process, as shown in Figure 9, in the divided region DA, a laser beam (not shown) is irradiated from the first main surface 1a side to the inside of the first groove 5 to remove the second protective layer 6 and the remainder of the second layer 3, thereby forming a second groove 7 inside the first groove 5 that penetrates the second protective layer 6 and the second layer 3 to reach the first layer 2 and has a second groove width W2 smaller than the first groove width W1. The bottom surface of the second groove 7 is located on the top surface or inside the first layer 2.

[0045] In the dicing process, as shown in Figure 10, with the second main surface 1b supported by a support member 20, the first substrate 1 is divided at the second groove 7 to form a plurality of element chips 10, each having an element region EA and a recess 10a at the outer edge on the first main surface 1a side. The dicing process in this embodiment includes, but is not limited to, a plasma dicing process in which the first substrate 1 is divided by etching the first layer 2 by exposing the second groove 7 to plasma. For example, the dicing process may include a laser irradiation process in which the first substrate 1 is divided by irradiating the second groove 7 with laser light, or a blade dicing process in which the first substrate 1 is divided at the second groove 7 with a blade (not shown) that is thinner than the second groove width W2.

[0046] In the second protective layer removal step, as shown in Figure 11, the second protective layer 6 is removed after the dicing step. As described above, the second protective layer 6 in this embodiment contains a water-soluble resin, and therefore can be removed by washing with a water-containing cleaning solution (for example, water).

[0047] The second substrate 50 prepared in the second substrate preparation step may comprise a semiconductor layer 51 and a wiring layer 52 provided on the upper surface of the semiconductor layer 51 and containing an insulator. An insulator (e.g., SiO2) and a metal electrode 52a are exposed on the outermost surface of the wiring layer 52.

[0048] In the bonding process, as shown in Figure 12, the first main surface 1a side of the element chip 10 prepared in the element chip preparation process is brought into close contact with the second substrate 50 prepared in the second substrate preparation process and bonded. At this time, since the element chip 10 has a recess 10a on the outer edge of the first main surface 1a side, even if there are minute protrusions (or burrs) on the bottom edge of the recess 10a, such minute protrusions will not come into contact with the surface of the second substrate 50. Therefore, the bonding can be performed well. Prior to the bonding process, it is preferable to make the first main surface 1a of the element chip 10 and the surface of the second substrate 50 hydrophilic by a plasma surface activation treatment and subsequent water washing treatment, respectively.

[0049] In the first groove formation and dicing processes, the plasma processing apparatus 30 (plasma etching apparatus 30) shown in Figure 13 may be used. The plasma processing apparatus 30 comprises a chamber 31 having a dielectric window at its top that defines a processing chamber 34, an antenna 32 as an upper electrode provided on the upper side of the chamber 31, a first high-frequency power supply 33 electrically connected to the antenna 32, a stage 35 as a lower electrode provided on the bottom side of the processing chamber 34 on which the first substrate 1 is placed, and a second high-frequency power supply 36 electrically connected to the stage 35. A gas inlet 37 provided in the chamber 31 is fluidically connected to a raw material gas source 38. An exhaust port 39 provided in the chamber 31 is fluidically connected to a vacuum exhaust section 40 including a vacuum pump.

[0050] In the plasma processing apparatus 30 shown in Figure 13, after the first substrate 1 is placed on the stage 35, the processing chamber 34 is depressurized by the vacuum exhaust unit 40, and raw material gas is supplied to the processing chamber 34 from the raw material gas source 38. Then, high-frequency power is supplied to the antenna 32 from the first high-frequency power supply 33 to generate plasma in the processing chamber 34 and irradiate the first substrate 1. The first layer 2 exposed at the bottom of the second groove 7 can be removed by the physicochemical action of radicals and ions in the plasma. Furthermore, by supplying high-frequency power to the stage 35 from the second high-frequency power supply 36, it is possible to control the collision velocity of radicals and ions with respect to the first substrate 1.

[0051] The processing conditions in the first groove formation step are, for example, as follows: As process gases, CF4 is supplied to the chamber 31 at a rate of 20 sccm to 80 sccm and Ar at a rate of 150 sccm to 300 sccm. The pressure inside the chamber 31 is 0.4 Pa to 1.0 Pa, the high-frequency power applied to the antenna 32 is 1000 W to 2000 W, and the high-frequency power applied to the stage 35 is 500 W to 1500 W. The processing time is 20 seconds to 360 seconds.

[0052] It is preferable to use a mixed gas of CF4 and Ar as the process gas. By using a mixed gas of CF4 and Ar, the decrease in the etching rate of metals such as Cu relative to the etching rate of insulating films such as SiO2 can be suppressed, making it easier to form the first groove even when the second layer 3 in the divided region DA includes a metal pattern exposed on the surface. Furthermore, by using a mixed gas of CF4 and Ar, it becomes possible to control the ratio of the etching rate of the first protective layer to the etching rate of the second layer 3, forming the first groove while recessing the first protective layer, thereby suppressing the adhesion of reaction products to the etched side surface.

[0053] In this example, CF4 is used as the fluorine-containing gas, but SF6 or C4F8 may also be used. Furthermore, Ar gas, which does not contain fluorine, may be used as the process gas. Additionally, if the second layer 3 in the divided region DA includes a metal pattern exposed on the surface, it is preferable that the process gas does not contain O2 to prevent inhibition of etching of the metal pattern.

[0054] The dicing process may be carried out by repeating the protective film deposition step, the protective film removal step, and the substrate etching step multiple times. The processing conditions in the protective film deposition step are, for example, as follows: C4F8 is supplied to the chamber 31 as a process gas at a concentration of 150 sccm or more and 600 sccm or less. The pressure in the chamber 31 is 8 Pa or more and 16 Pa or less, the high-frequency power applied to the antenna 32 is 2000 W or more and 8000 W or less, and the high-frequency power applied to the stage 35 is 15 W or more and 80 W or less. The processing time is 1 second or more and 5 seconds or less. The processing conditions in the protective film removal step are, for example, as follows: SF6 is supplied to the chamber 31 as a process gas at a concentration of 200 sccm or more and 800 sccm or less. The pressure inside the chamber 31 is 4 Pa ​​or more and 12 Pa or less, the high-frequency power applied to the antenna 32 is 2000 W or more and 8000 W or less, and the high-frequency power applied to the stage 35 is 150 W or more and 600 W or less. The processing time is 1 second or more and 5 seconds or less. The processing conditions in the substrate etching step are, for example, as follows: SF6 is supplied to the chamber 31 as a process gas at a concentration of 200 sccm or more and 800 sccm or less. The pressure inside the chamber 31 is 20 Pa or more and 40 Pa or less, the high-frequency power applied to the antenna 32 is 2500 W or more and 10000 W or less, and the high-frequency power applied to the stage 35 is 20 W or more and 100 W or less. The processing time is 2 seconds or more and 10 seconds or less. The number of repetitions of the protective film deposition step, protective film removal step, and substrate etching step is, for example, 20 times or more and 50 times or less.

[0055] Embodiment 2 Embodiment 2 of this disclosure will now be described. The method for manufacturing the jointed body in this embodiment differs from Embodiment 1 in that the planarization step is performed after the first groove formation step. The differences from Embodiment 1 will be mainly described below.

[0056] As shown in Figure 14, in the first protective layer formation step of this embodiment, a first protective layer having a first opening 4a that exposes the divided region DA is formed on the upper surface of the second layer 3 of the first substrate 1 prepared in the preparation step.

[0057] Subsequently, as shown in Figure 15, a first groove formation step is performed in which a first groove 5 having a first groove width W1 is formed in the divided region DA by etching a portion of the second layer 3 exposed to the first opening 4a.

[0058] Next, as shown in Figure 16, the first protective layer removal step is performed to remove the first protective layer 4.

[0059] Then, as shown in Figure 17, a planarization process is performed to flatten the upper surface of the second layer 3 by polishing the first main surface 1a side of the first substrate 1 having the first groove 5. As a result, even if minute protrusions (or burrs) are formed on the opening edge of the first groove 5, these minute protrusions can be removed during the planarization process.

[0060] Subsequently, by performing the thinning process, support process, second protective layer formation process, laser grooving process, dicing process, and second protective layer removal process in the same manner as in Embodiment 1 above, a plurality of element chips 10 having recesses 10a can be obtained.

[0061] Embodiment 3 Embodiment 3 of this disclosure will now be described. The method for manufacturing the bonded body in this embodiment differs from Embodiment 1 in that the thinning step is included in the preparation step. That is, although not shown in the figures, the preparation step of this embodiment includes a thinning step in which the first substrate 1 is thinned by grinding the second main surface 1b side of the first substrate 1. Each of the subsequent steps can be carried out in the same manner as in Embodiment 1, except for the thinning step.

[0062] Embodiment 4 Embodiment 4 of this disclosure will now be described. The method for manufacturing the bonded body in this embodiment differs from Embodiment 2 in that the thinning step is included in the preparation step. That is, although not shown in the figures, the preparation step of this embodiment includes a thinning step in which the first substrate 1 is thinned by grinding the second main surface 1b side of the first substrate 1. Each of the subsequent steps can be carried out in the same manner as in Embodiment 2, except for the thinning step.

[0063] Embodiment 5 Embodiment 5 of the present disclosure will now be described. The manufacturing method of the bonded body in this embodiment differs from Embodiment 1 in that the thinning step is performed after the planarization step and before the first protective layer formation step. That is, although not shown in the figures, the element chip preparation step of this embodiment further includes a thinning step in which the first substrate 1 is thinned by grinding the second main surface 1b side of the first substrate 1 after the planarization step and before the first protective layer formation step. In addition, in the support step, the second main surface 1b of the thinned first substrate 1 is supported by a support member 20.

[0064] Embodiment 6 Embodiment 6 of this disclosure will now be described. The method for manufacturing the bonded body in this embodiment differs from Embodiment 1 in that the first substrate 1 has a predetermined metal pattern 3c. The differences from Embodiment 1 will be mainly described below.

[0065] As shown in Figure 18, the first substrate 1 prepared in the preparation step of this embodiment includes a metal pattern 3c exposed on the surface of the second layer 3 in the divided region DA. This metal pattern 3c may constitute a TEG.

[0066] Figure 19 shows the first substrate 1 in which the first groove 5 has been formed by the first groove formation process of this embodiment. The etching of the second layer 3 in the first groove formation process of this embodiment includes sputter etching that etches the insulator and metal pattern 3c contained in the second layer 3. In Figure 19, it can be seen that the metal pattern 3c, which is relatively difficult to etch, protrudes more toward the first main surface 1a than the insulator, which is relatively easy to etch. Furthermore, in the thickness direction of the first substrate 1 (vertical direction in Figure 19), the maximum distance between the bottom surface of the first groove 5 and the second main surface 1b (i.e., the distance D1 between the top surface of the metal pattern 3c and the second main surface 1b) is smaller than the distance D2 between the top surface of the second layer 3 and the second main surface 1b in the element region EA.

[0067] Furthermore, when etching the second layer 3 in the first groove formation process is performed using plasma, it is preferable to use a mixed gas of CF4 and Ar as the process gas. By using a mixed gas of CF4 and Ar, it is possible to suppress the decrease in the etching rate of metals such as Cu relative to the etching rate of insulating films such as SiO2, and as a result, the protrusion of the metal pattern 3c at the bottom surface of the first groove 5 can be reduced.

[0068] Each step not shown here can be performed in the same manner as in Embodiment 1 described above. And, because the above-mentioned relationship of magnitude of distances in the thickness direction holds, even if minute protrusions exist on the edges of the bottom surface of the recess 10a in the multiple element chips 10 obtained in this embodiment (see Figure 20), these minute protrusions do not hinder direct bonding between the first substrate 1 and the second substrate 50.

[0069] [Note] The above description of embodiments discloses the following technologies. (Technology 1) A preparation step for preparing a substrate comprising a first layer which is a semiconductor layer and has a first main surface and a second main surface, and a second layer which is formed on the first main surface side of the first layer and includes an insulator, wherein the substrate comprises a plurality of element regions and divided regions which define the element regions. A planarization step is performed by polishing the first main surface side of the substrate to flatten the upper surface of the second layer, A first protective layer forming step is to form a first protective layer having a first opening that exposes the divided region on the upper surface of the second layer, A first groove forming step is to form a first groove having a first groove width in the divided region by etching a portion of the second layer exposed in the first opening, A support step of supporting the second main surface of the substrate with a support member, A second protective layer formation step in which a second protective layer is formed on the surface of the second layer, A laser grooving step is performed in the divided region by irradiating the inside of the first groove with laser light from the first main surface side to form a second groove inside the first groove that penetrates the second protective layer and the second layer, reaches the first layer, and has a second groove width smaller than the first groove width. A dicing step in which, with the second main surface supported by the support member, the substrate is divided in the second groove to form a plurality of element chips, each having the element region and a recess on the outer edge side of the first main surface; A method for manufacturing an element chip, comprising the same components. (Technology 2) The method for manufacturing an element chip according to Technology 1, wherein the planarization step is performed before the first protective layer formation step. (Technology 3) The method for manufacturing an element chip according to Technology 1, wherein the planarization step is performed after the first groove formation step. (Technology 4) The process further includes a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate after the first groove forming step, The method for manufacturing an element chip according to Technology 2, wherein in the support step, the second main surface of the thinned substrate is supported by the support member. (Technology 5) A method for manufacturing an element chip according to any one of the technologies 1 to 3, wherein the preparation step includes a thinning step of thinning the substrate by grinding the second main surface side of the substrate. (Technology 6) The process further comprises a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate after the planarization step, A method for manufacturing an element chip according to Technology 2 or 3, wherein in the support step, the second main surface of the thinned substrate is supported by the support member. (Technology 7) The second layer in the divided region includes a metal pattern exposed on the surface. The etching of the second layer in the first groove forming step includes sputter etching for etching the insulator and the metal pattern, A method for manufacturing an element chip according to any one of the technologies 1 to 6, wherein, in the thickness direction of the substrate, the maximum distance between the bottom surface of the first groove and the second main surface is smaller than the distance between the top surface of the second layer and the second main surface in the element region. (Technology 8) A method for manufacturing an element chip according to any one of the technologies 1 to 6, wherein the dicing step includes a plasma dicing step of dividing the substrate by exposing the second groove to plasma and etching the first layer. (Technology 9) A method for manufacturing an element chip according to any one of the technologies 1 to 6, wherein the dicing step includes a laser irradiation step of dividing the substrate by irradiating the second groove with laser light. (Technology 10) A method for manufacturing an element chip according to any one of the technologies 1 to 6, wherein the dicing step includes a blade dicing step in which the substrate is divided in the second groove with a blade thinner than the width of the second groove. (Technology 11) The chip preparation process involves preparing the chip, The second substrate preparation process involves preparing the second substrate, A bonding step of bonding the element chip to the second substrate, Equipped with, The above-mentioned element chip preparation process is: A preparation step for preparing a first substrate comprising a first main surface and a second main surface, a first layer which is a semiconductor layer, and a second layer which is formed on the first main surface side of the first layer and includes an insulator, wherein the first substrate comprises a plurality of element regions and divided regions which define the element regions. A planarization step in which the upper surface of the second layer is flattened by polishing the first main surface side of the first substrate, A first protective layer forming step is to form a first protective layer having a first opening that exposes the divided region on the upper surface of the second layer, A first groove forming step is to form a first groove having a first groove width in the divided region by etching a portion of the second layer exposed in the first opening, A support step of supporting the second main surface of the first substrate with a support member, A second protective layer formation step in which a second protective layer is formed on the surface of the second layer, A laser grooving step is performed in the divided region by irradiating the inside of the first groove with laser light from the first main surface side to form a second groove inside the first groove that penetrates the second protective layer and the second layer, reaches the first layer, and has a second groove width smaller than the first groove width. A dicing step in which, with the second main surface supported by the support member, the first substrate is divided in the second groove to form a plurality of element chips, each having the element region and a recess on the outer edge side of the first main surface; It has, A method for manufacturing a bonded body, wherein in the bonding step, the first main surface side of the element chip is brought into close contact with the second substrate and bonded. (Technology 12) A method for manufacturing a bonded body according to Technical 11, wherein in the element chip preparation step, the planarization step is performed before the first protective layer formation step. (Technology 13) A method for manufacturing a bonded body according to Technical 11, wherein in the element chip preparation step, the planarization step is performed after the first groove formation step. (Technology 14) The element chip preparation step further includes a thinning step, after the first groove forming step, in which the first substrate is thinned by grinding the second main surface side of the first substrate. The method for manufacturing a bonded body according to Technical Reference 12, wherein in the support step, the second main surface of the thinned first substrate is supported by the support member. (Technology 15) The method for manufacturing a bonded body according to any one of the technologies 11 to 13, wherein the preparation step includes a thinning step of thinning the first substrate by grinding the second main surface side of the first substrate. (Technology 16) The element chip preparation step further includes a thinning step, after the planarization step, in which the first substrate is thinned by grinding the second main surface side of the first substrate. A method for manufacturing a bonded body according to technology 12 or 13, wherein in the support step, the second main surface of the thinned first substrate is supported by the support member. (Technology 17) The second layer in the divided region includes a metal pattern exposed on the surface. The etching of the second layer in the first groove forming step includes sputter etching for etching the insulator and the metal pattern, A method for manufacturing a bonded body according to any one of the technologies 11 to 16, wherein, in the thickness direction of the first substrate, the maximum distance between the bottom surface of the first groove and the second main surface is smaller than the distance between the top surface of the second layer and the second main surface in the element region. (Technology 18) The method for manufacturing a bonded body according to any one of the technologies 11 to 16, wherein the dicing step includes a plasma dicing step of dividing the first substrate by exposing the second groove to plasma and etching the first layer. (Technology 19) The method for manufacturing a bonded body according to any one of the technologies 11 to 16, wherein the dicing step includes a laser irradiation step of dividing the first substrate by irradiating the second groove with laser light. (Technology 20) The method for manufacturing a bonded body according to any one of the technologies 11 to 16, wherein the dicing step includes a blade dicing step of dividing the first substrate in the second groove with a blade thinner than the width of the second groove. [Industrial applicability]

[0070] This disclosure can be used for manufacturing device chips and manufacturing assembled bodies. [Explanation of Symbols]

[0071] 1: First board 1a: First main surface 1b: Second principal surface 2: 1st layer 3:Second layer 3a: Metal electrode 3b: Metal electrode 3c: Metal pattern 4: 1st protective layer 4a: 1st opening 5: 1st groove 6:Second protective layer 7:Second groove 10: Element Chip 10a: Recess 20: Support member 30: Plasma processing equipment 31: Chamber 32: Antenna 33: 1st high frequency power supply 34: Processing Room 35: Stage 36:Second high frequency power supply 37: Gas inlet 38: Raw material gas source 39: Exhaust vent 40: Vacuum exhaust section 50: Second board 51: Semiconductor layer 52: Wiring layer 52a: Metal electrode D1, D2: Distance in the thickness direction DA:Divided area EA: Element Region W1: First groove width W2: Second groove width

Claims

1. A preparation step for preparing a substrate comprising a first layer which is a semiconductor layer and has a first main surface and a second main surface, and a second layer which is formed on the first main surface side of the first layer and includes an insulator, wherein the substrate comprises a plurality of element regions and divided regions which define the element regions. A planarization step is performed by polishing the first main surface side of the substrate to flatten the upper surface of the second layer, A first protective layer forming step is to form a first protective layer having a first opening that exposes the divided region on the upper surface of the second layer, A first groove forming step is performed by etching a portion of the second layer exposed in the first opening to form a first groove having a first groove width in the divided region, A support step of supporting the second main surface of the substrate with a support member, A second protective layer formation step, in which a second protective layer is formed on the surface of the second layer, A laser grooving step is performed in the divided region by irradiating the inside of the first groove with laser light from the first main surface side to form a second groove inside the first groove that penetrates the second protective layer and the second layer, reaches the first layer, and has a second groove width smaller than the first groove width. A dicing step in which, with the second main surface supported by the support member, the substrate is divided at the second groove to form a plurality of element chips, each having the element region and a recess at the outer edge on the first main surface side, A method for manufacturing an element chip, comprising the same components.

2. The method for manufacturing an element chip according to claim 1, wherein the planarization step is performed before the first protective layer formation step.

3. The method for manufacturing an element chip according to claim 1, wherein the planarization step is performed after the first groove formation step.

4. The process further includes a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate after the first groove forming step, The method for manufacturing an element chip according to claim 2, wherein in the support step, the second main surface of the thinned substrate is supported by the support member.

5. The method for manufacturing an element chip according to claim 1, wherein the preparation step includes a thinning step of thinning the substrate by grinding the second main surface side of the substrate.

6. The process further comprises a thinning step in which the substrate is thinned by grinding the second main surface side of the substrate after the planarization step, The method for manufacturing an element chip according to claim 2 or 3, wherein in the support step, the second main surface of the thinned substrate is supported by the support member.

7. The second layer in the divided region includes a metal pattern exposed on the surface. The etching of the second layer in the first groove forming step includes sputter etching for etching the insulator and the metal pattern, A method for manufacturing an element chip according to any one of claims 1 to 5, wherein, in the thickness direction of the substrate, the maximum distance between the bottom surface of the first groove and the second main surface is smaller than the distance between the top surface of the second layer and the second main surface in the element region.

8. The method for manufacturing an element chip according to any one of claims 1 to 5, wherein the dicing step includes a plasma dicing step of dividing the substrate by exposing the second groove to plasma and etching the first layer.

9. The method for manufacturing an element chip according to any one of claims 1 to 5, wherein the dicing step includes a laser irradiation step of dividing the substrate by irradiating the second groove with laser light.

10. The method for manufacturing an element chip according to any one of claims 1 to 5, wherein the dicing step includes a blade dicing step of dividing the substrate in the second groove with a blade thinner than the width of the second groove.

11. The chip preparation process involves preparing the chip, The second substrate preparation process involves preparing the second substrate, A bonding step of bonding the element chip to the second substrate, Equipped with, The above-mentioned element chip preparation process is: A preparation step for preparing a first substrate comprising a first main surface and a second main surface, a first layer which is a semiconductor layer, and a second layer which is formed on the first main surface side of the first layer and includes an insulator, wherein the first substrate comprises a plurality of element regions and divided regions which define the element regions. A planarization step is performed by polishing the first main surface side of the first substrate to flatten the upper surface of the second layer, A first protective layer forming step is to form a first protective layer having a first opening that exposes the divided region on the upper surface of the second layer, A first groove forming step is performed by etching a portion of the second layer exposed in the first opening to form a first groove having a first groove width in the divided region, A support step of supporting the second main surface of the first substrate with a support member, A second protective layer formation step, in which a second protective layer is formed on the surface of the second layer, A laser grooving step is performed in the divided region by irradiating the inside of the first groove with laser light from the first main surface side to form a second groove inside the first groove that penetrates the second protective layer and the second layer, reaches the first layer, and has a second groove width smaller than the first groove width. A dicing step in which, with the second main surface supported by the support member, the first substrate is divided in the second groove to form a plurality of element chips, each having the element region and a recess on the outer edge side of the first main surface, It has, A method for manufacturing a bonded body, wherein in the bonding step, the first main surface side of the element chip is brought into close contact with the second substrate and bonded.

12. The method for manufacturing a bonded body according to claim 11, wherein in the element chip preparation step, the planarization step is performed before the first protective layer formation step.

13. The method for manufacturing a bonded body according to claim 11, wherein in the element chip preparation step, the planarization step is performed after the first groove formation step.

14. The element chip preparation step further includes a thinning step, after the first groove forming step, in which the first substrate is thinned by grinding the second main surface side of the first substrate. The method for manufacturing a bonded body according to claim 12, wherein in the support step, the second main surface of the thinned first substrate is supported by the support member.

15. The method for manufacturing a bonded body according to claim 11, wherein the preparation step includes a thinning step of thinning the first substrate by grinding the second main surface side of the first substrate.

16. The element chip preparation step further includes a thinning step, after the planarization step, in which the first substrate is thinned by grinding the second main surface side of the first substrate. The method for manufacturing a bonded body according to claim 12 or 13, wherein in the support step, the second main surface of the thinned first substrate is supported by the support member.

17. The second layer in the divided region includes a metal pattern exposed on the surface. The etching of the second layer in the first groove forming step includes sputter etching for etching the insulator and the metal pattern, A method for manufacturing a bonded body according to any one of claims 11 to 15, wherein, in the thickness direction of the first substrate, the maximum distance between the bottom surface of the first groove and the second main surface is smaller than the distance between the top surface of the second layer and the second main surface in the element region.

18. The method for manufacturing a bonded body according to any one of claims 11 to 15, wherein the dicing step includes a plasma dicing step of dividing the first substrate by exposing the second groove to plasma and etching the first layer.

19. The method for manufacturing a bonded body according to any one of claims 11 to 15, wherein the dicing step includes a laser irradiation step of dividing the first substrate by irradiating the second groove with laser light.

20. The method for manufacturing a bonded body according to any one of claims 11 to 15, wherein the dicing step includes a blade dicing step of dividing the first substrate in the second groove with a blade thinner than the width of the second groove.

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