Transistor characteristic determination method, transistor characteristic determination circuit, and power conversion device

Abstract

The present invention aims to provide a transistor characteristic determination method, a transistor characteristic determination circuit, and a power conversion device that can suppress the increase in circuit size. [Solution] The transistor characteristic determination method involves simultaneously setting multiple transistors 12UU, 12UL, 12VU, 12VL, or 12WU, 12WL connected in series between the positive power supply line LP and the negative power supply line LN to the ON state (steps ST3, ST4), detecting the drain-source voltage of the target transistor to be characteristic determined from among the multiple transistors 12UU, 12UL, 12VU, 12VL, or 12WU, 12WL (step ST6), and determining the characteristics of the target transistor based on the detected drain-source voltage (steps ST7, ST8).

Description

Technical Field

[0001] The present invention relates to a transistor characteristic determination method, a transistor characteristic determination circuit, and a power conversion device.

Background Art

[0002] Patent Document 1 discloses a technique for suppressing fluctuations in the threshold voltage of a power semiconductor device when such fluctuations occur.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Power semiconductor devices have a drain current dependence on the on-voltage. Therefore, when converting fluctuations in the threshold voltage of a power semiconductor device based on changes in the on-voltage of the power semiconductor device as in the prior art, it is necessary to measure the drain current simultaneously in order to accurately measure the on-voltage of the power semiconductor device. Therefore, in the prior art, in addition to a measurement circuit for the on-voltage of the power semiconductor device, a current sensor is required. As a result, the prior art has a problem in that the circuit scale for determining fluctuations in transistor characteristics such as the threshold voltage of the power semiconductor device increases.

[0005] An object of the present invention is to provide a transistor characteristic determination method, a transistor characteristic determination circuit, and a power conversion device capable of suppressing an increase in circuit scale.

Means for Solving the Problems

[0006] To achieve the above objective, a transistor characteristic determination method according to one aspect of the present invention involves simultaneously turning on a plurality of silicon carbide metal oxide film semiconductor field-effect transistors connected in series between a positive-side power supply line and a negative-side power supply line, detecting the drain-source voltage of a target transistor among the plurality of silicon carbide metal oxide film semiconductor field-effect transistors that is the subject of characteristic determination, and determining the characteristics of the target transistor based on the detected voltage, which is the detected drain-source voltage.

[0007] Furthermore, in order to achieve the above objective, a transistor characteristic determination circuit according to one aspect of the present invention includes a detection unit that detects the drain-source voltage of a target transistor that is the subject of characteristic determination, which is one of a plurality of silicon carbide metal oxide film semiconductor field-effect transistors connected in series between a positive-side power supply line and a negative-side power supply line and set to be turned on simultaneously, and a determination unit that determines the characteristics of the target transistor based on the detected voltage, which is the drain-source voltage detected by the detection unit.

[0008] Furthermore, in order to achieve the above objective, a power conversion device according to one aspect of the present invention comprises a transistor characteristic determination circuit according to the above aspect and the plurality of silicon carbide metal oxide film semiconductor field-effect transistors. [Effects of the Invention]

[0009] According to each aspect of the present invention, it is possible to suppress an increase in the size of the circuit. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing an example of a schematic configuration of a power conversion device according to one embodiment of the present invention. [Figure 2] This figure shows an example of a schematic configuration of a transistor characteristic determination circuit and a gate drive circuit having a transistor characteristic determination circuit according to one embodiment of the present invention. [Figure 3]This figure illustrates the principle of a transistor characteristic determination method according to one embodiment of the present invention, and is a schematic graph showing an example of the relationship between the amount of variation in the threshold voltage of a transistor and the rate of change of the collector current. [Figure 4] This figure illustrates the principle of a transistor characteristic determination method according to one embodiment of the present invention, and is a schematic graph showing an example of the relationship between the amount of variation in the transistor threshold voltage and the amount of decrease in the drain-source voltage. [Figure 5] This flowchart shows an example of the processing flow for a transistor characteristic determination method according to one embodiment of the present invention. [Figure 6] This figure illustrates a method for determining transistor characteristics according to one embodiment of the present invention, and shows an example of an operating waveform of a transistor constituting the upper arm under normal conditions. [Figure 7] This figure illustrates a transistor characteristic determination method according to one embodiment of the present invention, and shows an example of an operating waveform in a degraded state of a transistor constituting the upper arm. [Figure 8] This figure illustrates a transistor characteristic determination method according to one embodiment of the present invention, and shows an example of the operating waveform of a transistor constituting the lower arm in a normal state. [Figure 9] This figure illustrates a transistor characteristic determination method according to one embodiment of the present invention, and shows an example of an operating waveform in a degraded state of a transistor constituting the lower arm. [Modes for carrying out the invention]

[0011] The embodiments of the present invention illustrate apparatus and methods for realizing the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0012] 1. Configuration of the power converter: A schematic configuration of a power converter according to one embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the schematic configuration of the power converter 1 according to this embodiment.

[0013] As shown in Figure 1, the power converter 1 comprises a positive terminal TP, a negative terminal TN, an inverter unit 10, and a control device 12. The positive terminal TP is connected to the positive power supply line LP. The negative terminal TN is connected to the negative power supply line LN. A DC power supply 2 is connected between the positive power supply line LP and the negative power supply line LN.

[0014] The inverter section 10 includes transistors 12UU, 12UL, 12VU, 12VL, 12WU, and 12WL, and gate drive circuits 11UU, 11UL, 11VU, 11VL, 11WU, and 11WL. The inverter section 10 may also include freewheeling diodes connected in antiparallel to each of the transistors 12UU, 12UL, 12VU, 12VL, 12WU, and 12WL. Hereinafter, "transistors 12UU, 12UL, 12VU, 12VL, 12WU, and 12WL" may be abbreviated as "transistors 12UU~12WL". Also, "gate drive circuits 11UU, 11UL, 11VU, 11VL, 11WU, and 11WL" may be abbreviated as "gate drive circuits 11UU~11WL".

[0015] Each of the transistors 12UU to 12WL is a power semiconductor device. Each of the transistors 12UU to 12WL is, for example, composed of a silicon carbide metal oxide semiconductor field effect transistor (SiCMOSFET).

[0016] Transistors 12UU and 12UL are connected in series between the positive - side power line LP and the negative - side power line LN. Transistors 12VU and 12VL are connected in series between the positive - side power line LP and the negative - side power line LN. Transistors 12WU and 12WL are connected in series between the positive - side power line LP and the negative - side power line LN.

[0017] The drain D of each of the transistors 12UU, 12VU, and 12WU is connected to the positive - side power line LP. The source S of each of the transistors 12UU, 12VU, and 12WU is connected to the motor 3 which is a load device. The drain D of each of the transistors 12UL, 12VL, and 12WL is connected to the motor 3 which is a load device. The source S of each of the transistors 12UL, 12VL, and 12WL is connected to the negative - side power line LN. The source S of the transistor 12UU is connected to the drain D of the transistor 12UL. The source S of the transistor 12VU is connected to the drain D of the transistor 12VL. The source S of the transistor 12WU is connected to the drain D of the transistor 12WL.

[0018] Transistors 12UU and 12UL, transistors 12VU and 12VL, and transistors 12WU and 12WL are connected in parallel between the positive - side power line LP and the negative - side power line LN. Thus, the inverter section 10 has a configuration in which transistors 12UU to 12WL are full - bridge connected between the positive - side power line LP and the negative - side power line LN, that is, between the positive - side electrode and the negative - side electrode of the DC power supply 2.

[0019] Transistors 12UU and 12UL constitute the U-phase output arm in the inverter section 10. Transistors 12VU and 12VL constitute the V-phase output arm in the inverter section 10. Transistors 12WU and 12WL constitute the W-phase output arm in the inverter section 10. Transistors 12UU, 12VU, and 12WU constitute the upper arm in the inverter section 10. Transistors 12UL, 12VL, and 12WL constitute the lower arm in the inverter section 10.

[0020] The inverter section 10 provided in the power converter 1 is connected in parallel between the positive-side power line LP and the negative-side power line LN and has multiple transistor groups 12UG, 12VG, and 12WG, each having multiple transistors. Transistor group 12UG has transistors 12UU and 12UL, transistor group 12VG has transistors 12VU and 12VL, and transistor group 12WG has transistors 12WU and 12WL.

[0021] The gate drive circuit 11UU is a circuit that drives transistor 12UU. The output terminal of the gate drive circuit 11UU is connected to the gate G of transistor 12UU. The gate drive circuit 11UL is a circuit that drives transistor 12UL. The output terminal of the gate drive circuit 11UL is connected to the gate G of transistor 12UL. The gate drive circuit 11VU is a circuit that drives transistor 12VU. The output terminal of the gate drive circuit 11VU is connected to the gate G of transistor 12VU. The gate drive circuit 11VL is a circuit that drives transistor 12VL. The output terminal of the gate drive circuit 11VL is connected to the gate G of transistor 12VL. The gate drive circuit 11WU is a circuit that drives transistor 12WU. The output terminal of the gate drive circuit 11WU is connected to the gate G of transistor 12WU. The gate drive circuit 11WL is a circuit that drives transistor 12WL. The output terminal of the gate drive circuit 11WL is connected to the gate G of transistor 12WL.

[0022] The inverter unit 10 outputs U-phase AC power to the motor 3, which is obtained by converting the DC power input from the DC power supply 2 through the on / off operation of transistors 12UU and 12UL. The inverter unit 10 outputs V-phase AC power to the motor 3, which is obtained by converting the DC power input from the DC power supply 2 through the on / off operation of transistors 12VU and 12VL. The inverter unit 10 outputs W-phase AC power to the motor 3, which is obtained by converting the DC power input from the DC power supply 2 through the on / off operation of transistors 12WU and 12WL.

[0023] Wiring inductance L is formed in the inverter section 10. Wiring inductance L is the inductance formed in the wiring of the main current (i.e., drain current) supplied from the DC power supply 2 and flowing through transistors 12UU to 12WL. As will be described in detail later, the drain-source voltage of each transistor 12UU to 12WL decreases due to the effect of wiring inductance L, and this decrease also changes with the change in threshold voltage. In this embodiment, the decrease in the drain-source voltage of each transistor 12UU to 12WL is used to determine the change in the characteristics of transistors 12UU to 12WL (threshold voltage in this embodiment).

[0024] The control device 12 is a device that controls the gate drive circuits 11UU to 11WL. The control device 12 outputs control signals Sin_uu, Sin_ul, Sin_vu, Sin_vl, Sin_wu, and Sin_wl to the gate drive circuits 11UU to 11WL for controlling them. The control device 12 also outputs detection command signals Sdc_uu, Sdc_ul, Sdc_vu, Sdc_vl, Sdc_wu, and Sdc_wl to the transistor characteristic determination circuits (not shown in Figure 1) provided in each of the gate drive circuits 11UU to 11WL for commanding the detection of the drain-source voltage. Furthermore, the control device 12 receives judgment result signals Soc_uu, Soc_ul, Soc_vu, Soc_vl, Soc_wu, and Soc_wl from the transistor characteristic determination circuits provided in each of the gate drive circuits 11UU to 11WL, which contain information on whether or not transistors 12UU to 12WL are degraded.

[0025] 2. Configuration of the transistor characteristic determination circuit: The schematic configuration of the transistor characteristic determination circuit 111 and gate drive circuits 11UU and 11UL according to this embodiment will be described with reference to Figure 1 and with reference to Figure 2. Figure 2 is a block diagram showing an example of the schematic configuration of gate drive circuits 11UU and 11UL equipped with the transistor characteristic determination circuit 111. Since the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU and the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL have similar configurations, the configuration of the transistor characteristic determination circuit 111 will be described below using the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU as an example.

[0026] As shown in Figure 2, the transistor characteristic determination circuit 111 is provided in the gate drive circuit 11UU. Therefore, the power converter 1 comprises the transistor characteristic determination circuit 111 according to this embodiment and a plurality of transistors 12UU to 12WL.

[0027] The gate drive circuit 11UU includes, in addition to the transistor characteristic determination circuit 111, switches 112 and 113, DC power supplies 114 and 115, a NOT gate 116, and a gate resistor 117.

[0028] The positive terminal of DC power supply 114 is connected to one terminal of switch 112, and the negative terminal of DC power supply 114 is connected to the positive terminal of DC power supply 115. The negative terminal of DC power supply 114 and the positive terminal of DC power supply 115 are connected to the source S of transistor 12UU and the drain D of transistor 12UL. The other terminal of switch 112 is connected to one terminal of switch 113 and one terminal of gate resistor 117. The other terminal of switch 113 is connected to the negative terminal of DC power supply 115. The other terminal of gate resistor 117 is connected to the gate G of transistor 12UU. The input terminal of NOT gate 116 is connected to the control terminal of switch 112 and the control device 12 (see Figure 1). The output terminal of NOT gate 116 is connected to the control terminal of switch 113.

[0029] Switches 112 and 113 are each composed of, for example, MOSFETs of the same conductivity type. The control terminal of switch 112 receives the control signal Sin_uu input from the control device 12 (see Figure 1). On the other hand, the control terminal of switch 113 receives the control signal Sin_uu, whose phase has been inverted by 180° by the NOT gate 116. As a result, switches 112 and 113 are controlled such that when one is ON, the other is OFF, and when one is OFF, the other is ON.

[0030] When switch 112 is ON and switch 113 is OFF, the positive voltage of the DC power supply 114 is applied to the gate G of transistor 12UU via the gate resistor 117, and the negative voltage of the DC power supply 114 is applied to the source S of transistor 12UU. As a result, a positive gate-source voltage VGS_uu is applied between the gate G and source S of transistor 12UU. Consequently, transistor 12UU is turned ON.

[0031] When switch 112 is off and switch 113 is on, the negative voltage of the DC power supply 115 is applied to the gate G of transistor 12UU via the gate resistor 117, and the positive voltage of the DC power supply 115 is applied to the source S of transistor 12UU. As a result, a negative gate-source voltage VGS_uu is applied between the gate G and source S of transistor 12UU. Consequently, transistor 12UU is in the off state. In this way, the gate drive circuit 11UU drives transistor 12UU based on the signal level of the control signal Sin_uu input from the control device 12.

[0032] The transistor characteristic determination circuit 111 comprises a detection unit 111a and a determination unit 111b. The detection unit 111a detects the drain-source voltage of the target transistor whose characteristics are to be determined, which is one of several (two in this embodiment) transistors 12UU, 12UL connected in series between the positive-side power supply line LP and the negative-side power supply line LN and set to the ON state simultaneously.

[0033] For example, if, among transistors 12UU and 12UL, the target transistor whose characteristics are to be determined (the target for characteristic determination) is transistor 12UU, the detection unit 111a provided in the gate drive circuit 11UU detects the drain-source voltage VDS_uu of transistor 12UU. In this case, the detection unit 111a provided in the gate drive circuit 11UL does not detect the drain-source voltage VDS_ul of transistor 12UL.

[0034] For example, if the target transistor for characteristic evaluation among transistors 12UU and 12UL is transistor 12UL, the detection unit 111a provided in the gate drive circuit 11UL detects the drain-source voltage VDS_ul of transistor 12UL. In this case, the detection unit 111a provided in the gate drive circuit 11UU does not detect the drain-source voltage VDS_uu of transistor 12UU. Thus, the detection unit 111a provided in the gate drive circuits 11UU and 11UL detects the drain-source voltages VDS_uu and VDS_ul when the target transistors are transistors 12UU and 12UL driven by the gate drive circuits 11UU and 11UL to which it is provided.

[0035] The determination unit 111b determines the characteristics of the target transistor, transistor 12UU, based on the detected voltage, which is the drain-source voltage VDS_uu detected by the detection unit 111a. Based on the detected voltage, the determination unit 111b determines whether or not the characteristics of transistor 12UU (in this embodiment, the characteristics of the threshold voltage) have deteriorated, and outputs a determination result signal Soc_uu, which includes information on the determination result, to the control device 12. Details of the method for determining the deterioration of the characteristics of transistor 12UU in the determination unit 111b will be described later.

[0036] The transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU, except that the connection points of the DC power supplies 114 and 115 are connected, the signals input from the control device 12 are different, the signals output to the control device 12 are different, and the transistor to be driven is different.

[0037] In the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL, the connections of the DC power supplies 114 and 115 are connected to the source S and negative side power supply line LN of the transistor 12UL. Furthermore, the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU when "transistor 12UU" is read as "transistor 12UL", "control signal Sin_uu" is read as "control signal Sin_ul", "detection command signal Sdc_uu" is read as "detection command signal Sdc_ul", and "determination result signal Soc_uu" is read as "determination result signal Soc_ul".

[0038] Although not shown in the diagram, transistor characteristic determination circuits are also provided in each of the gate drive circuits 11VU, 11VL, 11WU, and 11WL. The transistor characteristic determination circuit provided in the gate drive circuit 11VU (see Figure 1) has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU when "transistor 12UU" is read as "transistor 12VU" (see Figure 1), "control signal Sin_uu" is read as "control signal Sin_vu" (see Figure 1), "detection command signal Sdc_uu" is read as "detection command signal Sdc_vu" (see Figure 1), and "determination result signal Soc_uu" is read as "determination result signal Soc_vu" (see Figure 1).

[0039] The transistor characteristic determination circuit provided in the gate drive circuit 11VL (see Figure 1) has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL when "transistor 12UL" is read as "transistor 12VL" (see Figure 1), "control signal Sin_ul" is read as "control signal Sin_vl" (see Figure 1), "detection command signal Sdc_ul" is read as "detection command signal Sdc_vl" (see Figure 1), and "determination result signal Soc_ul" is read as "determination result signal Soc_vl" (see Figure 1).

[0040] The transistor characteristic determination circuit provided in the gate drive circuit 11WU (see Figure 1) has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU when "transistor 12UU" is read as "transistor 12WU" (see Figure 1), "control signal Sin_uu" is read as "control signal Sin_wu" (see Figure 1), "detection command signal Sdc_uu" is read as "detection command signal Sdc_wu" (see Figure 1), and "determination result signal Soc_uu" is read as "determination result signal Soc_wu" (see Figure 1).

[0041] The transistor characteristic determination circuit provided in the gate drive circuit 11WL (see Figure 1) has the same configuration as the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL when "transistor 12UL" is read as "transistor 12WL" (see Figure 1), "control signal Sin_ul" is read as "control signal Sin_wl" (see Figure 1), "detection command signal Sdc_ul" is read as "detection command signal Sdc_wl" (see Figure 1), and "determination result signal Soc_ul" is read as "determination result signal Soc_wl" (see Figure 1).

[0042] Thus, the transistor characteristic determination circuits 111 provided in each of the gate drive circuits 11UU to 11WL can determine the characteristics of transistors 12UU to 12WL (in this embodiment, the variation from the initial value of the threshold voltage) without detecting the drain current ID flowing through transistors 12UU to 12WL. For this reason, the transistor characteristic determination circuit 111 does not need to have a current sensor and a current detection unit. As a result, the transistor characteristic determination circuit 111 and the power conversion device 1 equipped therewith can be made smaller in scale.

[0043] 3. Principle of the transistor characteristic determination method: The principle of the transistor characteristic determination method according to this embodiment will be explained using Figures 3 and 4 with reference to Figure 2. Figure 3 is a schematic graph showing an example of the relationship between the amount of fluctuation in the threshold voltage of a SiCMOSFET and the rate of change of the drain current of the SiCMOSFET. In the graph in Figure 3, the horizontal axis represents the amount of fluctuation in the threshold voltage of the SiCMOSFET, and the vertical axis represents the rate of change of the drain current of the SiCMOSFET. Figure 4 is a schematic graph showing an example of the relationship between the amount of fluctuation in the threshold voltage of a SiCMOSFET and the decrease in the drain-source voltage of the SiCMOSFET. In the graph in Figure 4, the horizontal axis represents the amount of fluctuation in the threshold voltage of the SiCMOSFET, and the vertical axis represents the decrease in the drain-source voltage of the SiCMOSFET. The amount of fluctuation in the threshold voltage in Figures 3 and 4 is the amount of fluctuation relative to the initial value.

[0044] As shown in Figure 3, SiCMOSFETs have the characteristic that the rate of current increase decreases as the threshold voltage fluctuation increases. In other words, SiCMOSFETs have the characteristic that the turn-on speed decreases as the threshold voltage fluctuation increases.

[0045] As shown in Figure 4, SiCMOSFETs have the characteristic that the amount of drain-source voltage drop decreases as the threshold voltage fluctuation increases. Here, the amount of drain-source voltage drop of a SiCMOSFET will be explained. In the inverter section 10 of the power conversion device 1 according to this embodiment, for example, when both transistors 12UU and 12UL constituting the U-phase arm are turned on and the positive-side power supply line LP and the negative-side power supply line LN are short-circuited, a current path RT is formed consisting of the DC power supply 2, the wiring inductance L, transistors 12UU and 12UL, as shown in Figure 2.

[0046] Let VDS_uu be the drain-source voltage of transistor 12UU, VDS_ul be the drain-source voltage of transistor 12UL, VL be the induced voltage of the wiring inductance L, and Ed be the output voltage of DC power supply 2. Then, the following equation (1) holds in the current path RT: VDS_uu + VDS_ul + VL = Ed ... (1)

[0047] Assuming that the on-resistances of transistors 12UU and 12UL are the same, and VDS is the drain-source voltage of transistors 12UU and 12UL, the voltage is divided roughly equally between transistors 12UU and 12UL, so equation (1) can be expressed as equation (2) below. VDS = (Ed - VL) / 2 ... (2)

[0048] If we let Lv be the inductance value of the wiring inductance L, and i be the current flowing through the wiring inductance L, then equation (2) can be expressed as equation (3) below. VDS=(Ed-Lv×(di / dt)) / 2 ···(3)

[0049] Since the output voltage output of DC power supply 2 is constant, the term "Ed" on the right side of equation (3) is a constant. On the other hand, the current flowing through the wiring inductance L changes with time, so the term "Lv × (di / dt) / 2" on the right side of equation (3) is a variable. Since the wiring inductance L is formed in series with transistors 12UU and 12UL between transistors 12UU and 12UL and DC power supply 2, the current flowing through the wiring inductance L and the drain current ID flowing through transistors 12UU and 12UL are common. As shown in Figure 3, the rate of change of the drain current of a SiCMOSFET varies according to the amount of change in the threshold voltage of the SiCMOSFET. Therefore, the rate of change of the drain current ID of SiCMOSFETs transistors 12UU and 12UL varies according to the amount of change in the threshold voltage of transistors 12UU and 12UL. Therefore, the current flowing through the wiring inductance L also fluctuates according to the amount of change in the threshold voltage of transistors 12UU and 12UL.

[0050] The term "di / dt" on the right-hand side of equation (3) varies according to the amount of variation in the threshold voltages of transistors 12UU and 12UL. Therefore, the term "Lv × (di / dt) / 2" on the right-hand side of equation (3) is the factor that causes the drain-source voltage to vary according to the amount of variation in the threshold voltages of transistors 12UU and 12UL. If the amount of variation in the drain-source voltages of transistors 12UU and 12UL is ΔVDS, then this amount of variation can be expressed as shown in equation (4) below. ΔVDS = Lv × (di / dt) / 2 ... (4)

[0051] Incidentally, the threshold voltage of a SiCMOSFET tends to increase from its initial value due to aging degradation caused by the operation of the SiCMOSFET. Therefore, if the variation in the threshold voltage from the initial value exceeds a predetermined value, the SiCMOSFET will no longer be able to perform the desired operation. Accordingly, the maximum threshold voltage at which the variation from the initial value of the threshold voltage of each transistor 12UU to 12WL is allowed is defined as the lifetime threshold voltage Vth_lt. The decrease in drain-source voltage (i.e., the variation in drain-source voltage ΔVDS) when the threshold voltage of each transistor 12UU to 12WL reaches the lifetime threshold voltage Vth_lt is set as the degradation determination voltage Vo. As shown in Figure 4, when the threshold voltage is less than or equal to the lifetime threshold voltage Vth_lt, the decrease in drain-source voltage is greater than or equal to the degradation determination voltage Vo. On the other hand, when it is greater than the lifetime threshold voltage Vth_lt, the decrease in drain-source voltage is less than the degradation determination voltage Vo.

[0052] The left side of equation (3) corresponds to the drain-source voltage of each transistor 12UU to 12WL, and the fluctuation amount ΔVDS of the drain-source voltage of each transistor 12UU to 12WL corresponds to the term "Lv × (di / dt) / 2" on the right side of equation (3). Therefore, the drain-source voltage of each transistor 12UU to 12WL fluctuates according to the fluctuation amount of the threshold voltage of each transistor 12UU to 12WL. The transistor characteristic determination method according to this embodiment utilizes the characteristic that the drain-source voltage decreases due to an increase in the fluctuation amount of the threshold voltage. The transistor characteristic determination method according to this embodiment determines whether the transistor 12UU to 12WL is in a degraded state by comparing the detected drain-source voltage and the degradation determination voltage Vo, based on the result of the comparison.

[0053] In the transistor characteristic determination method according to this embodiment, when transistors 12UU and 12UL are turned on simultaneously, whether or not the target transistor is degraded is detected based on the difference between the drain-source voltage of the target transistor among transistors 12UU and 12UL and the degradation determination voltage Vo. Similarly, when transistors 12VU and 12VL are turned on simultaneously, whether or not the target transistor is degraded is detected based on the difference between the drain-source voltage of the target transistor among transistors 12VU and 12VL and the degradation determination voltage Vo. Similarly, when transistors 12WU and 12WL are turned on simultaneously, whether or not the target transistor is degraded is detected based on the difference between the drain-source voltage of the target transistor among transistors 12WU and 12WL and the degradation determination voltage Vo.

[0054] 4. Transistor characteristic determination method: The transistor characteristic determination method according to this embodiment will be explained with reference to Figures 1 to 4 and Figures 5 to 9. The transistor characteristic determination methods for each of the transistor groups 12UG, 12VG, and 12WG are the same. For this reason, the transistor characteristic determination method will be explained below using transistor group 12UG as an example. Figure 5 is a flowchart showing an example of the transistor characteristic determination process according to this embodiment. In this embodiment, the degradation determination of each of the transistors 12UU to 12WL is performed individually according to the transistor characteristic determination process shown in Figure 5.

[0055] The transistor characteristic determination process according to this embodiment may be performed before operation of the power converter 1, after operation, or during operation to the extent that it does not affect the operation of the power converter 1. Furthermore, the transistor characteristic determination process according to this embodiment may not be performed every time the power converter 1 is operated, but may be performed every predetermined number of operations or every predetermined operating time.

[0056] As shown in Figure 5, in the transistor characteristic determination method according to this embodiment, for example, when determining the characteristics of transistor 12UU, first, in step ST1, all transistors 12UU~12WL (see Figure 1) are set to the OFF state, and the process proceeds to step ST2. In order to drive transistors 12UU~12WL to the OFF state, for example, a gate signal with a low signal level is output from the gate drive circuit 11UU~11WL (see Figure 1) to the gate G of transistors 12UU~12WL.

[0057] In step ST2, the DC power supply 2 (see Figure 2) is charged, and the process proceeds to step ST3. In this embodiment, in the processes from step ST3 onward, which will be described later, an output voltage Ed, which is a voltage value that can bring transistors 12UU and 12UL into a fully ON state, is output from the DC power supply 2.

[0058] In step ST3, among transistors 12UU and 12UL, the asymmetric transistor whose transistor characteristics cannot be determined, such as transistor 12UL, is set to the ON state, and the process proceeds to step ST4. To drive transistor 12UL to the ON state, for example, a gate signal with a high signal level is output from the gate drive circuit 11UL to the gate G of transistor 12UL.

[0059] In the transistor characteristic determination method according to this embodiment, as shown in the flow from step ST1 to step ST3, when multiple transistor groups 12UG, 12VG, and 12WG (see Figure 1), each having multiple transistors 12UU, 12UL, multiple transistors 12VU, 12VL, and multiple transistors 12WU, 12WL, are connected in parallel between the positive-side power supply line LP and the negative-side power supply line LN (see Figure 1), the multiple transistors 12VU, 12VL, 12WU, and 12WL in the transistor groups 12VG and 12WG, which do not include the target transistor (transistor 12UU in this example), are set to the OFF state before the non-target transistor (transistor 12UL in this example) is set to the ON state, and remain in the OFF state even after the non-target transistor is set to the ON state.

[0060] In step ST4, among transistors 12UU and 12UL, the transistor whose transistor characteristics are to be determined, for example, transistor 12UU, is set to the ON state, and the process proceeds to step ST5. To drive transistor 12UU to the ON state, for example, a gate signal with a high signal level is output from the gate drive circuit 11UU to the gate G of transistor 12UU. In this way, in the transistor characteristic determination method according to this embodiment, transistors 12UU and 12UL (an example of multiple silicon carbide metal oxide film semiconductor field-effect transistors) connected in series between the positive side power supply line LP and the negative side power supply line LN (see Figure 1) are simultaneously set to the ON state.

[0061] In the transistor characteristic determination method according to this embodiment, when setting transistors 12UU and 12UL to the ON state simultaneously, as shown in the flow from step ST3 to step ST4, the non-target transistor (transistor 12UL in this example), excluding the target transistor (transistor 12UU in this example), is first set to the ON state, and then the target transistor is set to the ON state.

[0062] In step ST5, it is determined whether the rate of change of the drain current flowing through transistor 12UU has reached its peak. Specifically in this example, if the control device 12 determines that the rate of change of the drain current flowing through transistor 12UU has reached its peak (step ST5: YES), it proceeds to the process of step ST6. On the other hand, if the control device 12 determines that the rate of change of the current has not reached its peak (step ST5: NO), it repeats the process of step ST5. In this embodiment, for example, the control device 12 determines that the rate of change of the current has reached its peak when a predetermined time has elapsed since outputting the control signal Sin_uu for turning on transistor 12UU to the gate drive circuit 11UU. This predetermined time may be set based on the design value of the inverter unit 10, set by operation simulation of the inverter unit 10, or set based on measured values ​​during operation verification of the inverter unit 10.

[0063] In step ST6, the drain-source voltage (in this example, drain-source voltage VDS_uu) of the target transistor (in this example, transistor 12UU) among the multiple transistors 12UU, 12UL that are to be characterized is detected, and the process proceeds to step ST7. Specifically in this example, the control device 12 outputs a detection command signal Sdc_uu to the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU. When the detection command signal Sdc_uu is input to the detection unit 111a of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU, it detects the drain-source voltage VDS_uu of transistor 12UU.

[0064] As described above, in the transistor characteristic determination method according to this embodiment, as shown in the flow from step ST5 to ST6, the drain-source voltage VDS_uu is detected at the point when the rate of change of the drain current (an example of a short-circuit current) flowing through multiple transistors 12UU and 12UL reaches its peak during the turn-on period of the target transistor (transistor 12UU in this example).

[0065] In step ST7, the drain-source voltage VDS_uu detected in step ST6 is compared with the degradation determination voltage Vo (see Figure 4), and the process proceeds to step ST8. In this example, the degradation determination voltage Vo is set based on the relationship between the drain-source voltage VDS_uu of transistor 12UU and the threshold voltage. The degradation determination voltage Vo is set, for example, in the determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU. Therefore, in step ST7, the determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU compares the drain-source voltage VDS_uu detected in step ST6 by the detection unit 111a of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU with the set degradation determination voltage Vo, and determines the fluctuation of the threshold voltage of transistor 12UU. Thus, in the transistor characteristic determination method in this example, the fluctuation of the threshold voltage of transistor 12UU is determined based on the difference between the detected drain-source voltage VDS_uu (an example of a detected voltage) and the degradation determination voltage (an example of a determination voltage) which is set based on the relationship between the drain-source voltage VDS_uu of transistor 12UU and the threshold voltage.

[0066] In step ST8, it is determined whether the drain-source voltage detected in step ST6 is lower than the degradation detection voltage. Specifically in this example, if the determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU determines that the drain-source voltage VDS_uu detected in step ST6 is lower than the degradation detection voltage Vo (step ST8: YES), it proceeds to step ST9. On the other hand, if the determination unit 111b determines that the drain-source voltage VDS_uu detected in step ST6 is higher than the degradation detection voltage Vo (step ST8: NO), it proceeds to step ST10.

[0067] Thus, the transistor characteristic determination method according to this embodiment determines the characteristics of the target transistor based on the detected voltage, which is the drain-source voltage detected, through the processing flow from step ST7 to step ST8.

[0068] In step ST9, a determination result signal indicating that the target transistor is in a normal state is output, and the characteristic determination of one of the transistors 12UU to 12WL provided in the inverter unit 10 is completed. Specifically in this example, the determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU outputs a determination result signal Soc_uu to the control device 12, which contains information indicating that the characteristics of transistor 12UU have not deteriorated and are in a normal state.

[0069] In step ST10, a determination result signal indicating that the target transistor is in a degraded state is output, and the characteristic determination of one of the transistors 12UU to 12WL provided in the inverter unit 10 is completed. Specifically in this example, the determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU outputs a determination result signal Soc_uu to the control device 12, which contains information indicating that the characteristics of transistor 12UU are in a degraded state. The determination result signal may indicate, for example, whether the state of the target transistor is normal or degraded by the signal level. For example, if the target transistor is in a normal state, the signal level of the determination result signal may be set to a low level, and if the target transistor is in a degraded state, the signal level of the determination result signal may be set to a high level.

[0070] As described above, in the transistor characteristic determination method according to this embodiment, if the detected drain-source voltage (an example of a detected voltage) is lower than the degradation determination voltage (an example of a determination voltage) through the processing flow from step ST8 to step ST9, the threshold voltage fluctuation of the target transistor is within an acceptable range and the target transistor is determined to be in a normal state. On the other hand, in the transistor characteristic determination method according to this embodiment, if the detected drain-source voltage is higher than the degradation determination voltage, the threshold voltage fluctuation of the target transistor is outside an acceptable range and the target transistor is determined to be in a degraded state.

[0071] Next, the transistor characteristic determination method according to this embodiment will be explained with reference to the operating waveforms of the transistors. Figures 6 to 9 are diagrams showing examples of the operating waveforms of target transistors in the transistor characteristic determination process according to this embodiment. Figure 6 is a diagram showing an example of the operating waveform of a transistor that is in a normal state and constitutes the upper arm. Figure 7 is a diagram showing an example of the operating waveform of a transistor that is in a degraded state and constitutes the upper arm. Figure 8 is a diagram showing an example of the operating waveform of a transistor that is in a normal state and constitutes the lower arm. Figure 9 is a diagram showing an example of the operating waveform of a transistor that is in a degraded state and constitutes the lower arm. Figures 6 and 7 show the operating waveform of transistor 12UU as the target transistor, and Figures 8 and 9 show the operating waveform of transistor 12UL as the target transistor.

[0072] The upper sections of Figures 6 through 9 schematically illustrate the voltage waveforms of the gate-source voltages VGS_uu and VGS_ul of transistors 12UU and 12UL. The lower sections of Figures 6 and 7 schematically illustrate the voltage waveform of the drain-source voltage VDS_uu and the current waveform of the drain current ID flowing through transistor 12UU. The lower sections of Figures 8 and 9 schematically illustrate the voltage waveform of the drain-source voltage VDS_ul and the current waveform of the drain current ID flowing through transistor 12UL. "V114" in Figures 6 through 9 indicates the potential of the output voltage output from the DC power supply 114 provided on the gate drive circuits 11UU and 11UL. "Vref" in Figures 6 through 9 indicates the potential of the connection between DC power supply 114 and DC power supply 115, and serves as the reference potential for the gate-source voltage. In Figures 6 through 9, "Ed" indicates the voltage value of the output voltage output from DC power supply 2.

[0073] First, regarding the transistor characteristic determination method according to this embodiment, we will describe the case where the target transistor is the transistor 12UU that constitutes the upper arm of the inverter unit 10, and the transistor 12UU is in a normal state.

[0074] As shown in Figure 6, after all transistors 12UU to 12WL are set to the OFF state (step ST1), transistor 12UL, which is the non-asymmetrical transistor among transistors 12UU and 12UL, is set to the ON state (step ST3). As a result, a gate-source voltage VGS_ul with the voltage value "V114-Vref" is applied between the gate G and source S of transistor 12UL. This causes transistor 12UL to transition from the OFF state to the ON state.

[0075] On the other hand, since transistor 12UU is set to the off state, a gate-source voltage VGS_uu with the voltage value "-V115-Vref" is applied between the gate G and source S of transistor 12UU. Therefore, the drain-source voltage VDS_uu of transistor 12UU is half the voltage value Ed of the output voltage output from DC power supply 2. In this case, the potential of the drain D of transistor 12UU is approximately the same as the positive terminal potential of DC power supply 2, and the potential of the source S of transistor 12UU is approximately the same as half the positive terminal potential of DC power supply 2. Also, although transistor 12UL is in the on state, since transistor 12UU is in the off state, no drain current ID flows through transistors 12UU and 12UL.

[0076] At time t1, transistor 12UU, the target transistor among transistors 12UU and 12UL, is set to the ON state (step ST4). As a result, a gate-source voltage VGS_ul with the voltage value "V114-Vref" is applied between the gate G and source S of transistor 12UU. This causes transistor 12UU to transition from the OFF state to the ON state, so the drain-source voltage VDS_uu of transistor 12UU decreases, and a drain current ID (i.e., short-circuit current) flows through transistor 12UU.

[0077] When the rate of change of the drain current ID, di / dt, reaches its peak at time t2 (step ST5: YES), the drain-source voltage VDS_uu of transistor 12UU is detected (step ST6). At time t2, the drain-source voltage VDS_uu of transistor 12UU is lower than the potential of the source S of transistor 12UU (i.e., Ed / 2) by a voltage ΔVDS_uu due to the steep rise of the drain current ID (i.e., the rate of change of the drain current ID, di / dt) caused by the transition of transistor 12UU from the off state to the on state, and the wiring inductance L (see Figure 2). The voltage ΔVDS_uu of transistor 12UU corresponds to the amount of change ΔVDS in equation (4) above. The detection unit 111a (see Figure 2) of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU detects the voltage value Vdt of the drain-source voltage VDS_uu.

[0078] The rate of change of the drain current ID flowing through transistor 12UU increases as the amount of fluctuation from the initial value of the threshold voltage of transistor 12UU decreases (see Figure 3). When transistor 12UU is in a normal state, the amount of fluctuation from the initial value of the threshold voltage of transistor 12UU is small, so the rate of change of the drain current ID increases. That is, when transistor 12UU is in a normal state, the amount of fluctuation of the threshold voltage of transistor 12UU is within the acceptable range and becomes smaller than the lifetime threshold voltage Vth_lt. As a result, as shown in Figure 6, the voltage value Vdt of the drain-source voltage VDS_uu detected by the detection unit 111a becomes lower than the degradation judgment voltage Vo (step ST8: YES). The degradation judgment voltage Vo is set based on the potential of the negative side of the DC power supply 2 (e.g., 0V) for transistors 12UU, 12VU, and 12WU that constitute the upper arm.

[0079] The determination unit 111b (see Figure 2) of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU determines that the transistor 12UU is in a normal state because the voltage value Vdt of the drain-source voltage VDS_uu detected by the detection unit 111a is lower than the degradation determination voltage Vo. As a result, the determination unit 111b outputs a determination result signal Soc_uu, which contains information that the transistor 12UU is in a normal state, to the control device 12 (step ST9).

[0080] As shown in Figure 6, the drain-source voltage VDS_uu of transistor 12UU converges to approximately the same potential as the source S of transistor 12UU (i.e., the potential of the connection between transistor 12UU and transistor 12UL) by time t3 when transistor 12UU transitions to the off state.

[0081] Transistor 12UU experiences losses due to the drain current ID flowing through it. These losses cause the temperature to rise and the on-resistance to increase. Therefore, the drain current ID flowing through transistor 12UU rises between time t2 and time t3, and then decreases due to the increase in on-resistance.

[0082] At time t3, when the characteristic evaluation of the target transistor, transistor 12UU, is completed, a gate-source voltage VGS_uu with the voltage value "-V115-Vref" is applied between the gate G and source S of transistor 12UU, and transistor 12UU is set to the off state. As a result, the drain-source voltage VDS_uu of transistor 12UU converges to approximately half the voltage value Ed of the output voltage output from DC power supply 2, and the potential of the drain D of transistor 12UU becomes approximately the same as the positive terminal potential of DC power supply 2. Consequently, no drain current ID flows through transistors 12UU and 12UL.

[0083] Next, regarding the transistor characteristic determination method according to this embodiment, we will describe the case where the target transistor is a transistor 12UU that constitutes the upper arm of the inverter unit 10, and the transistor 12UU is in a degraded state.

[0084] As shown in Figure 7, when the target transistor is transistor 12UU and transistor 12UU is in a degraded state, the operation of transistor 12UU itself is the same as in the normal state, except that the voltage value Vdt of the drain-source voltage VDS_uu detected by the detection unit 111a is different.

[0085] When transistor 12UU degrades and the fluctuation in the threshold voltage falls outside the acceptable range and becomes greater than the lifetime threshold voltage Vth_lt, the voltage ΔVDS_uu of transistor 12UU at time t2 becomes smaller than the voltage ΔVDS_uu of transistor 12UU in its normal state. As a result, the voltage value Vdt of the drain-source voltage VDS_uu becomes higher than the degradation detection voltage Vo. Consequently, as shown in Figure 7, the voltage value Vdt of the drain-source voltage VDS_uu detected by the detection unit 111a of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU becomes higher than the degradation detection voltage Vo (Step ST8: NO).

[0086] The determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UU determines that transistor 12UU is in a degraded state because the voltage value Vdt of the drain-source voltage VDS_uu detected by the detection unit 111a is higher than the degradation determination voltage Vo. As a result, the determination unit 111b outputs a determination result signal Soc_uu, which contains information indicating that transistor 12UU is in a degraded state, to the control device 12 (step ST10).

[0087] Next, regarding the transistor characteristic determination method according to this embodiment, we will describe the case where the target transistor is transistor 12UL which constitutes the lower arm of the inverter unit 10, and transistor 12UL is in a normal state.

[0088] As shown in Figure 8, after all transistors 12UU~12WL are set to the OFF state (step ST1), transistor 12UU, which is the asymmetrical transistor among transistors 12UU and 12UL, is set to the ON state (step ST3). As a result, a gate-source voltage VGS_uu with the voltage value "V114-Vref" is applied between the gate G and source S of transistor 12UU. This causes transistor 12UU to transition from the OFF state to the ON state.

[0089] On the other hand, since transistor 12UL is set to the off state, a gate-source voltage VGS_ul with the voltage value "-V115-Vref" is applied between the gate G and source S of transistor 12UL. Therefore, the drain-source voltage VDS_ul of transistor 12UL is half the voltage value Ed of the output voltage output from DC power supply 2. In this case, the potential of the drain D of transistor 12UL is approximately the same as half the potential of the positive side of DC power supply 2, and the potential of the source S of transistor 12UL is approximately the same as the potential of the negative side of DC power supply 2. Also, although transistor 12UU is in the on state, since transistor 12UL is in the off state, no drain current ID flows through transistors 12UU and 12UL.

[0090] At time t1, transistor 12UL, the target transistor among transistors 12UU and 12UL, is set to the ON state (step ST4). As a result, a gate-source voltage VGS_ul with the voltage value "V114-Vref" is applied between the gate G and source S of transistor 12UL. This causes transistor 12UL to transition from the OFF state to the ON state, so the drain-source voltage VDS_ul of transistor 12UL decreases and a drain current ID (i.e., short-circuit current) flows through transistor 12UL.

[0091] When the rate of change of the drain current ID, di / dt, reaches its peak at time t2 (step ST5: YES), the drain-source voltage VDS_ul of transistor 12UL is detected (step ST6). At time t2, the drain-source voltage VDS_ul of transistor 12UL is lower than the potential of the source S of transistor 12UL (the negative terminal potential of the DC power supply 2 (e.g., 0V)) by a voltage ΔVDS_ul due to the steep rise of the drain current ID (i.e., the rate of change of the drain current ID, di / dt) caused by the transition of transistor 12UL from the off state to the on state, and the wiring inductance L (see Figure 2). The voltage ΔVDS_ul of transistor 12UL corresponds to the amount of change ΔVDS in equation (4) above. The detection unit 111a (see Figure 2) of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL detects the voltage value Vdt of the drain-source voltage VDS_ul.

[0092] The rate of change of the drain current ID flowing through transistor 12UL is larger when the fluctuation of the threshold voltage of transistor 12UL from its initial value is small, similar to transistor 12UU (see Figure 3). When transistor 12UL is in a normal state, the fluctuation of the threshold voltage of transistor 12UL from its initial value is small, so the rate of change of the drain current ID is large. That is, when transistor 12UL is in a normal state, the fluctuation of the threshold voltage of transistor 12UL is within the acceptable range and is smaller than the lifetime threshold voltage Vth_lt. As a result, as shown in Figure 8, the voltage value Vdt of the drain-source voltage VDS_ul detected by the detection unit 111a is lower than the degradation determination voltage Vo (step ST8: YES). The degradation determination voltage Vo is set based on a negative potential (e.g., -Ed / 2) lower than the potential on the negative side of the DC power supply 2 for transistors 12UL, 12VL, and 12WL that constitute the lower arm.

[0093] The determination unit 111b (see Figure 2) of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL determines that transistor 12UL is in a normal state because the voltage value Vdt of the drain-source voltage VDS_ul detected by the detection unit 111a is lower than the degradation determination voltage Vo. As a result, the determination unit 111b outputs a determination result signal Soc_ul, which contains information that transistor 12UL is in a normal state, to the control device 12 (step ST9).

[0094] As shown in Figure 8, the drain-source voltage VDS_ul of transistor 12UL converges to approximately the same potential as the source S of transistor 12UL (i.e., the negative terminal potential of DC power supply 2) by time t3 when transistor 12UL transitions to the off state.

[0095] Similar to transistor 12UU, transistor 12UL experiences losses due to the drain current ID flowing through it. These losses cause a temperature increase and an increase in on-resistance. Therefore, the drain current ID flowing through transistor 12UL rises between time t2 and time t3, and then decreases due to the increase in on-resistance.

[0096] At time t3, when the characteristic evaluation of the target transistor, transistor 12UL, is completed, a gate-source voltage VGS_ul with the voltage value "-V115-Vref" is applied between the gate G and source S of transistor 12UL, and transistor 12UL is set to the off state. As a result, the drain-source voltage VDS_ul of transistor 12UL converges to approximately the same voltage as half the voltage value Ed of the output voltage output from DC power supply 2, and the potential of the drain D of transistor 12UL becomes approximately the same potential as half the voltage value Ed of the output voltage output of DC power supply 2. As a result, no drain current ID flows through transistors 12UU and 12UL.

[0097] Next, regarding the transistor characteristic determination method according to this embodiment, we will describe the case where the target transistor is transistor 12UL which constitutes the lower arm of the inverter unit 10, and transistor 12UL is in a degraded state.

[0098] As shown in Figure 9, when the target transistor is transistor 12UL and transistor 12UL is in a degraded state, the operation of transistor 12UL itself is the same as in the normal state, except that the voltage value Vdt of the drain-source voltage VDS_ul detected by the detection unit 111a is different.

[0099] When transistor 12UL degrades and the fluctuation in the threshold voltage falls outside the acceptable range and becomes greater than the lifetime threshold voltage Vth_lt, the voltage ΔVDS_ul of transistor 12UL at time t2 becomes smaller than the voltage ΔVDS_ul of transistor 12UL in its normal state. As a result, the voltage value Vdt of the drain-source voltage VDS_ul becomes higher than the degradation detection voltage Vo. Consequently, as shown in Figure 9, the voltage value Vdt of the drain-source voltage VDS_ul detected by the detection unit 111a of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL becomes higher than the degradation detection voltage Vo (Step ST8: NO).

[0100] The determination unit 111b of the transistor characteristic determination circuit 111 provided in the gate drive circuit 11UL determines that transistor 12UL is in a degraded state because the voltage value Vdt of the drain-source voltage VDS_ul detected by the detection unit 111a is higher than the degradation determination voltage Vo. As a result, the determination unit 111b outputs a determination result signal Soc_ul, which contains information that transistor 12UL is in a degraded state, to the control device 12 (step ST10).

[0101] In the transistor characteristic determination method according to this embodiment, it is preferable that the time for setting both transistor 12UU and transistor 12UL, which are included in the transistor group 12UG, to the ON state is within the short-circuit withstand time of transistors 12UU and 12UL, and is the minimum time necessary to detect the drain-source voltage.

[0102] Thus, the transistor characteristic determination method according to this embodiment can determine the characteristics of transistors 12UU to 12WL (in this embodiment, the variation from the initial value of the threshold voltage) without detecting the drain current ID flowing through transistors 12UU to 12WL. For this reason, the transistor characteristic determination method according to this embodiment does not require a current sensor and a current detection unit. As a result, the transistor characteristic determination method according to this embodiment can suppress the increase in circuit size.

[0103] As described above, the transistor characteristic determination circuit 111 according to this embodiment includes a detection unit 111a that detects the drain-source voltage of a target transistor that is the subject of characteristic determination, which is one of a plurality of transistors 12UU, 12UL, 12VU, 12VL, and 12WU, 12WL that are connected in series between the positive-side power supply line LP and the negative-side power supply line LN and set to be turned on simultaneously, and a determination unit 111b that determines the characteristics of the target transistor based on the detected voltage, which is the drain-source voltage detected by the detection unit 111a.

[0104] Furthermore, the power conversion device 1 according to this embodiment includes a transistor characteristic determination circuit 111 according to this embodiment and a plurality of transistors 12UU to 12WL.

[0105] Furthermore, the transistor characteristic determination method according to this embodiment involves simultaneously setting multiple transistors 12UU, 12UL, 12VU, 12VL, or 12WU, 12WL connected in series between the positive power supply line LP and the negative power supply line LN to the ON state (steps ST3, ST4), detecting the drain-source voltage of the target transistor to be characteristic determined from among the multiple transistors 12UU, 12UL, 12VU, 12VL, or 12WU, 12WL (step ST6), and determining the characteristics of the target transistor based on the detected drain-source voltage (steps ST7, ST8).

[0106] With this configuration, the transistor characteristic determination circuit 111, power converter 1, and transistor characteristic determination method according to this embodiment can suppress an increase in circuit size.

[0107] The present invention is not limited to the embodiments described above and can be modified in various ways. The power converter 1 according to the above embodiment includes an inverter section 10 having two transistors 12UU, 12UL, etc., connected in series between the positive-side power supply line LP and the negative-side power supply line LN, but the present invention is not limited thereto. For example, the power converter may include a 3-level inverter having four SiCMOSFETs connected in series between the positive-side power supply line and the negative-side power supply line, and a transistor characteristic determination circuit provided corresponding to each of the four SiCMOSFET transistors. In this case as well, one of the four SiCMOSFETs can be designated as the target transistor, and the remaining three SiCMOSFETs can be designated as non-target transistors, and the characteristics of each of the four transistors can be determined in the same manner as the transistor characteristic determination method according to the above embodiment.

[0108] In the transistor determination method according to the above embodiment, the fluctuation of the threshold voltage is determined as a characteristic of the target transistor, but the present invention is not limited thereto. For example, the fluctuation of the current change rate of the drain current may be determined according to the difference between the amount of decrease in the drain-source voltage and the degradation determination voltage.

[0109] In the transistor determination method according to the above embodiment, the threshold voltage fluctuation is determined as a characteristic of the target transistor based on the difference between the amount of decrease in the drain-source voltage when it is determined that the rate of change of the drain current has reached its peak, and the degradation determination voltage. However, the present invention is not limited to this. For example, the threshold voltage fluctuation may be determined as a characteristic of the target transistor based on the correlation between the amount of threshold voltage fluctuation of the SiCMOSFET and the amount of decrease in the drain-source voltage of the SiCMOSFET, as shown in Figure 4. More specifically, step ST5 shown in Figure 5 may be replaced with a determination of whether the drain-source voltage is at its peak value, and in steps ST7 and ST8, which are processed after it is determined to be at its peak value (step ST5: YES), the "detected drain-source voltage" shown in Figure 5 may be replaced with the "peak value of the drain-source voltage". In this case, the processing of step ST6 shown in Figure 5 may be omitted.

[0110] The technical scope of the present invention is not limited to the illustrative and described embodiments, but also includes all embodiments that produce effects equivalent to those aimed at by the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of features of the invention defined by the claims, but can be defined by any desired combination of specific features from all disclosed features. [Explanation of symbols]

[0111] 1. Power converter 2 DC power supply 3 motors 10 Inverter section 11UL, 11UU, 11VL, 11VU, 11WL, 11WU Gate Drive Circuit 12 Control device 12UG, 12VG, 12WG transistor group 12UL, 12UU, 12VL, 12VU, 12WL, 12WU Transistors 111 Transistor Characteristic Determination Circuit 111a Detection unit 111b Judgment section L Wiring Inductance LN Negative side power line LP positive terminal power line Sdc_ul, Sdc_uu, Sdc_vl, Sdc_vu, Sdc_wl, Sdc_wu detection command signals Soc_ul,Soc_uu,Soc_vl,Soc_vu,Soc_wl,Soc_wu Judgment result signal Vo degradation detection voltage Vth_lt Lifetime threshold voltage

Claims

1. Multiple silicon carbide metal oxide film semiconductor field-effect transistors connected in series between the positive and negative power lines are simultaneously turned ON. The drain-source voltage of the target transistor, which is the subject of characteristic evaluation, among the plurality of silicon carbide metal oxide film semiconductor field-effect transistors, is detected. The characteristics of the target transistor are determined based on the detected drain-source voltage, which is the detected voltage. Transistor characteristic determination method.

2. The threshold voltage fluctuation is determined as a characteristic of the target transistor. The transistor characteristic determination method according to claim 1.

3. The threshold voltage fluctuation of the target transistor is determined based on the relationship between the drain-source voltage and the threshold voltage, and the difference between the detection voltage and the determination voltage, which is set based on the relationship between the drain-source voltage and the threshold voltage. The transistor characteristic determination method according to claim 2.

4. If the detection voltage is lower than the determination voltage, the fluctuation of the threshold voltage is within an acceptable range and the target transistor is determined to be in a normal state. If the detection voltage is higher than the determination voltage, the fluctuation of the threshold voltage is outside the acceptable range and the target transistor is determined to be in a degraded state. The transistor characteristic determination method according to claim 3.

5. After setting the non-asymmetric transistors among the plurality of silicon carbide metal oxide film semiconductor field-effect transistors, excluding the target transistor, to the ON state, the target transistor is then set to the ON state. A method for determining transistor characteristics according to any one of claims 1 to 4.

6. During the turn-on period of the target transistor, the drain-source voltage is detected at the point when the rate of change of the short-circuit current flowing through the plurality of silicon carbide metal oxide film semiconductor field-effect transistors reaches its peak. The transistor characteristic determination method according to claim 5.

7. When a plurality of transistor groups, each having a plurality of silicon carbide metal oxide film semiconductor field-effect transistors, are connected in parallel between the positive-side power supply line and the negative-side power supply line, the plurality of silicon carbide metal oxide film semiconductor field-effect transistors in the transistor group that does not include the target transistor are set to the off state before the non-target transistor is set to the on state, and remain in the off state even after the non-target transistor is set to the on state. The transistor characteristic determination method according to claim 5.

8. When a plurality of transistor groups, each having a plurality of silicon carbide metal oxide film semiconductor field-effect transistors, are connected in parallel between the positive-side power supply line and the negative-side power supply line, the plurality of silicon carbide metal oxide film semiconductor field-effect transistors in the transistor group that does not include the target transistor are set to the off state before the non-target transistor is set to the on state, and remain in the off state even after the non-target transistor is set to the on state. The transistor characteristic determination method according to claim 6.

9. A detection unit for detecting the drain-source voltage of a target transistor, which is the subject of characteristic evaluation, among a plurality of silicon carbide metal oxide film semiconductor field-effect transistors connected in series between the positive and negative power supply lines and set to be turned on simultaneously. A determination unit that determines the characteristics of the target transistor based on the detected voltage, which is the drain-source voltage detected by the detection unit. A transistor characteristic determination circuit equipped with the following features.

10. The transistor characteristic determination circuit according to claim 9, The plurality of silicon carbide metal oxide film semiconductor field-effect transistors and A power conversion device equipped with the following features.

11. The system comprises a group of transistors connected in parallel between the positive electrode power supply line and the negative electrode power supply line, each having a plurality of silicon carbide metal oxide film semiconductor field-effect transistors. The power conversion device according to claim 10.

Images