Semiconductor components and methods for manufacturing the same

Abstract

The present invention provides a semiconductor component that is less susceptible to thermal loss of electric current and a method for manufacturing the same. [Solution] The shielding gas introduction step involves vacuuming the cavity, then introducing a shielding gas to heat the stage to between 250°C and 480°C. The reaction gas introduction step involves stopping the introduction of the shielding gas and introducing a reaction gas to maintain the stage temperature between 250°C and 480°C, the reaction gas containing hydrogen and benzene vapor. The deposition step involves reintroducing the shielding gas and activating the plasma, maintaining the stage temperature between 250°C and 480°C to decompose the benzene vapor and form a graphene layer on the circuit pattern layer, with a graphene layer thickness of 0.3 nanometers to 4.5 nanometers.

Description

Technical Field

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[0005]

[0001] The present invention belongs to the field of semiconductors, and particularly relates to semiconductor components and a method for manufacturing the same.

Background Art

[0002] As the line width of semiconductor components gradually becomes narrower, the resistance of the wiring (pattern) formed of copper also significantly increases, and heat loss of current is likely to occur. Further, as a result, heat tends to accumulate in the semiconductor components, and the lifespan tends to be shortened. In addition, due to the recent rise of artificial intelligence (AI), the influence of the increase in the amount of heat generated by resistance has been attracting more and more attention.

[0003] Current measures for improving such a situation include plating a highly conductive material on the circuit pattern layer, for example, coating graphene on a pattern formed of copper.

Summary of the Invention

[0007] In the above embodiment, the material of the circuit pattern layer may be selected from the group consisting of copper, nickel, aluminum, and alloys thereof.

[0008] Furthermore, in the above embodiment, the line width of the circuit pattern layer may be less than 60 nanometers.

[0009] Furthermore, in the above embodiment, the thickness of the graphene layer may be 0.3 nanometers to 3 nanometers.

[0010] Furthermore, in the above embodiment, the temperature of the stage may be maintained at 300°C to 400°C during the shielding gas introduction step, the reaction gas introduction step, and the deposition step.

[0011] Furthermore, in the above embodiment, the flow rate at which the shielding gas is introduced in the deposition step is 10 sccm to 75 sccm, and the flow rate at which the reaction gas is introduced may be less than 15 sccm.

[0012] Furthermore, in another aspect of the present invention, a semiconductor component comprising a semiconductor substrate, a circuit pattern layer, and a graphene layer, The circuit pattern layer is located on the semiconductor substrate, and the line width of the circuit pattern layer is less than 100 nanometers. A semiconductor component wherein the graphene layer is located on the surface of the circuit pattern layer, and the thickness of the graphene layer is 0.3 nanometers to 4.5 nanometers.

[0013] In the above embodiment, the material of the circuit pattern layer may be selected from the group consisting of copper, nickel, aluminum, and alloys thereof.

[0014] Furthermore, in the above embodiment, the line width of the circuit pattern layer may be less than 60 nanometers.

[0015] Furthermore, in the above embodiment, the thickness of the graphene layer may be 0.3 nanometers to 3 nanometers. [Effects of the Invention]

[0016] As described above, according to the present invention, since graphene is formed only on the surface of the metal, by using benzene vapor as a carbon source at low temperatures and utilizing plasma decomposition to deposit single or multilayer graphene on the surface of the circuit pattern layer, the resistance of the circuit can be significantly reduced. [Brief explanation of the drawing]

[0017] [Figure 1] This is a flowchart showing the manufacturing process for semiconductor components. [Figure 2] This is a functional block diagram of semiconductor component manufacturing equipment. [Figure 3] This is a partial top view of a semiconductor sample. [Figure 4] It is a partial cross-sectional view of a semiconductor sample. [Figure 5] It is a photograph taken by a scanning electron microscope showing an embodiment of a semiconductor component. [Figure 6] It is a photograph taken by a scanning electron microscope showing another embodiment of a semiconductor component.

Embodiments for Carrying Out the Invention

[0018] In the following description, expressions such as "first", "second", and "third" are used only to distinguish one element, component, region, layer, or part from other elements, components, regions, layers, or parts, and do not imply any sequence or order.

[0019] Furthermore, in this specification, relative expressions such as "lower" and "upper", "inner" and "outer" may be used, but they are used to describe the relationship between one element and another element. It should be understood that relative terms are intended to encompass various directions of the device in addition to the directions shown in the figures. That is, for example, if the device is turned over so that up and down are reversed, what is described as the lower side in this application will naturally be located on the upper side, but even in such a case, it is included in the technical scope, and terms such as "upper" are used to describe relative positional relationships and do not indicate absolute positional relationships.

[0020] Also, in the drawings, the widths of some components, regions, etc. may be exaggerated for clarity, but throughout the specification, the same reference numerals denote the same components.

[0021] For example, when an element is expressed as being "above" or "connected to" another element, that element may be directly "above" or connected to the other element, or may be "above" or connected in a state where intervening elements exist. In contrast, when a restrictive expression such as "directly above" or "directly connected to" is used for an element with respect to another element, there are no intervening elements.

[0022] Embodiments of the present invention will be described below with reference to Figures 1 to 3. Figure 1 is a flowchart of the semiconductor component manufacturing method. Figure 2 is a functional block diagram of the semiconductor component manufacturing apparatus. Figure 3 is a partial top view of a semiconductor sample. As shown in Figure 1, the semiconductor component manufacturing method S1 includes a preparation step S10, a shielding gas introduction step S20, a reaction gas introduction step 30, and a deposition step S40.

[0023] As shown in Figure 2, the semiconductor component manufacturing apparatus 200 includes a cavity 510, a shielding gas tank 520, a hydrogen tank 530, a benzene barrel 540, and a controller 550.

[0024] The cavity 510 includes a stage 511, a heating device 513, and a vacuum device 515. The benzene barrel 540 is further equipped with a heater 545 to heat liquid benzene into benzene vapor.

[0025] The first access port 517A, the second access port 517B, and the third access port 517C of the cavity 510 are connected to the shielded gas tank 520, the hydrogen tank 530, and the benzene barrel 540, respectively, and the amount of gas introduced is controlled by the control valve 560.

[0026] The explanation will be given with simultaneous reference to Figures 1 to 3. Preparation step S10 in Figure 1 involves preparing the semiconductor sample 600 and placing it on the stage 511 of the cavity 510 in Figure 2. The semiconductor sample 600 includes a semiconductor substrate 110 and a circuit pattern layer 120, as shown in Figure 3. The circuit pattern layer 120 is provided on the semiconductor substrate 110, and the line width of the circuit pattern layer 120 is less than 100 nanometers. Here, the semiconductor sample 600 is a semi-finished product of the semiconductor component 100.

[0027] In the shielding gas introduction step S20 shown in Figure 1, the vacuum device 515 sucks out air to create a vacuum in the cavity 510, and then the controller 550 controls the shielding gas tank 520 to introduce the shielding gas. The shielding gas can be argon or helium. The heating device 513 is controlled by the controller 550 so that the stage 511 is heated between 250°C and 480°C, preferably between 300°C and 400°C, for example between 350°C and 380°C.

[0028] The reaction gas introduction step S30 stops the introduction of the shielding gas and controls the introduction of hydrogen and benzene vapor from the hydrogen tank 530 and benzene barrel 540 as reaction gases to maintain the temperature of the stage 511 between 250°C and 480°C.

[0029] In deposition step S40, the shielding gas is reintroduced and the plasma is activated. The plasma frequency and energy are approximately 10MHz to 20MHz, and the output power is 250W to 400W.

[0030] The temperature of stage 511 is maintained at 250°C to 480°C, and benzene vapor is decomposed through the plasma and heat source, forming a graphene layer 130 (see Figure 4 below) on the circuit pattern layer 120. The thickness of the graphene layer 130 is 0.3 nanometers to 4.5 nanometers.

[0031] After cooling and removing the reaction gas and shielding gas, the completed semiconductor component 100 can be removed. In the deposition step S40, the flow rate of the shielding gas is 10 sccm (Standard Cubic Centimeter per Minute, sccm) to 75 sccm, and the flow rate of the reaction gas is less than 15 sccm. The ratio between them is approximately 5:1.

[0032] Next, we will explain with reference to Figure 4. Figure 4 is a partial cross-sectional view of a semiconductor sample. As shown in Figure 4, the semiconductor component 100 is manufactured by the above manufacturing method and comprises a semiconductor substrate 110, a circuit pattern layer 120, and a graphene layer 130.

[0033] The circuit pattern layer 120 is located on the semiconductor substrate 110, and the line width of the circuit pattern layer 120 is less than 100 nanometers (narrow).

[0034] The graphene layer 130 is located on the surface of the circuit pattern layer 120, and its thickness ranges from 0.3 nanometers to 4.5 nanometers. Here, the graphene layer 130 can be controlled to be a single layer or a multilayer, with a thickness of approximately 0.3 nanometers to 3 nanometers.

[0035] More specifically, the material of the circuit pattern layer 120 is selected from the group consisting of copper, nickel, aluminum, and alloys thereof, and is preferably copper or a copper-nickel alloy. In some embodiments, the line width of the circuit pattern layer 120 is less than 60 nanometers, for example, 45 nanometers.

[0036] However, this is merely one example and is not limited to the numerical values ​​exemplified in the embodiment. In reality, this is merely a result created using laboratory equipment and was successfully verified; it is believed that the line width can be made even thinner when using more advanced equipment.

[0037] The following explanation will use actual experiments. The main manufacturing apparatus 200 used here is the MKST11-301. The MKST11-301 is equipped with a tubular high-temperature furnace as the cavity 510, and is also equipped with a gas flow meter. The vacuum apparatus 515 is equipped with a ULVAC GLD-N280 vacuum pump and a TTR91 Pfeiffer GmbH vacuum measurement system.

[0038] The AK3540S 2P 4T 4T is equipped with control valve 560 and pressure gauge, and the controller 550 is a WEINTEK MT8102iE PLC human-machine interface controller. A Seren USA SU-R301 RF plasma source is also used.

[0039] After manufacturing is complete, a Labram HR manufactured by Horiba Jobin Yvon will be used as a micro-Raman analyzer to confirm that the deposit is graphene. It will also be used for structural analysis in combination with a general scanning electron microscope (SEM).

[0040] First, a semiconductor sample 600 having a thin-film circuit pattern layer 120 on a semiconductor substrate 110 is placed on the stage 511 of the cavity 510. Here, the semiconductor substrate 110 is a silicon substrate with a silicon dioxide layer deposited on its surface.

[0041] The minimum line width of the circuit pattern layer 120 is 45 nanometers. Next, process parameters are set using the PLC human-machine interface controller. First, the cavity environment is evacuated to 0.9 to 10 to 10 to 10. Simultaneously, the heater 545 is started to heat the benzene barrel 540, converting the benzene from liquid to gaseous benzene vapor, with a heating temperature of approximately 78°C to 80°C.

[0042] After the desired vacuum state is reached, the shielding gas introduction step S20 is performed, and with the stage 511 heated to 350°C to 480°C, argon gas is introduced as the shielding gas at a flow rate of 200 sccm for 1800 seconds.

[0043] Next, in reaction gas introduction step S30, the introduction of the shielding gas is stopped, hydrogen is introduced at a flow rate of 150 sccm, and benzene vapor is introduced as the reaction gas and maintained for 3600 seconds.

[0044] Next, argon gas is reintroduced, the hydrogen gas flow rate is reduced, and a voltage is applied to activate the plasma for approximately 10 to 30 seconds. The plasma energy, along with the thermal energy on stage 511 and semiconductor sample 600, decomposes the benzene vapor, which is then deposited only on the surface of the circuit pattern layer 120 according to the properties of the graphene.

[0045] In deposition step S40, the flow rate of argon gas is 10 sccm to 75 sccm, and the flow rate of hydrogen gas is 0 sccm to 15 sccm.

[0046] Finally, the introduction of reaction gas is stopped, and the shielding gas is maintained while the stage 511 is left as is for approximately 1160 seconds until it reaches room temperature. Finally, residual gas is discharged, the vacuum is released, and the manufacturing of semiconductor component 100 is completed.

[0047] Then, the peak deposited on the surface of the circuit pattern layer 120 is detected by Raman spectroscopy to determine whether it corresponds to graphene. Here, the thickness of the graphene layer 130 can be adjusted by controlling the time of the deposition step S40.

[0048] Embodiments of the present invention will be described with reference to Figures 5 and 6. Here, Figure 5 is a scanning electron microscope image showing an embodiment of a semiconductor component. Figure 6 is a scanning electron microscope image showing another embodiment of the semiconductor component. When the plasma is activated for 10 seconds, a single layer of graphene (Gr) with a thickness of approximately 0.3 nanometers is formed on the 45 nanometer circuit pattern layer 120, as shown in Figure 5.

[0049] In Figure 6, the deposition step S40 is extended to 30 seconds to form a multilayer graphene with a thickness of approximately 2 to 3 nanometers. Note that the top layer of graphene is a shielding layer for preparing the sample for scanning electron microscopy and is not part of the semiconductor component 100.

[0050] As described above, by utilizing the characteristic that graphene is formed only on the surface of metal, and by using benzene vapor as a carbon source at low temperatures, single-layer or multi-layer graphene can be deposited on the surface of the circuit pattern layer 120 by plasma decomposition, the resistance of the circuit can be significantly reduced, and the impedance loss of high-frequency components operating at high speeds can be reduced.

[0051] The technical content of the present invention is described by the preferred embodiments described above, but these do not limit the technical scope of the present invention. Therefore, changes and modifications made by those skilled in the art without departing from the spirit of the present invention are included within the technical scope of the present invention. Furthermore, the technical scope of the present invention is defined based on the claims. [Explanation of symbols]

[0052] 100 semiconductor components 110 Semiconductor substrates 120 circuit pattern layers 130 Graphene layer 200 Manufacturing equipment 510 Cavity 511 Stages 513 Heating device 515 Vacuum equipment 517A First access port 517B Second access port 517C Third access port 520 Shielded gas tank 530 hydrogen tanks 540 benzene barrels 545 Heater 550 Controller 560 Control valve 600 semiconductor samples S1 Semiconductor component manufacturing method S10 Preparation Steps S20 Shielding gas introduction step S30 Reaction gas introduction step S40 Sedimentary Step

Claims

1. A method for manufacturing a semiconductor component, comprising a preparation step, a shielding gas introduction step, a reaction gas introduction step, and a deposition step, The preparation step involves preparing a semiconductor sample and placing it on a cavity stage, wherein the semiconductor sample includes a semiconductor substrate and a circuit pattern layer, the circuit pattern layer is located on the semiconductor substrate, and the line width of the circuit pattern is less than 100 nanometers. The shielding gas introduction step involves vacuuming the cavity, then introducing shielding gas to heat the stage to a temperature between 250°C and 480°C. The reaction gas introduction step involves stopping the introduction of the shielding gas and introducing the reaction gas, maintaining the temperature of the stage between 250°C and 480°C, and the reaction gas comprises hydrogen and benzene vapor. A method for manufacturing a semiconductor component, characterized in that the deposition step involves reintroducing the shielding gas and initiating a plasma, maintaining the temperature of the stage between 250°C and 480°C to decompose the benzene vapor and form a graphene layer on the circuit pattern layer, wherein the thickness of the graphene layer is between 0.3 nanometers and 4.5 nanometers.

2. The method for manufacturing a semiconductor component according to claim 1, characterized in that the material of the circuit pattern layer is selected from the group consisting of copper, nickel, aluminum, and alloys thereof.

3. The method for manufacturing a semiconductor component according to claim 1, characterized in that the line width of the circuit pattern layer is less than 60 nanometers.

4. The method for manufacturing a semiconductor component according to claim 1, characterized in that the thickness of the graphene layer is 0.3 nanometers to 3 nanometers.

5. The method for manufacturing a semiconductor component according to claim 1, characterized in that, in the shielding gas introduction step, the reaction gas introduction step, and the deposition step, the temperature of the stage is maintained at 300°C to 400°C.

6. The method for manufacturing a semiconductor component according to claim 1, characterized in that, in the deposition step, the flow rate at which the shielding gas is introduced is 10 sccm to 75 sccm, and the flow rate at which the reaction gas is introduced is less than 15 sccm.

7. A semiconductor component comprising a semiconductor substrate, a circuit pattern layer, and a graphene layer, The circuit pattern layer is located on the semiconductor substrate, and the line width of the circuit pattern layer is less than 100 nanometers. The semiconductor component is characterized in that the graphene layer is located on the surface of the circuit pattern layer, and the thickness of the graphene layer is 0.3 nanometers to 4.5 nanometers.

8. The semiconductor component according to claim 7, characterized in that the material of the circuit pattern layer is selected from the group consisting of copper, nickel, aluminum, and alloys thereof.

9. The semiconductor component according to claim 7, characterized in that the line width of the circuit pattern layer is less than 60 nanometers.

10. The semiconductor component according to claim 7, characterized in that the thickness of the graphene layer is 0.3 nanometers to 3 nanometers.

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