Register set control system, register set control method, program, and logic circuit

Abstract

This provides new technology to address processor anomalies. [Solution] The register set control system of this disclosure determines whether each of the multiple register sets included in the processor is normal or not, and updates status information indicating whether each register set is normal or not based on the result of the determination. The register set control system also selects the register set to be used for interrupt processing by the processor from among the register sets that are indicated as normal in the status information.

Description

Technical Field

[0001] The present disclosure relates to a register set control system, a register set control method, a program, and a logic circuit.

Background Art

[0002] Techniques for dealing with processor abnormalities have been developed. For example, Patent Document 1 discloses a technique for dealing with CPU abnormalities in a multi-CPU (Central Processing Unit) system that performs a lockstep operation. In this system, when a hardware abnormality occurs in one CPU, the abnormal CPU is stopped and processing is continued only with the normal CPUs.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Document 1 targets a multi-CPU system. Therefore, the technique of Patent Document 1 cannot deal with CPU abnormalities that occur in a single-CPU system.

Means for Solving the Problems

[0005] A register set control system according to an embodiment determines whether each of a plurality of register sets included in a processor is normal, and updates state information based on the determination result. The state information indicates whether each register set is normal. Further, the register set control system selects a register set used for interrupt processing by the processor from among the normal register sets.

Effects of the Invention

[0006] According to the above embodiment, a new technique for dealing with processor abnormalities is provided. [Brief explanation of the drawing]

[0007] [Figure 1] This diagram illustrates the general operation of a register set control system. [Figure 2] This diagram illustrates the selection of a register set by a register set control system. [Figure 3] This is a block diagram illustrating the functional configuration of a register set control system. [Figure 4] This is a block diagram illustrating the hardware configuration of a computer that implements a register set control system. [Figure 5] This diagram illustrates a logic circuit that incorporates a program to implement the selection function. [Figure 6] This flowchart illustrates the process for monitoring the state of a register set. [Figure 7] This flowchart illustrates the process of selecting a register set. [Figure 8] This diagram illustrates state information implemented as a list. [Figure 9] This flowchart provides a more concrete example of the process for selecting a register set. [Modes for carrying out the invention]

[0008] Embodiments of the present disclosure will be described in detail below with reference to the drawings. In each drawing, the same or corresponding elements are denoted by the same reference numerals, and redundant explanations are omitted as necessary for clarity. Unless otherwise specified, predetermined values ​​such as specified values ​​and thresholds are stored in advance in a storage device accessible from the device that uses those values. Furthermore, unless otherwise specified, the storage unit is composed of one or any number of storage devices.

[0009] <Overview> Figure 1 illustrates an overview of the operation of the register set control system 2000. Herein, Figure 1 is intended to facilitate understanding of the register set control system 2000's overview, and its operation is not limited to what is shown in Figure 1.

[0010] The register set control system 2000 handles the processor 30. The processor 30 is a variety of processor, such as an MPU (Microprocessor Unit), a CPU (Central Processing Unit), or an FPGA (Field-Programmable Gate Array).

[0011] The processor 30 has multiple register sets 10. Each register set 10 contains multiple registers used for program execution. Examples of registers included in register set 10 are the program counter, stack pointer, data register, or address register.

[0012] In the processor 30, when an interrupt occurs during application execution, the application and the interrupt handler use different sets of registers 10. Furthermore, even when multiple interrupt handlers are executed, each of the multiple interrupt handlers uses a different set of registers 10.

[0013] In this case, one or more register sets 10 in the processor 30 may enter an abnormal state. If an abnormal register set 10 is used in a process, it may not be possible to perform that process correctly.

[0014] Therefore, the register set control system 2000 monitors the state of each register set 10 so that the register set 10 in an abnormal state is not used. Then, when an interrupt occurs, the register set control system 2000 selects a register set 10 to be used for a new interrupt process (hereinafter, the target interrupt process) from the register sets 10 in a normal state. The processor 30 executes the target interrupt process using the register set 10 selected by the register set control system 2000.

[0015] Specifically, the register set control system 2000 operates as follows. The register set control system 2000 performs a determination (hereinafter, the abnormality determination) as to whether each of the plurality of register sets 10 is abnormal. Then, the register set control system 2000 updates the state information 20 based on the result of the abnormality determination. The state information 20 indicates whether each register set 10 is abnormal. In FIG. 1, a check mark represents normal, and a cross mark represents abnormal.

[0016] When an interrupt occurs, the register set control system 2000 uses the state information 20 to select a register set 10 to be used for an interrupt process (the target interrupt process) for handling the interrupt. Specifically, the register set control system 2000 selects the register set 10 to be used for the target interrupt process from the register sets 10 indicated as normal in the state information 20. Therefore, the register set 10 in an abnormal state is not used for the execution of the target interrupt process.

[0017] FIG. 2 is a diagram illustrating the selection of the register set 10 by the register set control system 2000. Two cases are illustrated in FIG. 2. In either case, the processor 30 has three register sets 10, namely, register set 10-1 to register set 10-3. Also, an application 40 is being executed using the register set 10-1. Further, an interrupt process 50 is executed to process an interrupt that occurred during the execution of the application 40.

[0018] The interrupt process 50 is executed using a register set 10 different from the register set 10 used for the execution of the application 40 (that is, a register set 10 other than the register set 10-1). In the example of FIG. 2, the register set control system 2000 preferentially selects a register set 10 with a smaller identifier.

[0019] In the case of the upper part of FIG. 2, the state information 20 indicates that all the register sets 10 are normal. Therefore, the register set control system 2000 selects the register set 10-2 as the register set 10 to be used for the interrupt process 50.

[0020] On the other hand, in the case of the lower part of FIG. 2, the state information 20 indicates that the register set 10-2 is in an abnormal state. Therefore, the register set control system 2000 selects the register set 10-3 as the register set 10 to be used for the interrupt process 50.

[0021] <Example of effects> According to the register set control system 2000, an abnormality determination is made for each of the plurality of register sets 10 included in the processor 30. And the register set 10 determined to be abnormal is not selected as the register set 10 to be used for the interrupt process 50. Thus, according to the register set control system 2000, a new technique for coping with processor abnormalities is provided.

[0022] Here, the abnormality detection of register set 10 can be performed using the processor 30. For example, as will be described later, by executing an instruction in the processor 30 that changes the value of each register included in register set 10, it is possible to determine whether or not register set 10 is normal. Therefore, the detection of abnormalities in register set 10 can be achieved with a single processor. Furthermore, even if a certain register set 10 becomes abnormal, the processor 30 can continue to be used by having it utilize the other register sets 10.

[0023] Based on the above, the Register Set Control System 2000 provides a technology for dealing with processor abnormalities that can be implemented even with only one processor. In other words, the Register Set Control System 2000 provides a technology for dealing with processor abnormalities that can be applied to single-processor systems.

[0024] Examples of single-processor systems include small microcontrollers installed in vehicles. Many small microcontrollers have limitations in space and cost that make it difficult to incorporate multiple processors. According to the Register Set Control System 2000, even in systems where it is difficult to incorporate multiple processors, it is possible to deal with processor failures.

[0025] Furthermore, the Register Set Control System 2000 does not necessarily have to be provided only for single-processor systems; it can also be applied to multi-processor systems.

[0026] The register set control system 2000 of this embodiment will be described in more detail below.

[0027] <Example of functional configuration> Figure 3 is a block diagram illustrating the functional configuration of the register set control system 2000. The register set control system 2000 includes a determination unit 2020, an update unit 2040, and a selection unit 2060. The determination unit 2020 performs an abnormality determination for each of the multiple register sets 10. The update unit 2040 updates the state information 20 based on the result of the abnormality determination. The selection unit 2060 selects the register set 10 to be used for executing the interrupt processing 50 from among the register sets 10 that are indicated as normal in the state information 20.

[0028] <Example of hardware configuration> Each functional component of the register set control system 2000 may be implemented by hardware (e.g., hardwired electronic circuits) or by a combination of hardware and software (e.g., a combination of electronic circuits and programs that control them). Figure 4 is a block diagram illustrating the hardware configuration of computer 1000 that implements the register set control system 2000. Computer 1000 is any computer. Computer 1000 may be a dedicated computer designed to implement the register set control system 2000, or it may be a general-purpose computer.

[0029] Computer 1000 includes a processor 30, a bus 1020, memory 1060, a storage device 1080, an input / output interface (I / F) 1100, and a network interface 1120. The bus 1020 is a data transmission path for the processor 30, memory 1060, storage device 1080, input / output interface 1100, and network interface 1120 to send and receive data from each other. However, the method of connecting the processor 30 and other components to each other is not limited to bus connection.

[0030] Memory 1060 is a main memory device implemented using RAM (Random Access Memory), etc. Storage device 1080 is an auxiliary storage device implemented using ROM (Read Only Memory), flash memory, or a memory card, etc. Input / Output interface 1100 is an interface for connecting computer 1000 and input / output devices. Network interface 1120 is an interface for connecting computer 1000 to a network.

[0031] The storage device 1080 stores a program that implements some or all of the functional components of the register set control system 2000. The processor 30 reads this program into memory 1060 and executes it to implement each functional component of the register set control system 2000.

[0032] The method for obtaining a program stored on storage device 1080 is arbitrary. For example, the program can be obtained by copying it from the storage medium on which it is stored to storage device 1080. The storage medium on which the program is stored can be any storage medium, such as a DVD (Digital Versatile Disk) or a USB (Universal Serial Bus) memory. Alternatively, for example, the program can be downloaded from a server device that manages the storage device on which it is stored and stored on storage device 1080.

[0033] The register set control system 2000 may have a logic circuit into which a program that implements some or all of the functions of the register set control system 2000 is pre-installed. For example, the program that implements the determination unit 2020 and the update unit 2040 is stored in the storage device 1080, while the program that implements the selection unit 2060 is incorporated into the logic circuit. In this case, monitoring of the state of the register set 10 is performed by executing the program stored in the storage device 1080 on the processor 30. On the other hand, the selection of the register set 10 is performed by the logic circuit described above.

[0034] Figure 5 illustrates a logic circuit incorporating a program that implements the selection unit 2060. In Figure 5, logic circuit 70 is a logic circuit incorporating a program that implements the selection unit 2060. Logic circuit 70 is communicated with the processor 30, the interrupt controller 60, and the memory unit 80.

[0035] The interrupt controller 60 sends an interrupt signal to the processor 30 to inform it of an interrupt from the hardware. The interrupt signal is sent to the logic circuit 70.

[0036] The logic circuit 70, upon receiving an interrupt signal, selects a set of registers 10 to be used for the interrupt processing 50 (target interrupt processing) corresponding to the received interrupt signal. In this example, the state information 20 is stored in the memory unit 80. The memory unit 80 is an arbitrary memory element implemented by RAM or the like. The logic circuit 70 refers to the state information 20 stored in the memory unit 80 and selects a set of registers 10 to be used for the target interrupt processing.

[0037] The logic circuit 70 sends an interrupt signal and a control signal to the processor 30 to make use of the selected register set 1. The processor 30 executes the interrupt process 50 (target interrupt process) corresponding to the received interrupt signal using the register set 10 (register set 10 selected by the register set control system 2000) represented by the received control signal.

[0038] In Figure 5, the logic circuit 70 is shown as being located outside the processor 30. However, the logic circuit 70 may be located inside the processor 30. Similarly, the storage unit 80 may be located inside the processor 30.

[0039] <Processing flow> As mentioned above, the register set control system 2000 monitors the state of the register set 10 and selects the register set 10. Figure 6 is a flowchart illustrating the process flow for monitoring the state of the register set 10. The determination unit 2020 performs an abnormality determination for each of the multiple register sets 10 (S102). The update unit 2040 updates the state information 20 based on the result of the abnormality determination (S104). Hereinafter, the series of processes shown in Figure 6 (i.e., abnormality determination and updating of state information 20) are also called the state monitoring process.

[0040] The status monitoring process is executed repeatedly. For example, the status monitoring process is executed repeatedly at predetermined time intervals. In addition, for example, the status monitoring process is executed when a predetermined time has elapsed since the last execution and the processor 30 is in an idle state.

[0041] Note that the register set 10 for which an abnormality check is performed in a single state monitoring process does not have to be all of the register set 10. For example, the number of register sets 10 for which an abnormality check is performed in a single state monitoring process is M, which is less than the total number of register sets 10 N. In this case, an abnormality check is performed once for each of the [M / N] state monitoring processes. Here, [x] represents the smallest integer greater than or equal to x.

[0042] Figure 7 is a flowchart illustrating the process for selecting a register set 10. The selection unit 2060 detects the occurrence of an interrupt (S202). The occurrence of an interrupt can be detected, for example, by receiving an interrupt signal from the interrupt controller, as described above. The selection unit 2060 selects one of the register sets 10 that are indicated as normal in the status information 20 as the register set 10 to be used for the target interrupt processing (S204).

[0043] <Abnormality judgment: S102> The determination unit 2020 performs an abnormality determination for each of the multiple register sets 10 (S102). The abnormality determination of a register set 10 is a process that determines whether or not each register included in the register set 10 is abnormal.

[0044] For example, the determination unit 2020 determines that a register set 10 is abnormal if at least one of the registers included in the register set 10 is in an abnormal state. On the other hand, the determination unit 2020 determines that a register set 10 is normal if all of the registers included in the register set 10 are not abnormal.

[0045] Here, various existing techniques can be used to determine whether a register is in an abnormal state. For example, whether a certain register is normal can be determined using a pair of "an instruction that changes the value of that register, and the value that should be stored in that register after the instruction is executed" (hereinafter referred to as test data). The determination unit 2020 uses one or more test data to determine whether each register included in the register set 10 is abnormal. The test data is prepared such that the value of each register included in the register set 10 is changed at least once.

[0046] For example, suppose test data D1 is prepared to check for an anomaly in register R1. In this case, test data D1 includes instruction I1 that changes the value of register R1, and the value v1 that should be stored in register R1 after the execution of instruction I1.

[0047] The determination unit 2020 causes the processor 30 to execute instruction I1. Then, the determination unit 2020 determines whether the value stored in register R1 matches the value v1 shown in test data D1. If these values ​​match, the determination unit 2020 determines that register R1 is normal. On the other hand, if these values ​​do not match, the determination unit 2020 determines that register R1 is abnormal.

[0048] Note that for register sets 10 that have already been indicated as abnormal in status information 20 (i.e., register sets 10 that were determined to be abnormal in a previous abnormality determination), the abnormality determination may be omitted. In this case, the determination unit 2020 checks the status of the i-th register set 10 as indicated in status information 20 before determining whether the i-th register set 10 is abnormal or not.

[0049] If the status information 20 indicates that the i-th register set 10 is normal, the determination unit 2020 performs an abnormality determination on the i-th register set 10. On the other hand, if the status information 20 indicates that the i-th register set 10 is abnormal, the determination unit 2020 does not perform an abnormality determination on the i-th register set 10.

[0050] This method reduces the number of times anomaly detection is performed. Therefore, the time required for status monitoring can be reduced. Furthermore, the computing resources used for status monitoring can be reduced.

[0051] <Status information 20 update: S104> The update unit 2040 updates the status information 20 based on the result of the abnormality determination (S104). For example, in the initial state, the status information 20 indicates that all register sets 10 are in a normal state. In this case, the update unit 2040 updates the status information 20 to indicate that the register set 10 determined to be abnormal in the abnormality determination is indeed abnormal.

[0052] Here, the specific structure of the state information 20 is arbitrary. For example, the state information 20 can be implemented as a table that associates the identifier of the register set 10 with the state of the register set 10, as shown in Figures 1 and 2. Alternatively, the state information 20 can be implemented as a list in which the state of each register set 10 is shown in the element corresponding to that register set 10.

[0053] Figure 8 illustrates the state information 20 implemented as a list. In Figure 8, the i-th element of the state information 20 indicates whether the i-th register set 10 is normal or not.

[0054] In the example in Figure 8, each element of the state information 20 represents either 0 or 1. A value of 1 indicates that the register set 10 is normal. On the other hand, a value of 0 indicates that the register set 10 is abnormal. For example, in the initial state, all elements of the state information 20 represent 1. Note that the method for indicating whether the register set 10 is normal or not is arbitrary and is not limited to the method described here.

[0055] The update unit 2040 updates the elements of the state information 20 corresponding to the register set 10 that was determined to be abnormal in the abnormality determination. For example, as mentioned above, suppose that an abnormality in the register set 10 is represented by a value of 0. In this case, the update unit 2040 changes the value of the element of the state information 20 corresponding to each register set 10 that was determined to be abnormal in the abnormality determination to 0.

[0056] For example, suppose that in the abnormality detection process, the first register set 10 and the third register set 10 are both determined to be abnormal. In this case, the update unit 2040 changes the values ​​of the first and third elements of the state information 20 to 0.

[0057] <Application 40 terminated successfully> A lower limit may be set for the number of normal register sets 10 as a condition for the continued use of the processor 30. The lower limit for the number of normal register sets 10 is set to a value of 0 or greater.

[0058] After the status monitoring process, the update unit 2040 determines whether the number of normal register sets 10 is below a lower limit. If the number of normal register sets 10 is below the lower limit, the update unit 2040 terminates the execution of the application 40 running on the processor 30. In this way, the application 40 can be terminated in a normal state. Therefore, it is possible to prevent the execution result of the register sets 10 from becoming an abnormal result.

[0059] <Selection of Register Set 10: S204> The selection unit 2060 selects the register set 10 to be used for executing the target interrupt process (S204). Here, the selection unit 2060 selects the register set 10 to be used for executing the target interrupt process from among the register sets 10 that are indicated as normal in the status information 20.

[0060] For example, the selection unit 2060 prioritizes selecting the register set 10 with a smaller identifier, as illustrated in Figure 2.

[0061] Figure 9 is a flowchart illustrating the process of selecting a register set 10 in more detail. The selection unit 2060 sets the variable x, which represents the identifier of the register set 10, to a value obtained by adding 1 to the largest identifier among the already used identifiers of the register set 10 (S302).

[0062] For example, suppose that application 40 and one interrupt handler 50 are currently running. Also, suppose that the first register set 10 is used for the execution of the application, and the third register set 10 is used for the execution of the interrupt handler 50. In this case, in S302, x will be set to 4.

[0063] Steps S304 to S310 constitute a loop process L1. Loop process L1 is executed repeatedly as long as the value of x is less than or equal to N (the total number of registers in register set 10).

[0064] In S304, the selection unit 2060 determines whether x is less than or equal to N. If x is greater than N, there is no register set 10 available for executing the target interrupt handler. Therefore, the selection unit 2060 performs error handling (S312). For example, error handling is the process of terminating the execution of application 40.

[0065] In this way, even if there is no register set 10 available to execute the target interrupt handler, the application 40 can be terminated in a normal state. Therefore, it is possible to prevent the execution result of application 40 from becoming abnormal.

[0066] If x is less than or equal to N in S304, the selection unit 2060 determines whether the state information 20 indicates that the x-th register set 10 is normal (S306). If the state information 20 indicates that the x-th register set 10 is normal (S306: YES), the selection unit 2060 selects the x-th register set 10 as the register set 10 to be used for the target interrupt processing (S314). Then the process in Figure 9 ends.

[0067] On the other hand, the status information 20 indicates that the x-th register set 10 is not normal (S306: NO). In this case, the x-th register set 10 cannot be assigned to the target interrupt processing. Therefore, the selection unit 2060 adds 1 to x in order to check the next register set 10 (S310). Since S312 is the end of loop processing L1, loop processing L1 is executed again from S304.

[0068] It is not necessary to prioritize the selection of register sets 10 with smaller identifiers. For example, the selection unit 2060 may randomly select a register set 10 from among the register sets 10 that are indicated as normal in the status information 20.

[0069] In addition, for example, the selection unit 2060 may select the register set 10 that has been used the fewest times among the register sets 10 that are indicated as normal in the status information 20. This makes it possible to equalize the number of times each register set 10 has been used. The selection unit 2060 stores the number of times each register set 10 has been used in an arbitrary memory unit. Specifically, each time the selection unit 2060 selects a register set 10, it increments the number of times the selected register set 10 has been used by 1.

[0070] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0071] Each drawing is merely illustrative to illustrate one or more embodiments. Each drawing may be associated with one or more other embodiments rather than with only one specific embodiment. As those skilled in the art will understand, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings, for example, to create embodiments not explicitly shown or described. Not all features or steps shown in any one drawing to illustrate an exemplary embodiment are necessarily required, and some features or steps may be omitted. The order of steps shown in any of the drawings may be changed as appropriate.

[0072] In this disclosure, a program includes a set of instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more of the functions described in the embodiments. A program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. A program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrical, optical, acoustic or other forms of propagating signals.

[0073] <Note> Some or all of the above embodiments may also be described as follows, but are not limited to the following: (Note 1) A determination unit that determines whether each of the multiple register sets contained in the processor is normal or not, Based on the result of the above determination, an update unit updates status information indicating whether each of the above register sets is normal or not, A register set control system having a selection unit that selects the register set to be used for interrupt processing by the processor from among the register sets that are indicated to be normal in the status information. (Note 2) The aforementioned update unit is Determine whether the number of register sets that are shown as normal in the updated status information is equal to or greater than a predetermined lower limit. The register set control system described in Appendix 1 terminates the application being executed by the processor if the number of register sets indicated as normal in the updated status information is less than the lower limit. (Note 3) The register set control system described in Appendix 1, wherein the lower limit is 2 or greater. (Note 4) The aforementioned selection unit is Upon receiving an interrupt signal, the set of registers to be used for the interrupt processing corresponding to the interrupt signal is selected. The register set control system described in Appendix 1, which transmits to the processor a signal having the same content as the received interrupt signal and a signal representing the selected register set. (Note 5) The program representing the processing of the determination unit and the processing of the update unit is executed by the processor. The program representing the processing of the selection unit is incorporated into a logic circuit different from the processor, and is part of the register set control system described in Appendix 1. (Note 6) A determination step to determine whether each of the multiple register sets contained in the processor is normal, Based on the result of the above determination, an update step is performed to update status information indicating whether each of the above register sets is normal or not, A register set control method executed by a computer, comprising: a selection step of selecting the register set to be used for interrupt processing by the processor from among the register sets that are indicated to be normal in the status information. (Note 7) A determination step to determine whether each of the multiple register sets contained in the processor is normal, A program that causes a computer to perform an update step, which updates status information indicating whether each of the register sets is normal or not based on the result of the above determination. (Note 8) The system references status information indicating whether each of the multiple register sets contained within the processor is normal or not, in response to an interrupt being detected. A logic circuit that selects the set of registers used by the processor for interrupt processing to handle the detected interrupt from the set of registers that are indicated as normal in the state information. (Note 9) The memory element in which the instructions are stored, A processor having multiple register sets, The processor executes the instruction, Determine whether each of the multiple register sets is normal or not. Based on the result of the above determination, the status information indicating whether each register set is normal or not is updated. A register set control system that selects the register set to be used for interrupt processing from the register set that is indicated as normal in the status information. (Note 10) One or more memory elements in which instructions are stored, A processor having multiple register sets, It has a logic circuit and, The processor executes the instruction, Determine whether each of the multiple register sets is normal or not. Based on the result of the above determination, the status information indicating whether each register set is normal or not is updated. The logic circuit is a register set control system that selects the register set used by the processor for interrupt processing from the register set indicated as normal in the state information.

[0074] Some or all of the elements (e.g., configuration and function) described in Appendices 2 to 5 that are subordinate to Appendice 1 may also be subordinate to Appendices 6 to 10, respectively, in the same way as those described in Appendices 2 to 5. Some or all of the elements described in any appendice may be applied to various hardware, software, recording units, systems, and methods for recording software. [Explanation of Symbols]

[0075] 10 Register Sets 20 Status Information 30 processors 40 Applications 50 Interrupt handling 60 Interrupt Controllers 70 Logic Circuits 80 Storage section 1000 computers 1020 Bus 1060 memory 1080 Storage Devices 1100 Input / Output Interface 1120 Network Interface 2000 Register Set Control System 2020 Judgment Department 2040 Update Department 2060 Selection Section

Claims

1. A determination unit that determines whether each of the multiple register sets contained in the processor is normal or not, Based on the result of the above determination, an update unit updates status information indicating whether each of the above register sets is normal or not, A register set control system having a selection unit that selects the register set to be used for interrupt processing by the processor from among the register sets that are indicated to be normal in the status information.

2. The aforementioned update unit is Determine whether the number of register sets that are shown as normal in the updated status information is equal to or greater than a predetermined lower limit. The register set control system according to claim 1, wherein if the number of register sets indicated as normal in the updated state information is less than the lower limit, the application being executed by the processor is terminated.

3. The register set control system according to claim 1, wherein the lower limit is 2 or more.

4. The aforementioned selection unit is Upon receiving an interrupt signal, the set of registers to be used for the interrupt processing corresponding to the interrupt signal is selected. The register set control system according to claim 1, which transmits to the processor a signal having the same content as the received interrupt signal and a signal representing the selected register set.

5. The program representing the processing of the determination unit and the processing of the update unit is executed by the processor. The register set control system according to claim 1, wherein the program representing the processing of the selection unit is incorporated into a logic circuit different from the processor.

6. A determination step to determine whether each of the multiple register sets contained in the processor is normal, Based on the result of the above determination, an update step is performed to update status information indicating whether each of the above register sets is normal or not, A register set control method executed by a computer, comprising: a selection step of selecting the register set to be used for interrupt processing by the processor from among the register sets that are indicated to be normal in the status information.

7. A determination step to determine whether each of the multiple register sets contained in the processor is normal, A program that causes a computer to perform an update step, which updates status information indicating whether each of the register sets is normal or not based on the result of the above determination.

8. The system references status information indicating whether each of the multiple register sets contained within the processor is normal or not, in response to an interrupt being detected. A logic circuit that selects the set of registers used by the processor for interrupt processing to handle the detected interrupt from the set of registers that are indicated as normal in the state information.

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