Isolation module and gate driver

Abstract

To suppress the occurrence of surface discharge. [Solution] The transchip 80 comprises a first coil 41A and a second coil 42A arranged opposite to each other spaced apart in the z direction, a first electrode pad 81 connected to the first coil 41A, a second electrode pad 82 provided at a position spaced apart from the first electrode pad 81 in a plan view and connected to the second coil 42A, a passivation layer 150 formed on the surface 85s of the insulating layer 85 and made of a material containing silicon nitride, a low dielectric layer 160 formed on the surface 150s of the passivation layer 150 and made of a material containing silicon oxide and having a lower dielectric constant than the passivation layer 150, and a mold resin 110 covering the low dielectric layer 160.

Description

Technical Field

[0001] The present disclosure relates to an insulation module and a gate driver.

Background Art

[0002] Conventionally, an insulating transformer having a primary coil and a secondary coil arranged to face each other through an insulating layer has been known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a conventional insulating transformer, each coil is covered with an insulating layer, and the surface of the insulating layer is covered with a protective insulating layer made of silicon nitride (SiN). Further, the protective insulating layer is covered with a mold resin.

[0005] By the way, when a high voltage is applied to the insulating transformer, surface discharge may occur at the interface between the protective insulating layer and the mold resin. Such a problem is not limited to insulating transformers, but is the same for insulation modules insulated by capacitors.

[0006] An insulating module that solves the above problems comprises: a first conductor and a second conductor embedded in an insulating layer and arranged opposite to each other at a distance in the thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode provided at a position spaced apart from the first electrode when viewed from the thickness direction of the insulating layer and connected to the second conductor; a passivation layer formed on the surface of the insulating layer and made of a material containing silicon nitride; a low dielectric layer formed on the surface of the passivation layer and made of a material containing silicon oxide and having a lower dielectric constant than the passivation layer; and a mold resin covering the low dielectric layer.

[0007] A gate driver that solves the above problems applies a drive voltage signal to the gate of a switching element and comprises a low-voltage circuit configured to operate when a first voltage is applied, a high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied, and an insulating module, wherein the low-voltage circuit and the high-voltage circuit are connected via the insulating module and are configured to transmit signals via the insulating module, the insulating module comprises a first conductor and a second conductor embedded in an insulating layer and spaced apart and facing each other in the thickness direction of the insulating layer, a first electrode connected to the first conductor, a second electrode provided at a position spaced apart from the first electrode when viewed from the thickness direction of the insulating layer and connected to the second conductor, a passivation layer formed on the surface of the insulating layer and made of a material containing silicon nitride, a low dielectric layer formed on the surface of the passivation layer and made of a material containing silicon oxide and having a lower dielectric constant than the passivation layer, and a mold resin covering the low dielectric layer. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic circuit diagram of the gate driver of the first embodiment. [Figure 2] Figure 2 is a plan view showing the internal configuration of the gate driver of the first embodiment. [Figure 3]Figure 3 is a perspective view of the transformer chip of the gate driver according to the first embodiment. [Figure 4] Figure 4 is a plan view of the transformer chip shown in Figure 3. [Figure 5] Figure 5 is a schematic cross-sectional view showing the internal structure of the transformer chip shown in Figure 3. [Figure 6] Figure 6 is a schematic cross-sectional view showing the internal structure of the transformer chip in Figure 3 at a different location than that shown in Figure 5. [Figure 7] Figure 7 is a cross-sectional view taken along line 7-7 in Figure 4, showing the transformer chip mounted on the low-voltage die pad. [Figure 8] Figure 8 is a magnified view of a portion of the transformer chip shown in Figure 7. [Figure 9] Figure 9 is a magnified view of a portion of the transformer chip shown in Figure 7 that differs from that shown in Figure 8. [Figure 10] Figure 10 is a cross-sectional view of the gate driver of the second embodiment, showing the transformer chip mounted on the low-voltage die pad. [Figure 11] Figure 11 is a schematic circuit diagram of the gate driver of the third embodiment. [Figure 12] Figure 12 is a plan view showing the internal configuration of the gate driver of the third embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing the transformer chip of the gate driver of the third embodiment mounted on a low-voltage die pad. [Figure 14] Figure 14 is a schematic circuit diagram of the gate driver according to the fourth embodiment. [Figure 15] Figure 15 is a cross-sectional view showing the transformer chip of the gate driver of the fourth embodiment mounted on a low-voltage die pad. [Figure 16] Figure 16 is a plan view showing the internal configuration of the modified gate driver. [Figure 17] Figure 17 is a schematic circuit diagram of the modified gate driver.

[0009] [Detailed explanation] The following describes embodiments of the gate driver with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to those described below.

[0010] [First Embodiment] The gate driver 10 of the first embodiment will be described with reference to Figures 1 to 9. Figure 1 shows a simplified example of the circuit configuration of the gate driver 10.

[0011] As shown in Figure 1, the gate driver 10 applies a drive voltage signal to the gate of a switching element and is applied, for example, to an inverter device 500 installed in an electric vehicle or a hybrid vehicle. The inverter device 500 comprises a pair of switching elements 501 and 502 connected in series, the gate driver 10, and an ECU (Electronic Control Unit) 503 that controls the gate driver 10. Switching element 501 is, for example, a high-side switching element connected to a power supply, and switching element 502 is a low-side switching element. Examples of switching elements 501 and 502 include transistors such as SiMOSFETs (Si Metal-Oxide-Semiconductor Field-Effect Transistors), SiCMOSFETs, and IGBTs (Insulated Gate Bipolar Transistors). In this embodiment, the gate driver 10 applies a drive voltage signal to the gate of switching element 501. In the following description, the case in which SiCMOSFETs are used for switching elements 501 and 502 will be described.

[0012] A gate driver 10 is provided for each switching element 501, 502, and drives the switching elements 501, 502 individually. In this embodiment, for the sake of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0013] The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, and a transformer 40 provided between the low-voltage circuit 20 and the high-voltage circuit 30. That is, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0014] The gate driver 10 of the present embodiment is configured such that a signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the transformer 40 based on a control signal from the ECU 503, and a drive voltage signal is output from the high-voltage circuit 30.

[0015] As the signal transmitted from the low-voltage circuit 20 toward the high-voltage circuit 30, that is, the signal output from the low-voltage circuit 20, for example, is a signal for driving the switching element 501, and examples include a set signal and a reset signal. The set signal is a signal that transmits the rising edge of the control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of the control signal from the ECU 503. It can also be said that the set signal and the reset signal are signals for generating the drive voltage signal of the switching element 501. Therefore, the set signal and the reset signal correspond to the "first signal".

[0016] More specifically, the low-voltage circuit 20 is a circuit configured to operate when the first voltage V1 is applied. The low-voltage circuit 20 is a circuit electrically connected to the ECU 503, and generates a set signal and a reset signal based on a control signal input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to the rising edge of the control signal, while generating a reset signal in response to the falling edge of the control signal. Then, the low-voltage circuit 20 transmits the generated set signal and reset signal toward the high-voltage circuit 30.

[0017] The high-voltage circuit 30 is a circuit configured to operate when a second voltage V2 is applied. The high-voltage circuit 30 is electrically connected to the gate of the switching element 501 and generates a drive voltage signal to drive the switching element 501 based on the set signal and reset signal received from the low-voltage circuit 20, and applies that drive voltage signal to the gate of the switching element 501. In other words, the high-voltage circuit 30 also generates a drive voltage signal to be applied to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal to turn on the switching element 501 based on the set signal and applies that drive voltage signal to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal to turn off the switching element 501 based on the reset signal and applies that drive voltage signal to the gate of the switching element 501. In this way, the on / off state of the switching element 501 is controlled by the gate driver 10.

[0018] The high-voltage circuit 30 includes, for example, an RS-type flip-flop circuit to which set signals and reset signals are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS-type flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 can be arbitrarily changed.

[0019] In the gate driver 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are isolated by the transformer 40. More specifically, the transformer 40 restricts the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as set signals and reset signals.

[0020] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are isolated means that the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30 is blocked, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0021] The dielectric strength of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. In this embodiment, the dielectric strength of the gate driver 10 is approximately 5000 Vrms. However, the specific value of the dielectric strength of the gate driver 10 is not limited to this and is arbitrary.

[0022] In this embodiment, the ground of the low-voltage circuit 20 and the ground of the high-voltage circuit 30 are provided independently. Hereinafter, the ground potential of the low-voltage circuit 20 will be referred to as the first reference potential, and the ground potential of the high-voltage circuit 30 will be referred to as the second reference potential. In this case, the first voltage V1 is the voltage from the first reference potential, and the second voltage V2 is the voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0023] The following provides a detailed explanation of Transformer 40. The gate driver 10 of this embodiment is equipped with two transformers 40 to accommodate the transmission of two types of signals from the low-voltage circuit 20 to the high-voltage circuit 30. More specifically, the gate driver 10 is equipped with a transformer 40 used for transmitting a set signal and a transformer 40 used for transmitting a reset signal. For the sake of explanation, the transformer 40 used for transmitting the set signal will be referred to as "transformer 40A," and the transformer 40 used for transmitting the reset signal will be referred to as "transformer 40B."

[0024] The gate driver 10 includes a low-voltage signal line 21A connecting the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B connecting the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the transformer 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the transformer 40B.

[0025] The gate driver 10 includes a high-voltage signal line 31A connecting transformer 40A and high-voltage circuit 30, and a high-voltage signal line 31B connecting transformer 40B and high-voltage circuit 30. Therefore, high-voltage signal line 31A transmits a set signal from transformer 40A to high-voltage circuit 30. High-voltage signal line 31B transmits a reset signal from transformer 40B to high-voltage circuit 30.

[0026] Transformer 40A transmits the set signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically isolating the low-voltage circuit 20 from the high-voltage circuit 30. The dielectric strength of transformer 40A is, for example, 2500Vrms to 7500Vrms. Alternatively, the dielectric strength of transformer 40A may be, for example, 2500Vrms to 5700Vrms.

[0027] The transformer 40A includes a first coil 41A and a second coil 42A that is electrically insulated from the first coil 41A and magnetically coupled to it. The first coil 41A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A, while also being connected to the ground of the low-voltage circuit 20. In other words, the first end of the first coil 41A is electrically connected to the low-voltage circuit 20, and the second end of the first coil 41A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the first coil 41A becomes the first reference potential. The first reference potential is, for example, 0V.

[0028] The second coil 42A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A, while also being connected to the ground of the high-voltage circuit 30. In other words, the first end of the second coil 42A is electrically connected to the high-voltage circuit 30, and the second end of the second coil 42A is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the second coil 42A becomes the second reference potential. Since the ground of the high-voltage circuit 30 is connected to the source of the switching element 501, the second reference potential fluctuates with the driving of the inverter device 500 and may exceed, for example, 600V.

[0029] Transformer 40B transmits a reset signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically isolating the low-voltage circuit 20 from the high-voltage circuit 30. The dielectric breakdown voltage of transformer 40B is the same as that of transformer 40A. Transformer 40B includes a first coil 41B and a second coil 42B that is electrically insulated from the first coil 41B and magnetically coupled. The connection configuration of transformer 40B is the same as that of transformer 40A, so a detailed explanation is omitted. In this embodiment, the first coils 41A and 41B correspond to the "first conductor," and the second coils 42A and 42B correspond to the "second conductor."

[0030] Figure 2 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Figure 1 shows a simplified circuit configuration of the gate driver 10, so the number of external terminals of the gate driver 10 in Figure 2 is greater than the number of external terminals of the gate driver 10 in Figure 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 1). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Figure 2 is greater than the number of signal lines of the gate driver 10 in Figure 1.

[0031] As shown in Figure 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged together, and is mounted on a circuit board provided in, for example, the inverter device 500. Note that each switching element 501, 502 is mounted on a separate mounting board from the circuit board. A cooler is attached to this mounting board.

[0032] The gate driver 10 is packaged in a Small Outline (SO) format, and in this embodiment, it is a Small Outline Package (SOP). The gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 as semiconductor chips, a low-voltage lead frame 90 on which the low-voltage circuit chip 60 is mounted, a high-voltage lead frame 100 on which the high-voltage circuit chip 70 is mounted, and a molding resin 110 that seals parts of each lead frame 90, 100 and each chip 60, 70, 80. In this embodiment, the transformer chip 80 and the molding resin 110 correspond to an "insulation module" that insulates the low-voltage circuit 20 and the high-voltage circuit 30. Also, in Figure 2, the molding resin 110 is shown with a dashed line for the purpose of explaining the internal structure of the gate driver 10. Furthermore, the package format of the gate driver 10 can be arbitrarily changed.

[0033] The molded resin 110 is made of an electrically insulating material, for example, a black epoxy resin. The molded resin 110 is formed in the shape of a rectangular plate with the z-direction as the thickness direction. The molded resin 110 has four resin sides 111 to 114. More specifically, the molded resin 110 has resin sides 111 and 112 as end faces in the x-direction, and resin sides 113 and 114 as end faces in the y-direction. The x-direction and y-direction are perpendicular to the z-direction. The x-direction and y-direction are orthogonal to each other. In the following description, "plan view" means viewing from the z-direction.

[0034] The low-pressure lead frame 90 and the high-pressure lead frame 100 are each made of a conductor, which in this embodiment is made of Cu (copper). Each lead frame 90, 100 is provided spanning both the inside and outside of the molded resin 110.

[0035] The low-pressure lead frame 90 includes a low-pressure die pad 91 located within the molded resin 110, and a plurality of low-pressure leads 92 arranged across the inside and outside of the molded resin 110. Each low-pressure lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see Figure 1).

[0036] In this embodiment, both the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91. In a plan view, the low-voltage die pad 91 is positioned such that its center in the y-direction is closer to the resin side surface 113 than the center of the mold resin 110 in the y-direction. In this embodiment, the low-voltage die pad 91 is not exposed from the mold resin 110. In a plan view, the shape of the low-voltage die pad 91 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0037] Multiple low-pressure leads 92 are arranged spaced apart from each other in the x-direction. Each of the low-pressure leads 92 located at both ends in the x-direction is integrated with the low-pressure die pad 91. A portion of each low-pressure lead 92 protrudes outward from the resin side surface 113 toward the mold resin 110.

[0038] The high-voltage lead frame 100 includes a high-voltage die pad 101 located inside the molded resin 110, and a plurality of high-voltage leads 102 arranged to span both the inside and outside of the molded resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to external electronic equipment such as the gate of a switching element 501 (see Figure 1).

[0039] A high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. In a plan view, the high-voltage die pad 101 is positioned closer to the resin side surface 114 than the low-voltage die pad 91 in the y-direction. In this embodiment, the high-voltage die pad 101 is not exposed from the molded resin 110. In a plan view, the shape of the high-voltage die pad 101 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0040] The low-pressure die pad 91 and the high-pressure die pad 101 are spaced apart in the y-direction. Therefore, the y-direction can also be considered the direction of alignment of both die pads 91 and 101. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are determined by the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91, and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. Therefore, the y-direction dimension of the low-voltage die pad 91 is larger than that of the high-voltage die pad 101.

[0041] Multiple high-voltage leads 102 are arranged spaced apart from each other in the x-direction. One pair of the multiple high-voltage leads 102 is integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 toward the molded resin 110.

[0042] In this embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Figure 2, the multiple low-voltage leads 92 and the multiple high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can be changed as needed.

[0043] In this embodiment, the low-voltage die pad 91 is supported by a pair of low-voltage leads 92 integrated with the low-voltage die pad 91, and the high-voltage die pad 101 is supported by a pair of high-voltage leads 102 integrated with the high-voltage die pad 101. Therefore, each die pad 91, 101 is not provided with suspension leads exposed from the resin sides 111, 112. As a result, the insulation distance between the low-voltage lead frame 90 and the high-voltage lead frame 100 can be made larger.

[0044] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from each other in the y-direction. In the y-direction, they are arranged in the order of low-voltage circuit chip 60, transformer chip 80, and high-voltage circuit chip 70 from the low-voltage lead 92 toward the high-voltage lead 102.

[0045] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in Figure 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with a short side and a long side. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 such that the long side is along the x-direction and the short side is along the y-direction. The low-voltage circuit chip 60 has a main chip surface 60s and a chip back surface (not shown) that face opposite each other in the z-direction. The chip back surface of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 by a conductive bonding material such as solder or Ag (silver) paste.

[0046] Multiple first electrode pads 61, multiple second electrode pads 62, and multiple third electrode pads 63 are formed on the main surface 60s of the low-voltage circuit chip 60. Each electrode pad 61 to 63 is electrically connected to the low-voltage circuit 20.

[0047] Multiple first electrode pads 61 are positioned closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y-direction. Multiple first electrode pads 61 are arranged in the x-direction. Multiple second electrode pads 62 are positioned at the ends of the chip main surface 60s in the y-direction that are closer to the transformer tip 80. Multiple second electrode pads 62 are arranged in the x-direction. Multiple third electrode pads 63 are positioned at both ends of the chip main surface 60s in the x-direction.

[0048] The high-voltage circuit chip 70 includes the high-voltage circuit 30 shown in Figure 1. In plan view, the high-voltage circuit chip 70 has a rectangular shape with a short side and a long side. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 such that the long side is along the x-direction and the short side is along the y-direction. The high-voltage circuit chip 70 has a main chip surface 70s and a chip back surface (not shown) that face opposite each other in the z-direction. The chip back surface of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 by a conductive bonding material.

[0049] Multiple first electrode pads 71, multiple second electrode pads 72, and multiple third electrode pads 73 are formed on the main surface 70s of the high-voltage circuit chip 70. Each electrode pad 71 to 73 is electrically connected to the high-voltage circuit 30.

[0050] Multiple first electrode pads 71 ​​are located at the end of the chip main surface 70s in the y-direction that is closer to the transformer tip 80. The multiple first electrode pads 71 ​​are arranged in the x-direction. Multiple second electrode pads 72 are located at the end of the chip main surface 70s in the y-direction that is further from the transformer tip 80. That is, the multiple second electrode pads 72 are located at the end of the chip main surface 70s in the y-direction that is closer to the high-voltage lead 102. The multiple second electrode pads 72 are arranged in the x-direction. Multiple third electrode pads 73 are located at the end of the chip main surface 70s in the x-direction.

[0051] The transchip 80 includes the transchip 40 shown in Figure 1. In plan view, the shape of the transchip 80 is rectangular with a short side and a long side. In this embodiment, in plan view, the transchip 80 is mounted on the low-pressure die pad 91 such that the long side is aligned with the x-direction and the short side is aligned with the y-direction.

[0052] The transformer chip 80 is positioned adjacent to the low-voltage circuit chip 60 in the y-direction. The transformer chip 80 is positioned closer to the high-voltage circuit chip 70 than to the low-voltage circuit chip 60. In other words, the transformer chip 80 is positioned between the low-voltage circuit chip 60 and the high-voltage circuit chip 70 in the y-direction.

[0053] The trans tip 80 has a main tip surface 80s and a back tip surface 80r (see Figure 7) that face opposite each other in the z-direction. The back tip surface 80r of the trans tip 80 is bonded to the low-pressure die pad 91 by a conductive bonding material SD (see Figure 7).

[0054] As shown in Figure 2, the main surface 80s of the transformer chip 80 has a plurality of first electrode pads 81 and a plurality of second electrode pads 82 formed thereon. In this embodiment, each first electrode pad 81 corresponds to a "first electrode," and each second electrode pad 82 corresponds to a "second electrode."

[0055] Multiple first electrode pads 81 are arranged, for example, at the end of the chip main surface 80s in the y-direction that is closer to the low-voltage circuit chip 60. Multiple first electrode pads 81 are arranged in the x-direction. Multiple second electrode pads 82 are arranged, for example, near the center of the chip main surface 80s in the y-direction. Multiple second electrode pads 82 are arranged in the x-direction. Transformers 40A and 40B are located near the center of the chip main surface 80s in the y-direction in a plan view. As shown in Figure 4, in a plan view, the multiple second electrode pads 82 and transformers 40A and 40B are positioned so as not to overlap each other. Each electrode pad 81 and 82 is electrically connected to transformers 40A and 40B.

[0056] As shown in Figure 2, in order to set the dielectric strength of the gate driver 10 to a predetermined dielectric strength, it is necessary to space out the low-voltage die pad 91 and the high-voltage die pad 101, where each lead frame 90, 100 is closest to each other. For this reason, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0057] Multiple wires W are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each wire W is a bonding wire formed by a wire bonding apparatus and consists of a conductor such as Au (gold), Al (aluminum), or Cu.

[0058] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wire W. More specifically, the multiple first electrode pads 61 and multiple third electrode pads 63 of the low-voltage circuit chip 60 and the multiple low-voltage leads 92 are connected by wire W. The multiple third electrode pads 63 of the low-voltage circuit chip 60 and a pair of low-voltage leads 92 integrated with the low-voltage die pad 91 are connected by wire W. As a result, the low-voltage circuit 20 and the multiple low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503) are electrically connected. In this embodiment, the pair of low-voltage leads 92 integrated with the low-voltage die pad 91 constitute the ground terminal, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wire W, so the low-voltage die pad 91 is at the same potential as the ground of the low-voltage circuit 20.

[0059] Each of the high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are electrically connected by a wire W. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the high-voltage leads 102 by a wire W. As a result, the high-voltage circuit 30 and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the switching element 501, etc.) are electrically connected. In this embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute the ground terminal, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by a wire W, so that the high-voltage die pad 101 is at the same potential as the ground of the high-voltage circuit 30.

[0060] The transformer chip 80 is connected to both the low-voltage circuit chip 60 and the high-voltage circuit chip 70 by wires W. More specifically, the multiple first electrode pads 81 of the transformer chip 80 are connected to the multiple second electrode pads 62 of the low-voltage circuit chip 60 by wires W. The multiple second electrode pads 82 of the transformer chip 80 are connected to the multiple first electrode pads 71 ​​of the high-voltage circuit chip 70 by wires W.

[0061] Furthermore, both the first coil 41A of transformer 40A and the first coil 41B of transformer 40B (see Figure 1) are electrically connected to the ground of the low-voltage circuit 20 via wire W and the low-voltage circuit chip 60, etc. Both the second coil 42A of transformer 40A and the second coil 42B of transformer 40B (see Figure 1) are electrically connected to the ground of the high-voltage circuit 30 via wire W and the high-voltage circuit chip 70, etc.

[0062] Referring to Figures 3 to 9, an example of the configuration of the transformer chip 80 will be described. Note that the transformer 40B has the same configuration as the transformer 40A, so its description will be omitted. In the following description, the direction from the back surface 80r of the transformer chip 80 toward the main surface 80s of the chip will be considered upward, and the direction from the main surface 80s toward the back surface 80r of the chip will be considered downward.

[0063] Figure 4 is a plan view of the transformer chip 80, and for the sake of explanation, the transformers 40A and 40B, and the shield electrode 86 and dummy pattern 120, which will be described later, are shown with dashed lines.

[0064] Figure 5 is a cross-sectional view of the first coils 41A and 41B of each transformer 40AA, 40AB, 40BA, and 40BB in the transformer chip 80, cut in the xy plane at the z-direction position, showing the connection relationship of the first coils 41A and 41B of each transformer 40AA, 40AB, 40BA, and 40BB. Figure 6 is a cross-sectional view of the second coils 42A and 42B of each transformer 40AA, 40AB, 40BA, and 40BB in the transformer chip 80, cut in the xy plane at the z-direction position, showing the connection relationship of the second coils 42A and 42B of each transformer 40AA, 40AB, 40BA, and 40BB. For convenience, hatching has been omitted in Figures 5 and 6.

[0065] Figure 7 is a cross-sectional view of the transformer 40A and its surroundings in the transformer chip 80, cut along the line 7-7 in Figure 4. For convenience, Figure 7 shows the transformer chip 80 sealed by the molding resin 110 of the gate driver 10. Also, for the sake of readability, some of the hatching in Figure 7 has been omitted. Figures 8 and 9 are enlarged views of parts of Figure 7, and similarly, some of the hatching has been omitted.

[0066] As shown in Figure 4, the transformer chip 80 includes both transformers 40A and 40B, or more specifically, both transformers 40A and 40B are integrated into a single chip. In other words, the transformer chip 80 is a semiconductor chip dedicated to both transformers 40A and 40B, separate from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (both seen in Figure 2). The transformer chip 80 has four chip sides 80a, 80b, 80c, and 80d that are orthogonal to both the main chip surface 80s and the back surface 80r. The chip sides 80a to 80d are located between the main chip surface 80s and the back surface 80r in the z direction. The chip sides 80a and 80b constitute the end faces in the y direction of the transformer chip 80, and the chip sides 80c and 80d constitute the end faces in the x direction of the transformer chip 80. In a plan view, the chip sides 80a and 80b constitute the long sides of the transformer chip 80, and the chip sides 80c and 80d constitute the short sides of the transformer chip 80. In this embodiment, chip side 80a is closer to the high-voltage circuit chip 70 (see Figure 2) than chip side 80b, and chip side 80b is closer to the low-voltage circuit chip 60 (see Figure 2) than chip side 80a.

[0067] As shown in Figure 7, the transformer chip 80 has a substrate 84 and an insulating layer 85 formed on the substrate 84. The substrate 84 is made of, for example, a semiconductor substrate, and in this embodiment, a substrate formed from a material containing Si (silicon). The substrate 84 may be a wide-bandgap semiconductor or a compound semiconductor. Alternatively, instead of a semiconductor substrate, the substrate 84 may be an insulating substrate formed from a material containing glass.

[0068] A wide-bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0069] The substrate 84 has a main substrate surface 84s and a substrate back surface 84r that face opposite each other in the z direction. The substrate back surface 84r constitutes the chip back surface 80r of the transformer chip 80.

[0070] In this embodiment, multiple insulating layers 85 are laminated on the main surface 84s of the substrate 84 in the z direction. In other words, the z direction can also be said to be the thickness direction of the insulating layer 85. The insulating layer 85 is formed on the main surface 84s of the substrate 84. In this embodiment, the total thickness T1 of the multiple insulating layers 85 is greater than the thickness T2 of the substrate 84 (T1 > T2). However, the number of layers of insulating layer 85 is set according to the required dielectric strength of the transformer chip 80. Therefore, depending on the number of layers of insulating layer 85, the thickness T1 may be less than the thickness T2 (T1 <T2)。

[0071] The insulating layer 85 comprises a first insulating layer 85A and a second insulating layer 85B formed on the first insulating layer 85A. The first insulating layer 85A is, for example, an etching stopper layer and is made of SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. In this embodiment, the first insulating layer 85A is made of SiN. The second insulating layer 85B is, for example, an interlayer insulating layer and is made of SiO2 (silicon oxide). As shown in Figure 7, the thickness of the second insulating layer 85B is greater than the thickness of the first insulating layer 85A. The thickness of the first insulating layer 85A may be 100 nm or more and less than 1000 nm. The thickness of the second insulating layer 85B may be 1000 nm or more and 3000 nm or less. In this embodiment, the thickness of the first insulating layer 85A is, for example, about 300 nm, and the thickness of the second insulating layer 85B is, for example, about 2000 nm.

[0072] Both the bottom insulating layer 85L and the top insulating layer 85U, which are in contact with the main surface 84s of the substrate 84, are made of the second insulating layer 85B. Therefore, the thickness of both the bottom insulating layer 85L and the top insulating layer 85U is thinner than that of the other insulating layers 85. The thickness of both the bottom insulating layer 85L and the top insulating layer 85U is greater than or equal to the thickness of the first insulating layer 85A and less than or equal to the thickness of the second insulating layer 85B.

[0073] The thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U can be arbitrarily changed. For example, the thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U may be greater than the thickness of the second insulating layer 85B, and may be greater than or equal to the thickness of the insulating layer 85 consisting of the first insulating layer 85A and the second insulating layer 85B.

[0074] The outer surface of the uppermost insulating layer 85U is located inward compared to the outer surfaces of the other insulating layers 85. For example, as shown in Figure 7, the outer surface of the uppermost insulating layer 85U that faces the same side as the chip side 80a is located inward in the y-direction compared to the chip side 80a. The outer surface of the uppermost insulating layer 85U that faces the same side as the chip side 80b is located inward in the y-direction compared to the chip side 80b.

[0075] The transformer chip 80 is equipped with a shield electrode 86 formed within the insulating layer 85. The shield electrode 86 suppresses the intrusion of moisture into the insulating layer 85 and the occurrence of cracks in the insulating layer 85. In a plan view, the shield electrode 86 is provided on the outer periphery of the insulating layer 85 (the outer periphery of the transformer chip 80). More specifically, as shown in Figures 4 to 6, the shield electrode 86 is provided spaced apart from the chip sides 80a to 80d. In a plan view, the shield electrode 86 is formed in a strip shape and extends along the chip sides 80a to 80d. In this embodiment, the shape of the shield electrode 86 in a plan view is a rectangular annular shape. The shield electrode 86 divides the insulating layer 85 into an inner region 87 and an outer region 88. In this embodiment, as shown in Figure 7, the uppermost insulating layer 85U is formed so as to straddle the shield electrode 86 in a plan view. In other words, the uppermost insulating layer 85U can also be said to have an outer region 88.

[0076] As shown in Figure 4, the inner region 87 is the region of the insulating layer 85 protected by the shield electrode 86. In a plan view, the shape of the inner region 87 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side. The outer region 88 is a rectangular annular region surrounding the inner region 87 in a plan view. In a plan view, the outer region 88 is the region between the shield electrode 86 and the chip sides 80a to 80d. In other words, the outer region 88 is a rectangular annular region including the chip sides 80a to 80d.

[0077] The material of the shield electrode 86 is appropriately selected from one or more of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). As shown in Figure 7, the shield electrode 86 penetrates multiple insulating layers 85 in the z direction. More specifically, the shield electrode 86 is positioned to overlap the coils 41A, 41B, 42A, and 42B of the transformers 40A and 40B when viewed from a direction perpendicular to the z direction. In this embodiment, the shield electrode 86 penetrates in the z direction from two insulating layers 85 below the uppermost insulating layer 85U to one insulating layer 85 above the lowest insulating layer 85L. The lowest insulating layer 85L is provided with vias 89 that penetrate the lowest insulating layer 85L in the z direction. The vias 89 are positioned to overlap the shield electrode 86 in a plan view and connect the shield electrode 86 to the substrate 84. As a result, the shield electrode 86 is electrically connected to the substrate 84. The via 89 may be formed from the same material as the shield electrode 86, for example.

[0078] Transformers 40A and 40B are embedded within the insulating layer 85. Transformers 40A and 40B are located in the inner region 87. As shown in Figure 4, transformers 40A and 40B are aligned in the y-direction and spaced apart in the x-direction. In a plan view, transformers 40A and 40B are also arranged in a direction perpendicular to the direction in which each chip 60, 70, and 80 are arranged. The transformer chip 80 of this embodiment includes two transformers 40A and two transformers 40B. For convenience, the two transformers near the chip side surface 80c in the x-direction are referred to as "transformer 40AA" and "transformer 40AB," and the two transformers near the chip side surface 80d in the x-direction are referred to as "transformer 40BA" and "transformer 40BB."

[0079] As shown in Figure 4, in the x-direction, the transformers 40AA, 40AB, 40BA, and 40BB are arranged in this order as we move from the chip side 80c to the chip side 80d.

[0080] As shown in Figure 7, the first coil 41A and the second coil 42A of the transformer 40AA are arranged facing each other in the z direction via an insulating layer 85. In this embodiment, the first coil 41A and the second coil 42A are arranged facing each other in the z direction via a plurality of insulating layers 85.

[0081] Each coil 41A and 42A is configured as a conductive layer embedded within a single insulating layer 85. More specifically, the insulating layer 85X in which each coil 41A and 42A is embedded has grooves formed that penetrate both the first insulating layer 85A and the second insulating layer 85B in the z direction. The conductive layers constituting each coil 41A and 42A are embedded in the grooves of the insulating layer 85X. The insulating layer 85X in which each coil 41A and 42A is embedded is covered by the insulating layer 85X and the insulating layer 85 adjacent to it in the z direction. Thus, it can also be said that each coil 41A and 42A is embedded in the insulating layer 85.

[0082] In the z-direction, the second coil 42A is located further from the substrate 84 than the first coil 41A. In other words, the second coil 42A is located above the first coil 41A. Also, the first coil 41A is located closer to the substrate 84 than the second coil 42A. In this embodiment, the distance between the first coil 41A and the second coil 42A in the z-direction is greater than the distance between the first coil 41A and the main surface 84s of the substrate 84.

[0083] As shown in Figure 4, the shape of the second coil 42A in plan view is an elliptical spiral. The first coil 41A has the same shape as the second coil 42A. The first coil 41A and the second coil 42A are formed by the same winding direction in plan view. In this embodiment, the number of turns of the first coil 41A is the same as the number of turns of the second coil 42A. Each coil 41A, 42A can be made of one or more of the following materials as appropriate: Ti, TiN, Au, Ag, Cu, Al, and W. The configuration of transformer 40AB is the same as that of transformer 40AA, so its description is omitted.

[0084] As shown in Figure 4, in a plan view, the multiple first electrode pads 81 and the multiple second electrode pads 82 are each arranged within an inner region 87. As shown in Figure 7, each electrode pad 81, 82 is formed on an insulating layer 85 that is one layer below the uppermost insulating layer 85U. The uppermost insulating layer 85U is formed in a position aligned with each electrode pad 81, 82. It can also be said that each electrode pad 81 and each electrode pad 82 are embedded in the insulating layer 85. As shown in Figure 7, in this embodiment, each electrode pad 81 and each electrode pad 82 are positioned away from the substrate 84 relative to the second coils 42A, 42B of the transformers 40A, 40B. In other words, each electrode pad 81 and each electrode pad 82 are located above the second coils 42A, 42B of the transformers 40A, 40B. In this embodiment, the distance between the first coil 41A and the second coil 42A is greater than the distance between the second coil 42A and each electrode pad 81, 82 in the z-direction.

[0085] The uppermost insulating layer 85U is formed to cover the outer periphery of each electrode pad 81, 82. That is, as shown in Figures 8 and 9, the uppermost insulating layer 85U has a first insulating layer opening 85Ua for exposing the first electrode pad 81 and a second insulating layer opening 85Ub for exposing the second electrode pad 82. Multiple first insulating layer openings 85Ua are provided corresponding to multiple pairs of first electrode pads 81, and multiple second insulating layer openings 85Ub are provided corresponding to multiple pairs of second electrode pads 82.

[0086] As shown in Figure 4, in a plan view, the multiple first electrode pads 81 are positioned in the x-direction aligned with the two transformers 40AA, 40AB and the two transformers 40BA, 40BB, between transformers 40AA and 40AB in the x-direction, and between transformers 40BA and 40BB in the x-direction. In the y-direction, the multiple first electrode pads 81 are positioned closer to the chip side surface 80b than the transformers 40AA, 40AB, 40BA, 40BB. In other words, the multiple first electrode pads 81 are positioned between the transformers 40AA, 40AB, 40BA, 40BB and the chip side surface 80b in the y-direction. In a plan view, it can also be said that the multiple first electrode pads 81 are positioned closer to the low-voltage leads 92 (see Figure 2) than the transformers 40AA, 40AB, 40BA, 40BB. For convenience, the multiple first electrode pads 81 extending from the chip side 80c to the chip side 80d will be referred to as first electrode pad 81A, first electrode pad 81B, first electrode pad 81C, first electrode pad 81D, first electrode pad 81E, and first electrode pad 81F. When explaining matters common to the first electrode pads 81A to 81F, they will be referred to simply as first electrode pad 81.

[0087] The first electrode pad 81A is positioned to overlap with transformer 40AA when viewed from the y-direction. The first electrode pad 81B is positioned to overlap with the portion between transformers 40AA and 40AB in the x-direction when viewed from the y-direction. The first electrode pad 81C is positioned to overlap with transformer 40AB when viewed from the y-direction. The first electrode pad 81D is positioned to overlap with transformer 40BA when viewed from the y-direction. The first electrode pad 81E is positioned to overlap with the portion between transformers 40BA and 40BB in the x-direction when viewed from the y-direction. The first electrode pad 81F is positioned to overlap with transformer 40BB when viewed from the y-direction. Each of the first electrode pads 81A to 81F consists of a pair of electrode pads adjacent to each other in the x-direction. The multiple first electrode pads 81A to 81F are arranged aligned with each other in the y-direction and spaced apart from each other in the x-direction.

[0088] In a plan view, the multiple second electrode pads 82 are positioned within each transformer 40AA, 40AB, 40BA, and 40BB, between transformers 40AA and 40AB in the x-direction, and between transformers 40BA and 40BB in the x-direction. When viewed from the x-direction, the multiple second electrode pads 82 are positioned to overlap with transformers 40AA, 40AB, 40BA, and 40BB. For convenience, the multiple second electrode pads 82 extending from the chip side surface 80c to the chip side surface 80d will be referred to as second electrode pad 82A, second electrode pad 82B, second electrode pad 82C, second electrode pad 82D, second electrode pad 82E, and second electrode pad 82F. When explaining matters common to second electrode pads 82A to 82F, they will be referred to simply as second electrode pad 82.

[0089] The second electrode pad 82A is located in the inner space formed in the elliptical spiral second coil 42A of the transformer 40AA. The second electrode pad 82B is located between the transformers 40AA and 40AB in the x-direction. The second electrode pad 82C is located in the inner space formed in the elliptical spiral second coil 42A of the transformer 40AB. The second electrode pad 82D is located in the inner space formed in the elliptical spiral second coil 42B of the transformer 40BA. The second electrode pad 82E is located between the transformers 40BA and 40BB in the x-direction. The second electrode pad 82F is located in the inner space formed in the elliptical spiral second coil 42B of the transformer 40BB. Each second electrode pad 82A to 82F consists of a pair of electrode pads adjacent to each other in the x-direction. Each second electrode pad 82A to 82F is arranged aligned with each other in the y-direction and spaced apart from each other in the x-direction.

[0090] As shown in Figures 4, 5, and 7, the first electrode pads 81A to 81F are individually electrically connected to the first coils 41A and 41B of the transformers 40AA, 40AB, 40BA, and 40BB. As shown in Figures 4, 6, and 7, the second electrode pads 82A to 82F are individually electrically connected to the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB.

[0091] As shown in Figures 5 and 6, the transformer tip 80 is provided with connecting wiring for individually connecting each electrode pad 81A-81F, 82A-82F to each coil 41A, 41B, 42A, 42B of the transformer 40AA, 40AB, 40BA, 40BB. In this embodiment, this connecting wiring includes first connecting wiring 131A-131F, second connecting wiring 132A, 132B, third connecting wiring 133A-133D, and fourth connecting wiring 134A, 134B. Each connecting wiring 131A-131D, 132A, 132B, 133A-133D, 134A, 134B is provided within an inner region 87 and is appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0092] As shown in Figures 4 and 5, the first connecting wire 131A connects the first electrode pad 81A to the first end of the first coil 41A of the transformer 40AA. The first connecting wire 131B connects the first electrode pad 81C to the first end of the first coil 41A of the transformer 40AB. The first connecting wire 131C connects the first electrode pad 81D to the first end of the first coil 41B of the transformer 40BA. The first connecting wire 131D connects the first electrode pad 81F to the first end of the first coil 41B of the transformer 40BB.

[0093] The second connecting wire 132A connects the first electrode pad 81B to both the second end of the first coil 41A of transformer 40AA and the second end of the first coil 41A of transformer 40AB. The second connecting wire 132B connects the first electrode pad 81E to both the second end of the first coil 41B of transformer 40BA and the second end of the first coil 41B of transformer 40BB.

[0094] Note that the first connection wires 131A to 131D have similar structures, and the second connection wires 132A and 132B have similar structures. Therefore, the following will describe the configuration of the first connection wire 131A and the second connection wire 132A, and will omit detailed descriptions of the first connection wires 131B to 131D and the second connection wire 132B.

[0095] As shown in Figure 7, the first connecting wiring 131A has a first wiring portion 135 that extends in the z direction so as to penetrate a plurality of insulating layers 85, a second wiring portion 136 that extends in the y direction, and a third wiring portion 137 that connects to the first end of the first coil 41A of the transformer 40AA.

[0096] The first wiring section 135 is positioned to overlap with the first electrode pad 81A in a plan view and is connected to the first electrode pad 81A. The first wiring section 135 penetrates from one insulating layer 85 below the uppermost insulating layer 85U to two insulating layers 85 above the lowest insulating layer 85L among the multiple insulating layers 85. The first wiring section 135 has a flat wiring section provided at the same position as the insulating layer 85X on which each coil 41A, 42A is provided, and a plurality of vias provided between the two wiring sections in the z direction, between the upper wiring section and the first electrode pad 81A, and between the lower wiring section and the second wiring section 136.

[0097] The second wiring section 136 is located closer to the substrate 84 than the first wiring section 135. The second wiring section 136 is located closer to the substrate 84 than the first coil 41A. In this embodiment, the second wiring section 136 is located on an insulating layer 85 one layer above the bottom insulating layer 85L among the multiple insulating layers 85. Of the x-direction ends of the second wiring section 136, the end closer to the chip side surface 80b of the transformer chip 80 is located in a position that overlaps with the first wiring section 135 in a plan view. The second wiring section 136 is connected to the first wiring section 135. Of the x-direction ends of the second wiring section 136, the end closer to the chip side surface 80a of the transformer chip 80 is located in a position that overlaps with the first coil 41A of the transformer 40AA in a plan view.

[0098] The third wiring section 137 is positioned to overlap with the second electrode pad 82A in a plan view. The third wiring section 137 has a coil connection wiring section provided at the same position as the first coil 41A in the z direction, and a connecting wiring section that connects the coil connection wiring section and the second wiring section 136. The coil connection wiring section is connected to the first end of the first coil 41A. The connecting wiring section is positioned to overlap with the coil connection wiring section in a plan view and penetrates the insulating layer 85 between the coil connection wiring section and the second wiring section 136 in the z direction.

[0099] As shown in Figure 5, the second connection wiring 132A has the same configuration as the first connection wiring 131A. In the second connection wiring 132A, unlike the first connection wiring 131A, the third wiring section 137 is connected to the second end of the first coil 41A of the transformers 40AA, 40AB.

[0100] As shown in Figures 4 and 6, the third connecting wire 133A is a wire that connects the second electrode pad 82A to the first end of the second coil 42A of the transformer 40AA. The third connecting wire 133A is positioned to overlap with the second electrode pad 82A in a plan view. In a plan view, the third connecting wire 133A is aligned in the x direction with respect to the third wiring portion 137 of the first connecting wire 131A, and is positioned in the y direction closer to the chip side 80a of the transformer chip 80.

[0101] The third connection wiring 133B is a wiring that connects the second electrode pad 82C to the first end of the second coil 42A of the transformer 40AB. The third connection wiring 133B is positioned so as to overlap with the second electrode pad 82C in a plan view. In a plan view, the third connection wiring 133B is aligned in the x direction with respect to the third wiring portion 137 of the first connection wiring 131B and is positioned in the y direction closer to the chip side 80a of the transformer chip 80.

[0102] The third connecting wire 133C is a wire that connects the second electrode pad 82D to the first end of the second coil 42B of the transformer 40BA. In a plan view, the third connecting wire 133C is positioned to overlap with the second electrode pad 82D. In a plan view, the third connecting wire 133C is aligned in the x direction with respect to the third wiring portion 137 of the first connecting wire 131C, and is positioned in the y direction closer to the chip side 80a of the transformer chip 80.

[0103] The third connection wiring 133D is a wiring that connects the second electrode pad 82F to the first end of the second coil 42B of the transformer 40BB. The third connection wiring 133D is positioned to overlap with the second electrode pad 82F in a plan view. In a plan view, the third connection wiring 133C is positioned in the y direction closer to the chip side 80a of the transformer chip 80, while being aligned in the x direction with respect to the third wiring portion 137 of the first connection wiring 131D.

[0104] The fourth connecting wire 134A is a wire that connects the second electrode pad 82B to the second end of the second coil 42A of transformer 40AA and the second end of the second coil 42A of transformer 40AB. The fourth connecting wire 134A is positioned between the second coil 42A of transformer 40AA and the second coil 42A of transformer 40AB in the x-direction. When viewed from the x-direction, the fourth connecting wire 134A is positioned to overlap with the second coils 42A of transformers 40AA and 40AB.

[0105] The fourth connecting wire 134B is a wire that connects the second electrode pad 82D to the second end of the second coil 42B of transformer 40BA and the second end of the second coil 42B of transformer 40BB. The fourth connecting wire 134B is positioned between the second coil 42B of transformer 40BA and the second coil 42B of transformer 40BB in the x-direction. When viewed from the x-direction, the fourth connecting wire 134B is positioned to overlap with the second coil 42B of transformers 40BA and 40BB.

[0106] As shown in Figures 4 and 6, in this embodiment, the transformer chip 80 includes dummy patterns 120 provided around the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB.

[0107] The dummy pattern 120 is provided in the inner region 87 and has a first dummy pattern 121, a second dummy pattern 122, and a third dummy pattern 123. The material of each dummy pattern 121 to 123 is appropriately selected from one or more of Ti, TiN, Au, Ag, Cu, Al, and W.

[0108] The first dummy pattern 121 is provided in each of the following regions in a plan view: the region between the second coil 42A of transformer 40AA and the second coil 42A of transformer 40AB in the x-direction, the region between the second coil 42B of transformer 40BA and the second coil 42B of transformer 40BB in the x-direction, and the region between the second coil 42B of transformer 40AB and the second coil 42B of transformer 40BA in the x-direction.

[0109] The first dummy pattern 121 is electrically connected to the second coil 42B via the fourth connecting wire 134B. The first dummy pattern 121 may also be electrically connected to the second coil 42A. In other words, the first dummy pattern 121 only needs to be electrically connected to at least one of the second coils 42A and 42B. Thus, the first dummy pattern 121 is at the same potential as the second coils 42A and 42B. Therefore, as the second reference potential of the second coils 42A and 42B changes, the voltage of the first dummy pattern 121 may become higher than that of the first coil 41B, similar to the voltage of the second coil 42B. As shown in Figure 6, the first dummy pattern 121 is formed with a different pattern than the second coils 42A and 42B.

[0110] Although not shown in the diagram, the first dummy pattern 121 is positioned in the z-direction in the same position as the second coils 42A and 42B. In other words, the first dummy pattern 121 is positioned further from the substrate 84 than the first coils 41A and 41B. In other words, the dummy pattern 120 can be said to be provided around the coil that is closer to the main chip surface 80s of the transformer chip 80 among the transformers 40AA, 40AB, 40BA, and 40BB.

[0111] By having the first dummy pattern 121 at the same voltage as the second coils 42A and 42B, the voltage drop between the second coils 42A and 42B and the first dummy pattern 121 can be suppressed. Therefore, electric field concentration on the second coils 42A and 42B can be suppressed.

[0112] As shown in Figure 6, the third dummy pattern 123 is formed in a plan view so as to surround the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB. The third dummy pattern 123 is electrically connected to the first dummy pattern 121. Therefore, similar to the first dummy pattern 121, the voltage of the third dummy pattern 123 may become higher than that of the first coil 41B when the second reference potential of the second coil 42B changes.

[0113] As shown in Figure 7, the third dummy pattern 123 is positioned in the z-direction aligned with the second coil 42A. Although not shown, the third dummy pattern 123 is also positioned in the z-direction aligned with the second coil 42B. In other words, the third dummy pattern 123 is positioned further from the substrate 84 than the first coils 41A and 41B. Thus, each dummy pattern 121 to 123 is positioned in the z-direction aligned with each other.

[0114] By having the third dummy pattern 123 have the same voltage as the second coils 42A and 42B, the voltage drop between the second coils 42A and 42B and the third dummy pattern 123 can be suppressed. Therefore, electric field concentration on the second coils 42A and 42B can be suppressed.

[0115] The second dummy pattern 122 is formed to surround the third dummy pattern 123 in a plan view. The second dummy pattern 122 is independent of the second coils 42A and 42B. In other words, the second dummy pattern 122 is not electrically connected to the second coils 42A and 42B.

[0116] As shown in Figure 7, the second dummy pattern 122 is positioned in the z-direction aligned with the second coil 42A. Although not shown, the second dummy pattern 122 is also positioned in the z-direction aligned with the second coil 42B. In other words, the second dummy pattern 122 is positioned further from the substrate 84 than the first coils 41A and 41B. The second dummy pattern 122 suppresses the increase in electric field strength around the second coils 42A and 42B, and also suppresses electric field concentration on the second electrode pads 82A to 82F.

[0117] As shown in Figure 7, the transformer chip 80 includes a passivation layer 150 that protects the insulating layer 85. The passivation layer 150 is formed on the surface 85s of the insulating layer 85. The surface 85s of the insulating layer 85 is the surface of the uppermost insulating layer 85U among the multiple insulating layers 85. The surface of the uppermost insulating layer 85U faces the same side as the main substrate surface 84s of the substrate 84. The passivation layer 150 is provided near the main chip surface 80s of the transformer chip 80. For this reason, the dummy pattern 120 can also be said to be provided around the coils (in this embodiment, the second coils 42A and 42B) among the first coils 41A and 41B and the second coils 42A and 42B that are located near the passivation layer 150.

[0118] The passivation layer 150 covers each electrode pad 81 and each electrode pad 82 such that a portion of each electrode pad 81 and each electrode pad 82 is exposed from the z direction. In other words, the passivation layer 150 has a first protective layer opening 151 that exposes each electrode pad 81 and a second protective layer opening 152 that exposes each electrode pad 82. That is, the passivation layer 150 has a plurality of first protective layer openings 151 corresponding to a plurality of first electrode pads 81 and a plurality of second protective layer openings 152 corresponding to a plurality of second electrode pads 82. Each first protective layer opening 151 exposes both of a pair of first electrode pads 81 that are adjacent in the x direction among the plurality of first electrode pads 81. Each second protective layer opening 152 exposes both of a pair of second electrode pads 82 that are adjacent in the x direction among the plurality of second electrode pads 82.

[0119] As shown in Figure 8, the first protective layer opening 151 is located in a position that overlaps with the first electrode pad 81 in a plan view and penetrates the passivation layer 150. The first protective layer opening 151 communicates with the first insulating layer opening 85Ua of the uppermost insulating layer 85U. The first inner surface constituting the first protective layer opening 151 is flush with, for example, the first inner surface constituting the first insulating layer opening 85Ua.

[0120] As shown in Figure 9, the second protective layer opening 152 is located in a position that overlaps with the second electrode pad 82 in a plan view and penetrates the passivation layer 150. The second protective layer opening 152 communicates with the second insulating layer opening 85Ub of the uppermost insulating layer 85U. The second inner surface constituting the second protective layer opening 152 is flush with, for example, the second inner surface constituting the second insulating layer opening 85Ub.

[0121] As shown in Figure 7, the passivation layer 150 is formed in the inner region 87. In a plan view, the passivation layer 150 is positioned to overlap with the shield electrode 86. In a plan view, the passivation layer 150 slightly extends outward from the shield electrode 86. In other words, the passivation layer 150 is also formed in part of the outer region 88. In this embodiment, the passivation layer 150 covers the entire surface 85s of the uppermost insulating layer 85U. The outer surface of the passivation layer 150 is flush with the outer surface of the uppermost insulating layer 85U. For this reason, a stepped portion 88a is formed in the outer region 88 of the transchip 80. In a plan view, the stepped portion 88a is formed outward from the shield electrode 86.

[0122] The passivation layer 150 is formed from a material containing, for example, silicon nitride. Examples of materials containing silicon nitride include SiN and SiCN. In this embodiment, the passivation layer 150 is formed from a material containing SiN.

[0123] In one example, as shown in Figure 8, the thickness TP of the passivation layer 150 is less than or equal to the thickness TR of the insulating layer 85. The thickness TP of the passivation layer 150 is thinner than the thickness TRU of the uppermost insulating layer 85U. Alternatively, the thickness TP of the passivation layer 150 may be equal to the thickness of the first insulating layer 85A.

[0124] As shown in Figures 8 and 9, the passivation layer 150 has a first raised portion 153 and a second raised portion 154. The first raised portion 153 covers the uppermost insulating layer 85U that covers the outer periphery of a pair of first electrode pads 81 aligned in the x direction. The second raised portion 154 covers the uppermost insulating layer 85U that covers the outer periphery of a pair of second electrode pads 82 aligned in the x direction. The first raised portion 153 constitutes the first protective layer opening 151, and the second raised portion 154 constitutes the second protective layer opening 152. In plan view, the shapes of the first raised portion 153 and the second raised portion 154 are rectangular, with the x direction being the longer side and the y direction being the shorter side.

[0125] As shown in Figure 7, the transchip 80 includes a low dielectric layer 160 formed on the surface 150s of the passivation layer 150. In this embodiment, the low dielectric layer 160 is in contact with the passivation layer 150. Here, the surface 150s of the passivation layer 150 is the surface of the passivation layer 150 that faces the same side as the main substrate surface 84s of the substrate 84 in a plan view.

[0126] In this embodiment, the low dielectric layer 160 is formed over the entire surface 150s of the passivation layer 150 in a plan view. More specifically, in a plan view, the outer edge of the low dielectric layer 160 is aligned with the outer edge of the passivation layer 150. That is, as shown in Figure 8, the outer surface of the low dielectric layer 160 and the outer surface of the passivation layer 150 are flush.

[0127] The low dielectric layer 160 can also be said to be interposed between the passivation layer 150 and the mold resin 110 in the z-direction so that the passivation layer 150 and the mold resin 110 do not come into contact with each other. As shown in Figure 8, the thickness TE of the low dielectric layer 160 is less than or equal to the thickness TP of the passivation layer 150. In this embodiment, the thickness TE of the low dielectric layer 160 is thinner than the thickness TP of the passivation layer 150.

[0128] The thickness TE of the low dielectric layer 160 can be changed as needed. For example, the thickness TE of the low dielectric layer 160 may be thicker than the thickness TP of the passivation layer 150. As shown in Figures 8 and 9, the low dielectric layer 160 has a first dielectric layer opening 161 located at a position that overlaps with each first protective layer opening 151 in a plan view, and a second dielectric layer opening 162 located at a position that overlaps with each second protective layer opening 152 in a plan view. In other words, the low dielectric layer 160 has a plurality of first dielectric layer openings 161 corresponding to a plurality of first protective layer openings 151, and a plurality of second dielectric layer openings 162 corresponding to a plurality of second protective layer openings 152. The first dielectric layer openings 161 communicate with the first protective layer openings 151, and the second dielectric layer openings 162 communicate with the second protective layer openings 152.

[0129] The first inner surface constituting the first dielectric layer opening 161 and the first inner surface constituting the first protective layer opening 151 are flush with each other. The second inner surface constituting the second dielectric layer opening 162 and the second inner surface constituting the second protective layer opening 152 are flush with each other.

[0130] As described above, in this embodiment, the transchip 80 has a first opening 171 consisting of a first insulating layer opening 85Ua, a first protective layer opening 151, and a first dielectric layer opening 161, and a second opening 172 consisting of a second insulating layer opening 85Ub, a second protective layer opening 152, and a second dielectric layer opening 162. In this embodiment, it can be said that the first opening 171 and the second opening 172 each penetrate both the passivation layer 150 and the low dielectric layer 160. Furthermore, it can be said that the first opening 171 and the second opening 172 each penetrate the uppermost insulating layer 85U. In other words, the first opening 171 is an opening that exposes the first electrode pad 81 from the z direction, and the second opening 172 is an opening that exposes the second electrode pad 82 from the z direction. A wire W (not shown in Figures 7 and 8) is connected to the first electrode pad 81 through the first opening 171. A wire W (not shown in Figures 7 and 9) is connected to the second electrode pad 82 through the second opening 172.

[0131] Furthermore, as shown in Figures 8 and 9, the low dielectric layer 160 has a first raised portion 163 and a second raised portion 164. The first raised portion 163 covers the first raised portion 153 of the passivation layer 150. The second raised portion 164 covers the second raised portion 154.

[0132] Thus, since the first opening 171 is composed of the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160, a first raised portion 173 is provided around the first opening 171 to cover the outer periphery of the pair of first electrode pads 81 aligned in the x direction. In other words, the first raised portion 173 consists of the portion of the uppermost insulating layer 85U that covers the outer periphery of the pair of first electrode pads 81, the first raised portion 153 of the passivation layer 150, and the first raised portion 163 of the low dielectric layer 160.

[0133] Since the second opening 172 is composed of the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160, a second raised portion 174 is provided around the second opening 172 to cover the outer periphery of a pair of second electrode pads 82 aligned in the x direction. In other words, the second raised portion 174 consists of the portion of the uppermost insulating layer 85U that covers the outer periphery of the pair of second electrode pads 82, the second raised portion 154 of the passivation layer 150, and the second raised portion 164 of the low dielectric layer 160.

[0134] As shown in Figures 7 to 9, the transchip 80 includes a resin layer 180 formed on the low dielectric layer 160. The resin layer 180 is in contact with the low dielectric layer 160. The resin layer 180 is formed from a material including, for example, polyimide (PI). The resin layer 180 is a layer that relieves stress between the mold resin 110, the insulating layer 85, and the substrate 84. The outer surface of the resin layer 180 is flush with the outer surface of the low dielectric layer 160.

[0135] As shown in Figure 8, the thickness TD of the resin layer 180 is greater than the thickness TE of the low dielectric layer 160. In other words, the thickness TE of the low dielectric layer 160 is less than the thickness TD of the resin layer 180. The thickness TD of the resin layer 180 is greater than the thickness TRU of the top insulating layer 85U and greater than the thickness TP of the passivation layer 150.

[0136] As shown in Figures 3 and 4, the resin layer 180 is separated into an inner resin layer 181 and an outer resin layer 182 by a separation groove 183. In plan view, the separation groove 183 is formed to surround the transformers 40AA, 40AB, 40BA, and 40BB. Therefore, in plan view, the inner resin layer 181 includes a region that overlaps with the transformers 40AA, 40AB, 40BA, and 40BB. More specifically, as shown in Figure 7, in plan view, the inner resin layer 181 includes a region that overlaps with the dummy pattern 120. The inner resin layer 181 is also formed to surround a pair of adjacent second electrode pads 82 in the x-direction in plan view. The outer resin layer 182 includes the outer peripheral region of the low dielectric layer 160 in plan view. The outer resin layer 182 is also formed to surround a pair of adjacent first electrode pads 81 in the x-direction in plan view. Furthermore, in the separation groove 183, the surface 160s of the low dielectric layer 160 is exposed in the z direction from the resin layer 180. In plan view, the shape of the separation groove 183 is a rectangular annular shape with the x direction being the longer side and the y direction being the shorter side. In this embodiment, the separation groove 183 corresponds to a "groove that exposes the surface of the low dielectric layer".

[0137] As described above, in this embodiment, an uneven structure 190 is provided in the region between the first electrode pad 81 and the second electrode pad 82 on the surface 160s of the low dielectric layer 160. The uneven structure 190 in this embodiment consists of an inner resin layer 181, an outer resin layer 182, and a separation groove 183. More specifically, the uneven structure 190 is composed of a bonding surface between the low dielectric layer 160 and the molded resin 110, and a bonding surface between the resin layer 180 and the molded resin 110. More specifically, the uneven structure 190 is composed of a bonding surface between the low dielectric layer 160 and the molded resin 110 provided in the opening 184, a bonding surface between the inner resin layer 181 and the molded resin 110, a bonding surface between the resin layer 180 and the low dielectric layer 160 and the molded resin 110 in the separation groove 183, and a bonding surface between the outer resin layer 182 and the molded resin 110.

[0138] The separation grooves 183 may be provided in multiple locations, for example, spaced apart from each other. In this case, the number of irregularities in the uneven structure 190 increases, thus increasing the creepage distance between the first electrode pad 81 and the second electrode pad 82.

[0139] As shown in Figures 8 and 9, the resin layer 180 includes a first resin layer opening 184 located at a position overlapping with each first opening 171 in a plan view, and a second resin layer opening 185 located at a position overlapping with each second opening 172 in a plan view. In other words, the resin layer 180 includes a plurality of first resin layer openings 184 corresponding to a plurality of first openings 171, and a plurality of second resin layer openings 185 corresponding to a plurality of second openings 172.

[0140] The opening area of ​​the first resin layer opening 184 is larger than the opening area of ​​the first opening 171. The first resin layer opening 184 accommodates the first raised portion 173. In a plan view, the inner surface constituting the first resin layer opening 184 is located outward from the first raised portion 173. As a result, the first raised portion 173 is exposed from the resin layer 180 in the z direction. In other words, in a plan view, the portion of the surface 160s of the low dielectric layer 160 located within the first resin layer opening 184 is exposed from the first resin layer opening 184 in the z direction. The portion of the surface 160s of the low dielectric layer 160 located within the first resin layer opening 184 includes the first raised portion 173 and the portion surrounding it.

[0141] The opening area of ​​the second resin layer opening 185 is larger than the opening area of ​​the second opening 172. The second resin layer opening 185 accommodates the second raised portion 174. In a plan view, the inner surface constituting the first resin layer opening 184 is located outward from the second raised portion 174. As a result, the second raised portion 174 is exposed from the resin layer 180 in the z direction. In other words, in a plan view, the portion of the surface 160s of the low dielectric layer 160 located within the second resin layer opening 185 is exposed from the second resin layer opening 185 in the z direction. The portion of the surface 160s of the low dielectric layer 160 located within the second resin layer opening 185 includes the second raised portion 174 and the surrounding portion of the surface 160s of the low dielectric layer 160.

[0142] The first resin layer opening 184 communicates with the first dielectric layer opening 161, and the second resin layer opening 185 communicates with the second dielectric layer opening 162. In other words, each first electrode pad 81 is exposed to the trans tip 80 in the z direction through each first dielectric layer opening 161, each first protective layer opening 151, and each first resin layer opening 184. Each second electrode pad 82 is exposed to the trans tip 80 in the z direction through each second dielectric layer opening 162, each second protective layer opening 152, and each second resin layer opening 185.

[0143] The molding resin 110 of the gate driver 10 covers the transchip 80. More specifically, as shown in Figure 7, the molding resin 110 is formed to cover the resin layer 180. The resin layer 180 is formed to cover the passivation layer 150, the low dielectric layer 160, and the sides of the resin layer 180. The molding resin 110 is embedded in the separation groove 183. As a result, the molding resin 110 is in contact with the surface 160s of the low dielectric layer 160 within the separation groove 183. The molding resin 110 is filled into the separation groove 183. As a result, the molding resin 110 is in contact with both the outer surface of the inner resin layer 181 and the inner surface of the outer resin layer 182 of the resin layer 180 that constitutes the separation groove 183.

[0144] Furthermore, the mold resin 110 has entered each first resin layer opening 184 and each second resin layer opening 185. As a result, the mold resin 110 is in contact with the surface 160s of the low dielectric layer 160 within each first resin layer opening 184 and each second resin layer opening 185. The mold resin 110 is filling each first resin layer opening 184 and each second resin layer opening 185. As a result, the mold resin 110 is in contact with the first inner surface of the resin layer 180 constituting each first resin layer opening 184 and the second inner surface of the resin layer 180 constituting each second resin layer opening 185.

[0145] Furthermore, the molded resin 110 is contained within each of the first openings 171 and each of the second openings 172. As a result, the molded resin 110 is in contact with the first electrode pad 81 through the first opening 171 and with the second electrode pad 82 through the second opening 172.

[0146] In this embodiment, the molded resin 110 enters each first opening 171 and is in contact with the pair of first electrode pads 81 exposed from each first opening 171. The molded resin 110 is filled into each first opening 171. As a result, the molded resin 110 is in contact with the first inner surface of the first insulating layer opening 85Ua, the first inner surface of the first protective layer opening 151, and the first inner surface of the first dielectric layer opening 161, which constitute each first opening 171, within each first opening 171.

[0147] In this embodiment, the molded resin 110 enters each second opening 172 and is in contact with the pair of second electrode pads 82 exposed from each second opening 172. The molded resin 110 fills each second opening 172. As a result, the molded resin 110 is in contact with the second inner surface of the second insulating layer opening 85Ub, the second inner surface of the second protective layer opening 152, and the second inner surface of the second dielectric layer opening 162, which constitute each second opening 172, within each second opening 172.

[0148] Next, the relationship between the dielectric constants of the insulating layer 85, the passivation layer 150, the low dielectric layer 160, the resin layer 180, and the molding resin 110 will be explained. In this embodiment, the insulating layer 85 is made of a material containing SiO2, so the dielectric constant of the insulating layer 85 is about 4.1. The passivation layer 150 is made of a material containing SiN, so the dielectric constant of the passivation layer 150 is about 7.0. In other words, the dielectric constant of the passivation layer 150 is higher than that of the insulating layer 85.

[0149] In this embodiment, the resin layer 180 is made of a material containing polyimide, so the dielectric constant of the resin layer 180 is about 2.9. Furthermore, in this embodiment, since the mold resin 110 is made of a material containing epoxy resin, the dielectric constant of the mold resin 110 is approximately 3.9. In other words, the dielectric constant of the mold resin 110 is lower than that of the passivation layer 150. The dielectric constant of the mold resin 110 is higher than that of the resin layer 180.

[0150] The low dielectric constant of the low dielectric layer 160 is lower than that of the passivation layer 150. For example, the dielectric constant of the low dielectric layer 160 is less than or equal to that of the insulating layer 85. More specifically, the dielectric constant of the low dielectric layer 160 is lower than that of the first insulating layer 85A of the insulating layer 85. The dielectric constant of the low dielectric layer 160 is less than or equal to that of the second insulating layer 85B of the insulating layer 85. The dielectric constant of the low dielectric layer 160 may also be less than or equal to that of the molding resin 110.

[0151] The low dielectric layer 160 may be formed from a material containing SiO2, for example. Thus, the low dielectric layer 160 may be formed from the same material as the second insulating layer 85B of the insulating layer 85. Also, the dielectric constant of the low dielectric layer 160 may be lower than that of the insulating layer 85. The low dielectric layer 160 may be formed from a Low-K film. As the Low-K film, for example, an appropriate selection can be made from SiOC (carbon-doped silicon oxide film), Siof (fluorine-doped silicon oxide film), a porous film, etc. When the low dielectric layer 160 is made of Siof (SiOC), the dielectric constant of the low dielectric layer 160 is 2.5 or more and 3.0 or less. When the low dielectric layer 160 is made of Siof (SiOF), the dielectric constant of the low dielectric layer 160 is 3.4 or more and 3.8 or less. When the low dielectric layer 160 is made of a porous film, the dielectric constant of the low dielectric layer 160 is less than 2.5. In this way, by using a Low-K film for the low-dielectric layer 160, the dielectric constant of the low-dielectric layer 160 can be made lower than that of the insulating layer 85 and the molding resin 110.

[0152] An example of a manufacturing method for the gate driver 10 of this embodiment will be outlined below. First, a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 are prepared. The manufacturing method for the transformer chip 80 mainly comprises the steps of preparing a substrate 84, forming an insulating layer 85 on the substrate 84, embedding a plurality of transformers 40 and a plurality of dummy patterns 120 in the insulating layer 85, forming a plurality of first electrode pads 81 and a plurality of second electrode pads 82, embedding a shield electrode 86, forming a passivation layer 150, forming a low dielectric layer 160, forming each first opening 171 and each second opening 172, and forming a resin layer 180.

[0153] In the process of forming each first opening 171 and each second opening 172, a passivation layer 150 is laminated on the uppermost insulating layer 85U of the multiple insulating layers 85. Next, a low dielectric layer 160 is laminated on the passivation layer 150. Then, each first opening 171 and each second opening 172 are formed so as to penetrate the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160 in the z direction.

[0154] In the process of forming the resin layer 180, the resin layer 180 is formed with each first opening 171 and each second opening 172 masked. Subsequently, the masks for each first opening 171 and each second opening 172 are removed. Through these steps, the trans tip 80 is manufactured.

[0155] Next, a lead frame is prepared, on which a low-pressure die pad 91 and low-pressure lead 92, and a high-pressure die pad 101 and high-pressure lead 102 are formed. In this step, the low-pressure lead 92 and high-pressure lead 102 are integrated with the lead frame.

[0156] Next, the low-voltage circuit chip 60 and the transformer chip 80 are die-bonded to the low-voltage die pad 91, for example, and the high-voltage circuit chip 70 is die-bonded to the high-voltage die pad 101, for example. Subsequently, a wire bonding apparatus is used to form wires W connecting the electrode pads 61, 63 of the low-voltage circuit chip 60 to the low-voltage lead 92, wires W connecting the second electrode pad 62 of the low-voltage circuit chip 60 to the first electrode pad 81 of the transformer chip 80, wires W connecting the second electrode pad 82 of the transformer chip 80 to the first electrode pad 71 of the high-voltage circuit chip 70, and wires W connecting the electrode pads 72, 73 of the high-voltage circuit chip 70 to the high-voltage lead 102.

[0157] Next, a sealing layer is formed to seal at least the low-pressure die pad 91, the high-pressure die pad 101, the low-pressure circuit chip 60, the high-pressure circuit chip 70, the transformer chip 80, and the multiple wires W. The sealing layer is made of, for example, a black epoxy resin and is formed by compression molding.

[0158] Next, the sealing layer and lead frame are cut. This forms the mold resin 110, the low-pressure lead 92, and the high-pressure lead 102. Through these steps, the gate driver 10 is manufactured.

[0159] (Operation of the first embodiment) The operation of the gate driver 10 in this embodiment will now be described. In the following description, a transformer chip in which the low dielectric layer 160 is omitted from the transformer chip 80 of the gate driver 10 will be referred to as the comparative transformer chip.

[0160] In the comparative example transchip, the passivation layer 150 has a portion that is exposed from the resin layer 180. In other words, in the comparative example transchip, a portion is formed where the passivation layer 150 and the mold resin 110 are in contact. When the transchip 80 is sealed with the mold resin 110, a void exists within the mold resin 110 during the molding process. This void may be located at the boundary between the mold resin 110 and the passivation layer 150. In such a state, if a high voltage is applied to the comparative example transchip, partial discharge may occur through the void located at the boundary between the mold resin 110 and the passivation layer 150. As a result of this partial discharge, creepage discharge may occur along the boundary between the mold resin 110 and the passivation layer 150. Regarding such discharge, the inventors of the present invention have found that the higher the dielectric constant of the layer in contact with the mold resin 110, the lower the starting voltage for partial discharge becomes, and the more likely partial discharge and creepage discharge are to occur. In other words, in the comparative example transchip, the passivation layer 150 in contact with the mold resin 110 is made of a material containing SiN, and its dielectric constant is 7.0, which is higher than that of the other layers. As a result, the initiation voltage of partial discharge is lower, and partial discharge and creepage discharge are more likely to occur.

[0161] Therefore, the inventors of the present invention have found that the passivation layer 150 can be covered with a layer having a lower dielectric constant than the passivation layer 150, thereby creating a structure in which the passivation layer 150 does not come into contact with the molded resin 110. In this embodiment, the transchip 80 is provided with a low dielectric layer 160 that covers the passivation layer 150. The low dielectric layer 160 is a layer that comes into contact with the molded resin 110. This suppresses contact between the molded resin 110 and the passivation layer 150. As a result, it is possible to suppress the occurrence of partial discharge, and consequently creepage discharge, due to air gaps existing at the boundary between the molded resin 110 and the passivation layer 150. In addition, the low dielectric layer 160 has a lower dielectric constant than the passivation layer 150. Therefore, the initiation voltage of partial discharge at the boundary between the low dielectric layer 160 and the molding resin 110 is higher than the initiation voltage of partial discharge at the boundary between the passivation layer 150 and the molding resin 110. Consequently, it is possible to suppress the occurrence of partial discharge, and consequently creepage discharge, due to voids present at the boundary between the molding resin 110 and the low dielectric layer 160.

[0162] (Effects of the first embodiment) The gate driver 10 of this embodiment provides the following benefits. (1-1) The transchip 80 comprises first coils 41A, 41B and second coils 42A, 42B, a first electrode pad 81 connected to the first coils 41A, 41B, a second electrode pad 82 provided at a position spaced apart from the first electrode pad 81 in a plan view and connected to the second coils 42A, 42B, a passivation layer 150 formed on the surface 85s of the insulating layer 85 to protect the insulating layer 85, and a low dielectric layer 160 formed on the surface 150s of the passivation layer 150 and having a lower dielectric constant than the passivation layer 150. The low dielectric layer 160 is covered with a mold resin 110.

[0163] With this configuration, the low dielectric layer 160 is interposed between the passivation layer 150 and the molded resin 110, thereby suppressing contact between the passivation layer 150 and the molded resin 110. This suppresses the occurrence of partial discharge, and consequently surface discharge, due to voids present at the boundary between the molded resin 110 and the passivation layer 150. Therefore, the reliability of the transchip 80 can be improved.

[0164] (1-2) The dielectric constant of the low dielectric layer 160 is less than or equal to the dielectric constant of the mold resin 110. This configuration allows for a higher starting voltage for partial discharge at the boundary between the low dielectric layer 160 and the molded resin 110. This suppresses the occurrence of partial discharge, and consequently surface discharge, caused by voids at the boundary between the low dielectric layer 160 and the molded resin 110.

[0165] (1-3) The thickness TE of the low dielectric layer 160 is less than or equal to the thickness TP of the passivation layer 150. This configuration makes it possible to suppress an increase in the z-direction dimension of the transchip 80.

[0166] (1-4) When the gate driver 10 is driven, a high voltage is applied to each second electrode pad 82 in the transchip 80, so a high electric field is formed around each second electrode pad 82. Therefore, although the low dielectric layer 160 suppresses the occurrence of creepage discharge, creepage discharge is more likely to occur at the boundary between the low dielectric layer 160 and the mold resin 110 around each second electrode pad 82 compared to other boundary areas. If creepage discharge occurs and the creepage discharge moves from the second electrode pad 82 to the first electrode pad 81, in a configuration where the creepage distance between the second electrode pad 82 and the first electrode pad 81 is short, the second electrode pad 82 and the first electrode pad 81 may become electrically connected.

[0167] Therefore, in this embodiment, an uneven structure 190 is provided between the first electrode pad 81 and the second electrode pad 82 on the surface 160s of the low dielectric layer 160. This allows for a larger creepage distance between the first electrode pad 81 and the second electrode pad 82. Consequently, even if a creepage discharge occurs at the boundary between the low dielectric layer 160 and the mold resin 110, it becomes difficult for the first electrode pad 81 and the second electrode pad 82 to conduct electricity.

[0168] (1-5) In a plan view, a dummy pattern 120 is provided around the second coils 42A and 42B. With this configuration, the electric field concentration on the second coils 42A and 42B is mitigated, thereby suppressing the occurrence of partial discharge and, consequently, surface discharge caused by the void at the boundary between the low dielectric layer 160 and the molded resin 110 near the second coils 42A and 42B.

[0169] (1-6) The gate driver 10 includes a low-voltage circuit 20 configured to operate when a first voltage V1 is applied, a high-voltage circuit 30 configured to operate when a second voltage V2 higher than the first voltage V1 is applied, and a transformer chip 80. The low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer chip 80 and are configured to transmit signals via the transformer chip 80. The transchip 80 comprises first coils 41A, 41B and second coils 42A, 42B; first electrode pads 81 connected to the first coils 41A, 41B; second electrode pads 82 located spaced apart from the first electrode pads 81 in a plan view and connected to the second coils 42A, 42B; a passivation layer 150 formed on the surface 85s of the insulating layer 85 to protect the insulating layer 85; and a low dielectric layer 160 formed on the surface 150s of the passivation layer 150, having a lower dielectric constant than the surface 150s of the passivation layer 150. The low dielectric layer 160 is covered with a molding resin 110. With this configuration, the same effects as in (1-1) above can be obtained, and a highly reliable gate driver 10 can be obtained.

[0170] (1-7) As a configuration in which the gate driver 10 includes a transformer 40, for example, a configuration in which the low-voltage circuit chip includes the low-voltage circuit 20 and the transformer 40, or a configuration in which the high-voltage circuit chip includes the high-voltage circuit 30 and the transformer 40 can be considered. However, in these configurations, if the circuit configuration of the low-voltage circuit 20 or the high-voltage circuit 30 is changed, the entire chip must be changed, which increases the cost when manufacturing multiple types of gate drivers.

[0171] In this embodiment, the transformer 40 is included in a transformer chip 80, which is a separate chip from the low-voltage circuit chip 60 and the high-voltage circuit chip 70. In other words, a chip dedicated to the transformer 40 is provided. Therefore, a common transformer chip 80 can be used for different low-voltage circuits 20 and high-voltage circuits 30. This reduces costs when manufacturing multiple types of gate drivers 10, at least one of which is different from the low-voltage circuit 20 and the high-voltage circuit 30.

[0172] [Second Embodiment] Referring to Figure 10, the gate driver 10 of the second embodiment will be described. In the gate driver 10 of this embodiment, the shape of the low dielectric layer 160 of the trans chip 80 is different from that of the gate driver 10 of the first embodiment. In the following description, the differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0173] As shown in Figure 10, the low dielectric layer 160 of this embodiment further comprises a first inner surface cover portion 165, a second inner surface cover portion 166, and an outer surface cover portion 167, compared to the low dielectric layer 160 of the first embodiment. In this embodiment, in a plan view, the portion of the low dielectric layer 160 that covers the passivation layer 150 is designated as the main cover portion 168. In this embodiment, the low dielectric layer 160 is an integrated unit comprising the first inner surface cover portion 165, the second inner surface cover portion 166, the outer surface cover portion 167, and the main cover portion 168.

[0174] In this embodiment, the first opening 171 consists of the first protective layer opening 151 of the passivation layer 150 and the first insulating layer opening 85Ua of the uppermost insulating layer 85U. The second opening 172 consists of the second protective layer opening 152 of the passivation layer 150 and the second insulating layer opening 85Ub of the uppermost insulating layer 85U. The uppermost insulating layer 85U has a first inner surface that constitutes the first insulating layer opening 85Ua and a second inner surface that constitutes the second insulating layer opening 85Ub. The passivation layer 150 has a first inner surface that constitutes the first protective layer opening 151 and a second inner surface that constitutes the second protective layer opening 152. Here, in this embodiment, the first inner surface of the first protective layer opening 151 corresponds to the "first inner surface of the first opening," and the second inner surface of the second protective layer opening 152 corresponds to the "second inner surface of the second opening."

[0175] The first inner surface cover portion 165 is formed on the first inner surface of the first protective layer opening 151. In other words, the first inner surface cover portion 165 covers the first inner surface of the first protective layer opening 151. In this embodiment, the leading edge of the first inner surface cover portion 165 is in contact with the first electrode pad 81. That is, it can also be said that the first inner surface cover portion 165 is formed on the first inner surface of the first opening 171. In this embodiment, the leading edge of the first inner surface cover portion 165 is in contact with the first electrode pad 81.

[0176] As described above, in this embodiment, the first dielectric layer opening 161 forms an opening that opens the first electrode pad 81 from the z direction. The first dielectric layer opening 161 is composed of the first inner surface cover portion 165. Although not shown, a wire W is connected to the first electrode pad 81 through the first dielectric layer opening 161.

[0177] The second inner surface cover portion 166 is formed on the second inner surface of the second protective layer opening 152. In other words, the second inner surface cover portion 166 covers the second inner surface of the second protective layer opening 152. In this embodiment, the leading edge of the second inner surface cover portion 166 is in contact with the second electrode pad 82. That is, it can also be said that the second inner surface cover portion 166 is formed on the second inner surface of the second opening 172.

[0178] As described above, in this embodiment, the second dielectric layer opening 162 forms an opening that opens the second electrode pad 82 from the z direction. The second dielectric layer opening 162 is composed of the second inner surface cover portion 166. Although not shown, a wire W is connected to the second electrode pad 82 through the second dielectric layer opening 162.

[0179] The outer surface cover portion 167 is formed on the outer surface of the passivation layer 150 located in the outer region 88. In other words, the outer surface cover portion 167 covers the outer surface of the passivation layer 150 located in the outer region 88. The outer surface of the passivation layer 150 is the surface that constitutes the stepped portion 88a. That is, the outer surface cover portion 167 covers the entire outer surface of the passivation layer 150. For this reason, it can also be said that the low dielectric layer 160 covers the end face of the passivation layer 150.

[0180] Thus, in this embodiment, the low dielectric layer 160 prevents the passivation layer 150 from coming into contact with the mold resin 110. This suppresses the formation of a gap between the passivation layer 150 and the mold resin 110, thereby suppressing the occurrence of partial discharge caused by this gap.

[0181] Furthermore, in this embodiment, the leading edge of the outer surface cover portion 167 is in contact with the surface of the insulating layer 85 one layer below the uppermost insulating layer 85U among the multiple insulating layers 85. In other words, the outer surface cover portion 167 covers the entire outer surface of the uppermost insulating layer 85U.

[0182] An example of a manufacturing method for the gate driver 10 of this embodiment will be outlined. In the manufacturing method of the gate driver 10 of this embodiment, the methods for forming each of the openings 171, 172 of the trans tip 80 and the low dielectric layer 160 differ from those of the manufacturing method of the gate driver 10 of the first embodiment. The methods for forming each of the openings 171, 172 of the trans tip 80 and the low dielectric layer 160 will be described below.

[0183] In the process of forming the openings 171 and 172 of the transchip 80, unlike the first embodiment, the passivation layer 150 is formed on the uppermost insulating layer 85U, and then the openings 171 and 172 are formed by penetrating the passivation layer 150.

[0184] Next, a low dielectric layer 160 is formed on the passivation layer 150. In this case, a portion of the low dielectric layer 160 is formed within each opening 171, 172. Subsequently, the low dielectric layer 160 formed within each opening 171, 172 is removed so that each electrode pad 81, 82 is exposed in the z direction. This forms the first inner surface cover portion 165 and the second inner surface cover portion 166.

[0185] Furthermore, a portion of the low dielectric layer 160 is formed in the stepped portion 88a of the outer region 88. Subsequently, the low dielectric layer 160 formed on the uppermost insulating layer 85 of the multiple insulating layers 85 is removed from the low dielectric layer 160 formed in the stepped portion 88a. This forms the outer surface cover portion 167. Through the above steps, the low dielectric layer 160 is formed.

[0186] (Effects of the second embodiment) According to the gate driver 10 of this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0187] (2-1) The low dielectric layer 160 is formed on both the first inner surface constituting the first opening 171 and the second inner surface constituting the second opening 172. The low dielectric layer 160 covers the end face of the passivation layer 150.

[0188] With this configuration, since the passivation layer 150 constituting each opening 171, 172 and the outer surface of the passivation layer 150 are covered by the low dielectric layer 160, direct contact between the passivation layer 150 and the molded resin 110 can be further suppressed. Therefore, when a high voltage is applied to the transformer chip 80, partial discharge and creepage discharge can be further suppressed.

[0189] [Third Embodiment] The gate driver 10 of the third embodiment will be described with reference to Figures 11 to 13. In the gate driver 10 of this embodiment, the insulation structure of the transformer is different from that of the gate driver 10 of the first embodiment. In the following description, the differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted. In Figure 13, for convenience, the shape of the coils, dummy patterns, and shield electrodes of each transformer are simplified compared to the first embodiment, and the connection structure between each electrode pad and coil is omitted.

[0190] As shown in Figure 11, the gate driver 10 of this embodiment has a double insulation structure with multiple transformers. Specifically, transformer 40A has a first transformer 43A and a second transformer 44A connected in series with each other. Transformer 40B has a first transformer 43B and a second transformer 44B connected in series with each other. In this way, since each of transformers 40A and 40B has a double insulation structure, the dielectric strength of the gate driver 10 is higher than that of the first and second embodiments, for example, to about 7500 Vrms.

[0191] The first transformer 43A is electrically connected to the low-voltage circuit 20. The first transformer 43A includes a first coil 45A and a second coil 46A that is insulated from the first coil 45A and is magnetically coupled to it.

[0192] The second transformer 44A is electrically connected to the high-voltage circuit 30. The second transformer 44A connects the first transformer 43A to the high-voltage circuit 30. The second transformer 44A has a first coil 47A and a second coil 48A that is insulated from the first coil 47A and is magnetically coupled to it.

[0193] The first coil 45A is electrically connected to the low-voltage circuit 20 by the low-voltage signal line 21A, while also being connected to the ground of the low-voltage circuit 20. In other words, the first end of the first coil 45A is electrically connected to the low-voltage circuit 20, and the second end of the first coil 45A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the first coil 45A becomes the first reference potential. The first reference potential is, for example, 0V.

[0194] The second coil 46A is connected to the first coil 47A of the second transformer 44A. In one example, the second coil 46A and the first coil 47A are connected to each other in an electrically floating state. That is, the first end of the second coil 46A is connected to the first end of the first coil 47A, and the second end of the second coil 46A is connected to the second end of the first coil 47A. In this way, the second coil 46A and the first coil 47A act as relay coils that relay the transmission of the set signal from the first coil 45A to the second coil 48A.

[0195] The second coil 48A is electrically connected to the high-voltage circuit 30 by the high-voltage signal line 31A, while also being connected to the ground of the high-voltage circuit 30. In other words, the first end of the second coil 48A is connected to the high-voltage circuit 30, and the second end of the second coil 48A is connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the second coil 48A becomes the second reference potential. The second reference potential fluctuates with the driving of the inverter device 500, and can be, for example, 600V or higher.

[0196] Furthermore, the shapes of the coils 45A and 46A of the first transformer 43A and the coils 47A and 48A of the second transformer 44A in a plan view are elliptical spirals, similar to the first embodiment (see Figure 12). The winding directions of the coils 45A and 46A of the first transformer 43A and the winding directions of the coils 47A and 48A of the second transformer 44A are opposite. Note that the winding directions of each coil 45A, 46A, 47A, and 48A can be arbitrarily changed. In one example, the winding directions of the coils 45A and 46A and the winding directions of the coils 47A and 48A may be the same.

[0197] The first transformer 43B of transformer 40B has a first coil 45B electrically connected to the low-voltage circuit 20, and a second coil 46B that is insulated from the first coil 45B and can be magnetically coupled.

[0198] The second transformer 44B of transformer 40B has a first coil 47B electrically connected to the high-voltage circuit 30, and a second coil 48B that is insulated from the first coil 47B and can be magnetically coupled. Since transformer 40B is the same as transformer 40A, a detailed explanation is omitted.

[0199] Figure 12 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Figure 11 shows a simplified circuit configuration of the gate driver 10, so the number of external terminals of the gate driver 10 in Figure 12 is greater than the number of external terminals of the gate driver 10 in Figure 11. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 11). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 of Figure 12 is greater than the number of signal lines of the gate driver 10 in Figure 11.

[0200] As shown in Figure 12, the transformer chip 80 includes first transformers 43A, 43B and second transformers 44A, 44B, and more specifically, these transformers 43A, 44A, 43B, and 44B are packaged together. In the transformer chip 80, the first transformer 43A and the second transformer 44A are aligned with each other in the x-direction and spaced apart in the y-direction. The first transformer 43B and the second transformer 44B are aligned with each other in the x-direction and spaced apart in the y-direction. The first transformer 43A and the first transformer 43B are aligned with each other in the y-direction and spaced apart in the x-direction. It can also be said that the first transformer 43A and the second transformer 44A are spaced apart in the direction in which each chip 60, 70, and 80 are arranged. The second transformer 44A and the second transformer 44B are aligned with each other in the y-direction and spaced apart in the x-direction. It can also be said that the first transformer 43B and the second transformer 44B are arranged spaced apart from each other in the direction in which the chips 60, 70, and 80 are arranged.

[0201] The first transformers 43A and 43B are positioned closer to the low-voltage circuit chip 60 than the second transformers 44A and 44B of the transformer chip 80. As a result, the conductive path between the low-voltage circuit 20 and the first transformers 43A and 43B, which are electrically connected to the low-voltage circuit chip 60, can be shortened because they are positioned close to the low-voltage circuit chip 60.

[0202] The second transformers 44A and 44B are positioned closer to the high-voltage circuit chip 70 than the first transformers 43A and 43B of the transformer chip 80. As a result, the conductive path between the high-voltage circuit 30 and the second transformers 44A and 44B, which are electrically connected to the high-voltage circuit chip 70, can be shortened because they are positioned closer to the high-voltage circuit chip 70.

[0203] As shown in Figure 12, the arrangement of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70, and the connection of the wires W, are the same as in the first embodiment. The arrangement of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 with respect to the low-voltage die pad 91 and the high-voltage die pad 101 is the same as in the first embodiment.

[0204] Referring to Figure 13, an example of the internal structure of the transformer chip 80 will be described. Figure 13 shows a schematic cross-sectional structure of transformer 40A of the transformer chip 80. Since transformer 40B has the same configuration as transformer 40A, a detailed explanation of it will be omitted. In the following explanation, the direction from the back surface 80r of the transformer chip 80 towards the main surface 80s of the chip will be considered upward, and the direction from the main surface 80s towards the back surface 80r of the chip will be considered downward.

[0205] As shown in Figure 13, the first transformer 43A and the second transformer 44A are embedded within the insulating layer 85. The first transformer 43A and the second transformer 44A are also spaced apart from each other in the direction in which the chips 60, 70, and 80 are arranged. Both the first transformer 43A and the second transformer 44A are located in the inner region 87 of the insulating layer 85.

[0206] The first coil 45A and the second coil 46A of the first transformer 43A are arranged facing each other in the z direction via an insulating layer 85. In this embodiment, the first coil 45A and the second coil 46A are arranged facing each other in the z direction via a plurality of insulating layers 85. Each coil 45A, 46A is configured as a conductive layer embedded in a single insulating layer 85, similar to the first embodiment.

[0207] In the z-direction, the second coil 46A is located further from the substrate 84 than the first coil 45A. In other words, the second coil 46A is located above the first coil 45A. Also, the first coil 45A is located closer to the substrate 84 than the second coil 46A in the z-direction.

[0208] The first coil 47A and the second coil 48A of the second transformer 44A are positioned opposite each other in the z direction via an insulating layer 85. Each coil 47A and 48A, like each coil 45A and 46A, is configured as a conductive layer embedded within a single insulating layer 85. In the z direction, the first coil 47A is located further from the substrate 84 than the second coil 48A. In other words, the first coil 47A is located above the second coil 48A. Also, the second coil 48A is located closer to the substrate 84 than the first coil 47A in the z direction.

[0209] The positions of the first coils 45A, 47A and the second coils 46A, 48A within the transformer chip 80 are set so that the dielectric strength of the transformer chip 80 is a preset dielectric strength.

[0210] The distance D11 between the first coil 45A and the second coil 46A is greater than the distance D12 between the first coil 47A and the second coil 48A. This suppresses dielectric breakdown caused by a short circuit between the first coil 45A and the second coil 46A. In one example, the distance D11 is more than twice the distance D12. However, it is not limited to this, and the distance D11 may be less than twice the distance D12.

[0211] In this embodiment, the second coil 46A and the first coil 47A are positioned in the same location in the z-direction. On the other hand, in the z-direction, the second coil 48A is located further away from the substrate 84 (i.e., higher) than the first coil 45A. As a result, the distance D11 is greater than the distance D12.

[0212] In this case, viewed from the y-direction, the second coil 48A is positioned between the first coil 45A and the second coil 46A in the z-direction. That is, the distance D14 between the second coil 48A and the substrate 84 is greater than the distance D13 between the first coil 45A and the substrate 84. This allows for a larger distance D14 between the second coil 48A, which is prone to high voltage application, and the substrate 84, thereby improving the dielectric strength of the transformer chip 80. In one example, the distance D14 is more than twice the distance D13. However, it is not limited to this, and the distance D14 may be less than twice the distance D13.

[0213] Since the second coil 48A is electrically connected to the high-voltage die pad 101 (see Figure 12), the second end of the second coil 48A and the substrate 84 may be at different potentials. For this reason, the second coil 48A and the substrate 84 need to be insulated. In other words, by increasing the distance D14 between the second coil 48A and the substrate 84, the dielectric strength of the transformer chip 80 can be improved.

[0214] In one example, the distance D14 between the second coil 48A and the substrate 84 is greater than or equal to the distance D12 between the first coil 47A and the second coil 48A. This allows for a larger distance D14 while suppressing an increase in the z-direction dimensions of the transformer chip 80, thereby improving the dielectric strength of the transformer chip 80. Furthermore, since the voltage applied between the first coil 45A and the second coil 46A tends to be lower than the voltage applied between the second coil 48A and the substrate 84, the dielectric strength of the transformer chip 80 can be ensured even if the distance D12 is small.

[0215] In this embodiment, distance D14 is greater than distance D12. In one example, distance D14 is more than twice the distance D12. However, it is not limited to this, and distance D14 may be less than twice the distance D12.

[0216] In another example, the distance D14 between the second coil 48A and the substrate 84 is greater than or equal to the distance D11 between the first coil 45A and the second coil 46A. This allows for a larger distance D14 between the second coil 48A, which is prone to high voltage application, and the substrate 84, thereby improving the dielectric strength of the transformer chip 80. In this embodiment, the distance D14 is equal to the distance D11.

[0217] Due to this relationship between distances D11 and D14, the first coil 45A is located closer to the substrate 84 than the second coil 48A. Since both the first coil 45A and the substrate 84 are electrically connected to the low-voltage die pad 91, the ground of the first coil 45A and the substrate 84 are at the same potential. Therefore, even if the first coil 45A is placed close to the substrate 84, a decrease in the dielectric strength of the transformer chip 80 can be suppressed. In this embodiment, the distance D13 between the first coil 45A and the substrate 84 is smaller than the distance D11 between the first coil 45A and the second coil 46A. Distance D13 is less than or equal to half of distance D11. However, it is not limited to this, and distance D13 may be greater than half of distance D11.

[0218] In another example, the distance D15 between the second coil 48A and the first coil 45A is greater than or equal to the distance D14 between the second coil 48A and the substrate 84. Distance D15 is the shortest distance between the second coil 48A and the first coil 45A. This makes dielectric breakdown due to a short circuit between the first coil 45A and the second coil 48A less likely to occur. Therefore, the dielectric strength of the transformer chip 80 can be improved.

[0219] In this embodiment, distance D15 is equal to distance D14. Distance D15 is greater than or equal to distance D11. In this embodiment, since distance D14 is equal to distance D11, distance D15 is equal to distance D11.

[0220] The distance between the second coil 48A and the first coil 47A in the y-direction is set according to the distance D15 between the second coil 48A and the first coil 45A. Specifically, the central axis J1 of the first coil 45A coincides with the central axis J2 of the second coil 46A, and the central axis J3 of the first coil 47A coincides with the central axis J4 of the second coil 48A. Therefore, the x-direction and y-direction positions of the first coil 45A and the second coil 48A are set along with the distance D15. In a plan view, the x-direction and y-direction positions of the second coil 46A and the first coil 47A are the same as the x-direction and y-direction positions of the first coil 45A and the second coil 48A, so the distance between the second coil 48A and the first coil 47A in the y-direction is set.

[0221] Dummy patterns may be provided around the second coils 46A and 46B of the first transformer 43A and around the second coils 48A and 48B of the second transformer 44A. This suppresses electric field concentration on the second coils 46A, 46B, 48A, and 48B. In the following description, the dummy patterns provided around the second coils 46A and 46B will be referred to as dummy pattern 120A, and the dummy patterns provided around the second coils 48A and 48B will be referred to as dummy pattern 120B. The configuration of these dummy patterns 120A and 120B is the same as the configuration of dummy pattern 120 in the first embodiment. The relationship between the second coils 46B and 48B and the dummy patterns 120A and 120B is the same as the relationship between the second coils 46A and 48A and the dummy patterns 120A and 120B. Therefore, the following explanation will describe the relationship between the second coils 46A and 48A and the dummy patterns 120A and 120B, while omitting the explanation of the relationship between the second coils 46B and 48B and the dummy patterns 120A and 120B.

[0222] Dummy pattern 120A is positioned in the z-direction aligned with the second coil 46A, and dummy pattern 120B is positioned in the z-direction aligned with the second coil 48A. Therefore, the distance D31 between dummy pattern 120A and the first coil 45A in the z-direction is greater than the distance D12 between the first coil 45A and the second coil 46A. The distance D32 between dummy pattern 120B and the substrate 84 in the z-direction is greater than or equal to the distance D12 between the first coil 47A and the second coil 48A in the z-direction. In this embodiment, distance D32 is greater than distance D12.

[0223] Since the second coil 48A is positioned closer to the substrate 84 than the second coil 46A, the dummy pattern 120B is positioned closer to the substrate 84 than the dummy pattern 120A. Also, since the second coil 48A is positioned further from the substrate 84 than the first coil 45A, it can be said that the dummy pattern 120B is positioned further from the substrate 84 than the first coil 45A in the z direction. It can also be said that the dummy pattern 120B is positioned between the first coil 45A and the second coil 46A in the z direction.

[0224] The distance D15 between the first coil 45A and the second coil 48A is greater than or equal to the distance D32 between the dummy pattern 120B and the substrate 84 in the z-direction. In this embodiment, the distance D15 is equal to the distance D32. Alternatively, the distance D15 may be greater than or equal to the distance D31 between the dummy pattern 120A and the first coil 45A in the z-direction.

[0225] In this embodiment, the dummy pattern 120B is provided around the coil (second coil 48A) that is further from the passivation layer 150 (chip main surface 80s) among the first coil 47A and the second coil 48A. However, the formation position of the dummy pattern 120B is not limited to this. For example, the dummy pattern 120B may be provided around the first coil 47A. In other words, the dummy pattern 120B may be provided around the coil (first coil 47A) that is closer to the passivation layer 150 (chip main surface 80s) among the first coil 47A and the second coil 48A.

[0226] On one of the multiple insulating layers 85, below the uppermost insulating layer 85U, are multiple first electrode pads 81, multiple second electrode pads 82, and multiple connecting wires 83. Each connecting wire 83 connects the first transformer 43A (43B) and the second transformer 44A (44B), and is made of, for example, Al or Cu. Each connecting wire 83 is covered by, for example, the uppermost insulating layer 85U. Each first electrode pad 81 is positioned in the y-direction opposite the second transformer 44A to the first transformer 43A. Each second electrode pad 82 is positioned in the y-direction opposite the first transformer 43A to the second transformer 44A.

[0227] The multiple connection wires 83 include a first connection wire connecting the second coil 46A of the first transformer 43A and the first coil 47A of the second transformer 44A, and a second connection wire connecting the second coil 46B of the first transformer 43B and the first coil 47B of the second transformer 44B. Therefore, compared to a configuration in which the second coil 46A and the first coil 47A are connected using wire W, and a configuration in which the second coil 46B and the first coil 47B are connected using wire W, both the distance between the second coil 46A and the first coil 47A and the distance between the second coil 46B and the first coil 47B can be reduced.

[0228] On the uppermost insulating layer 85U, a passivation layer 150, a low dielectric layer 160, and a resin layer 180 are laminated in the same order as in the first embodiment. The passivation layer 150 is formed to cover all of the transformers 40A, 40B and dummy patterns 120A, 120B in a plan view. The low dielectric layer 160 is formed to cover the entire passivation layer 150 in a plan view, similar to the first embodiment. In other words, the low dielectric layer 160 is formed to cover all of the transformers 40A, 40B, dummy patterns 120A, 120B, and each connecting wire 83 in a plan view.

[0229] (Effects of the third embodiment) According to the gate driver 10 of this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0230] (3-1) Transformer 40A has a first transformer 43A and a second transformer 44A connected in series with each other. Transformer 40B has a first transformer 43B and a second transformer 44B connected in series with each other. With this configuration, the signal line transmitting the set signal has a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30 due to the first transformer 43A and the second transformer 44A, and the signal line transmitting the reset signal has a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30 due to the first transformer 43B and the second transformer 44B, thereby improving the dielectric strength of the gate driver 10.

[0231] [Fourth Embodiment] The gate driver 10 of the third embodiment will be described with reference to Figures 14 and 15. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment in that the insulating structure has been changed from one using a transformer 40 to one using a capacitor 50. In the following description, the differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0232] As shown in Figure 14, the capacitor 50, which serves as an insulating structure to electrically isolate the low-voltage circuit 20 from the high-voltage circuit 30, has a capacitor 50A connected to a signal line that transmits a set signal and a capacitor 50B connected to a signal line that transmits a reset signal. Both capacitors 50A and 50B are provided between the low-voltage circuit 20 and the high-voltage circuit 30.

[0233] Capacitor 50A has a first electrode plate 51A and a second electrode plate 52A, and capacitor 50B has a first electrode plate 51B and a second electrode plate 52B. The first electrode plate 51A of capacitor 50A is connected to the low-voltage circuit 20 by a low-voltage signal line 21A, and the second electrode plate 52A of capacitor 50A is connected to the high-voltage circuit 30 by a high-voltage signal line 31A. The first electrode plate 51B of capacitor 50B is connected to the low-voltage circuit 20 by a low-voltage signal line 21B, and the second electrode plate 52B of capacitor 50B is connected to the high-voltage circuit 30 by a high-voltage signal line 31B. In this way, the low-voltage circuit 20 and the high-voltage circuit 30 transmit a set signal via capacitor 50A and a reset signal via capacitor 50B.

[0234] In this embodiment, the gate driver 10 includes a low-voltage circuit chip 60, a capacitor chip 200 (see Figure 15), and a high-voltage circuit chip 70 (see Figure 2). Although not shown, both the low-voltage circuit chip 60 and the capacitor chip 200 are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90 (see Figure 15), and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 of the high-voltage lead frame 100 (see Figure 2). The arrangement of the low-voltage circuit chip 60, the capacitor chip 200, and the high-voltage circuit chip 70 is the same as the arrangement of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 in the first embodiment. In other words, in this embodiment, the transformer chip 80 of the first embodiment is replaced with the capacitor chip 200.

[0235] As shown in Figure 15, the capacitor chip 200 has a main chip surface 200s and a back surface 200r that face opposite each other in the z direction. The back surface 200r of the capacitor chip 200 is bonded to the low-pressure die pad 91 by a conductive bonding material SD.

[0236] Multiple first electrode pads 81 and multiple second electrode pads 82 are formed on the main surface 200s of the capacitor chip 200. Although not shown, the multiple first electrode pads 81 are located at the end of the main surface 200s in the y-direction that is closer to the low-voltage circuit chip 60. The multiple first electrode pads 81 are arranged in the x-direction. The multiple second electrode pads 82 are located at the end of the main surface 200s in the y-direction that is closer to the high-voltage circuit chip 70. The multiple second electrode pads 82 are arranged in the x-direction. In a plan view, the capacitors 50A and 50B are arranged between the multiple first electrode pads 81 and the multiple second electrode pads 82 in the y-direction. The capacitors 50A and 50B are aligned with each other in the y-direction and spaced apart from each other in the x-direction.

[0237] Referring to Figure 15, an example of the internal structure of the capacitor chip 200 will be described. Figure 15 shows a schematic cross-sectional structure of capacitor 50A. Note that capacitor 50B has the same configuration as capacitor 50A, so its description will be omitted. In the following description, the direction from the back surface 200r of the capacitor chip 200 toward the main surface 200s of the chip will be considered upward, and the direction from the main surface 200s toward the back surface 200r of the chip will be considered downward. Also, components of the capacitor chip 200 that are common with the transformer chip 80 will be denoted by the same reference numerals, and their descriptions will be omitted.

[0238] As shown in Figure 15, the first electrode plate 51A and the second electrode plate 52A of the capacitor 50A are arranged facing each other in the z direction via an insulating layer 85. Each electrode plate 51A, 52A is configured as a conductive layer embedded within a single insulating layer 85. In other words, the insulating layer 85 into which each electrode plate 51A, 52A is embedded has openings that penetrate both the first insulating layer 85A and the second insulating layer 85B in the z direction. The conductive layers constituting each electrode plate 51A, 52A are embedded in the openings of the insulating layer 85.

[0239] In the z-direction, the second electrode plate 52A is located further from the substrate 84 than the first electrode plate 51A. In other words, the second electrode plate 52A is located above the first electrode plate 51A. The first electrode plate 51A is connected to the first electrode pad 81 by the first connecting wire 131A. The second electrode plate 52A is connected to the second electrode pad 82 by the third connecting wire 133A.

[0240] On the uppermost insulating layer 85U, a passivation layer 150, a low dielectric layer 160, and a resin layer 180 are laminated in the same order as in the first embodiment. The shapes of the passivation layer 150, the low dielectric layer 160, and the resin layer 180 are the same as in the first embodiment. Thus, according to this embodiment, the same effects as in the first embodiment can be obtained.

[0241] [Example of changes] The embodiments described above are illustrative of possible forms of isolation modules and gate drivers according to this disclosure and are not intended to limit their forms. Isolation modules and gate drivers according to this disclosure may take forms different from those illustrated in the embodiments described above. For example, these may be forms in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not technically contradict each other. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0242] In each embodiment, another insulating layer or low dielectric layer may be interposed between the passivation layer 150 and the low dielectric layer 160. In other words, the low dielectric layer 160 may not be in contact with the passivation layer 150.

[0243] In the first to third embodiments, the resin layer 180 may be omitted from the transformer chip 80. This omits the uneven structure 190 from the transformer chip 80. Similarly, in the fourth embodiment, the resin layer 180 may be omitted from the capacitor chip 200.

[0244] In each embodiment, the passivation layer 150 is not limited to a material containing silicon nitride, as long as it is a layer that can protect the insulating layer 85. However, the passivation layer 150 is made of a material with a dielectric constant higher than that of the low dielectric layer 160.

[0245] In each embodiment, the dielectric constant of the low dielectric layer 160 may be higher than the dielectric constant of the mold resin 110, as long as it is in a range lower than the dielectric constant of the passivation layer 150. In the first and second embodiments, the arrangement of transformers 40AA, 40AB, 40BA, and 40BB can be arbitrarily changed. For example, transformers 40AA, 40BA, 40AB, and 40BB may be arranged in the order of transformer 40AA, transformer 40BA, transformer 40AB, and transformer 40BB from the chip side 80c to the chip side 80d of the transformer chip 80.

[0246] In the first and second embodiments, the first dummy pattern 121 of the dummy pattern 120 was electrically connected to the second coil 42B, but this is not limited to that. For example, the first dummy pattern 121 may be provided independently of the second coils 42A and 42B. That is, the first dummy pattern 121 does not have to be electrically connected to the second coils 42A and 42B. Also, in the first and second embodiments, the third dummy pattern 123 was electrically connected to the first dummy pattern 121, but this is not limited to that. For example, the third dummy pattern 123 does not have to be electrically connected to the first dummy pattern 121. In the first transformer chip 80A, each dummy pattern 121 to 123 may be configured to have a voltage higher than the voltage applied to the first coils 41A and 41B applied to it. Note that the dummy patterns 120A and 120B in the third embodiment can also be modified in the same way as the dummy pattern 120.

[0247] In the first to third embodiments, the configuration of the dummy patterns 120, 120A, and 120B can be arbitrarily changed. For example, in the dummy patterns 120, 120A, and 120B, one or two of the first dummy pattern 121, the second dummy pattern 122, and the third dummy pattern 123 may be omitted. Also, the dummy patterns 120, 120A, and 120B may be omitted from the transchip 80.

[0248] In the second embodiment, the first inner surface cover portion 165 of the low dielectric layer 160 may be spaced apart from the first electrode pad 81 in the z direction. Also, the second inner surface cover portion 166 of the low dielectric layer 160 may be spaced apart from the second electrode pad 82 in the z direction.

[0249] In the second embodiment, the first inner surface cover portion 165 of the low dielectric layer 160 only needs to be formed on the first inner surface of the first protective layer opening 151 of the passivation layer 150, and does not need to be formed on the first inner surface of the first insulating layer opening 85Ua of the uppermost insulating layer 85U. Also, the second inner surface cover portion 166 of the low dielectric layer 160 only needs to be formed on the second inner surface of the second protective layer opening 152 of the passivation layer 150, and does not need to be formed on the second inner surface of the second insulating layer opening 85Ub of the uppermost insulating layer 85U.

[0250] In the second embodiment, one or two of the first inner surface cover portion 165, the second inner surface cover portion 166, and the outer surface cover portion 167 may be omitted from the low dielectric layer 160. In the third embodiment, the gate driver 10 may include a first transformer chip 80A and a second transformer chip 80B instead of the transformer chip 80. That is, as shown in Figure 16, the gate driver 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, a first transformer chip 80A, and a second transformer chip 80B. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the first transformer chip 80A, and the second transformer chip 80B are arranged spaced apart from each other in the y-direction. These chips 60, 70, 80A, and 80B can also be said to be arranged in the direction of the arrangement of the low-voltage die pad 91 and the high-voltage die pad 101.

[0251] In the illustrated example, the low-voltage circuit chip 60, the first transformer chip 80A, the second transformer chip 80B, and the high-voltage circuit chip 70 are arranged in that order from the low-voltage lead 92 to the high-voltage lead 102. In other words, in a plan view, each transformer chip 80A and 80B is positioned between the low-voltage circuit chip 60 and the high-voltage circuit chip 70.

[0252] In the illustrated example, both the low-voltage circuit chip 60 and the first transformer chip 80A are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90. Both the high-voltage circuit chip 70 and the second transformer chip 80B are mounted on the high-voltage die pad 101 of the high-voltage lead frame 100.

[0253] The first transformer chip 80A includes the first transformer 43A of transformer 40A and the first transformer 43B of transformer 40B, and more specifically, both transformers 43A and 43B are packaged together. In other words, the first transformer chip 80A includes the transformers 40A and 40B, which are circuit-wise positioned closer to the low-voltage circuit 20 than to the high-voltage circuit 30.

[0254] The second transformer chip 80B includes the second transformer 44A of transformer 40A and the second transformer 44B of transformer 40B, and more specifically, both transformers 44A and 44B are packaged together. In other words, the second transformer chip 80B includes the transformer 40A and 40B that is circuit-wise positioned closer to the high-voltage circuit 30 than to the low-voltage circuit 20.

[0255] In the illustrated example, the configuration of the first transformer chip 80A is the same as that of the transformer chip 80 in the first embodiment. The second transformer chip 80B differs from the configuration of the transformer chip 80 in the first embodiment in the arrangement of each coil 47A, 47B, 48A, 48B and the arrangement of each coil 47A, 47B, 48A, 48B and each electrode pad 81, 82.

[0256] More specifically, the multiple first electrode pads 81 of the second transformer chip 80B are located near the center in the y-direction of the main chip surface 80s of the second transformer chip 80B. The multiple second electrode pads 82 of the second transformer chip 80B are located at the ends of the main chip surface 80s of the second transformer chip 80B that are closer to the high-voltage circuit chip 70.

[0257] In the second transformer chip 80B, although not shown in the diagram, the first coils 47A and 47B are positioned further from the substrate 84 than the second coils 48A and 48B. In other words, the second coils 48A and 48B are positioned closer to the substrate 84 than the first coils 47A and 47B. The first coils 47A and 47B are individually electrically connected to multiple first electrode pads 81 of the second transformer chip 80B. The second coils 48A and 48B are individually electrically connected to multiple second electrode pads 82 of the second transformer chip 80B.

[0258] The low-voltage circuit chip 60 and the first transformer chip 80A are connected by a wire W. More specifically, the second electrode pad 62 of the low-voltage circuit chip 60 and the first electrode pad 81 of the first transformer chip 80A are connected by a wire W. As a result, the low-voltage circuit 20 and the first coil 45A of the first transformer 43A (see Figure 11) are electrically connected, and the low-voltage circuit 20 and the first coil 45B of the first transformer 43B (see Figure 11) are electrically connected.

[0259] The first transformer chip 80A and the second transformer chip 80B are connected by a wire W. More specifically, the second electrode pad 82 of the first transformer chip 80A and the first electrode pad 81 of the second transformer chip 80B are connected by a wire W. As a result, the second coil 46A of the first transformer 43A and the first coil 47A of the second transformer 44A are electrically connected, and the second coil 46B of the first transformer 43B and the first coil 47B of the second transformer 44B are electrically connected.

[0260] The second transformer chip 80B and the high-voltage circuit chip 70 are connected by a wire W. More specifically, the second electrode pad 82 of the second transformer chip 80B and the first electrode pad 71 of the high-voltage circuit chip 70 are connected by a wire W. As a result, the second coil 48A of the second transformer 44A (see Figure 11) and the high-voltage circuit 30 are electrically connected, and the second coil 48B of the second transformer 44B (see Figure 11) and the high-voltage circuit 30 are electrically connected.

[0261] In the third and fourth embodiments, the shape of the low dielectric layer 160 can be arbitrarily changed. For example, the low dielectric layer 160 may have the shape of the low dielectric layer 160 in the second embodiment. In the first to third embodiments, the low-voltage circuit 20 and the transformer 40 were formed as separate chips, but this is not limited to this. The transformer 40 and the low-voltage circuit 20 may be mounted on a single chip. This chip is covered with a molding resin 110. Therefore, the low-dielectric layer 160 provided on the chip is covered with the molding resin 110. In one example, the low-voltage circuit 20 may be formed on the substrate 84 of the transformer chip 80. The transformer chip 80 is covered with the molding resin 110. Similarly, in the fourth embodiment, the capacitor 50 and the low-voltage circuit 20 may be mounted on a single chip. In other words, the insulating module and the low-voltage circuit 20 may be mounted on a single chip.

[0262] In the first to third embodiments, the high-voltage circuit 30 and the transformer 40 were formed as separate chips, but the invention is not limited to this. The transformer 40 and the high-voltage circuit 30 may be mounted on a single chip. This chip is covered with a molding resin 110. Therefore, the low-dielectric layer 160 provided on the chip is covered with the molding resin 110. In one example, the high-voltage circuit 30 may be formed on the substrate 84 of the transformer chip 80. In this case, the transformer chip 80 is mounted on a high-voltage die pad 101. The transformer chip 80 is covered with the molding resin 110. Similarly, in the fourth embodiment, the capacitor 50 and the high-voltage circuit 30 may be mounted on a single chip. In other words, the insulating module and the high-voltage circuit 30 may be mounted on a single chip.

[0263] In the first to third embodiments, the gate driver 10 may include an isolation module housing a transformer 40 in a single package. The isolation module includes a transformer chip 80 and a molded resin 110 that seals the transformer chip 80. The isolation module may further include a die pad on which the transformer chip 80 is mounted, a plurality of leads, and wires that connect the plurality of leads to the transformer chip 80. The molded resin 110 seals at least the transformer chip 80, the die pad, and the wires. The plurality of leads are electrically connectable to both the low-voltage circuit 20 and the high-voltage circuit 30. Similarly in the fourth embodiment, the gate driver 10 may also include an isolation module housing a capacitor 50 in a single package. That is, the isolation module includes an insulating chip and a molded resin that seals the insulating chip. This isolation module is used to isolate the low-voltage circuit 20 and the high-voltage circuit 30 included in the gate driver 10.

[0264] In the first to third embodiments, the gate driver 10 may include a low-voltage circuit unit that houses a low-voltage circuit 20 and a transformer 40 in a single package. The low-voltage circuit unit may include a low-voltage circuit chip 60, a transformer chip 80, and a molding resin 110 that encapsulates the low-voltage circuit chip 60 and the transformer chip 80. The low-voltage circuit unit may further include a die pad, a plurality of first leads, first wires connecting the plurality of first leads to the low-voltage circuit chip 60, a plurality of second leads, and second wires connecting the plurality of second leads to the transformer chip 80. The molding resin 110 encapsulates at least the low-voltage circuit chip 60, the transformer chip 80, the die pad, and each wire. The plurality of first leads are electrically connectable to, for example, an ECU 503, and the plurality of second leads are electrically connectable to a high-voltage circuit 30. Similarly, in the fourth embodiment, the gate driver 10 may also include a low-voltage circuit unit that houses the low-voltage circuit 20 and the capacitor 50 in a single package. In other words, the low-voltage circuit unit only needs to include a low-voltage circuit chip 60, an insulating module, and a molding resin 110 that seals both the low-voltage circuit chip 60 and the insulating module.

[0265] In the first to third embodiments, the gate driver 10 may include a high-voltage circuit unit that houses a high-voltage circuit 30 and a transformer 40 in a single package. The high-voltage circuit unit may include a high-voltage circuit chip 70, a transformer chip 80, and a molding resin 110 that seals both the high-voltage circuit chip 70 and the transformer chip 80. The high-voltage circuit unit may further include a die pad, a plurality of first leads, first wires connecting the plurality of first leads to the high-voltage circuit chip 70, a plurality of second leads, and second wires connecting the plurality of second leads to the transformer chip 80. The molding resin 110 seals at least the high-voltage circuit chip 70, the transformer chip 80, the die pad, and each wire. The plurality of first leads can be electrically connected to, for example, the source of a switching element 501, and the plurality of second leads can be electrically connected to a low-voltage circuit 20. Similarly in the fourth embodiment, the gate driver 10 may also include a high-voltage circuit unit that houses a high-voltage circuit 30 and a capacitor 50 in a single package. In other words, the high-voltage circuit unit only needs to include a high-voltage circuit chip 70, an insulating module, and a molded resin 110 that seals both the high-voltage circuit chip 70 and the insulating module.

[0266] In each embodiment, the gate driver 10 may transmit signals from the high-voltage circuit 30 to the low-voltage circuit 20 via an isolation module. As an example, as shown in Figure 17, a configuration is described in which a signal path for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20 is added to the gate driver 10 of the first embodiment.

[0267] As shown in Figure 17, the gate driver 10 is equipped with a transformer 40C for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20. The transformer 40C transmits signals from the high-voltage circuit 30 to the low-voltage circuit 20 while isolating the high-voltage circuit 30 from the low-voltage circuit 20. This signal is, for example, an abnormality detection signal that is output when an abnormality of the switching element 501 is detected. Examples of abnormalities of the switching element 501 include an abnormality where the temperature of the switching element 501 rises excessively (temperature abnormality), an abnormality where an excessively large current flows through the switching element 501 (overcurrent), and an abnormality where an excessively high voltage is applied to the switching element 501 (overvoltage). In other words, when the gate driver 10 detects a temperature abnormality, overcurrent, overvoltage, etc. of the switching element 501, it transmits an abnormality detection signal from the high-voltage circuit 30 to the low-voltage circuit 20 via the transformer 40C.

[0268] Transformer 40C has the same configuration as transformers 40A and 40B, and includes a first coil 41C and a second coil 42C. The first coil 41C is connected to the low-voltage signal line 21C, which is connected to the low-voltage circuit 20, and is also connected to the ground of the low-voltage circuit 20. The second coil 42C is connected to the high-voltage signal line 31C, which is connected to the high-voltage circuit 30, and is also connected to the ground of the high-voltage circuit 30. The signal output from the high-voltage circuit 30 is transmitted to the low-voltage circuit 20 via the transformer 40C.

[0269] As shown in Figure 17, in the modified example, signals are transmitted bidirectionally between the low-voltage circuit 20 and the high-voltage circuit 30. These signals include a first signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 and a second signal transmitted from the high-voltage circuit 30 to the low-voltage circuit 20. The first signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the first coil 41A (41B) and the second coil 42A (42B) in that order. The second signal is transmitted from the high-voltage circuit 30 to the low-voltage circuit 20 via the second coil 42C and the first coil 41C in that order.

[0270] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in this embodiment, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contacting B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0271] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical.

[0272] In this specification, the phrase "at least one of A and B" should be understood to mean "A alone, or B alone, or both A and B." [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. The reference numerals for the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. These reference numerals are provided as examples to aid understanding, and the components described in each appendix should not be limited to those indicated by these reference numerals.

[0273] (Note 1) A first conductor (41A, 41B / 51A, 51B) and a second conductor (42A, 42B / 52A, 52B) are embedded within the insulating layer (85) and are positioned opposite each other, spaced apart in the thickness direction (z direction) of the insulating layer (85), The first electrode (81) connected to the first conductor (41A, 41B / 51A, 51B), Viewed from the thickness direction (z direction) of the insulating layer (85), the second electrode (82) is provided at a position spaced apart from the first electrode (81) and is connected to the second conductor (42A, 42B / 52A, 52B), A passivation layer (150) formed on the surface (85s) of the insulating layer (85); A low dielectric layer (160) formed on the surface (150s) of the passivation layer (150) and having a lower dielectric constant than the passivation layer (150); An insulating module comprising a mold resin (110) covering the low dielectric layer (160).

[0274] (Appendix 2) The passivation layer (150) is formed of a material containing silicon nitride The insulating module according to Appendix 1.

[0275] (Appendix 3) The dielectric constant of the low dielectric layer (160) is not greater than the dielectric constant of the mold resin (110). The insulating module according to Appendix 1 or 2.

[0276] (Appendix 4) The thickness (TE) of the low dielectric layer (160) is not greater than the thickness (TP) of the passivation layer (150). The insulating module according to any one of Appendices 1 to 3.

[0277] (Appendix 5) At positions overlapping the first electrode (81) when viewed from the thickness direction (z direction) of the insulating layer (85) in the passivation layer (150) and the low dielectric layer (160), a first opening (171) penetrating both the passivation layer (150) and the low dielectric layer (160) is formed; At positions overlapping the second electrode (82) when viewed from the thickness direction (z direction) of the insulating layer (85) in the passivation layer (150) and the low dielectric layer (160), a second opening (172) penetrating both the passivation layer (150) and the low dielectric layer (160) is formed; The mold resin (110) is in contact with the first electrode (81) through the first opening (171) and is in contact with the second electrode (82) through the second opening (172). An insulating module as described in any one of the appendices 1 to 4.

[0278] (Note 6) In the passivation layer (150), a first opening (171) is formed at a position that overlaps with the first electrode (81) when viewed from the thickness direction (z direction) of the insulating layer (85), and the passivation layer (150) is penetrated therein. In the passivation layer (150), a second opening (172) is formed at a position that overlaps with the second electrode (82) when viewed from the thickness direction (z direction) of the insulating layer (85), and the passivation layer (150) is penetrated therein. The low dielectric layer (160 / 165,166) is formed on both the first inner surface constituting the first opening (171) and the second inner surface constituting the second opening (172). The low dielectric layer (160 / 167) covers the end face of the passivation layer (150). An insulating module as described in any one of the appendices 1 to 4.

[0279] (Note 7) The surface (160s) of the low dielectric layer (160) is provided with a resin layer (180) having grooves (183) that expose the surface (160s) of the low dielectric layer (160). The region between the first electrode (81) and the second electrode (82) on the surface (160s) of the low dielectric layer (160) is provided with an uneven structure (190) formed by the bonding surface between the molding resin (110) and the resin layer (180) and the bonding surface between the molding resin (110) and the low dielectric layer (160). An insulating module as described in any one of the appendices 1 to 6.

[0280] (Note 8) The first conductor is the first coil (41A, 41B), The second conductor is the second coil (42A, 42B), The transformer (40 / 40A, 40B) is composed of the first coil (41A, 41B) and the second coil (42A, 42B). An insulating module as described in any one of the notes 1 to 7.

[0281] (Note 9) A dummy pattern (120) is provided around the coils (42A, 42B) of the first coils (41A, 41B) and the second coils (42A, 42B) that are located near the passivation layer (150). The insulating module described in Appendix 9.

[0282] (Note 10) The first conductor is the first electrode plate (51A, 51B), The second conductor is the second electrode plate (52A, 52B), The capacitor (50 / 50A, 50B) is composed of the first electrode plates (51A, 51B) and the second electrode plates (52A, 52B). An insulating module as described in any one of the notes 1 to 7.

[0283] (Note 11) A gate driver (10) that applies a drive voltage signal to the gate of a switching element (501), A low-voltage circuit (20) configured to operate when a first voltage (V1) is applied, A high-voltage circuit (30) configured to operate when a second voltage (V2) higher than the first voltage (V1) is applied, It includes an isolation module (80, 110), The low-voltage circuit (20) and the high-voltage circuit (30) are connected via the isolation modules (80, 110), and are configured to transmit signals via the isolation modules (80, 110). The aforementioned isolation module (80, 110) Embedded in the insulating layer (85) and disposed opposite to each other with a separation in the thickness direction (z-direction) of the insulating layer (85) are a first conductor (41A, 41B / 51A, 51B) and a second conductor (42A, 42B / 51A, 51B), a first electrode (81) connected to the first conductor (41A, 41B / 51A, 51B), a second electrode (82) provided at a position spaced apart from the first electrode (81) when viewed from the thickness direction (z-direction) of the insulating layer (85) and connected to the second conductor (42A, 42B / 52A, 52B), a passivation layer (150) formed on the surface (85s) of the insulating layer (85) to protect the insulating layer (85), a low dielectric layer (160) formed on the surface (150s) of the passivation layer (150) and having a lower dielectric constant than the passivation layer (150), and a mold resin (110) covering the low dielectric layer (160). A gate driver comprising the above is provided.

[0284] (Appendix 12) The signal includes a first signal, The first signal output from the low-voltage circuit (20) is transmitted to the high-voltage circuit (30) via the insulation module (80, 110), The high-voltage circuit (30) generates the drive voltage signal based on the first signal from the low-voltage circuit (20). The gate driver according to Appendix 11.

[0285] (Appendix 13) The signal includes a second signal, The second signal output from the high-voltage circuit (30) is transmitted to the low-voltage circuit (20) via the insulation module (80, 110). The gate driver according to Appendix 12.

[0286] (Appendix 14) The insulation module (80, 110) and the low-voltage circuit (20) are mounted on one chip. The gate driver according to any one of Appendices 11 to 13.

[0287] (Note 15) The isolation modules (80, 110) and the high-voltage circuit (30) are mounted on a single chip. The gate driver described in any one of the appendices 11-13.

[0288] (Note 16) The aforementioned transformer (40 / 40A, 40B) includes a first transformer (43A, 43B) and a second transformer (44A, 44B) connected in series with each other. The first transformers (43A, 43B) are connected to the low-voltage circuit (20), The second transformers (44A, 44B) are connected to both the first transformers (43A, 43B) and the high-voltage circuit (30). The insulating module described in Appendix 8.

[0289] (Note A1) A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer and is connected to the second conductor, A passivation layer formed on the surface of the insulating layer, A low dielectric layer is formed on the surface of the passivation layer and has a dielectric constant lower than that of the passivation layer, A resin layer formed on the surface of the low dielectric layer, A molding resin covering the low dielectric layer and the resin layer, Equipped with, In the passivation layer and the low dielectric layer, a first opening is formed at a position that overlaps with the first electrode when viewed from the thickness direction of the insulating layer, and the first opening penetrates both the passivation layer and the low dielectric layer. A second opening is formed in the passivation layer and the low dielectric layer at a position that overlaps with the second electrode when viewed from the thickness direction of the insulating layer, and the second opening penetrates both the passivation layer and the low dielectric layer. The low dielectric layer includes a first region located away from the first opening and in which the resin layer and the molding resin are arranged sequentially in the thickness direction of the insulating layer, and a second region between the first opening and the first region that is directly covered by the molding resin. The low dielectric layer includes a third region located away from the second opening and in which the resin layer and the molding resin are arranged sequentially in the thickness direction of the insulating layer, and a fourth region between the second opening and the third region that is directly covered by the molding resin. Insulation module.

[0290] (Appendix A2) The passivation layer is formed from a material containing silicon nitride. The insulating module described in Appendix A1.

[0291] (Note A3) The dielectric constant of the low dielectric layer is less than or equal to the dielectric constant of the molding resin. The insulating module described in Appendix A1 or A2.

[0292] (Note A4) The thickness of the low dielectric layer is less than or equal to the thickness of the passivation layer. The insulating module specified in one of the appendices A1 to A3.

[0293] (Note A5) The mold resin is in contact with the first electrode through the first opening and in contact with the second electrode through the second opening. The insulating module specified in one of the appendices A1 to A4.

[0294] (Note A6) The low dielectric layer is formed on both the first inner surface constituting the first opening and the second inner surface constituting the second opening. The low dielectric layer covers the end face of the passivation layer. The insulating module specified in one of the appendices A1 to A4.

[0295] (Note A7) The surface of the low dielectric layer is provided with a resin layer having grooves that expose the surface of the low dielectric layer. The region between the first electrode and the second electrode on the surface of the low dielectric layer is provided with an uneven structure formed by the bonding surface between the molding resin and the resin layer and the bonding surface between the molding resin and the low dielectric layer. The insulating module specified in one of the appendices A1 to A6.

[0296] (Note A8) The first conductor is the first coil, The aforementioned second conductor is the second coil, The transformer is composed of the first coil and the second coil. The insulating module specified in one of the appendices A1 to A7.

[0297] (Note A9) A dummy pattern is provided around the coil located near the passivation layer among the first and second coils. The insulating module described in Appendix A8.

[0298] (Note A10) The first conductor is the first electrode plate, The aforementioned second conductor is a second electrode plate, The capacitor is composed of the first electrode plate and the second electrode plate. The insulating module specified in one of the appendices A1 to A7.

[0299] (Note A11) A gate driver that applies a drive voltage signal to the gate of a switching element, A low-voltage circuit configured to operate when a first voltage is applied, A high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied, Insulation module and, Equipped with, The low-voltage circuit and the high-voltage circuit are connected via the isolation module, and are configured to transmit signals via the isolation module. The aforementioned isolation module is A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer and is connected to the second conductor, A passivation layer formed on the surface of the insulating layer and protecting the insulating layer, A low dielectric layer is formed on the surface of the passivation layer and has a dielectric constant lower than that of the passivation layer, A resin layer formed on the surface of the low dielectric layer, A molding resin covering the low dielectric layer and the resin layer, Equipped with, In the passivation layer and the low dielectric layer, a first opening is formed at a position that overlaps with the first electrode when viewed from the thickness direction of the insulating layer, and the first opening penetrates both the passivation layer and the low dielectric layer. A second opening is formed in the passivation layer and the low dielectric layer at a position that overlaps with the second electrode when viewed from the thickness direction of the insulating layer, and the second opening penetrates both the passivation layer and the low dielectric layer. The low dielectric layer includes a first region located away from the first opening and in which the resin layer and the molding resin are arranged sequentially in the thickness direction of the insulating layer, and a second region between the first opening and the first region that is directly covered by the molding resin. The low dielectric layer includes a third region located away from the second opening and in which the resin layer and the molding resin are arranged sequentially in the thickness direction of the insulating layer, and a fourth region between the second opening and the third region that is directly covered by the molding resin. Gate driver.

[0300] (Note A12) The aforementioned signal includes the first signal, The first signal output from the low-voltage circuit is transmitted to the high-voltage circuit via the isolation module. The high-voltage circuit generates the drive voltage signal based on the first signal from the low-voltage circuit. The gate driver described in Appendix A11.

[0301] (Note A13) The aforementioned signal includes a second signal, The second signal output from the high-voltage circuit is transmitted to the low-voltage circuit via the isolation module. The gate driver described in Appendix A12.

[0302] (Note A14) The isolation module and the low-voltage circuit are mounted on a single chip. The gate driver specified in any one of the appendices A11 to A13.

[0303] (Note A15) The aforementioned isolation module and the aforementioned high-voltage circuit are mounted on a single chip. The gate driver specified in any one of the appendices A11 to A13.

[0304] (Note A16) A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer and is connected to the second conductor, A laminate with a three-layer structure, comprising at least a silicon oxide layer and a silicon nitride layer, is formed on the surface of the insulating layer so as to cover the insulating layer, A resin layer formed on the surface of the laminate, The mold resin formed on the surface of the resin layer, Equipped with, A first opening is formed that penetrates the laminate at a position overlapping with the first electrode when viewed from the thickness direction of the insulating layer. A second opening is formed through the laminate at a position that overlaps with the second electrode when viewed from the thickness direction of the insulating layer. The outer periphery of the first electrode and the outer periphery of the second electrode are inclined with respect to the thickness direction of the insulating layer. The laminate includes a first raised portion covering the outer periphery of the first electrode and a second raised portion covering the outer periphery of the second electrode. The first raised portion and the second raised portion are exposed from the resin layer. Insulation module.

[0305] (Note A17) A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer and is connected to the second conductor, A passivation layer formed on the surface of the insulating layer, A low dielectric layer is formed on the surface of the passivation layer and has a dielectric constant lower than that of the passivation layer, A molding resin covering the low dielectric layer, Equipped with, The thickness of the low dielectric layer is less than or equal to the thickness of the passivation layer. Insulation module. [Explanation of Symbols]

[0306] 10…Gate driver, 20…Low voltage circuit, 30…High voltage circuit, 40, 40A, 40B, 40AA, 40AB, 40BA, 40BB, 40C…Transformers, 41A, 41B…First coil (first conductor), 42A, 42B…Second coil (second conductor), 43A, 43B…First transformer, 44A, 44B…Second transformer, 45A, 45B, 47A, 47B…First coil (first conductor), 46A, 46B, 48A, 48B…Second coil (second conductor), 80…Transformer tip, 50, 50A, 50B…Capacitor, 51A, 51B…First conductor Electrode plate (first conductor), 52A, 52B... Second electrode plate (second conductor), 81, 81A~81F... First electrode pad (first electrode), 82, 82A~82F... Second electrode pad (second electrode), 85... Insulating layer, 85s... Surface, 110... Molded resin, 120, 120A, 120B... Dummy pattern, 150... Passivation layer, 150s... Surface, 160... Low dielectric layer, 160s... Surface, 171... First opening, 172... Second opening, 180... Resin layer, 190... Uneven structure, 200... Capacitor chip, 501, 502... Switching element.

Claims

1. A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer, and is connected to the second conductor, A passivation layer formed on the surface of the insulating layer and made of a material containing silicon nitride, A low dielectric layer is formed on the surface of the passivation layer, is composed of a material containing silicon oxide, and has a lower dielectric constant than the passivation layer. A molding resin covering the low dielectric layer, Equipped with Insulation module.

2. The thickness of the passivation layer is smaller than the thickness of the low dielectric layer. The insulating module according to claim 1.

3. The low dielectric layer and the mold resin are provided with a resin layer. The insulating module according to claim 1 or claim 2.

4. A first opening is formed in the passivation layer and the low dielectric layer at a position that overlaps with the first electrode when viewed from the thickness direction of the insulating layer, and the opening penetrates both the passivation layer and the low dielectric layer. A second opening is formed in the passivation layer and the low dielectric layer at a position that overlaps with the second electrode when viewed from the thickness direction of the insulating layer, and the opening penetrates both the passivation layer and the low dielectric layer. The mold resin is in contact with the first electrode through the first opening and in contact with the second electrode through the second opening. An insulating module according to any one of claims 1 to 3.

5. A first opening is formed in the passivation layer at a position that overlaps with the first electrode when viewed from the thickness direction of the insulating layer, and the passivation layer penetrates the passivation layer. A second opening is formed in the passivation layer at a position that overlaps with the second electrode when viewed from the thickness direction of the insulating layer, and the second opening penetrates the passivation layer. The low dielectric layer is formed on both the first inner surface constituting the first opening and the second inner surface constituting the second opening. The low dielectric layer covers the end face of the passivation layer. An insulating module according to any one of claims 1 to 3.

6. The surface of the low dielectric layer is provided with a resin layer having grooves that expose the surface of the low dielectric layer. The region between the first electrode and the second electrode on the surface of the low dielectric layer is provided with an uneven structure formed by the bonding surface between the molding resin and the resin layer and the bonding surface between the molding resin and the low dielectric layer. An insulating module according to any one of claims 1 to 5.

7. The first conductor is the first coil, The aforementioned second conductor is a second coil, The transformer is composed of the first coil and the second coil. An insulating module according to any one of claims 1 to 6.

8. A dummy pattern is provided around the first coil and the second coil, which is located near the passivation layer. The insulating module according to claim 7.

9. The first conductor is the first electrode plate, The aforementioned second conductor is a second electrode plate, The capacitor is composed of the first electrode plate and the second electrode plate. An insulating module according to any one of claims 1 to 6.

10. A gate driver that applies a drive voltage signal to the gate of a switching element, A low-voltage circuit configured to operate when a first voltage is applied, A high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied, Insulation module and, Equipped with, The low-voltage circuit and the high-voltage circuit are connected via the isolation module, and are configured to transmit signals via the isolation module. The aforementioned isolation module is A first conductor and a second conductor are embedded within an insulating layer and arranged opposite each other at a distance in the thickness direction of the insulating layer, A first electrode connected to the first conductor, A second electrode is provided at a position spaced apart from the first electrode when viewed in the thickness direction of the insulating layer, and is connected to the second conductor, A passivation layer formed on the surface of the insulating layer and made of a material containing silicon nitride, A low dielectric layer is formed on the surface of the passivation layer, is composed of a material containing silicon oxide, and has a lower dielectric constant than the passivation layer. A molding resin covering the low dielectric layer, Equipped with Gate driver.

11. The aforementioned signal includes the first signal, The first signal output from the low-voltage circuit is transmitted to the high-voltage circuit via the isolation module. The high-voltage circuit generates the drive voltage signal based on the first signal from the low-voltage circuit. The gate driver according to claim 10.

12. The aforementioned signal includes a second signal, The second signal output from the high-voltage circuit is transmitted to the low-voltage circuit via the isolation module. The gate driver according to claim 11.

13. The isolation module and the low-voltage circuit are mounted on a single chip. A gate driver according to any one of claims 10 to 12.

14. The aforementioned isolation module and the aforementioned high-voltage circuit are mounted on a single chip. A gate driver according to any one of claims 10 to 12.

15. The thickness of the passivation layer is smaller than the thickness of the low dielectric layer. A gate driver according to any one of claims 10 to 14.

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