Nitride semiconductor equipment

Abstract

To improve the accuracy of temperature detection in nitride semiconductor devices. [Solution] The nitride semiconductor device 10 includes a nitride semiconductor layer, a first region R1 where the first transistor 100 is located, a second region R2 where the second transistor 200 is located, and a third region R3 located between the first region R1 and the second region R2 where the temperature sensor 300 and gate connection wiring 310 are located. The temperature sensor 300 includes a first sensor electrode 302 and a second sensor electrode 303 located on the nitride semiconductor layer, and a temperature sensing unit 304 located between the first sensor electrode 302 and the second sensor electrode 303 and made of the nitride semiconductor layer. The gate connection wiring 310 spans over the temperature sensing unit 304 and electrically connects the first gate electrode 24 of the first transistor 100 and the second gate electrode 24 of the second transistor 200.

Description

[Technical Field]

[0001] This invention relates to nitride semiconductor devices. [Background technology]

[0002] Currently, the commercialization of high-electron-mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices utilizing HEMTs are recognized as devices that enable low on-resistance and high-frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transport layer composed of a gallium nitride (GaN) layer, and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. In the electron transport layer, a 2DEG is formed near the interface of the heterojunction between the electron transport layer and the electron supply layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-73506

[0005] [overview] High-speed switching elements such as nitride semiconductor HEMTs offer high conversion efficiency due to low switching losses. However, as switching speeds increase and switching transition times shorten, voltage ringing (circuit resonance) during switching becomes more likely. Voltage ringing during switching can cause unintended temperature increases. Therefore, in nitride semiconductor HEMTs, improved temperature detection accuracy may be required to ensure that the temperature does not exceed the operating range.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a nitride semiconductor layer, a first region where a first transistor is located, a second region where a second transistor is located, and a third region located between the first region and the second region where a temperature sensor and gate connection wiring are located, wherein the nitride semiconductor layer includes a first nitride semiconductor layer and a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, and the first transistor includes a first electron transport layer formed by the first nitride semiconductor layer in the first region, a first electron supply layer formed by the second nitride semiconductor layer in the first region, and a first gate electrode, a first source electrode, and a first drain electrode located on the first electron supply layer. The second transistor includes a second electron transport layer made of the first nitride semiconductor layer in the second region, a second electron supply layer made of the second nitride semiconductor layer in the second region, and a second gate electrode, a second source electrode, and a second drain electrode located on the second electron supply layer, and the temperature sensor includes a first sensor electrode and a second sensor electrode located spaced apart from each other on the second nitride semiconductor layer in the third region, and a temperature sensing unit located between the first sensor electrode and the second sensor electrode and made of the nitride semiconductor layer in the third region, and the gate connection wiring spans over the temperature sensing unit and electrically connects the first gate electrode and the second gate electrode. [Brief explanation of the drawing]

[0007] [Figure 1]Figure 1 is an illustrative schematic plan view of a nitride semiconductor device according to an embodiment. [Figure 2] Figure 2 is a plan view that is an enlarged portion of Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along the line F3-F3 in Figure 2. [Figure 4] Figure 4 is a cross-sectional view taken along the line F4-F4 in Figure 2. [Figure 5] Figure 5 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in Figure 1. [Figure 6] Figure 6 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 6. [Figure 8] Figure 8 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 8. [Figure 10] Figure 10 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 9. [Figure 11] Figure 11 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 10. [Figure 12] Figure 12 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 11. [Figure 13] Figure 13 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 12. [Figure 14] Figure 14 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 13. [Figure 15] Figure 15 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 14. [Figure 16] Figure 16 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 5. [Figure 17] Figure 17 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 16. [Figure 18] Figure 18 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 17. [Figure 19]FIG. 19 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 19. [Figure 21] FIG. 21 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 20. [Figure 22] FIG. 22 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 21. [Figure 23] FIG. 23 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 22. [Figure 24] FIG. 24 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 23. [Figure 25] FIG. 25 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 24. [Figure 26] FIG. 26 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 25.

[0008] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] The terms “first,” “second,” “third,” etc. used in the present disclosure are used to clearly distinguish the components of the object and do not rank the object. Also, the expression “at least one” used in the present disclosure means one or more of a plurality of desired options. As an example, if the number of options is two, the expression “at least one” means only one option or both of the two options. As another example, if the number of options is three or more, the expression “at least one” means only one option or any combination of two or more options.

[0010] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0011] [Schematic structure of nitride semiconductor device] Figure 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to one embodiment. Figure 2 is a schematic cross-sectional view of the nitride semiconductor device 10.

[0012] The nitride semiconductor device 10 is used, for example, as a switching element in an inverter device. The nitride semiconductor device 10 includes a semiconductor substrate 12 and a nitride semiconductor layer 15 located on the semiconductor substrate 12 (see Figures 3 and 4). The nitride semiconductor device 10 includes a first transistor 100 comprising the nitride semiconductor layer 15, a second transistor 200 comprising the nitride semiconductor layer 15, and a temperature sensor 300 comprising the nitride semiconductor layer 15. Details of the first transistor 100, the second transistor 200, and the temperature sensor 300 will be described later.

[0013] As shown in Figures 3 and 4, the semiconductor substrate 12 can be formed from Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm to 1500 μm. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0014] The nitride semiconductor layer 15 includes a first nitride semiconductor layer 15A located on the semiconductor substrate 12 via a buffer layer 14, and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A. The buffer layer 14 may be made of any material that facilitates the epitaxial growth of the first nitride semiconductor layer 15A.

[0015] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different Al composition. For example, the buffer layer 14 may consist of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make it semi-insulating. In that case, the impurities may be, for example, carbon (C) or iron (Fe), and the concentration of the impurities may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0016] The first nitride semiconductor layer 15A may be, for example, a GaN layer. The first nitride semiconductor layer 15A may have a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the first nitride semiconductor layer 15A, an impurity may be introduced into a part of the first nitride semiconductor layer 15A to make the region other than the surface region of the first nitride semiconductor layer 15A semi-insulating. In this case, the impurity may be, for example, C, and the concentration of the impurity in the first nitride semiconductor layer 15A may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0017] The second nitride semiconductor layer 15B has a larger band gap than the first nitride semiconductor layer 15A. The second nitride semiconductor layer 15B may be, for example, an AlGaN layer. Since the band gap increases with increasing Al composition, the second nitride semiconductor layer 15B, which is an AlGaN layer, has a larger band gap than the first nitride semiconductor layer 15A, which is a GaN layer. For example, the second nitride semiconductor layer 15B is an Al with an Al composition ratio of X. X Ga (1-X)It is composed of N. The Al composition ratio X may be 0.1 < X < 0.4, and preferably may be 0.1 < X < 0.3. The second nitride semiconductor layer 15B may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the second nitride semiconductor layer 15B is 8 nm or more.

[0018] The first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the first nitride semiconductor layer 15A and the nitride semiconductor (for example, AlGaN) constituting the second nitride semiconductor layer 15B form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the first nitride semiconductor layer 15A near the hetero-junction interface becomes lower than the Fermi level. As a result, the 2DEG 20 spreads in the first nitride semiconductor layer 15A at a position close to the hetero-junction interface between the first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B (for example, within a range of about several nm from the interface).

[0019] Here, the Z-axis direction of the XYZ axes shown in each drawing is the thickness direction of the nitride semiconductor layer 15, and the X-axis direction and the Y-axis direction are two mutually orthogonal directions on a plane orthogonal to the Z-axis direction. The term "planar view" used in the present disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction unless otherwise explicitly stated. Also, unless otherwise stated, the thickness means the thickness in the Z-axis direction.

[0020] As shown in FIGS. 1 and 2, the nitride semiconductor device 10 includes a first region R1 where the first transistor 100 is located, a second region R2 where the second transistor 200 is located, and a third region R3 where the temperature sensor 300 and the gate connection wiring 310 are located. The first region R1, the second region R2, and the third region R3 are arranged side by side in the Y-axis direction.

[0021] More specifically, the first region R1 and the second region R2 are spaced apart in the Y-axis direction. The third region R3 is located between the first region R1 and the second region R2 in the Y-axis direction. The first region R1 and the third region R3, and the second region R2 and the third region R3, are each spaced apart without overlapping in a plan view.

[0022] In the example shown in Figure 1, in a plan view, the first region R1 is rectangular in shape extending in the Y-axis direction. The second region R2 is rectangular in shape extending in the Y-axis direction. The third region R3 is rectangular in shape extending in the X-axis direction. The Y-axis length L1 of the first region R1 and the Y-axis length L2 of the second region R2 are, for example, between 300 μm and 1000 μm. The lengths L1 of the first region R1 and L2 of the second region R2 may be the same or different. The Y-axis length L3 of the third region R3 is, for example, between 10 μm and 50 μm.

[0023] [Schematic structure of the first and second transistors] The first transistor 100 and the second transistor 200 are configured as HEMTs using nitride semiconductors.

[0024] In the following, we will first describe the cross-sectional structure of the first transistor 100 with reference to Figure 3, and then describe the planar layout of the first transistor 100 with reference to Figures 1 and 2. Figure 3 shows the structure of a HEMT using GaN as an example of the first transistor 100.

[0025] The first transistor 100 includes a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The first transistor 100 further includes an electron transport layer 16 located on the buffer layer 14 and an electron supply layer 18 located on the electron transport layer 16. The electron transport layer 16 is composed of a first nitride semiconductor layer 15A in a first region R1. The electron supply layer 18 is composed of a second nitride semiconductor layer 15B in the first region R1. Within the electron transport layer 16, 2DEG20 extends near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18.

[0026] The first transistor 100 further includes a gate layer 22 located on the electron supply layer 18 and a gate electrode 24 located on the gate layer 22. The gate layer 22 is partially provided on the electron supply layer 18.

[0027] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. For example, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. In one example, the gate layer 22 is GaN containing at least one of Mg and Zn as an impurity.

[0028] The gate electrode 24 includes one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. In another example, the gate electrode 24 includes a first metal layer formed of Ti and a second metal layer located on the first metal layer and formed of TiN. The gate electrode 24 forms a Schottky junction with the gate layer 22. The gate electrode 24 is partially provided on the gate layer 22. The gate electrode 24 may have a thickness of, for example, 50 nm or more and 200 nm or less.

[0029] The first transistor 100 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed of at least one of the following materials: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 50 nm to 150 nm.

[0030] The passivation layer 26 includes a source opening 26A and a drain opening 26B that are spaced apart from each other in the X-axis direction. The gate layer 22 is located between the source opening 26A and the drain opening 26B. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0031] The first transistor 100 includes a source electrode 28 that contacts the electron supply layer 18 through a source opening 26A, and a drain electrode 30 that contacts the electron supply layer 18 through a drain opening 26B. The source electrode 28 and the drain electrode 30 may include one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including a Ti layer, AlCu layer, Ti layer, and TiN layer in that order from the top.

[0032] The source electrode 28 includes a source contact portion 28A filled within the source opening 26A and an extension portion 28B formed integrally with the source contact portion 28A and located on the passivation layer 26. The source contact portion 28A is in ohmic contact with the 2DEG20 directly beneath the electron supply layer 18 via the source opening 26A. The extension portion 28B functions as a source field plate electrode.

[0033] In the example shown in Figure 3, the extension portion 28B (source field plate electrode) covers the gate electrode 24 and the entire gate layer 22. The extension portion 28B includes an end portion 28BE facing the drain electrode 30 as the source field plate electrode end portion. The extension portion 28B (source field plate electrode) plays a role in mitigating electric field concentration near the end of the gate layer 22 when a high voltage is applied between the source and drain in the off state, when 2DEG20 in the region of the electron transport layer 16 directly below the gate layer 22 has disappeared.

[0034] The drain electrode 30 includes a drain contact portion 30A filled within the drain opening 26B. The drain contact portion 30A is in ohmic contact with the 2DEG20 directly beneath the electron supply layer 18 via the drain opening 26B.

[0035] In the first transistor 100 configured as described above, the inclusion of acceptor-type impurities in the gate layer 22 raises the energy levels of the electron transport layer 16 and the electron supply layer 18. As a result, in the region directly beneath the gate layer 22, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Consequently, when a gate control voltage that turns off the first transistor 100 is applied to the gate electrode 24 (for example, when the gate-source voltage is 0V or lower), 2DEG20 is not formed in the region of the electron transport layer 16 directly beneath the gate layer 22. On the other hand, 2DEG20 is formed in the regions of the electron transport layer 16 other than the region directly beneath the gate layer 22.

[0036] Thus, the presence of the acceptor-type impurity-doped gate layer 22 causes 2DEG20 to disappear in the region of the electron transport layer 16 directly beneath the gate layer 22, thereby realizing the normally-off operation of the transistor. When an appropriate gate control voltage (on voltage) is applied to the gate electrode 24, a channel formed by 2DEG20 is created in the region of the electron transport layer 16 directly beneath the gate layer 22, and the source-drain junction becomes conductive.

[0037] The first transistor 100 includes a source electrode 28, a drain electrode 30, and an interlayer insulating film 40 covering the passivation layer 26. The interlayer insulating film 40 is formed of at least one of the following: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the interlayer insulating film 40 is formed of SiO2. The interlayer insulating film 40 may have a thickness of, for example, 500 nm to 2000 nm.

[0038] Source wiring 41 and drain wiring 42 are arranged on the interlayer insulating film 40. Source wiring 41 is electrically connected to the source electrode 28 through source via 40A which penetrates the interlayer insulating film 40. Drain wiring 42 is electrically connected to the drain electrode 30 through drain via 40B which penetrates the interlayer insulating film 40. Although not shown in Figure 3, gate wiring 43 is also arranged on the interlayer insulating film 40. Gate wiring 43 is electrically connected to the gate electrode 24 through gate via 40C which penetrates the interlayer insulating film 40 (see Figure 1). Details of gate wiring 43 and gate via 40C will be described later.

[0039] The gate wiring 43, source wiring 41, and drain wiring 42 may include one or more metal layers. For example, the gate wiring 43, source wiring 41, and drain wiring 42 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the gate wiring 43, source wiring 41, and drain wiring 42 have a four-layer structure (Ti layer / TiN layer / AlCu layer / TiN layer) including a Ti layer, TiN layer, AlCu layer, and TiN layer in that order from the top.

[0040] The planar layout of the first transistor 100 in the first region R1 will be described with reference to Figures 1 and 2. Figure 2 is an enlarged planar view of a portion of Figure 1. Figure 3 is a cross-sectional view taken along the line F3-F3 in Figure 2. In Figure 1, the gate layer 22, the passivation layer 26, and the interlayer insulating film 40 are omitted from the illustration. Also, in Figure 1, the extension portion 28B of the source electrode 28 is omitted from the illustration, and only the source contact portion 28A is shown.

[0041] As shown in Figure 1, in the first region R1, the source contact portion 28A, the gate electrode 24, and the drain electrode 30 are arranged side by side in the X-axis direction. The combination of the source electrode 28, gate electrode 24, and drain electrode 30 arranged side by side in the X-axis direction constitutes one HEMT cell. Note that the example in Figure 1 shows a case where multiple HEMT cells arranged side by side in the X-axis direction are formed. The number of HEMT cells is not particularly limited, and the first transistor 100 may include one or more HEMT cells.

[0042] As shown in Figure 1, a plurality of source wirings 41 and a plurality of drain wirings 42 are arranged on the interlayer insulating film 40 in the first region R1. In the first region R1, the plurality of source wirings 41 and a plurality of drain wirings 42 are arranged alternately, spaced apart in the Y-axis direction. Each of the plurality of source wirings 41 and a plurality of drain wirings 42 is rectangular in shape in a plan view, extending in the X-axis direction, and is arranged to straddle a plurality of gate electrodes 24, a plurality of source electrodes 28, and a plurality of drain electrodes 30 in the X-axis direction. Each of the source wirings 41 is electrically connected to a source pad (not shown). Each of the drain wirings 42 is electrically connected to a drain pad (not shown).

[0043] As shown in Figure 1, in a plan view, the gate electrode 24 is formed in a ring shape so as to surround the source contact portion 28A of the source electrode 28. The ring-shaped gate electrode 24 includes two main body portions 24A, a first connecting portion 24B, and a second connecting portion 24C. The two main body portions 24A extend in the Y-axis direction and are spaced apart in the X-axis direction with the source contact portion 28A in between. The first connecting portion 24B is the Y-axis end of the two main body portions 24A and connects the ends opposite to the third region R3. The second connecting portion 24C is the Y-axis end of the two main body portions 24A and connects the ends on the third region R3 side.

[0044] The gate wiring 43 is located in the first region R1 on the opposite side of the third region R3 from the multiple source wirings 41 and multiple drain wirings 42 that are aligned in the Y-axis direction. In other words, the gate wiring 43 is located adjacent to the Y-axis direction of the wiring that is located at the opposite end of the multiple source wirings 41 and multiple drain wirings 42 that are aligned in the Y-axis direction from the third region R3.

[0045] Although a cross-sectional view is omitted, the gate wiring 43 is located on the interlayer insulating film 40, specifically on the first connection portion 24B of the gate electrode 24. The gate wiring 43 is electrically connected to the first connection portion 24B of the gate electrode 24 through a gate via 40C that penetrates the interlayer insulating film 40. The gate wiring 43 is also electrically connected to a gate pad (not shown).

[0046] The schematic structure of the second transistor 200 in the second region R2 is the same as the schematic structure of the first transistor 100 in the first region R1 described above. Therefore, the second transistor 200 is given the same reference numeral as the first transistor 100 in the drawing, and its detailed description is omitted.

[0047] Hereinafter, the electron transport layer 16, electron supply layer 18, gate layer 22, gate electrode 24, passivation layer 26, source opening 26A, drain opening 26B, source electrode 28, and drain electrode 30 included in the first transistor 100 may be referred to as the first electron transport layer 16, first electron supply layer 18, first gate layer 22, first gate electrode 24, first passivation layer 26, first source opening 26A, first drain opening 26B, first source electrode 28, and first drain electrode 30, respectively. Also, the interlayer insulating film 40, source wiring 41, drain wiring 42, and gate wiring 43 included in the first transistor 100 may be referred to as the first interlayer insulating film 40, first source wiring 41, first drain wiring 42, and first gate wiring 43, respectively.

[0048] Similarly, the electron transport layer 16, electron supply layer 18, gate layer 22, gate electrode 24, passivation layer 26, source opening 26A, drain opening 26B, source electrode 28, and drain electrode 30 included in the second transistor 200 may be described as the second electron transport layer 16, second electron supply layer 18, second gate layer 22, second gate electrode 24, second passivation layer 26, second source opening 26A, second drain opening 26B, second source electrode 28, and second drain electrode 30, respectively. In addition, the interlayer insulating film 40, source wiring 41, drain wiring 42, and gate wiring 43 included in the second transistor 200 may be described as the second interlayer insulating film 40, second source wiring 41, second drain wiring 42, and second gate wiring 43, respectively.

[0049] [Simultaneous structure of the temperature sensor] Below, we will first describe the cross-sectional structure of the temperature sensor 300 with reference to Figure 4, and then describe the planar layout of the temperature sensor 300 with reference to Figure 2.

[0050] The temperature sensor 300 includes a first nitride semiconductor layer 15A and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A. The temperature sensor 300 includes a third passivation layer 301 covering the second nitride semiconductor layer 15B in the third region R3. The third passivation layer 301 is a single layer continuous with the first passivation layer 26 of the first transistor 100 and the second passivation layer 26 of the second transistor 200. Therefore, the first passivation layer 26, the second passivation layer 26, and the third passivation layer 301 have the same material and film thickness.

[0051] The third passivation layer 301 includes a first sensor aperture 301A and a second sensor aperture 301B that are spaced apart from each other in the X-axis direction. The temperature sensor 300 includes a first sensor electrode 302 that contacts the second nitride semiconductor layer 15B through a first sensor aperture 301A, and a second sensor electrode 303 that contacts the second nitride semiconductor layer 15B through a second sensor aperture 301B. The first sensor electrode 302 and the second sensor electrode 303 are positioned spaced apart from each other in the X-axis direction on the second nitride semiconductor layer 15B in the third region R3.

[0052] The first sensor electrode 302 is in ohmic contact with 2DEG20 directly beneath the electron supply layer 18 via the first sensor aperture 301A. The second sensor electrode 303 is in ohmic contact with 2DEG20 directly beneath the electron supply layer 18 via the second sensor aperture 301B.

[0053] The first sensor electrode 302 and the second sensor electrode 303 may include one or more metal layers. For example, the first sensor electrode 302 and the second sensor electrode 303 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including a Ti layer, AlCu layer, Ti layer, and TiN layer in that order from the top.

[0054] The film thickness of the first sensor electrode 302 and the second sensor electrode 303 is, for example, between 150 μm and 500 μm. In one example, the first source electrode 28 and the first drain electrode 30 of the first transistor, the second source electrode 28 and the second drain electrode 30 of the second transistor, and the first sensor electrode 302 and the second sensor electrode 303 are made of the same material and have the same film thickness.

[0055] The temperature sensor 300 further includes a temperature sensing unit 304. The temperature sensing unit 304 is composed of a first nitride semiconductor layer 15A and a second nitride semiconductor layer 15B located between the first sensor electrode 302 and the second sensor electrode 303 in the X-axis direction.

[0056] The length L5 of the temperature sensing unit 304 in the X-axis direction is, for example, 0.5 mm or more and 2 mm or less. The length L5 of the temperature sensing unit 304 is, for example, the distance between the contact surface of the first sensor electrode 302 and the second nitride semiconductor layer 15B and the contact surface of the second sensor electrode 303 and the second nitride semiconductor layer 15B. The length of the temperature sensing unit 304 in the Y-axis direction is equal to the length L3 of the third region R3 in the Y-axis direction (see Figure 2).

[0057] The temperature sensing unit 304 includes a first sensor electrode 302, a second sensor electrode 303, and a third interlayer insulating film 305 covering the third passivation layer 301. The third interlayer insulating film 305 is a single layer continuous with the first interlayer insulating film 40 of the first transistor 100 and the second interlayer insulating film 40 of the second transistor 200. Therefore, the first interlayer insulating film 40, the second interlayer insulating film 40, and the third interlayer insulating film 305 have the same material and film thickness.

[0058] A first sensor wiring 306 and a second sensor wiring 307 are arranged on the third interlayer insulating film 305. The first sensor wiring 306 is electrically connected to the first sensor electrode 302 through a first sensor via 304A that penetrates the third interlayer insulating film 305. The second sensor wiring 307 is electrically connected to the second sensor electrode 303 through a second sensor via 304B that penetrates the third interlayer insulating film 305.

[0059] The first sensor wiring 306 and the second sensor wiring 307 may include one or more metal layers. For example, the first sensor wiring 306 and the second sensor wiring 307 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the first source wiring 41, first drain wiring 42, and first gate wiring 43 of the first transistor 100, the second source wiring 41, second drain wiring 42, and second gate wiring 43 of the second transistor 200, and the first sensor wiring 306 and second sensor wiring 307 of the temperature sensing unit 304 are made of the same material and have the same film thickness.

[0060] The temperature sensor 300 utilizes the nitride semiconductor layer 15 located in the temperature sensing unit 304 as a resistance thermometer. As the temperature increases, phonon scattering due to GaN lattice vibrations increases in the nitride semiconductor layer 15. As a result, the 2DEG20 formed in the first nitride semiconductor layer 15A diffuses, and the electrical resistance of the nitride semiconductor layer 15, which is the temperature sensing unit 304, increases. The temperature sensor 300 detects the electrical resistance of the temperature sensing unit 304 caused by the temperature change. The temperature sensor 300 is used to estimate the temperature of the nitride semiconductor device 10 from the electrical resistance of the temperature sensing unit 304.

[0061] [Schematic structure of element isolation region] As shown in Figure 1, the nitride semiconductor device 10 includes an element isolation region R4 for separating the first region R1, the second region R2, and the third region R3. In a plan view, the element isolation region R4 is located between the first region R1 and the third region R3, and between the second region R2 and the third region R3. The element isolation region R4 also surrounds the first region R1, the second region R2, and the third region R3. Each of the first region R1, the second region R2, and the third region R3 is defined in a plan view as a region surrounded by the element isolation region R4.

[0062] The element isolation region R4 functionally separates the first region R1, the second region R2, and the third region R3 by partially eliminating 2DEG20 which extends across the first nitride semiconductor layer 15A.

[0063] The element isolation region R4 is, for example, a region on the first nitride semiconductor layer 15A where the second nitride semiconductor layer 15B is partially absent. An example of the structure of the element isolation region R4 is shown in Figure 4. In the example shown in Figure 4, an element isolation region R4 is formed by removing a portion of the first nitride semiconductor layer 15A. As shown in Figure 4, in the element isolation region R4, a portion R4A is provided where the second nitride semiconductor layer 15B has been removed. Furthermore, in the portion R4A, the surface layer on the second nitride semiconductor layer 15B side of the first nitride semiconductor layer 15A is also partially removed.

[0064] The second nitride semiconductor layer 15B can be removed by etching or the like. Furthermore, the surface layer of the first nitride semiconductor layer 15A can be removed together with the second nitride semiconductor layer 15B when the second nitride semiconductor layer 15B is removed by etching or the like. Note that the configuration for removing the surface layer of the first nitride semiconductor layer 15A is intended to ensure that the first nitride semiconductor layer 15A does not remain after etching, and therefore can be omitted.

[0065] In the element isolation region R4, the above-mentioned portion R4A is filled by the third interlayer insulating film 305 in the third region R3, the first interlayer insulating film 40 in the first region R1, and the second interlayer insulating film 40 in the second region R2.

[0066] Furthermore, the element isolation region R4 may be a region in the second nitride semiconductor layer 15B that contains inert atoms. For example, in a plan view, inert atoms that cause 2DEG20 to disappear are implanted into the portion of the second nitride semiconductor layer 15B that becomes the element isolation region R4. The inert atoms are, for example, argon (Ar). Due to the implantation of inert atoms, the second nitride semiconductor layer 15B, although existing on the first nitride semiconductor layer 15A, loses its ability to form 2DEG20 in the first nitride semiconductor layer 15A. As a result, the 2DEG20 directly beneath the ion-implanted second nitride semiconductor layer 15B in the first nitride semiconductor layer 15A partially disappears.

[0067] As shown in Figure 2, the length L4 in the Y-axis direction of the element isolation region R4 is, for example, 1 μm or more and 10 μm or less. The length L4 of the element isolation region R4 may be constant or may vary from part to part.

[0068] [Gate connection wiring] As shown in Figure 1, in a plan view, the first gate electrode 24 located in the first region R1 and the second gate electrode 24 located in the second region R2 are arranged so as to be aligned in the Y-axis direction with the third region R3 in between. Multiple pairs of the first gate electrode 24 and the second gate electrode 24, which are aligned in the Y-axis direction with the third region R3 in between, are arranged so as to be aligned in the X-axis direction.

[0069] The nitride semiconductor device 10 includes gate connection wiring 310 that electrically connects the first gate electrode 24 and the second gate electrode 24, which are aligned in the Y-axis direction with a third region R3 in between. In the example shown in Figure 1, one gate connection wiring 310 is provided for each pair of first gate electrode 24 and second gate electrode 24 aligned in the Y-axis direction. Alternatively, multiple gate connection wirings 310 aligned in the X-axis direction may be provided for each pair.

[0070] As shown in Figure 2, the gate connection wiring 310 includes a first portion located in the first region R1 and a second portion located in the second region R2. The first portion is located on the first gate electrode 24 in the first region R1, with the first interlayer insulating film 40 in between. The first portion is located on the first interlayer insulating film 40 and is electrically connected to the first gate electrode 24 through a first connection via 40D1 that penetrates the first interlayer insulating film 40. The second portion is located on the second gate electrode 24 in the second region R2, with the second interlayer insulating film 40 in between. The second portion is located on the second interlayer insulating film 40 and is electrically connected to the second gate electrode 24 through a second connection via 40D2 that penetrates the second interlayer insulating film 40.

[0071] The gate connection wiring 310 may include one or more metal layers. For example, the gate connection wiring 310 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the first sensor wiring 306, the second sensor wiring 307, and the gate connection wiring 310 have the same material and film thickness. Also in one example, the first source wiring 41, the first drain wiring 42, and the first gate wiring 43 of the first transistor 100, the second source wiring 41, the second drain wiring 42, and the second gate wiring 43 of the second transistor 200, the first sensor wiring 306 and the second sensor wiring 307 of the temperature sensing unit 304, and the gate connection wiring 310 have the same material and film thickness.

[0072] The length L6 of the gate connection wiring 310 in the X-axis direction is, for example, 10 μm or more and 100 μm or less (see Figure 4). The length L6 of the gate connection wiring 310 may be the same for all gate connection wirings 310, or it may be different for each gate connection wiring 310.

[0073] The diameter of the first connection via 40D1 is, for example, 0.5 μm or more and 1.0 μm or less. There may be one or more first connection vias 40D1 connected to the first portion of the gate connection wiring 310. The diameter of the second connection via 40D2 is, for example, 0.5 μm or more and 1.0 μm or less. There may be one or more second connection vias 40D2 connected to the second portion of a single gate connection wiring 310.

[0074] [Manufacturing method for nitride semiconductor devices] Next, an example of a manufacturing method for the nitride semiconductor device 10 shown in Figure 1 will be described. Figures 5 to 26 are schematic cross-sectional views illustrating exemplary manufacturing processes for the nitride semiconductor device 10. Figure 5 is a cross-sectional view showing the manufacturing process common to the first transistor 100, the second transistor 200, and the temperature sensor 300. Figures 6 to 15 are cross-sectional views showing the manufacturing processes for the first transistor 100 and the second transistor 200, corresponding to the cross-sectional structure of the first transistor 100 shown in Figure 3. Figures 16 to 26 are cross-sectional views showing the manufacturing process for the temperature sensor 300, corresponding to the cross-sectional structure of the temperature sensor 300 shown in Figure 4. For ease of understanding, in Figures 5 to 26, components similar to those in Figure 3 or Figure 4 are denoted by the same reference numerals.

[0075] As shown in Figure 5, the manufacturing method for the nitride semiconductor device 10 includes sequentially forming a buffer layer 14, a first nitride semiconductor layer 15A, a second nitride semiconductor layer 15B, a third nitride semiconductor layer 15C, and a first metal layer 401 on a semiconductor substrate 12. The buffer layer 14, the first nitride semiconductor layer 15A, the second nitride semiconductor layer 15B, and the third nitride semiconductor layer 15C can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD).

[0076] Although detailed illustrations are omitted, in one example, the buffer layer 14 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 12 and a grated AlGaN layer (second buffer layer) formed on the AlN layer. The grated AlGaN layer can be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0077] The first nitride semiconductor layer 15A formed on the buffer layer 14 may be a GaN layer. The second nitride semiconductor layer 15B formed on the first nitride semiconductor layer 15A may be an AlGaN layer. Therefore, the second nitride semiconductor layer 15B is composed of a nitride semiconductor having a larger band gap than the first nitride semiconductor layer 15A.

[0078] The third nitride semiconductor layer 15C is a layer for forming the gate layer 22, and is, for example, a GaN layer containing Mg as an acceptor-type impurity. The third nitride semiconductor layer 15C is formed by doping GaN with Mg while growing GaN on the second nitride semiconductor layer 15B. The first metal layer 401 is a layer for forming the gate electrode 24, and is, for example, a TiN layer. The first metal layer 401 is formed, for example, by sputtering.

[0079] As shown in Figure 6, the manufacturing method for the nitride semiconductor device 10 includes a step of forming a gate electrode 24 in a first region R1 and a second region R2. The gate electrode 24 is formed by selectively removing the first metal layer 401. In one example, a mask layer is formed on the first metal layer 401 to cover the region where the gate electrode 24 is to be formed. In one example, the mask layer is formed of a resist film. The gate electrode 24 is formed by selectively removing the first metal layer 401 using the mask layer. As shown in Figure 16, in the third region R3 and the element isolation region R4, the first metal layer 401 is removed in the step of forming the gate electrode 24.

[0080] As shown in Figure 7, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a gate layer 22 in the first region R1 and the second region R2. The gate layer 22 is formed by selectively removing the third nitride semiconductor layer 15C. In one example, a mask layer is formed on the third nitride semiconductor layer 15C to cover the region where the gate layer 22 is to be formed. The mask layer is formed, for example, from a resist film. The gate layer 22 is formed by selectively removing the third nitride semiconductor layer 15C using the mask layer. As shown in Figure 17, in the third region R3 and the device isolation region R4, the third nitride semiconductor layer 15C is removed in the step of forming the gate layer 22.

[0081] As shown in Figure 8, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a passivation layer 403 on the first nitride semiconductor layer 15A. The passivation layer 403 is a layer that becomes the first passivation layer 26 in the first region R1, and a layer that becomes the second passivation layer 26 in the second region R2. In one example, the passivation layer 403 can be formed by the Low Pressure Chemical Vapor Deposition (LPCVD) method. As shown in Figure 18, the passivation layer 403 is also formed in the third region R3 and the device isolation region R4 by the step of forming the passivation layer 403. The passivation layer 403 is a layer that becomes the third passivation layer 301 in the third region R3.

[0082] As shown in Figure 19, the manufacturing method of the nitride semiconductor device 10 includes a removal step to remove the passivation layer 403 and the second nitride semiconductor layer 15B in the element isolation region R4. In one example, a mask layer is formed on the passivation layer 403 that exposes the region that will become the element isolation region R4. In one example, the mask layer is formed of a resist film. The passivation layer 403 and the second nitride semiconductor layer 15B are selectively removed using the mask layer. In the removal step, a part of the surface side of the first nitride semiconductor layer 15A may also be removed. The removal step forms an opening 404 that penetrates the passivation layer 403 and the second nitride semiconductor layer 15B in the thickness direction.

[0083] As shown in Figure 9, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a source opening 26A and a drain opening 26B in a first region R1 and a second region R2. The source opening 26A and the drain opening 26B can be formed by selectively removing the passivation layer 403 (first passivation layer 26, second passivation layer 26).

[0084] As shown in Figure 20, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a first sensor aperture 301A and a second sensor aperture 301B in a third region R3. The first sensor aperture 301A and the second sensor aperture 301B can be formed by selectively removing the passivation layer 403 (third passivation layer 301). In one example, a mask layer is formed on the passivation layer 403 that exposes the regions for forming the source aperture 26A, drain aperture 26B, first sensor aperture 301A, and second sensor aperture 301B. In one example, the mask layer is formed of a resist film. By selectively removing the passivation layer 403 using the mask layer, the above-mentioned apertures are formed.

[0085] As shown in Figures 10 and 21, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a second metal layer 405 on the passivation layer 403. The second metal layer 405 is a layer that becomes the first source electrode 28 and the first drain electrode 30 in the first region R1, a layer that becomes the second source electrode 28 and the second drain electrode 30 in the second region R2, and a layer that becomes the first sensor electrode 302 and the second sensor electrode 303 in the third region R3. The second metal layer 405 is formed, for example, by sputtering. As shown in Figure 10, the second metal layer 405 is in contact with the second nitride semiconductor layer 15B (first electron supply layer 18, second electron supply layer 18) at the source opening 26A and the drain opening 26B. Also, as shown in Figure 21, the second metal layer 405 is in contact with the second nitride semiconductor layer 15B at the first sensor opening 301A and the second sensor opening 301B.

[0086] As shown in Figure 11, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a source electrode 28 and a drain electrode 30 in a first region R1 and a second region R2. The source electrode 28 and the drain electrode 30 are formed by selectively removing the second metal layer 405.

[0087] As shown in Figure 22, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a first sensor electrode 302 and a second sensor electrode 303 in a third region R3. The first sensor electrode 302 and the second sensor electrode 303 are formed by selectively removing the second metal layer 405.

[0088] In one example, a mask layer is formed on the second metal layer 405, covering the areas where the source electrode 28, drain electrode 30, first sensor electrode 302, and second sensor electrode 303 are to be formed. In one example, the mask layer is formed from a resist film. The above electrodes are formed by selectively removing the second metal layer 405 using the mask layer.

[0089] As shown in Figures 12 and 23, the manufacturing method of the nitride semiconductor device 10 includes a step of forming an interlayer insulating film 406. The interlayer insulating film 406 is a layer that becomes the first interlayer insulating film 40 in the first region R1, a layer that becomes the second interlayer insulating film 40 in the second region R2, and a layer that becomes the third interlayer insulating film 305 in the third region R3. In addition, the interlayer insulating film 406 fills the opening 404 in the element isolation region R4.

[0090] As shown in Figure 13, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a source via hole 406A, a drain via hole 406B, and a gate via hole (not shown) in the first region R1 and the second region R2. Although not shown, the manufacturing method for the nitride semiconductor device 10 also includes the step of forming a first connection via hole and a second connection via hole in the first region R1 and the second region R2. The source via hole 406A, the drain via hole 406B, and the gate via hole are through holes provided in the interlayer insulating film 406 for forming a source via 40A, a drain via 40B, and a gate via 40C. The first connection via hole and the second connection via hole are through holes provided in the interlayer insulating film 406 for forming a first connection via 40D1 and a second connection via 40D2. The source via hole 406A, drain via hole 406B, gate via hole, first connecting via hole, and second connecting via hole can be formed by selectively removing the interlayer insulating film 406.

[0091] As shown in Figure 24, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a first sensor via hole 406C and a second sensor via hole 406D in the third region R3. The first sensor via hole 406C and the second sensor via hole 406D are through holes provided in the interlayer insulating film 406 for forming a first sensor via 304A and a second sensor via 304B.

[0092] In one example, a mask layer is formed on the interlayer insulating film 406, exposing the regions where the source via hole 406A, drain via hole 406B, gate via hole, first connection via hole, second connection via hole, first sensor via hole 406C, and second sensor via hole 406D are to be formed. In one example, the mask layer is formed of a resist film. By using the mask layer to selectively remove the interlayer insulating film 406, the above-mentioned via holes are formed.

[0093] As shown in Figures 14 and 25, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a third metal layer 407 on an interlayer insulating film 406. The third metal layer 407 is a layer that becomes the first gate wiring 43, the first source wiring 41, and the first drain wiring 42 in the first region R1, a layer that becomes the second gate wiring 43, the second source wiring 41, and the second drain wiring 42 in the second region R2, and a layer that becomes the first sensor wiring 306 and the second sensor wiring 307 in the third region R3. The third metal layer 407 is also a layer that becomes the gate connection wiring 310 that spans the first region R1, the second region R2, and the third region R3. Furthermore, a portion of the third metal layer 407 fills each via hole formed in the interlayer insulating film 406, thereby forming the source via 40A, drain via 40B, gate via 40C, first sensor via 304A, second sensor via 304B, first connection via 40D1, and second connection via 40D2. The third metal layer 407 is formed, for example, by sputtering.

[0094] As shown in Figure 15, the manufacturing method of the nitride semiconductor device 10 includes the steps of forming a first gate wiring 43 (not shown), a first source wiring 41, a first drain wiring 42, a second gate wiring 43 (not shown), a second source wiring 41, and a second drain wiring 42 in a first region R1 and a second region R2. Each of the above wirings is formed by selectively removing the third metal layer 407.

[0095] As shown in Figure 26, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a first sensor wiring 306 and a second sensor wiring 307 in the third region R3. The first sensor wiring 306 and the second sensor wiring 307 are formed by selectively removing the third metal layer 407. The manufacturing method for the nitride semiconductor device 10 also includes the step of forming a gate connection wiring 310 that spans the first region R1, the second region R2, and the third region R3. The gate connection wiring 310 are formed by selectively removing the third metal layer 407.

[0096] In one example, a mask layer is formed on the third metal layer 407, covering the areas where the first gate wiring 43, first source wiring 41, first drain wiring 42, second gate wiring 43, second source wiring 41, second drain wiring 42, first sensor wiring 306, second sensor wiring 307, and gate connection wiring 310 are to be formed. In one example, the mask layer is formed from a resist film. The above wirings are formed by selectively removing the third metal layer 407 using the mask layer. Through the above steps, the nitride semiconductor device 10 shown in Figure 1 is obtained.

[0097] [Effect of the Embodiment] In a plan view, the nitride semiconductor device 10 has a temperature sensor 300 positioned between the first transistor 100 and the second transistor 200. In the nitride semiconductor device 10, the region between the adjacent first transistor 100 and the second transistor 200 is a region where the temperature tends to rise particularly easily. Therefore, by positioning the temperature sensor 300 between the first transistor 100 and the second transistor 200, the temperature rise of the nitride semiconductor device 10 can be detected early and with high accuracy.

[0098] On the other hand, if a temperature sensor 300 is placed between the first transistor 100 and the second transistor 200, the gate resistance of the first transistor 100 and the second transistor 200 increases. As shown in Figure 1, when a temperature sensor 300 is placed between the first transistor 100 and the second transistor 200 which are aligned in the Y-axis direction, the gate wiring 43 is placed on the opposite side of the temperature sensor 300 in the Y-axis direction, with the first transistor 100 (or the second transistor 200) in between. In this case, the gate electrode 24 has a shape that extends in the Y-axis direction from the gate wiring 43 side toward the temperature sensor 300 side. As a result, the distance from the gate wiring 43 to the tip of the gate electrode 24 closer to the temperature sensor 300 becomes longer, and the gate resistance increases. An increase in gate resistance is a factor that reduces the response speed of the nitride semiconductor device 10.

[0099] In the nitride semiconductor device 10 of this embodiment, a gate connection wiring 310 is provided that spans over the temperature sensing unit 304 and electrically connects the first gate electrode 24 of the first transistor 100 and the second gate electrode 24 of the second transistor 200. In other words, the tip of the gate electrode 24 of the first transistor 100 that is closer to the temperature sensor 300 and the tip of the gate electrode 24 of the second transistor 200 that is closer to the temperature sensor 300 are electrically connected via the gate connection wiring 310 placed on top of the temperature sensing unit 304 of the temperature sensor 300.

[0100] In this case, two conduction paths are formed to the tip of the gate electrode 24 on the side closer to the temperature sensor 300: a first conduction path passing through the gate wiring 43 and gate electrode 24 on the first transistor 100 side, and a second conduction path passing through the gate wiring 43 and gate electrode 24 on the second transistor 200 side. This suppresses the increase in gate resistance caused by the increased distance from the gate wiring 43 to the tip of the gate electrode 24 on the side closer to the temperature sensor 300.

[0101] [Effects of the Embodiment] (1) The nitride semiconductor device 10 includes a nitride semiconductor layer 15, a first region R1 where the first transistor 100 is located, a second region R2 where the second transistor 200 is located, and a third region R3 located between the first region R1 and the second region R2 where the temperature sensor 300 and the gate connection wiring 310 are located. The nitride semiconductor layer 15 includes a first nitride semiconductor layer 15A, and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A and having a larger band gap than the first nitride semiconductor layer 15A.

[0102] The temperature sensor 300 includes a first sensor electrode 302 and a second sensor electrode 303 located spaced apart from each other on the second nitride semiconductor layer 15B in the third region R3, and a temperature sensing unit 304 located between the first sensor electrode 302 and the second sensor electrode 303 and composed of the nitride semiconductor layer 15 in the third region R3. The gate connection wiring 310 spans over the temperature sensing unit 304 and electrically connects the gate electrode 24 of the first transistor 100 and the gate electrode 24 of the second transistor 200.

[0103] In this case, by placing the temperature sensor 300 between the first transistor 100 and the second transistor 200, the temperature rise of the nitride semiconductor device 10 can be detected with high accuracy. Therefore, control to protect the nitride semiconductor device 10 from becoming overheated can be performed with greater precision. In addition, by providing gate connection wiring 310 that electrically connects the gate electrodes 24 of the first transistor 100 and the second transistor 200, the increase in gate resistance caused by placing the temperature sensor 300 between the first transistor 100 and the second transistor 200 can be suppressed. Thus, both temperature detection and response speed of the nitride semiconductor device 10 can be achieved at a high level.

[0104] (2) The gate connection wiring 310 includes a first portion located on the first interlayer insulating film 40 and a second portion located on the second interlayer insulating film 40. It is electrically connected to the first gate electrode 24 via a first connection via 40D1 that penetrates the first interlayer insulating film 40 and to the second gate electrode 24 via a second connection via 40D2 that penetrates the second interlayer insulating film 40.

[0105] In this case, the gate electrode 24 of the first transistor 100 and the gate electrode 24 of the second transistor 200, which are located adjacent to each other across the third region R3 where the temperature sensor 300 is located, can be connected by the shortest distance. Therefore, the effect of suppressing the increase in gate resistance caused by providing the gate connection wiring 310 is more pronounced.

[0106] (3) The temperature sensor 300 includes a third passivation layer 301 that covers the second nitride semiconductor layer 15B and has a first sensor opening 301A and a second sensor opening 301B that are spaced apart from each other, a first sensor electrode 302 that is in contact with the second nitride semiconductor layer 15B through the first sensor opening 301A, and a second sensor electrode 303 that is in contact with the second nitride semiconductor layer 15B through the second sensor opening 301B.

[0107] In this case, the temperature sensor 300 detects the electrical resistance of the nitride semiconductor layer 15 (temperature sensing unit 304) based on the change in 2DEG20 caused by the temperature change. Therefore, the 2DEG20 formed on the nitride semiconductor layer 15 can be used by both the first transistor 100 and the second transistor 200, and the temperature sensor 300.

[0108] (4) The first sensor wiring 306 and the second sensor wiring 307 of the temperature sensor 300 and the gate connection wiring 310 are made of the same material and have the same film thickness. In this case, the first sensor wiring 306 and the second sensor wiring 307 of the temperature sensor 300 and the gate connection wiring 310 can be formed simultaneously in the same process. This contributes to simplifying the manufacturing process.

[0109] (5) The first passivation layer 26 of the first transistor 100, the second passivation layer 26 of the second transistor 200, and the third passivation layer 301 of the temperature sensor 300 are made of the same material and have the same film thickness. The first source electrode 28 and the first drain electrode 30 of the first transistor 100, the second source electrode 28 and the second drain electrode 30 of the first transistor 100, and the first sensor electrode 302 and the second sensor electrode 303 of the temperature sensor 300 are made of the same material and have the same film thickness. The first interlayer insulating film 40 of the first transistor 100, the second interlayer insulating film 40 of the second transistor 200, and the third interlayer insulating film 305 of the temperature sensor 300 are made of the same material and have the same film thickness. The first source wiring 41, first drain wiring 42, and first gate wiring 43 of the first transistor 100, the second source wiring 41, second drain wiring 42, and second gate wiring 43 of the second transistor 200, and the first sensor wiring 306 and second sensor wiring 307 of the temperature sensor 300 are made of the same material and have the same film thickness.

[0110] In this case, the components formed from the same material in the first transistor 100, the second transistor 200, and the temperature sensor 300 can be formed simultaneously in the same process. Therefore, the first transistor 100, the second transistor 200, and the temperature sensor 300 can be fabricated on the same chip without excessively increasing the number of manufacturing steps.

[0111] (6) The nitride semiconductor device 10 includes an element isolation region R4 located between the first region R1 and the third region R3, and between the second region R2 and the third region R3. In this case, it becomes easier to independently operate the first transistor 100 located in the first region R1 and the temperature sensor 300 located in the third region R3. It also becomes easier to independently operate the second transistor 200 located in the second region R2 and the temperature sensor 300 located in the third region R3.

[0112] One or more of the various examples described herein can be combined to the extent that they do not conflict with the technical specifications. As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are formed between the first and second elements.

[0113] The Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the Z-axis direction "up" and "down" being vertical. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0114] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments described above. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0115] [Note 1] Nitride semiconductor layer (15), The first region (R1) where the first transistor (100) is located, The second region (R2) where the second transistor (200) is located, A third region (R3) located between the first region (R1) and the second region (R2), in which a temperature sensor (300) and gate connection wiring (310) are located, is included. The nitride semiconductor layer (15) is The material includes a first nitride semiconductor layer (15A) and a second nitride semiconductor layer (15B) located on the first nitride semiconductor layer (15A) and having a larger band gap than the first nitride semiconductor layer (15A). The first transistor (100) is, A first electron transport layer (16) is formed by the first nitride semiconductor layer (15A) in the first region (R1), A first electron supply layer (18) is formed by the second nitride semiconductor layer (15B) in the first region (R1), The first electron supply layer (18) includes a first gate electrode (24), a first source electrode (28), and a first drain electrode (30), The aforementioned second transistor (200) is A second electron transport layer (16) is formed by the first nitride semiconductor layer (15A) in the second region (R2), A second electron supply layer (18) is formed by the second nitride semiconductor layer (15B) in the second region (R2), It includes a second gate electrode (24), a second source electrode (28), and a second drain electrode (30) located on a second electron supply layer (18), The temperature sensor (300) is A first sensor electrode (302) and a second sensor electrode (303) are located spaced apart from each other on the second nitride semiconductor layer (15B) in the third region (R3), The system includes a temperature sensing unit (304) located between the first sensor electrode (302) and the second sensor electrode (303), and composed of the nitride semiconductor layer (15) in the third region (R3), The gate connection wiring (310) spans over the temperature sensing unit (304) and electrically connects the first gate electrode (24) and the second gate electrode (24) of the nitride semiconductor device (10).

[0116] [Note 2] The first transistor (100) is, Located on the first electron supply layer (18), a first gate layer (22) containing acceptor-type impurities, The first gate electrode (24) located on the first gate layer (22), A first passivation layer (26) covers the first electron supply layer (18), the first gate layer (22), and the first gate electrode (24), and has a first source opening (26A) and a first drain opening (26B) that are spaced apart from each other with the first gate layer (22) in between, The first source electrode (28) is in contact with the first electron supply layer (18) through the first source opening (26A), The first drain electrode (30) is in contact with the first electron supply layer (18) through the first drain opening (26B), The aforementioned second transistor (200) is Located on the second electron supply layer (18), a second gate layer (22) containing acceptor-type impurities, The second gate electrode (24) located on the second gate layer (22), A second passivation layer (26) covers the second electron supply layer (18), the second gate layer (22), and the second gate electrode (24), and has a second source opening (26A) and a second drain opening (26B) that are spaced apart from each other with the second gate layer (22) in between, The second source electrode (28) is in contact with the second electron supply layer (18) through the second source opening (26A), The nitride semiconductor device (10) according to Appendix 1, further comprising the second drain electrode (30) in contact with the second electron supply layer (18) through the second drain opening (26B).

[0117] [Note 3] The first transistor (100) is, A first interlayer insulating film (40) covers the first passivation layer (26), the first source electrode (28), the first drain electrode (30), and the first gate electrode (24), A first source wiring (41) is located on the first interlayer insulating film (40) and is electrically connected to the first source electrode (28) via a source via (40A) that penetrates the first interlayer insulating film, A first drain wiring (42) is located on the first interlayer insulating film (40) and is electrically connected to the first drain electrode (30) via a drain via (40B) that penetrates the first interlayer insulating film (40), The first gate wiring (43) is located on the first interlayer insulating film (40) and is electrically connected to the first gate electrode (24) via a gate via (40C) that penetrates the first interlayer insulating film (40), The aforementioned second transistor (200) is A second interlayer insulating film (40) covers the second passivation layer (26), the second source electrode (28), the second drain electrode (30), and the second gate electrode (24), A second source wiring (41) is located on the second interlayer insulating film (40) and is electrically connected to the second source electrode (28) via a source via (40A) that penetrates the second interlayer insulating film (40), A second drain wiring (42) is located on the second interlayer insulating film (40) and is electrically connected to the second drain electrode (30) via a drain via (40B) that penetrates the second interlayer insulating film (40), A nitride semiconductor device (10) according to Appendix 2, comprising: a second gate wiring (43) located on the second interlayer insulating film (40) and electrically connected to the second gate electrode (24) via a gate via (40C) penetrating the second interlayer insulating film (40).

[0118] [Note 4] The gate connection wiring (310) is It includes a first portion located on the first interlayer insulating film (40) and a second portion located on the second interlayer insulating film (40), It is electrically connected to the first gate electrode (24) via a first connecting via (40D1) that penetrates the first interlayer insulating film (40), A nitride semiconductor device (10) as described in Appendix 3, electrically connected to the second gate electrode (24) via a second connecting via (40D2) penetrating the second interlayer insulating film (40).

[0119] [Note 5] The temperature sensor (300) is A third passivation layer (301) covers the second nitride semiconductor layer (15B) and has a first sensor opening (301A) and a second sensor opening (301B) that are spaced apart from each other, The first sensor electrode (302) is in contact with the second nitride semiconductor layer (15B) through the first sensor aperture (301A), The second sensor electrode (303) is in contact with the second nitride semiconductor layer (15B) through the second sensor aperture (301B), A third interlayer insulating film (305) covering the third passivation layer (301), the first sensor electrode (302), and the second sensor electrode (303), A first sensor wiring (306) is located on the third interlayer insulating film (305) and is electrically connected to the first sensor electrode (302) via a first sensor via (304A) that penetrates the third interlayer insulating film (305), A nitride semiconductor device (10) according to any one of appendices 1 to 4, comprising: a second sensor wiring (307) located on the third interlayer insulating film (305) and electrically connected to the second sensor electrode (303) via a second sensor via (304B) penetrating the third interlayer insulating film (305).

[0120] [Note 6] The nitride semiconductor device (10) described in Appendix 5, wherein one or more gate connection lines (310) are located on the third interlayer insulating film (305).

[0121] [Note 7] The first sensor wiring (306), the second sensor wiring (307), and the gate connection wiring (310) are nitride semiconductor device (10) as described in Appendix 5 or Appendix 6, wherein the material and film thickness are the same.

[0122] [Note 8] The temperature sensor (300) is A third passivation layer (301) covers the second nitride semiconductor layer (15B) and has a first sensor opening (301A) and a second sensor opening (301B) that are spaced apart from each other, The first sensor electrode (302) is in contact with the second nitride semiconductor layer (15B) through the first sensor aperture (301A), The second sensor electrode (303) is in contact with the second nitride semiconductor layer (15B) through the second sensor aperture (301B), A third interlayer insulating film (305) covering the third passivation layer (301), the first sensor electrode (302), and the second sensor electrode (303), A first sensor wiring (306) is located on the third interlayer insulating film (305) and is electrically connected to the first sensor electrode (302) via a first sensor via (304A) that penetrates the third interlayer insulating film (305), The system includes a second sensor wiring (307) located on the third interlayer insulating film (305) and electrically connected to the second sensor electrode (303) via a second sensor via (304B) that penetrates the third interlayer insulating film (305), The first passivation layer (26), the second passivation layer (26), and the third passivation layer (301) are made of the same material and have the same film thickness. The first source electrode (28), the first drain electrode (30), the second source electrode (28), the second drain electrode (30), the first sensor electrode (302), and the second sensor electrode (303) are made of the same material and have the same film thickness. The first interlayer insulating film (40), the second interlayer insulating film (40), and the third interlayer insulating film (305) have the same material and film thickness. The nitride semiconductor device (10) described in Appendix 3, wherein the first source wiring (41), the first drain wiring (42), the first gate wiring (43), the second source wiring (41), the second drain wiring (42), the second gate wiring (43), the first sensor wiring (306), and the second sensor wiring (307) are of the same material and film thickness.

[0123] [Note 9] A nitride semiconductor device (10) according to any one of the appendices 1 to 8, including an element isolation region (R4) located between the first region (R1) and the third region (R3), and between the second region (R2) and the third region (R3).

[0124] [Note 10] The nitride semiconductor device (10) as described in Appendix 9, wherein the element isolation region (R4) is a region on the first nitride semiconductor layer (15A) in which the second nitride semiconductor layer (15B) is partially absent.

[0125] [Note 11] The nitride semiconductor device (10) as described in Appendix 9, wherein the element isolation region (R4) is a region in the second nitride semiconductor layer (15B) that contains inert atoms. [Explanation of Symbols]

[0126] L1~L6...Length R1…first area R2…Second area R3...Third area R4…Element isolation area 10. Nitride semiconductor equipment 12… Semiconductor substrates 14…Buffer layer 15… Nitride semiconductor layer 15A...First nitride semiconductor layer 15B...Second nitride semiconductor layer 15C…Third nitride semiconductor layer 16…Electron transport layer, first electron transport layer, second electron transport layer 18...electron supply layer, first electron supply layer, second electron supply layer 22... Gate layer, 1st gate layer, 2nd gate layer 24...Gate electrode, 1st gate electrode, 2nd gate electrode 24A...Main unit 24B…1st connection part 24C…Second connection part 26… Passivation layer, 1st passivation layer, 2nd passivation layer 26A... Source opening, first source opening, second source opening 26B...Drain opening, first drain opening, second drain opening 28…Source electrode, first source electrode, second source electrode 28A…Source contact section 28B...Extension part 28BE…End 30... Drain electrode, first drain electrode, second drain electrode 30A...Drain contact section 40... Interlayer insulating film, first interlayer insulating film, second interlayer insulating film 40A... Source Beer 40B...Drain via 40C...Gate via 40D1…First connection via 40D2…Second connection via 41…Source wiring, first source wiring, second source wiring 42... Drain wiring, first drain wiring, second drain wiring 43... Gate wiring, 1st gate wiring, 2nd gate wiring 100...First transistor 200...2nd transistor 300... Temperature sensor 301...Third Passivation Layer 301A...First sensor aperture 301B...Second sensor aperture 302...First sensor electrode 303...Second sensor electrode 304...Temperature detection unit 304A... First Sensavior 304B... Second Sensavia 305...Third interlayer insulating film 306...First sensor wiring 307...Second sensor wiring 310...Gate connection wiring 401...first metal layer 403... Passivation layer 404…Aperture 405…Second metal layer 406...Interlayer insulating film 406A…Source via hole 406B...Drain via hole 406C…First sensor via hole 406D…Second sensor via hole 407…Third metal layer

Claims

1. Nitride semiconductor layer, The first region where the first transistor is located, The second region where the second transistor is located, A third region located between the first region and the second region, in which a temperature sensor and gate connection wiring are located, is included. The nitride semiconductor layer is The material includes a first nitride semiconductor layer and a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer. The first transistor is, A first electron transport layer composed of the first nitride semiconductor layer in the first region, A first electron supply layer composed of the second nitride semiconductor layer in the first region, The first electron supply layer includes a first gate electrode, a first source electrode, and a first drain electrode, The aforementioned second transistor is A second electron transport layer composed of the first nitride semiconductor layer in the second region, A second electron supply layer composed of the second nitride semiconductor layer in the second region, The second electron supply layer includes a second gate electrode, a second source electrode, and a second drain electrode, The aforementioned temperature sensor is A first sensor electrode and a second sensor electrode are located spaced apart from each other on the second nitride semiconductor layer in the third region, It includes a temperature sensing unit located between the first sensor electrode and the second sensor electrode and composed of the nitride semiconductor layer in the third region, The gate connection wiring spans over the temperature sensing unit and electrically connects the first gate electrode and the second gate electrode, in a nitride semiconductor device.

2. The first transistor is, A first gate layer located on the first electron supply layer and containing acceptor-type impurities, The first gate electrode located on the first gate layer, A first passivation layer covering the first electron supply layer, the first gate layer, and the first gate electrode, and having a first source opening and a first drain opening arranged apart from each other with the first gate layer in between, The first source electrode, which is in contact with the first electron supply layer through the first source opening, The first drain electrode is in contact with the first electron supply layer through the first drain opening, The aforementioned second transistor is A second gate layer located on the second electron supply layer and containing acceptor-type impurities, The second gate electrode located on the second gate layer, A second passivation layer covering the second electron supply layer, the second gate layer, and the second gate electrode, and having a second source opening and a second drain opening arranged apart from each other with the second gate layer in between, The second source electrode, which is in contact with the second electron supply layer through the second source opening, The nitride semiconductor device according to claim 1, further comprising: a second drain electrode in contact with the second electron supply layer through the second drain opening.

3. The first transistor is, The first passivation layer, the first source electrode, the first drain electrode, and the first interlayer insulating film covering the first gate electrode, A first source wiring located on the first interlayer insulating film and electrically connected to the first source electrode via a source via penetrating the first interlayer insulating film, A first drain wiring is located on the first interlayer insulating film and is electrically connected to the first drain electrode via a drain via that penetrates the first interlayer insulating film, Includes a first gate wiring located on the first interlayer insulating film and electrically connected to the first gate electrode via a gate via penetrating the first interlayer insulating film, The aforementioned second transistor is The second passivation layer, the second source electrode, the second drain electrode, and the second gate electrode are covered by a second interlayer insulating film, A second source wiring is located on the second interlayer insulating film and is electrically connected to the second source electrode via a source via that penetrates the second interlayer insulating film, A second drain wiring is located on the second interlayer insulating film and is electrically connected to the second drain electrode via a drain via that penetrates the second interlayer insulating film, The nitride semiconductor device according to claim 2, further comprising: a second gate wiring located on the second interlayer insulating film and electrically connected to the second gate electrode via a gate via penetrating the second interlayer insulating film.

4. The gate connection wiring is, Including a first portion located on the first interlayer insulating film and a second portion located on the second interlayer insulating film, It is electrically connected to the first gate electrode via a first connecting via that penetrates the first interlayer insulating film, The nitride semiconductor device according to claim 3, wherein the second gate electrode is electrically connected via a second connecting via that penetrates the second interlayer insulating film.

5. The aforementioned temperature sensor is A third passivation layer covering the second nitride semiconductor layer and having a first sensor opening and a second sensor opening arranged separately from each other, The first sensor electrode, which is in contact with the second nitride semiconductor layer through the first sensor aperture, The second sensor electrode, which is in contact with the second nitride semiconductor layer through the second sensor aperture, The third passivation layer, the first sensor electrode, and the third interlayer insulating film covering the second sensor electrode, A first sensor wiring is located on the third interlayer insulating film and is electrically connected to the first sensor electrode via a first sensor via that penetrates the third interlayer insulating film, The nitride semiconductor device according to claim 1, further comprising: a second sensor wiring located on the third interlayer insulating film and electrically connected to the second sensor electrode via a second sensor via penetrating the third interlayer insulating film.

6. The nitride semiconductor device according to claim 5, wherein the first sensor wiring, the second sensor wiring, and the gate connection wiring are made of the same material and have the same film thickness.

7. The aforementioned temperature sensor is A third passivation layer covering the second nitride semiconductor layer and having a first sensor opening and a second sensor opening arranged separately from each other, The first sensor electrode, which is in contact with the second nitride semiconductor layer through the first sensor aperture, The second sensor electrode, which is in contact with the second nitride semiconductor layer through the second sensor aperture, The third passivation layer, the first sensor electrode, and the third interlayer insulating film covering the second sensor electrode, A first sensor wiring is located on the third interlayer insulating film and is electrically connected to the first sensor electrode via a first sensor via that penetrates the third interlayer insulating film, The system includes a second sensor wiring located on the third interlayer insulating film and electrically connected to the second sensor electrode via a second sensor via that penetrates the third interlayer insulating film, The first passivation layer, the second passivation layer, and the third passivation layer have the same material and film thickness. The first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the first sensor electrode, and the second sensor electrode are made of the same material and have the same film thickness. The first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film have the same material and film thickness. The nitride semiconductor device according to claim 3, wherein the first source wiring, the first drain wiring, the first gate wiring, the second source wiring, the second drain wiring, the second gate wiring, the first sensor wiring, and the second sensor wiring are made of the same material and have the same film thickness.

8. The nitride semiconductor device according to claim 1, including an element isolation region located between the first region and the third region, and between the second region and the third region.

9. The nitride semiconductor device according to claim 8, wherein the element isolation region is a region on the first nitride semiconductor layer in which the second nitride semiconductor layer is partially absent.

10. The nitride semiconductor device according to claim 8, wherein the element isolation region is a region in the second nitride semiconductor layer that contains inert atoms.

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