High-frequency switch circuits, high-frequency modules, and communication devices

Abstract

The present invention provides a high-frequency switch circuit that can reduce the generation of reflected waves from high-frequency signals entering from external terminals when the charge pump is stopped. [Solution] The high-frequency switch circuit 1 includes a common terminal 2, a first input / output terminal 3, a first series FET 5, a first parallel FET 6, a charge pump 11, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 and ground. The voltage supply path 12 is connected to a connection node N1 to which the output section 11b of the charge pump 11 and the control electrode of the first series FET 5 are connected. The first switch SW1 is provided in the first path M1 connecting the first output section 11b of the charge pump 11 and the connection node N1. The second switch SW2 is provided in the voltage supply path 12.

Description

Technical Field

[0001] The present invention generally relates to a high-frequency switch circuit, a high-frequency module, and a communication device. More specifically, the present invention relates to a high-frequency switch circuit including a common terminal and input / output terminals, a high-frequency module including the high-frequency switch circuit, and a communication device including the high-frequency module.

Background Art

[0002] The positive / negative potential generation circuit described in Patent Document 1 includes a plurality of FETs and a power supply circuit that supplies a voltage to the plurality of FETs. The power supply circuit includes a charge pump. When turning on a predetermined FET among the plurality of FETs, the charge pump applies a positive voltage to the predetermined FET, and when turning off the predetermined FET, the charge pump applies a negative voltage to the predetermined FET.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the positive / negative potential generation circuit described in Patent Document 1, in the stopped state of the charge pump, since a voltage around 0V is applied to each FET, the conduction resistance of each FET does not become sufficiently small. Therefore, in the stopped state of the charge pump, when a high-frequency signal from an external terminal enters and passes through each FET, a reflected wave is generated due to the conduction resistance of each FET, and the generated reflected wave returns to the external terminal, which may deteriorate the reception sensitivity of the external terminal due to the reflected wave.

[0005] In view of the above problems, the present invention aims to provide a high-frequency switch circuit, a high-frequency module, and a communication device that can reduce the generation of reflected waves by high-frequency signals coming from an external terminal when the charge pump is stopped. [Means for solving the problem]

[0006] A high-frequency switch circuit according to one aspect of the present invention comprises a common terminal, a first input / output terminal, a first series FET, a first parallel FET, a charge pump, a voltage source, a voltage supply path, a first switch, and a second switch. The first input / output terminal is connected to the common terminal via a first signal path. The first series FET is connected to the common terminal and the first input / output terminal in the first signal path. The first parallel FET is connected between the signal path between the first input / output terminal and the first series FET and ground. The charge pump has an output section, from which it supplies a control voltage for controlling the first series FET and a control voltage for controlling the first parallel FET. The voltage source has a first output section and a second output section, each supplying voltage. The voltage source supplies the voltage to the charge pump from the second output section. The voltage supply path connects the first output section of the voltage source to a connection node to which the control electrode of the first series FET is connected. The first switch is provided in a first path connecting the output section of the charge pump and the connection node, and controls the conduction and interruption of the first path. The second switch is provided in the voltage supply path, and controls the conduction and interruption of the voltage supply path.

[0007] A high-frequency module according to one aspect of the present invention comprises the high-frequency switch circuit and an electronic component. The electronic component is connected between the first input / output terminal and the external terminal of the high-frequency switch circuit.

[0008] A communication device according to one aspect of the present invention comprises the high-frequency module and a signal processing circuit. The signal processing circuit is connected to the high-frequency module and processes high-frequency signals. [Effects of the Invention]

[0009] The high-frequency switch circuit, high-frequency module, and communication device according to the present invention have the advantage of reducing the generation of reflected waves by high-frequency signals coming from an external terminal when the charge pump is stopped. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a diagram showing the configuration of a high-frequency module and communication device according to Embodiment 1. [Figure 2] Figure 2 is a diagram showing the configuration of the high-frequency switch circuit provided by the high-frequency module mentioned above. [Figure 3] Figure 3 is a configuration diagram of a high-frequency switch circuit according to Embodiment 2. [Figure 4] Figure 4 is a diagram showing the configuration of a high-frequency switch circuit according to Embodiment 3. [Modes for carrying out the invention]

[0011] (1) Embodiment 1 The high-frequency switch circuit 1 according to Embodiment 1 will be described in detail with reference to the drawings.

[0012] (1-1) Overview As shown in Figure 2, the high-frequency switch circuit 1 according to Embodiment 1 includes a common terminal 2, a first input / output terminal 3, a first series FET (Field Effect Transistor) 5, a first parallel FET 6, a charge pump 11, a voltage source 10, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground. The charge pump 11 has a first output section 11b (output unit). From the first output section 11b, the charge pump 11 supplies a control voltage for controlling the first series FET 5 and a control voltage for controlling the first parallel FET 6. The voltage source 10 has a first output section 10a and a second output section 10b, which supply voltages, respectively. The voltage source 10 supplies the above voltage to the charge pump 11 from the second output section 10b. The voltage supply path 12 connects the first output section 10a of the voltage source 10 to the connection node N1 to which the control electrode of the first series FET 5 is connected. The first switch SW1 is provided in the first path M1 connecting the first output section 11b of the charge pump 11 to the connection node N1, and controls the conduction and disconnection of the first path M1. The second switch SW2 is provided in the voltage supply path 12, and controls the conduction and disconnection of the voltage supply path 12.

[0013] With this configuration, when the charge pump 11 is stopped, the first switch SW1 blocks the first path M1 and the second switch SW2 opens the voltage supply path 12, thereby applying the voltage (power supply voltage) applied to the voltage supply path 12 to the control electrode of the first series FET 5, and switching the first series FET 5 to an ON state with sufficiently low conduction resistance. Therefore, when the charge pump 11 is stopped and a high-frequency signal entering the common terminal 2 from an external terminal passes through the first series FET 5, the generation of reflected waves of the high-frequency signal due to the conduction resistance of the first series FET 5 can be reduced. As a result, the deterioration of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be reduced.

[0014] (1-2) Communication equipment Referring to Figure 1, an example configuration of a communication device 30 comprising a high-frequency module 31 including a high-frequency switch circuit 1 will be described.

[0015] As shown in Figure 1, the communication device 30 is a communication device equipped with a high-frequency module 31. The communication device 30 is, for example, a mobile terminal (e.g., a smartphone), but is not limited to a mobile terminal; it may also be, for example, a wearable device (e.g., a smartwatch). The high-frequency module 31 is, for example, a module compatible with 4G (fourth-generation mobile communication) standards and 5G (fifth-generation mobile communication) standards. The 4G standard is, for example, 3GPP (registered trademark, Third Generation Partnership Project) or the LTE standard. The 5G standard is, for example, 5G NR (New Radio).

[0016] In addition to the high-frequency module 31, the communication device 30 further includes a signal processing circuit 32 and an antenna 33.

[0017] The high-frequency module 31 is configured to amplify the received signal (high-frequency signal) received by the antenna 33 and output it to the signal processing circuit 32. The high-frequency module 31 is also configured to amplify the transmitted signal (high-frequency signal) output from the signal processing circuit 32 and transmit it from the antenna 33. The high-frequency module 31 is controlled, for example, by the signal processing circuit 32.

[0018] The signal processing circuit 32 is connected to the high-frequency module 31 and is configured to process the received signal output from the high-frequency module 31. The signal processing circuit 32 is also configured to process the transmitted signal output to the high-frequency module 31. The signal processing circuit 32 includes an RF (Radio Frequency) signal processing circuit 35 and a baseband signal processing circuit 34.

[0019] The RF signal processing circuit 35 is, for example, an RFIC (Radio Frequency Integrated Circuit), and performs signal processing on high-frequency signals (transmission signals and reception signals). The RF signal processing circuit 35 performs signal processing such as down-converting the reception signal output from the high-frequency module 31 and outputs it to the baseband signal processing circuit 34. Also, the RF signal processing circuit 35 performs signal processing such as up-converting the transmission signal output from the baseband signal processing circuit 34 and outputs it to the high-frequency module 31.

[0020] The baseband signal processing circuit 34 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 34 outputs the reception signal output from the RF signal processing circuit 35 to the outside. This output signal (reception signal) can be used, for example, as an image signal for image display or as an audio signal for a call. Also, the baseband signal processing circuit 34 generates a transmission signal from the baseband signal (for example, an audio signal and an image signal) input from the outside, and outputs the generated transmission signal to the RF signal processing circuit 35.

[0021] (1-3) Configuration example of high-frequency module As shown in FIG. 1, the high-frequency module 31 includes a high-frequency switch circuit 1, one or more (two in the example of FIG. 1) reception components 50 (electronic components), one or more (two in the example of FIG. 1) transmission components 51 (electronic components), and a plurality of external terminals 40a to 40c.

[0022] The reception component 50 is an electronic component used to process the reception signal. In the example of FIG. 1, the one or more reception components 50 are a reception filter 36 and a low-noise amplifier 38. The one or more reception components 50 are connected between the first input / output terminal 3 and the external terminal 40b.

[0023] The transmitting components 51 are electronic components used to process the transmitted signal. In the example shown in Figure 1, one or more transmitting components 51 are a transmitting filter 37 and a power amplifier 39. One or more transmitting components 51 are connected between the second input / output terminal 4 and the external terminal 40c.

[0024] External terminal 40a is an antenna terminal to which antenna 33 is connected. External terminal 40b is connected to the input section (not shown) of signal processing circuit 32 and is an output terminal that outputs the received signal processed by the high-frequency module 31 to the input section of signal processing circuit 32. External terminal 40c is connected to the output section (not shown) of signal processing circuit 32 and is an input terminal that inputs the transmitted signal processed by signal processing circuit 32 to high-frequency module 31.

[0025] The high-frequency switch circuit 1 is, for example, an antenna switch. The high-frequency switch circuit 1 has a common terminal 2 and a plurality of (two in the example in Figure 2) input / output terminals (first input / output terminal 3 and second input / output terminal 4). The input / output terminals are also called select terminals. The common terminal 2 can be selectively connected to one of the first input / output terminal 3 and the second input / output terminal 4. The common terminal 2 is connected to an external terminal 40a (antenna terminal). The first input / output terminal 3 is connected to an external terminal 40b via one or more receiving components 50. The second input / output terminal 4 is connected to an external terminal 40c via one or more transmitting components 51.

[0026] The receiving filter 36 has an input section 36a and an output section 36b. The input section 36a is connected to the first input / output terminal 3 of the high-frequency switch circuit 1. The output section 36b is connected to the input section 38a of the low-noise amplifier 38. The receiving filter 36 receives the signal (received signal) from the input section 36a, restricts the input signal to signals within the receiving band of the first communication band and passes it through, and outputs the passed signal from the output section 36b.

[0027] The transmit filter 37 has an input section 37a and an output section 37b. The input section 37a is connected to the output section 39b of the power amplifier 39. The output section 37b is connected to the second input / output terminal 4 of the high-frequency switch circuit 1. The transmit filter 37 receives the signal (transmit signal) from the input section 37a, restricts the input signal to signals within the transmission bandwidth of the second communication band and passes it through, and outputs the passed signal from the output section 37b. The second communication band may be the same communication band as the first communication band, or it may be a different communication band from the first communication band.

[0028] The low-noise amplifier 38 has an input section 38a and an output section 38b. The input section 38a is connected to the output section 36b of the receiving filter 36. The output section 38b is connected to the external terminal 40b. The low-noise amplifier 38 amplifies the signal (received signal) input to the input section 38a and outputs the amplified signal from the output section 38b.

[0029] The power amplifier 39 has an input section 39a and an output section 39b. The input section 39a is connected to an external terminal 40c. The output section 39b is connected to the input section 37a of the transmission filter 37. The power amplifier 39 amplifies the signal (transmission signal) input to the input section 39a and outputs the amplified signal from the output section 39b.

[0030] (1-4) Configuration of a high-frequency switch circuit Referring to Figure 2, the configuration of the high-frequency switch circuit 1 will be described in detail. As shown in Figure 2, in addition to the common terminal 2, first input / output terminal 3, and second input / output terminal 4 described above, the high-frequency switch circuit 1 further includes a first series FET 5, a first parallel FET 6, a second series FET 7, a second parallel FET 8, a third parallel FET 9 (parallel FET), a voltage source 10, a charge pump 11, a voltage supply path 12, first to fifth level shifters 13 to 17, resistors R1 to R5, a first switch SW1, and a second switch SW2. Note that the voltage source 10 does not necessarily have to be included in the configuration of the high-frequency switch circuit 1.

[0031] As described above, common terminal 2 is connected to external terminal 40a (see Figure 1).

[0032] As described above, the first input / output terminal 3 is connected to the external terminal 40b (see Figure 1) via one or more receiving components 50 (see Figure 1). Furthermore, the first input / output terminal 3 is connected to the common terminal 2 via the first signal path L1.

[0033] As described above, the second input / output terminal 4 is connected to the external terminal 40c (see Figure 1) via one or more transmitting components 51 (see reference). The second input / output terminal 4 is also connected to the common terminal 2 via the second signal path L2.

[0034] The first series FET 5 is, for example, an N-channel enhancement type MOSFET. The first series FET 5 is connected in series with the first signal path L1. That is, the first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first series FET 5 conducts and blocks the first signal path L1 by switching the first series FET 5 on and off. The first series FET 5 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first signal path L1 has signal paths L11 and L12. The first main electrode of the first series FET 5 is connected to the common terminal 2 via signal path L11. The second main electrode of the first series FET 5 is connected to the first input / output terminal 3 via signal path L12. The control electrode of the first series FET 5 is indirectly connected to the connection node N1 via a resistor R1 and a first level shifter 13.

[0035] The first parallel FET 6 is, for example, an N-channel enhancement type MOSFET. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground, and the on and off switching of the first parallel FET 6 conducts and blocks conduction between the signal path L12 and ground. The first parallel FET 6 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the first parallel FET 6 is connected to a connection node N2 provided in the signal path L12. The second main electrode of the first parallel FET 6 is connected to ground. The control electrode of the first parallel FET 6 is indirectly connected to a connection node N1 via a resistor R2 and a second level shifter 14.

[0036] The second series FET 7 is, for example, an N-channel enhancement type MOSFET. The second series FET 7 is connected in series with the second signal path L2. That is, the second series FET 7 is connected to the common terminal 2 and the second input / output terminal 4 in the second signal path L2. The second series FET 7 conducts and blocks the second signal path L2 by switching it on and off. The second series FET 7 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The second signal path L2 has signal paths L21 and L12. The first main electrode of the second series FET 7 is connected to the common terminal 2 via signal path L21. The second main electrode of the second series FET 7 is connected to the second input / output terminal 4 via signal path L22. The control electrode of the second series FET 7 is indirectly connected to the connection node N1 via resistor R3 and first level shifter 15.

[0037] The second parallel FET 8 is, for example, an N-channel enhancement type MOSFET. The second parallel FET 8 is connected between the signal path L22 between the second input / output terminal 4 and the second series FET 7 and ground, and the on and off switching of the second parallel FET 8 conducts and blocks conduction between the signal path L22 and ground. The second parallel FET 8 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the second parallel FET 8 is connected to a connection node N3 provided in the signal path L22. The second main electrode of the second parallel FET 8 is connected to ground. The control electrode of the second parallel FET 8 is indirectly connected to a connection node N1 via a resistor R4 and a fourth level shifter 16.

[0038] The third parallel FET 9 is, for example, an N-channel enhancement type MOSFET. The third parallel FET 9 is connected to the common terminal 2, and switching the third parallel FET 9 on and off connects and disconnects the common terminal 2 to ground. The third parallel FET 9 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the third parallel FET 9 is connected to a connection node N5 provided in the signal path L3. In the example in Figure 1, the signal path L3 between the common terminal 2 and the connection node N4 in signal path L11 and the signal path L3 between the common terminal 2 and the connection node N4 in signal path L21 constitute a common signal path. The second main electrode of the third parallel FET 9 is connected to ground. The control electrode of the third parallel FET 9 is indirectly connected to the connection node N1 via a resistor R5 and a fifth level shifter 17.

[0039] In the following explanation, when the first series FET 5, the first parallel FET 6, the second series FET 7, the second parallel FET 8, and the third parallel FET 9 are not distinguished, they may simply be referred to as FET5-9.

[0040] The voltage source 10 outputs a power supply voltage that is a constant voltage. The voltage source 10 outputs a power supply voltage based on the power supply voltage from a power supply circuit (not shown). The voltage source 10 has a first output section 10a and a second output section 10b. The first output section 10a is connected to one end of the voltage supply path 12. The second output section 10b is connected to the input section 11a of the charge pump 11. The voltage source 10 applies the power supply voltage output from the first output section 10a to the voltage supply path 12. The voltage source 10 also inputs the power supply voltage output from the second output section 10b to the input section 11a of the charge pump 11.

[0041] The charge pump 11 supplies positive and negative voltages as control electrodes to control each of the FETs 5 to 9 based on the power supply voltage input from the voltage source 10. In the example in Figure 2, the charge pump 11 supplies the control voltages to the first inputs 13a to 17a of the first to fifth level shifters 13 to 17. Here, the positive voltage is the control voltage for switching FETs 5 to 9 on, and the negative voltage is the control voltage for switching FETs 5 to 9 off.

[0042] More specifically, the charge pump 11 includes an input section 11a, a first output section 11b, and a second output section 11c.

[0043] The input section 11a is connected to the second output section 10b of the voltage source 10, and the power supply voltage from the voltage source 10 is input to it.

[0044] The first output section 11b is connected to the connection node N1 via the first path M1. The first path M1 is provided with the first switch SW1, which will be described later. The connection node N1 is connected to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17, respectively. Therefore, the first output section 11b is connected to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17, respectively, via the first switch SW1. Furthermore, the first to fifth level shifters 13 to 17 correspond one-to-one with FETs 5 to 9. Specifically, the first level shifter 13 corresponds to the first series FET 5, the second level shifter 14 corresponds to the first parallel FET 6, the third level shifter 15 corresponds to the second series FET 7, the fourth level shifter 16 corresponds to the second parallel FET 8, and the fifth level shifter 17 corresponds to the parallel FET 9. The output sections 13c to 17c of the first to fifth level shifters 13 to 17 are connected to the control electrodes of the corresponding FETs 5 to 9. Therefore, the first output section 11b is indirectly connected to the control electrodes of the corresponding FETs 5 to 9 via the first switch SW1 and the corresponding level shifter among the first to fifth level shifters 13 to 17. The second output section 11c is connected to the second input sections 13b to 17b of the first to fifth level shifters 13 to 17. The charge pump 11 boosts the power supply voltage input to the input section 11a to generate a positive voltage and outputs the generated positive voltage from the first output section 11b. The charge pump 11 can also generate a negative voltage by, for example, multiplying the generated positive voltage by a negative factor and outputting the generated negative voltage from the second output section 11c.

[0045] The voltage supply path 12 connects the first output section 10a of the voltage source 10 to the connection node N1. The power supply voltage output from the first output section 10a of the voltage source 10 is applied to the voltage supply path 12. The voltage supply path 12 is provided with a second switch SW2, which will be described later. As mentioned above, the connection node N1 is connected to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. Therefore, the voltage supply path 12 supplies the power supply voltage to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17 via the second switch SW2.

[0046] The first switch SW1 is located on the first path M1 and controls the conduction and disconnection of the first path M1. The first switch SW1 can be selectively switched on or off in response to a control signal from a control unit (not shown). When the first switch SW1 is switched on, it causes the first path M1 to conduct, and when it is switched off, it disconnects the first path M1. The conduction and disconnection of the first path M1 by the first switch SW1 selectively switches the supply and cessation of positive voltage from the first output section 11b of the charge pump 11 to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17.

[0047] The second switch SW2 is located in the voltage supply path 12 and controls the conduction and disconnection of the voltage supply path 12. The second switch SW2 can be selectively switched on or off in response to a control signal from a control unit (not shown). When the second switch SW2 is switched on, it causes the voltage supply path 12 to conduct, and when it is switched off, it disconnects the voltage supply path 12. The conduction and disconnection of the voltage supply path 12 by the second switch SW2 controls the supply and stop of positive voltage from the first output section 10a of the voltage source 10 to the first input sections 13a to 17a of the first level shifters 13 to 17.

[0048] The high-frequency switch circuit 1 has multiple operating modes, including a transmit / receive mode and a low-power mode. The transmit / receive mode is the mode in which the communication device 30 equipped with the high-frequency switch circuit 1 transmits and receives data. The low-power mode is the mode in which the communication device 30 does not transmit or receive data and is in a standby state. In the low-power mode, the charge pump is stopped. In the transmit / receive mode, the output voltage of the first output section 11b of the charge pump 11 is applied to the connected node N1 by switching the first switch SW1 to ON and the second switch SW2 to OFF. In the low-power mode, the power supply voltage applied to the voltage supply path 12 is applied to the connected node N1 by switching the first switch SW1 to OFF and the second switch SW2 to ON.

[0049] The first level shifter 13 has a first input section 13a, a second input section 13b, an output section 13c (first output section), and a control signal input section 13d. The first input section 13a is connected to a connection node N1, and the voltage (positive voltage or power supply voltage) applied to the connection node N1 is input to it. The second input section 13b is connected to the second output section 11c of the charge pump 11, and the output voltage (negative voltage) of the second output section 11c is input to it. The control signal input section 13d is selectively input to either a high-level signal or a low-level signal as a control signal from a control unit (not shown). The output section 13c is connected to the control electrode of the first series FET 5 via a resistor R1. The first level shifter 13 selectively outputs either the voltage (positive voltage or power supply voltage) input to the first input section 13a or the voltage (negative voltage) input to the second input section 13b from the output section 13c in response to the control signal input to the control signal input section 13d. For example, when a high-level signal is input to the control signal input 13d, the first level shifter 13 outputs the voltage input to the first input 13a from the output 13c, and when a low-level signal is input to the control signal input 13d, it outputs the voltage input to the second input 13b from the output 13c. The output voltage of the output 13c is applied to the control electrode of the first series FET 5, switching the first series FET 5 on and off.

[0050] The second level shifter 14 has a first input section 14a (third input section), a second input section 14b (fourth input section), an output section 14c (second output section), and a control signal input section 14d. The first input section 14a (third input section) is connected to connection node N1, and the voltage (positive voltage or power supply voltage) applied to connection node N1 is input to it. The second input section 14b (fourth input section) is connected to the second output section 11c of the charge pump 11, and the output voltage (negative voltage) of the second output section 11c is input to it. The control signal input section 14d selectively receives either a high-level signal or a low-level signal as a control signal from a control unit (not shown). The output section 14c is connected to the control electrode of the first parallel FET 6 via a resistor R2. The second level shifter 14 selectively outputs from its output unit 14c either the voltage input to the first input unit 14a (positive voltage or power supply voltage) or the voltage input to the second input unit 14b (negative voltage) in response to a control signal input to the control signal input unit 14d. For example, if a high-level signal is input to the control signal input unit 14d, the second level shifter 14 outputs the voltage input to the first input unit 14a from its output unit 14c, and if a low-level signal is input to the control signal input unit 14d, it outputs the voltage input to the second input unit 14b from its output unit 14c. The output voltage of the output unit 14c is applied to the control electrode of the first parallel FET 6, switching the first parallel FET 6 on and off.

[0051] The third level shifter 15 has a first input section 15a, a second input section 15b, an output section 15c, and a control signal input section 15d. The first input section 15a is connected to a connection node N1, and the voltage (positive voltage or power supply voltage) applied to the connection node N1 is input to it. The second input section 15b is connected to the second output section 11c of the charge pump 11, and the output voltage (negative voltage) of the second output section 11c is input to it. The control signal input section 15d is selectively input to either a high-level signal or a low-level signal as a control signal from a control unit (not shown). The output section 15c is connected to the control electrode of the second series FET 7 via a resistor R3. The third level shifter 15 selectively outputs either the voltage (positive voltage or power supply voltage) input to the first input section 15a or the voltage (negative voltage) input to the second input section 15b from the output section 15c in response to the control signal input to the control signal input section 15d. For example, when a high-level signal is input to the control signal input 15d, the third level shifter 15 outputs the voltage input to the first input 14a from the output 15c, and when a low-level signal is input to the control signal input 15d, it outputs the voltage input to the second input 14b from the output 15c. The output voltage of the output 15c is applied to the control electrode of the second series FET 7, switching the second series FET 7 on and off.

[0052] The fourth level shifter 16 has a first input section 16a, a second input section 16b, an output section 16c, and a control signal input section 16d. The first input section 16a is connected to a connection node N1, and the voltage (positive voltage or power supply voltage) applied to the connection node N1 is input to it. The second input section 16b is connected to the second output section 11c of the charge pump 11, and the output voltage (negative voltage) of the second output section 11c is input to it. The control signal input section 16d is selectively input to either a high-level signal or a low-level signal as a control signal from a control unit (not shown). The output section 16c is connected to the control electrode of the second parallel FET 8 via a resistor R4. The fourth level shifter 16 selectively outputs either the voltage (positive voltage or power supply voltage) input to the first input section 16a or the voltage (negative voltage) input to the second input section 16b from the output section 16c in response to the control signal input to the control signal input section 16d. For example, when a high-level signal is input to the control signal input 16d, the fourth level shifter 16 outputs the voltage input to the first input 16a from the output 16c, and when a low-level signal is input to the control signal input 16d, it outputs the voltage input to the second input 16b from the output 16c. The output voltage of the output 16c is applied to the control electrode of the second parallel FET 8, switching the second parallel FET 8 on and off.

[0053] The fifth level shifter 17 has a first input section 17a, a second input section 17b, an output section 17c, and a control signal input section 17d. The first input section 17a is connected to the connection node N1 and receives the voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 17b is connected to the second output section 11c of the charge pump 11 and receives the output voltage (negative voltage) of the second output section 11c. The control signal input section 17d selectively receives either a high-level signal or a low-level signal as a control signal from a control unit (not shown). The output section 17c is connected to the control electrode of the third parallel FET 9 via a resistor R5. The fifth level shifter 17 selectively outputs either the voltage (positive voltage or power supply voltage) input to the first input section 17a or the voltage (negative voltage) input to the second input section 17b from the output section 17c in response to the control signal input to the control signal input section 17d. For example, when a high-level signal is input to the control signal input 17d, the fifth level shifter 17 outputs the voltage input to the first input 17a from the output 17c, and when a low-level signal is input to the control signal input 17d, it outputs the voltage input to the second input 17b from the output 17c. The output voltage of the output 17c is applied to the control electrode of the third parallel FET 9, switching the third parallel FET 9 on and off.

[0054] (1-5) Operation of high-frequency switch circuits The operation of the high-frequency switch circuit 1 will be explained with reference to Figure 2.

[0055] (1-5-1) Operation in transmission mode In transmit / receive mode, the charge pump 11 operates to generate positive and negative voltages, outputting the generated positive voltage from the first output unit 11b and the generated negative voltage from the second output unit 11c. Also in transmit / receive mode, the first switch SW1 is switched ON and the second switch SW2 is switched OFF. Therefore, the output voltage (power supply voltage) of the first output unit 10a of the voltage source 10 is not applied to the connection node N1, and the output voltage (positive voltage) of the first output unit 11b of the charge pump 11 is applied to the connection node N1. As a result, the output voltage (positive voltage) of the first output unit 11b of the charge pump 11 is input to the first input units 13a to 17a of the first to fifth level shifters 13 to 17. In addition, the output voltage (negative voltage) of the second output unit 11c of the charge pump 11 is input to the second input units 13b to 17b of the first to fifth level shifters 13 to 17.

[0056] When the common terminal 2 is selectively connected to the first input / output terminal 3, the first series FET 5 is switched on, and the remaining FETs 6 to 9 are switched off. That is, a high-level signal is input to the control signal input section 13d of the first level shifter 13, and low-level signals are input to the control signal input sections 14d to 17d of the second to fifth level shifters 14 to 17. Therefore, the first series FET 5 is switched on, and the remaining FETs 6 to 9 are switched off. As a result, the common terminal 2 is selectively connected to the first input / output terminal 3. That is, the first signal path L1 between the common terminal 2 and the first input / output terminal 3 is conducted, and the second signal path L2 between the common terminal 2 and the second input / output terminal 4 is blocked.

[0057] Furthermore, when the common terminal 2 is selectively connected to the second input / output terminal 4, the second series FET 7 among FETs 5-9 is switched on, and the remaining FETs 5, 6, 8-9 are switched off. That is, a high-level signal is input to the control signal input section 15d of the third level shifter 15, and low-level signals are input to the control signal input sections 13d, 14d, 16d, and 17d of the first, second, fourth-fifth level shifters 13, 14, 16, and 17. Consequently, the second series FET 7 is switched on, and the remaining FETs 5, 6, 8, and 9 are switched off. As a result, the common terminal 2 is selectively connected to the second input / output terminal 4. That is, the second signal path L2 between the common terminal 2 and the second input / output terminal 4 is open, and the first signal path L1 between the common terminal 2 and the first input / output terminal 3 is blocked.

[0058] (1-5-2) Operation in low power consumption mode In low power consumption mode, the charge pump 11 stops and does not generate positive or negative voltages, outputting voltages near 0V from the first output section 11b and the second output section 11c. Also in low power consumption mode, the first switch SW1 is switched to off, and the second switch SW2 is switched to on. Therefore, the output voltage of the first output section 11b of the charge pump 11 (voltage near 0V) is not applied to the connection node N1, and the output voltage of the first output section 10a of the voltage source 10 (power supply voltage) is applied to the connection node N1. As a result, the output voltage of the first output section 10a of the voltage source 10 (power supply voltage) is input to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. In addition, the output voltage of the second output section 11c of the charge pump 11 (voltage near 0V) is input to the second input sections 13b to 17b of the first to fifth level shifters 13 to 17.

[0059] Furthermore, in low-power mode, all FETs 5 to 9 are switched on. That is, high-level signals are input to the control signal input sections 13d to 15d of the 1st to 5th level shifters 13 to 17. Therefore, the output voltage (power supply voltage) of the voltage source 10 applied to the voltage supply path 12 is applied to the control electrodes of FETs 5 to 9, and FETs 5 to 9 are switched on. In this on state, since FETs 5 to 9 are switched on by the power supply voltage, the conduction resistance of FETs 5 to 9 in the on state is sufficiently small. For this reason, in low-power mode, when a high-frequency signal transmitted from a nearby external terminal enters the high-frequency switch circuit 1, the generation of reflected waves of the high-frequency signal inside the high-frequency switch circuit 1 can be reduced. As a result, the amount of reflected waves that return to the external terminal can be reduced.

[0060] (1-5-3) Explanation of the reduction of reflected waves of high-frequency signals in high-frequency switch circuits When an external terminal is located near a communication device 30 equipped with a high-frequency switch circuit 1, a high-frequency signal transmitted from the external terminal may enter the communication device 30 (i.e., the high-frequency switch circuit 1) through the antenna 33 of the communication device 30. Let's consider the case where a high-frequency signal transmitted from an external terminal enters the high-frequency switch circuit 1 when the communication device 30 is in low-power mode. In this case, as described above, in low-power mode, the power supply voltage is applied to the control electrodes of FETs 5 to 9, so the conduction resistance of FETs 5 to 9 in the ON state is sufficiently small. It can be considered that there is virtually no conduction resistance. Therefore, in low-power mode, when the high-frequency signal that entered from the external terminal passes through each of FETs 5 to 9, it hardly generates any distortion (reflected waves) due to the conduction resistance of each of FETs 5 to 9. In other words, reflected waves of the high-frequency signal hardly occur because the conduction resistance of FETs 5 to 9 is sufficiently small.

[0061] Furthermore, since most of the high-frequency signal entering the high-frequency switch circuit 1 flows from the common terminal 2 through the third parallel FET 9 to ground, the intensity of the remaining high-frequency signal is sufficiently small. Therefore, even if the remaining high-frequency signal generates reflected waves, the intensity of the reflected waves is sufficiently small. Also, since the high-frequency signal flowing through the first signal path L1 flows through the first series FET 5 and the first parallel FET 6 to ground, almost no reflected waves are generated from the high-frequency signal. Similarly, since the high-frequency signal flowing through the second signal path L2 flows through the second series FET 7 and the second parallel FET 8 to ground, almost no reflected waves are generated from the high-frequency signal. Therefore, in low-power mode, reflected waves of the high-frequency signal are reduced in the high-frequency switch circuit 1. As a result, it is possible to reduce the degradation of the receiving sensitivity of the external terminal by preventing the reflected waves from returning to the external terminal.

[0062] (1-6) Comparative Examples The comparative high-frequency switch circuit (hereinafter simply referred to as "comparative example") will now be described. The comparative example differs from the high-frequency switch circuit 1 of Embodiment 1 in that the voltage supply path 12, the first switch SW1, and the second switch SW2 are omitted. Therefore, in the comparative example, regardless of whether it is in transmit / receive mode or low power consumption mode, the output voltage of the first output section 11b of the charge pump 11 is input to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. In low power consumption mode, the charge pump 11 is stopped, so no positive or negative voltage is generated, and the output voltages of the first output section 11b and the second output section 11c of the charge pump 11 are voltages near 0V. In the comparative example, in low power consumption mode, all of FETs 5 to 9 are switched on by the output voltage of the first output section 11b of the charge pump 11.

[0063] However, in the comparative example, in low power consumption mode, instead of a positive voltage, a voltage near 0V is applied from the output sections 13c to 17c of the first to fifth level shifters 13 to 17 to the control electrodes of FETs 5 to 9. As a result, FETs 5 to 9 in the comparative example cannot be sufficiently switched on, and a certain degree of large conduction resistance is generated when they are on. In this state, when a high-frequency signal transmitted from an external terminal enters the high-frequency switch circuit of the comparative example, distortion (i.e., reflected waves) is generated due to the certain degree of large conduction resistance as the incoming high-frequency signal flows through each FET 5 to 9, and the generated reflected waves return to the external terminal, degrading the reception sensitivity of the external terminal. In contrast, as described above, the high-frequency switch circuit 1 of Embodiment 1 can reduce the reflected waves, and therefore can reduce the degradation of the reception sensitivity of the external terminal.

[0064] (1-7) Effects The high-frequency switch circuit 1 according to Embodiment 1 includes a common terminal 2, a first input / output terminal 3, a first series FET 5, a first parallel FET 6, a charge pump 11, a voltage source 10, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground. The charge pump 11 has a first output section 11b (output section). From the first output section 11b, the charge pump 11 supplies a control voltage for controlling the first series FET 5 and a control voltage for controlling the first parallel FET 6. The voltage source 10 has a first output section 10a and a second output section 10b, which supply voltages, respectively. The voltage source 10 supplies the above voltage to the charge pump 11 from the second output section 10b. The voltage supply path 12 connects the first output section 10a of the voltage source 10 to the connection node N1 to which the control electrode of the first series FET 5 is connected. The first switch SW1 is provided in the first path M1 connecting the first output section 11b of the charge pump 11 to the connection node N1, and controls the conduction and disconnection of the first path M1. The second switch SW2 is provided in the voltage supply path 12, and controls the conduction and disconnection of the voltage supply path 12.

[0065] With this configuration, when the charge pump 11 is stopped, the first switch SW1 blocks the first path M1 and the second switch SW2 opens the voltage supply path 12, thereby applying the voltage (e.g., power supply voltage) applied to the voltage supply path 12 to the control electrode of the first series FET 5, and switching the first series FET 5 to an ON state with sufficiently low conduction resistance. Therefore, when the charge pump 11 is stopped and a high-frequency signal entering the common terminal 2 from an external terminal passes through the first series FET 5, the generation of reflected waves of the high-frequency signal due to the conduction resistance of the first series FET 5 can be reduced. As a result, the deterioration of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be reduced.

[0066] Furthermore, in the high-frequency switch circuit 1 according to Embodiment 1, the control electrode of the first parallel FET 6 is connected to a path (connection node N1 in the example of Figure 2) that connects the connection node N1 and the control electrode of the first series FET 5.

[0067] With this configuration, when the charge pump 11 is stopped, the first switch SW1 blocks the first path M1 and the second switch SW2 opens the voltage supply path 12. This allows the voltage applied to the voltage supply path 12 (e.g., power supply voltage) to be further applied to the control electrode of the first parallel FET 6, thereby switching the first parallel FET 6 to an ON state with sufficiently low conduction resistance. Therefore, when the charge pump 11 is stopped and a high-frequency signal entering the common terminal 2 from an external terminal passes through the first parallel FET 6, the generation of reflected waves due to the conduction resistance of the first parallel FET 6 can be reduced, and the high-frequency signal can be sent to ground. As a result, the reflected waves returning to the external terminal and degrading the reception sensitivity of the external terminal can be further reduced.

[0068] Furthermore, the high-frequency switch circuit 1 according to Embodiment 1 further comprises a second input / output terminal 4, a second series FET 7, and a second parallel FET 8. The second input / output terminal 4 is connected to the common terminal 2 via a second signal path L2. The second series FET 7 is connected to the common terminal 2 and the second input / output terminal 4 in the second signal path L2. The second parallel FET 8 is connected between the signal path L22 between the second input / output terminal 4 and the second series FET 7 and ground. The connection node N1 is further connected to the control electrode of the second series FET 7.

[0069] With this configuration, the second series FET 7 provided in the second signal path L2, like the first series FET 5, can reduce the generation of reflected waves due to the conduction resistance of the second series FET 7 when the charge pump 11 is stopped and a high-frequency signal entering the common terminal 2 from an external terminal passes through the second series FET 7. As a result, the deterioration of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be further reduced.

[0070] Furthermore, in the high-frequency switch circuit 1 according to Embodiment 1, the charge pump 11 supplies a control voltage to control each of the FETs 5 to 9 based on the voltage from the voltage source 10 (e.g., power supply voltage). With this configuration, the voltage source 10 for the voltage supply path 12 can be used as the voltage source for the charge pump 11. As a result, the high-frequency switch circuit 1 can be miniaturized.

[0071] Furthermore, the high-frequency switch circuit 1 according to Embodiment 1 further comprises a third parallel FET 9 (parallel FET). The third parallel FET 9 is connected between the common terminal 2 and ground.

[0072] With this configuration, the third parallel FET 9 connected between the common terminal 2 and ground, similar to the first series FET 5, can reduce the generation of reflected waves due to the conduction resistance of the third parallel FET 9 when the charge pump 11 is stopped and a high-frequency signal entering the common terminal 2 from an external terminal passes through the third parallel FET 9, and can also allow the high-frequency signal to flow to ground. As a result, the reflected waves returning to the external terminal and degrading the reception sensitivity of the external terminal can be further reduced.

[0073] Furthermore, the high-frequency switch circuit 1 according to Embodiment 1 further comprises a first level shifter 13 and a second level shifter 14. The first level shifter 13 controls the first series FET 5. The second level shifter 14 controls the first parallel FET 6. The first level shifter 13 has a first input section 13a, a second input section 13b, and an output section 13c (first output section). The first input section 13a is connected to the connection node N1. The second input section 13b is connected to the charge pump 11 (negative voltage supply circuit). The output section 13c is connected to the control electrode of the first series FET 5 and selectively outputs the voltage input to the first input section 13a and the voltage input to the second input section 13b. The second level shifter 14 has a first input section 14a (third input section), a second input section 14b (fourth input section), and an output section 14c (second output section). The first input section 14a is connected to path M1a or connection node N1 (connection node N1 in Embodiment 1). Path M1a is the path between the first output section 11b (output section) of the charge pump 11 and the first switch SW1. The second input section 14b is connected to the charge pump 11 (negative voltage supply circuit). The output section 14c is connected to the control electrode of the first parallel FET 6 and selectively outputs the voltage input to the first input section 14a and the voltage input to the second input section 14b.

[0074] With this configuration, even when a first level shifter 13 and a second level shifter 14 are provided, when the charge pump 11 is stopped, and a high-frequency signal entering the common terminal 2 from an external terminal passes through the FET (at least the first series FET 5 of the first series FET 5 and the first parallel FET 6 (in Embodiment 1, the first series FET 5 and the first parallel FET 6)), the generation of reflected waves due to the conduction resistance of the FET can be reduced. As a result, the deterioration of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be reduced.

[0075] Furthermore, the high-frequency module 31 according to Embodiment 1 comprises a high-frequency switch circuit 1 and an electronic component 50. The electronic component 50 is connected between the first input / output terminal 3 and the external terminal 40b of the high-frequency switch circuit 1. With this configuration, a high-frequency module 31 that exhibits the effects of the high-frequency switch circuit 1 can be provided.

[0076] Furthermore, the communication device 30 according to Embodiment 1 comprises a high-frequency module 31 and a signal processing circuit 32. The signal processing circuit 32 is connected to the high-frequency module 31 and processes high-frequency signals. With this configuration, a communication device 30 that achieves the effects of the high-frequency switch circuit 1 can be provided.

[0077] (1-8) Variations A modified example of Embodiment 1 will be described. Embodiment 1 illustrates a case where one or more receiving components 50 are connected between the first input / output terminal 3 and the external terminal 40b, and one or more transmitting components 51 are connected between the second input / output terminal 4 and the external terminal 40c. However, one or more transmitting components 51 may be connected between the first input / output terminal 3 and the external terminal 40b, and one or more receiving components 50 may be connected between the second input / output terminal 4 and the external terminal 40c. In this case, the external terminal 40b becomes an input terminal that inputs the transmitted signal processed by the signal processing circuit 32 to the high-frequency module 31, and the external terminal 40c becomes an output terminal that outputs the received signal processed by the high-frequency module 31 to the input section of the signal processing circuit 32.

[0078] (2) Embodiment 2 Referring to Figure 3, the high-frequency switch circuit 1 according to Embodiment 2 will be described. In the following description, components identical to those in Embodiment 1 may be denoted by the same reference numerals and their descriptions may be omitted.

[0079] (2-1) Composition Embodiment 1 illustrates the case where all control electrodes of FETs 5 to 9 are connected to connection node N1. More specifically, Embodiment 1 illustrates the case where all first input sections 13a to 17a of the first to fifth level shifters 13 to 17 are connected to connection node N1. In contrast, as shown in Figure 3, in Embodiment 2, the control electrodes of the first series FET 5 and the second series FET 7 among FETs 5 to 9 are connected to connection node N1, as in Embodiment 1. The control electrodes of the remaining first to third parallel FETs 6, 8, and 9 are connected to connection node N6 provided in path M1a. Here, path M1a is the portion of the first path M1 between the first output section 11b of the charge pump 11 and the first switch SW1, which is the path between the first output section 11b of the charge pump 11 and connection node N1.

[0080] More specifically, in Embodiment 2, the first input sections 13a and 15a of the first level shifter 13 and the third level shifter 15, corresponding to the first series FET 5 and the second series FET 7, are connected to connection node N1. On the other hand, the first input sections 14a, 16a and 17a of the second, fourth and fifth level shifters 14, 16 and 17, corresponding to the remaining first to third parallel FETs 6, 8 and 9, are connected to connection node N6 provided on path M1a.

[0081] In other words, in Embodiment 2, the first inputs 13a and 15a of the first level shifter 13 and the third level shifter 15 are selectively supplied with either the output voltage of the first output 11b of the charge pump 11 or the output voltage of the first output 10a of the voltage source 10, depending on whether the first switch SW1 and the second switch SW2 are switched on or off. However, the first inputs 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17a are always supplied with the output voltage of the first output 11b of the charge pump 11, regardless of whether the first and second switches are switched on or off.

[0082] (2-2) Operation In the transmit / receive mode of Embodiment 2, the first switch SW1 is switched ON and the second switch SW2 is switched OFF, similar to Embodiment 1. Therefore, in Embodiment 2, similar to Embodiment 1, the output voltage (positive voltage) of the first output section 11b of the charge pump 11 is applied to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17, and the output voltage (negative voltage) of the second output section 11c of the charge pump 11 is applied to the second input sections 13b to 17b of the first to fifth level shifters 13 to 17. Then, in accordance with the control signals input to the control signal input sections 13d to 17d of the first to fifth level shifters 13 to 17, the on / off state of FETs 5 to 9 is switched, similar to Embodiment 1.

[0083] In the low-power mode of Embodiment 2, similar to Embodiment 1, the first switch SW1 is switched to the OFF position and the second switch SW2 is switched to the ON position. As a result, the first inputs 13a and 15a of the first level shifter 13 and the third level shifter 15 are supplied with the output voltage (power supply voltage) of the first output 10a of the voltage source 10. On the other hand, in the low-power mode, the charge pump 11 is stopped, so the output voltages of the first output 11b and second output 11c of the charge pump 11 become voltages around 0V. Therefore, in the low-power mode, the first inputs 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17 are supplied with a voltage around 0V as the output voltage of the first output 11b of the charge pump 11. The output voltage (voltage near 0V) of the second output section 11c of the charge pump 11 is applied to the second input sections 13b to 17b of the first to fifth level shifters 13 to 17.

[0084] In Embodiment 2, as in Embodiment 1, in low-power mode, all of FETs 5 to 9 are switched on by the first to fifth level shifters 13 to 17. More specifically, in low-power mode, as described above, as in Embodiment 1, the output voltage (power supply voltage) of the first output section 10a of the voltage source 10 is applied to the first input sections 13a and 15a of the first and third level shifters 13 and 15, so that the first series FET 5 and the second series FET 7 are switched on by a sufficiently high voltage (power supply voltage). For this reason, as in Embodiment 1, even if a high-frequency signal from an external terminal enters the high-frequency switch circuit 1, the generation of reflected waves of the high-frequency signal is reduced when the high-frequency signal passes through the first series FET 5 and the second series FET 7.

[0085] Furthermore, in low power consumption mode, as described above, the output voltage of the first output section 11b of the charge pump 11 (voltage near 0V) is applied to the first input sections 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17, respectively. As a result, the first to third parallel FETs 6, 8, and 9 are switched on by the voltage near 0V. In other words, the first to third parallel FETs 6, 8, and 9 are not fully switched on, and the conduction resistance in the on state becomes somewhat high. Therefore, when a high-frequency signal from an external terminal enters the high-frequency switch circuit 1 and passes through the first to third parallel FETs 6, 8, and 9, a reflected wave of the high-frequency signal may be generated. However, in Embodiment 2, in low power consumption mode, the reflected wave of the high-frequency signal is reduced in the first series FET 5 and the second series FET 7. Although the effect is weaker compared to Embodiment 1, the overall reflection wave of the high-frequency signal can be reduced.

[0086] (2-3) Effects The high-frequency switch circuit 1 according to Embodiment 2 comprises a common terminal 2, a first input / output terminal 3, a first series FET 5, a first parallel FET 6, a charge pump 11, a voltage supply path 12, a first switch SW1, and a second switch SW2, similar to Embodiment 1. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET and ground. The charge pump 11 supplies a control voltage for controlling the first series FET 5 and a control voltage for controlling the first parallel FET 6. The voltage supply path 12 is connected to a connection node N1 to which the first output section 11b (output section) of the charge pump 11 and the control electrode of the first series FET 5 are connected. The first switch SW1 is provided in the first path M1 connecting the first output section 11b of the charge pump 11 and the connection node N1, and controls the conduction and disconnection of the first path M1. The second switch SW2 is provided in the voltage supply path 12, and controls the conduction and disconnection of the voltage supply path 12.

[0087] With this configuration, similar to Embodiment 1, when the charge pump 11 is stopped, the first switch SW1 blocks the first path M1 and the second switch SW2 opens the voltage supply path 12, thereby applying the power supply voltage applied to the voltage supply path 12 to the control electrode of the first series FET 5, and switching the first series FET 5 to an ON state with sufficiently low conduction resistance. Therefore, when the charge pump 11 is stopped and a high-frequency signal that has entered the common terminal 2 from an external terminal passes through the first series FET 5, the generation of reflected waves of the high-frequency signal due to the conduction resistance of the first series FET 5 can be reduced. As a result, the deterioration of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be reduced.

[0088] (3) Embodiment 3 Referring to Figure 4, the high-frequency switch circuit 1 according to Embodiment 3 will be described. In the following description, components identical to those in Embodiment 1 may be denoted by the same reference numerals and their descriptions may be omitted.

[0089] (3-1) Composition As shown in Figure 4, the high-frequency switch circuit 1 according to Embodiment 3 is configured similarly to the high-frequency switch circuit 1 according to Embodiment 1, except that it further includes a changeover switch 60 instead of the first switch SW1 and the second switch SW2.

[0090] In Embodiment 1, the changeover switch 60 is located at the connection node N1 and corresponds to a switch that includes a first switch SW1 and a second switch SW2.

[0091] The changeover switch 60 selectively connects one of the first path M1 and the voltage supply path 12 (in other words, one of the first output section 11b of the charge pump 11 and the first output section 10a of the voltage source 10) to the control electrodes of FETs 5 to 9.

[0092] More specifically, it has a common terminal 60a, a first selection terminal 60b, and a second selection terminal 60c.

[0093] The first selection terminal 60b is connected to the first output section 11b of the charge pump 11 via the first path M1. That is, the first selection terminal 60b is connected to one end of the first path M1. The second selection terminal 60c is connected to the first output section 10a of the voltage source 10 via the voltage supply path 12. That is, the second selection terminal 60c is connected to one end of the voltage supply path 12. The common terminal 60a can be selectively connected to either the first selection terminal 60b or the second selection terminal 60c. The common terminal 60a is connected to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. The first to fifth level shifters 13 to 17 correspond one-to-one with FETs 5 to 9. Also, the first to fifth level shifters 13 to 17 correspond one-to-one with resistors R1 to R5. The output sections 13c to 17c of the first to fifth level shifters 13 to 17 are connected to the corresponding control electrodes of FETs 5 to 9 via opposing resistors R1 to R5. Therefore, the common terminal 60a is connected to the control electrodes of FETs 5 to 9. More specifically, the common terminal 60a is indirectly connected to the control electrodes of FETs 5 to 9 via the corresponding first to fifth level shifters 13 to 17 and the corresponding resistors R1 to R5.

[0094] In transmit / receive mode, the changeover switch 60 selectively connects the common terminal 60a to the first selection terminal 60b. That is, in transmit / receive mode, the changeover switch 60 connects the first path M1 to the control electrodes of FETs 5 to 9. More specifically, the changeover switch 60 connects the first path M1 to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. As a result, in the transmit / receive mode of Embodiment 3, similar to the transmit / receive mode of Embodiment 1, the output voltage (positive voltage) of the first output section 11b of the charge pump 11 is applied to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17.

[0095] Furthermore, since the output sections 13c to 17c of the 1st to 5th level shifters 13 to 17 are connected to the corresponding control electrodes of FETs 5 to 9 via corresponding resistors R1 to R5, the changeover switch 60 connects the first path M1 to the control electrodes of FETs 5 to 9 in transmit / receive mode.

[0096] Furthermore, in low power consumption mode, the changeover switch 60 selectively connects the common terminal 60a to the second selection terminal 60c. That is, in low power consumption mode, the changeover switch 60 connects the voltage supply path 12 to the control electrodes of FETs 5 to 9. More specifically, the changeover switch 60 connects the voltage supply path 12 to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. As a result, in the low power consumption mode of Embodiment 3, similar to the low power consumption mode of Embodiment 1, the output voltage (power supply voltage) of the first output section 10a of the voltage source 10 is applied to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17.

[0097] Furthermore, since the output sections 13c to 17c of the 1st to 5th level shifters 13 to 17 are connected to the corresponding control electrodes of FETs 5 to 9 via corresponding resistors R1 to R5, the changeover switch 60 connects the voltage supply path 12 to the control electrodes of FETs 5 to 9 in low power consumption mode.

[0098] (3-2) Operation The operation of the high-frequency switch circuit 1 in Embodiment 3 is the same as that of the high-frequency switch circuit 1 in Embodiment 1, except that the first switch SW1 and the second switch SW2 are replaced with changeover switches 60. Therefore, a detailed explanation is omitted.

[0099] (3-3) Effects The high-frequency switch circuit 1 according to Embodiment 3 includes a changeover switch 60. The changeover switch 60 includes a first switch SW1 and a second switch SW2. The changeover switch 60 selectively connects one of the first path M1 and the voltage supply path 12 to the control electrode of the first series FET 5. With this configuration, the first switch SW1 and the second switch SW2 can be integrated by the changeover switch 60. As a result, the high-frequency switch circuit 1 can be miniaturized.

[0100] The embodiments and modifications described above are only a part of the various embodiments and modifications of the present invention. Furthermore, the embodiments and modifications can be modified in various ways depending on the design, etc., as long as the objectives of the present invention are achieved. [Explanation of symbols]

[0101] 1. High-frequency switch circuit 2 Common terminals 3 1st input / output terminal 4 2nd input / output terminal 5. First series FET 6 1st parallel FET 7. Second series FET 8 2nd parallel FET 9 3rd parallel FET 10 Voltage source 10a First output section 10b Second Output Section 11 Charge pump 11a Input section 11b First Output Section (Output Section) 11c 2nd output section 12 Voltage supply path 13 Level 1 Shifter 13a First Input Section 13b Second Input Section 13c Output section (First output section) 13d Control signal input section 14 Level 2 Shifter 14a First input section (third input section) 14b Second input section (fourth input section) 14c Output section (2nd output section) 14d Control signal input section 15. Level 3 Shifter 15a First Input Section 15b Second Input Section 15c output section 15d Control signal input section 16. Level 4 Shifter 16a First Input Section 16b Second Input Section 16c output section 16d Control signal input section 17. Level 5 Shifter 17a First Input Section 17b Second Input Section 17c Output section 17d Control signal input section 30 Communication equipment 31 High-Frequency Modules 32 Signal Processing Circuits 33 Antennas 34 Baseband signal processing circuit 35 RF signal processing circuit 36 Receiving Filter 36a Input section 36b Output section 37 Transmission Filter 37a Input section 37b Output section 38. Low-noise amplifier (electronic component) 38a Input section 38b Output section 39 Power Amplifier 39a Input section 39b Output section 40a~10d External terminals 50 Receiving parts (electronic parts) 51 Transmission parts (electronic parts) 60 Changeover switch 60a Common terminal 60b First Select Terminal 60c Second Select Terminal L1 First signal path L2 Second signal path L3, L11, L12, L21, L22 signal paths M1 First Route M1a Route N1~N6 Connection Nodes R1~R5 Resistors SW1 1st switch SW2 Second Switch

Claims

1. Common terminal and A first input / output terminal connected to the common terminal via a first signal path, A first series FET connected to the common terminal and the first input / output terminal in the first signal path, A first parallel FET is connected between the signal path between the first input / output terminal and the first series FET and ground, A charge pump having an output section, which supplies a control voltage for controlling the first series FET and a control voltage for controlling the first parallel FET from the output section, A voltage source having a first output section and a second output section that supply voltage, and the second output section supplies the voltage to the charge pump, A voltage supply path connecting the first output section of the voltage source and the connection node to which the control electrode of the first series FET is connected, A first switch is provided in the first path connecting the output section of the charge pump and the connection node, and the first switch is provided in the first path for conducting and disconnecting the first path, The system includes a second switch provided in the voltage supply path for conducting and interrupting the voltage supply path, High-frequency switch circuit.

2. The control electrode of the first parallel FET is connected to a path that connects the connection node and the control electrode of the first series FET. The high-frequency switch circuit according to claim 1.

3. A second input / output terminal connected to the common terminal via a second signal path, In the second signal path, a second series FET is connected to the common terminal and the second input / output terminal, The system further comprises a second parallel FET connected between the signal path between the second input / output terminal and the second series FET and ground, The connection node is further connected to the control electrode of the second series FET. The high-frequency switch circuit according to claim 1 or 2.

4. The charge pump supplies the control voltage based on the voltage from the voltage source. A high-frequency switch circuit according to any one of claims 1 to 3.

5. The system further comprises a parallel FET connected between the common terminal and the ground. A high-frequency switch circuit according to any one of claims 1 to 4.

6. The system further comprises a changeover switch including the first switch and the second switch, The changeover switch selectively connects one of the first path and the voltage supply path to the control electrode of the first series FET. A high-frequency switch circuit according to any one of claims 1 to 5.

7. A first level shifter that controls the first series FET, The system further comprises a second level shifter for controlling the first parallel FET, The aforementioned first level shifter is The first input unit connected to the aforementioned connection node, A second input section connected to a negative voltage supply circuit, It has a first output unit connected to the control electrode of the first series FET, which selectively outputs the voltage input to the first input unit and the voltage input to the second input unit, The aforementioned second level shifter is The path between the output section of the charge pump and the first switch, or the third input section connected to the connection node, A fourth input unit connected to the aforementioned negative voltage supply circuit, It has a second output unit connected to the control electrode of the first parallel FET, which selectively outputs the voltage input to the third input unit and the voltage input to the fourth input unit. A high-frequency switch circuit according to any one of claims 1 to 5.

8. A high-frequency switch circuit according to any one of claims 1 to 7, The high-frequency switch circuit comprises an electronic component connected between the first input / output terminal and the external terminal. High-frequency module.

9. The high-frequency module according to claim 8, The system includes a signal processing circuit connected to the aforementioned high-frequency module for processing high-frequency signals. Communication device.

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