Semiconductor equipment

Abstract

To obtain a small semiconductor device with high voltage resistance, which combines a switching element with a protective element to protect it. [Solution] The device comprises an n-type first semiconductor region 11 and an n-type common contact region 12 formed locally on the first semiconductor region 11 with a high impurity concentration, which is connected to a common electrode that serves as both the first main electrode of the switching element and the first electrode on the protection element side. In the switching element region R1, a p-type second semiconductor region 13 is formed in the first semiconductor region 11 at a location radially separated from the common contact region 12, and an n-type third semiconductor region 14 is formed in the second semiconductor region 13. The second main electrode is connected to the third semiconductor region 14. In the protection element region R2, a p-type fourth semiconductor region 16 is formed in the first semiconductor region 11 at a location radially separated from the common contact region 12, and the second electrode on the protection element side is connected to the fourth semiconductor region 16.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device comprising a lateral switching element and a protective element thereof. [Background technology]

[0002] As a power semiconductor device, a laterally diffused MOS (LDMOS) transistor (switching element) having a drift layer through which the on-current flows in the plane direction of the semiconductor layer is preferred because it can achieve a high breakdown voltage. In this case, the length of the region where the breakdown voltage should be ensured (high breakdown voltage region) along the electric field direction is set in the in-plane direction of the semiconductor layer so that the breakdown voltage is ensured because the electric field strength is particularly high when the device is off.

[0003] Furthermore, as described in Patent Document 1, for example, a technique is used in which a protective element (e.g., a diode) is connected between the source and drain of the LDMOS, and when a surge voltage exceeding the withstand voltage is applied to the LDMOS, the protective element is broken down instead of the LDMOS to bypass the current and prevent damage to the LDMOS and the electrical circuit connected to it.

[0004] In this case, the breakdown voltage of this protective element (diode) is set high in correspondence with that of the LDMOS. For this reason, this diode is also horizontal, and like the LDMOS, a high breakdown voltage region is set to a certain size in the diode as well. In the technology described in Patent Document 1, an LDMOS is formed in one region on a plane, and the region constituting the diode is formed surrounding this LDMOS. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-319072 [Overview of the project] [Problems that the invention aims to solve]

[0006] As described above, in order to form both the LDMOS and the lateral protection element on a common semiconductor substrate and increase the breakdown voltages of both, a large area is required in total for both regions. Alternatively, when the area is limited, the current flowing through the LDMOS or the protection element cannot be increased, resulting in a degradation of the protection function. Therefore, it has been difficult to obtain a small-sized semiconductor device with a high breakdown voltage, in which a switching element and a protection element for protecting the same are combined.

[0007] The present disclosure has been made in view of such problems, and an object thereof is to provide a semiconductor device that solves the above problems.

Means for Solving the Problems

[0008] In order to solve the above problems, the present disclosure has the following configuration. The semiconductor device of the present disclosure includes, on a semiconductor substrate, a switching element whose on / off is controlled by the potential of a control electrode between a first main electrode on the high potential side and a second main electrode on the low potential side, and a protection element that bypasses and conducts current between a first protection element side electrode on the high potential side and a second protection element side electrode on the low potential side when the switching element is off. The semiconductor device is formed with a first semiconductor region of a second conductivity type opposite to the first conductivity type formed on the surface side of the semiconductor substrate of the first conductivity type, a common electrode that also serves as the first main electrode and the first protection element side electrode, and a common contact region of the second conductivity type that is locally formed on the first semiconductor region at a high impurity concentration and is connected to the common electrode. In a circumferential direction region centered on the common contact region in a plan view, one region and another region are respectively a switching element region where the switching element is formed and a protection element region where the protection element is formed. In the switching element region, a second semiconductor region of the first conductivity type that is locally formed at a location radially separated from the common contact region in the first semiconductor region in a plan view, and a third semiconductor region of the second conductivity type that is locally formed in the second semiconductor region in a plan view are provided. The second main electrode is connected to the third semiconductor region. In the protection element region, a fourth semiconductor region of the first conductivity type that is locally formed at a location radially separated from the common contact region in the first semiconductor region in a plan view is provided. The second protection element side electrode is connected to the fourth semiconductor region. The first semiconductor region is integrated across the switching element region and the protection element region, and in a plan view, the end on the common contact region side of the second semiconductor region and the end on the common contact region side of the fourth semiconductor region are separated from each other. The shortest distance from the common contact region to the fourth semiconductor region in the protection element region may be set shorter than the shortest distance from the common contact region to the second semiconductor region in the switching element region. The semiconductor substrate comprises a second conductivity type embedded semiconductor region formed deeper than the first semiconductor region on the common contact region side and connected to the first semiconductor region, wherein the shortest distance from the common contact region to the second semiconductor region is equal to the shortest distance from the common contact region to the fourth semiconductor region, and the shortest distance between the embedded semiconductor region and the second semiconductor region in the switching element region is set to be shorter than the shortest distance between the embedded semiconductor region and the fourth semiconductor region in the protection element region. A plurality of field plates, composed of a conductor and facing the surface of the first semiconductor region via an insulating layer, may be formed to surround the common electrode in a plan view, such that they capacitively couple with each other between the common electrode and the control electrode, and between the common electrode and the second electrode on the protection element side. The protection element side may have a fifth semiconductor region of the second conductivity type locally formed within the fourth semiconductor region, and the second electrode on the protection element side may be connected to the fifth semiconductor region. The shortest distance between the common contact region and the second semiconductor region in the switching element region may be set to be equal to the shortest distance between the common contact region and the fourth semiconductor region in the protection element region. One of the second semiconductor region and the fourth semiconductor region may be formed inside the first semiconductor region in a plan view. In a plan view, one of the second semiconductor region and the fourth semiconductor region may be connected to the semiconductor substrate on the radially outer side. The second semiconductor region is formed inside the first semiconductor region in a plan view, and the distance between the outermost radial edge of the first semiconductor region in one direction and the outermost radial edge of the first semiconductor region in the other direction, which does not directly contact the semiconductor substrate other than the portion in which the first semiconductor region is formed, may be less than or equal to the distance between the second semiconductor region and the fourth semiconductor region in the circumferential direction. In a plan view, on the surface of the first semiconductor region between the second and fourth semiconductor regions, where the second and fourth semiconductor regions are locally separated in the circumferential direction, an inter-element field plate made of a conductor may be formed on the surface of the first semiconductor region via an insulating layer. The inter-element field plate may be connected to the second semiconductor region, the fourth semiconductor region, or the control electrode by a conductive material. [Effects of the Invention]

[0009] As described above, this disclosure provides a compact semiconductor device with high voltage resistance, which combines a switching element with a protective element to protect it. [Brief explanation of the drawing]

[0010] [Figure 1] This is a circuit diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] This is a cross-sectional view of the switching element region side of the semiconductor device according to an embodiment of the present disclosure. [Figure 3] This is a cross-sectional view of the protective element region side of the semiconductor device according to an embodiment of the present disclosure. [Figure 4] This is a top view showing the configuration of a semiconductor device (excluding the field plate) according to an embodiment of the present disclosure. [Figure 5] This is a cross-sectional view of an example of a semiconductor device according to an embodiment of the present disclosure, in which the depth profiles of the second semiconductor region and the fourth semiconductor region are different. [Figure 6] This is a cross-sectional view of an example of a semiconductor device according to an embodiment of the present disclosure, showing a different structure of the first semiconductor region. [Figure 7] This is a top view (a) and a partially enlarged view (b) showing the configuration of a field plate in a semiconductor device according to an embodiment of the present disclosure. [Figure 8] This is a circuit diagram showing the configuration of a first modified example of a semiconductor device according to an embodiment of the present disclosure. [Figure 9]This is a cross-sectional view of the protective element region side of a first modified example of a semiconductor device according to an embodiment of the present disclosure. [Figure 10] This is a top view of a semiconductor device according to an embodiment of the present disclosure, showing the first semiconductor region, the second semiconductor region, and the fourth semiconductor region in two different positional relationships. [Figure 11] This is a top view of a first modified example of a semiconductor device according to an embodiment of the present disclosure, showing the first semiconductor region, the second semiconductor region, and the fourth semiconductor region in four different positional relationships. [Figure 12] This figure shows the setting of the distance between each layer in a semiconductor device according to an embodiment of the present disclosure, where the potentials of the second semiconductor region and the fourth semiconductor region are different. [Figure 13] This is a top view of an example of a semiconductor device according to an embodiment of the present disclosure, in which a protective element is more easily broken down than a switching element. [Figure 14] This is a top view partially showing the configuration of a second modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 15] This is a partial cross-sectional view of a second modified example of the semiconductor device according to an embodiment of the present disclosure. [Figure 16] This is a plan view of the configuration of another example (Part 1) of the inter-element field plate in a second modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 17] This is a plan view of the configuration of another example (part 2) of the inter-element field plate in a second modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 18] This is a circuit diagram showing the configuration of a third modified example of the semiconductor device according to the embodiment of this disclosure. [Modes for carrying out the invention]

[0011] The following describes a semiconductor device that is an embodiment of this disclosure. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the lengths of each part, etc., may differ from reality. Therefore, specific dimensions should be determined by referring to the following explanation. It should also be noted that there are parts where the relationships and ratios of dimensions differ between drawings. Furthermore, the embodiments shown below are illustrative examples of devices for realizing the technical idea of ​​this disclosure, and the technical idea of ​​this disclosure does not limit the shape, structure, arrangement, etc. of the components to those described below. Various modifications can be made to the embodiments of this invention within the scope of the claims. In this disclosure, terms such as "top" and "bottom" are used for convenience of description, and even if they are provided on the side surface, if they are substantially identical to the constituent elements of this disclosure, they fall within the scope of the rights of this disclosure. Also, "top" includes not only cases where it is formed in contact with the object, but also cases where it is formed through another layer. Furthermore, in this disclosure, "connection" is not limited to direct connection; even if a connection is made by interposing something such as a resistor, if it is substantially the same as the constituent elements of this disclosure, it falls within the scope of the rights of this disclosure.

[0012] Figure 1 is a circuit diagram showing the configuration of this semiconductor device 1. Here, an n-channel MOSFET (LDMOS) element (switching element) T1 and a diode (pn diode) element (protection element) T2 are formed on a common semiconductor substrate. Here, the n-type layer (drift layer) connected to the drain (D: high-potential side electrode (first main electrode)) of element T1 and the n-type layer connected to the cathode (CA) of element T2 are common. The source (S: low-potential side electrode (second main electrode)), gate (G: first control electrode), and related structures are the same as those of a normal MOSFET. When the potential VS of the source (S) is set to, for example, the ground potential (GND) and the potential VD of the drain (D) is set to a positive potential, the on / off state of the current between the drain (D) and source (S) is controlled by the voltage VG of the gate (G).

[0013] In this case, the potential VBG of the body layer (BG) of element T1 (MOSFET) may be equal to the source (S), but it may also be controlled independently of VS by applying a predetermined potential to the back gate electrode (second control electrode). This allows for adjustment of the characteristics of element T1.

[0014] Furthermore, element T2 is a pn-type diode, and its cathode (CA: first electrode on the protection element side) is shared with the drain (D: first main electrode) of element T1, so the aforementioned VD is applied. Also, the potential of its anode (AN: second electrode on the protection element side) is set to VAN, which is close to the ground potential, similar to VBG. With the VD and VAN potential settings described above, element T2 is normally off (reverse biased), but as VD increases, element T2 breaks down and can flow a large current. This characteristic can be fine-tuned with VAN, etc.

[0015] If a positive voltage, such as a high-voltage surge, is applied to the drain (D) side when element T1 is off, element T1 may break down. In this case, if element T2 breaks down before element T1 (bypassing the current through element T2), the large current flowing due to the breakdown in element T1 can be suppressed, and damage to element T1 or the electrical circuit connected to it can be prevented.

[0016] Note that the VBG in element T1 and the VAN in element T2 may be common (dashed line in the figure), or they may be controlled individually, which can be easily achieved by wiring connections. Furthermore, as will be described later, it is also possible to realize a structure in Figure 1 where either the VBG or VAN automatically becomes GND.

[0017] Here, on the element T1 side, the planar region in the semiconductor layer where the electric field strength is high when the semiconductor device 1 is turned off is the region between the gate (G) and drain (D), where the potential difference between its ends is particularly large. On the element T2 side, the region where the electric field strength is high when the semiconductor device 1 is turned off is the region between the cathode (CA) and anode (AN). Therefore, in order to achieve high breakdown voltage, it is necessary to make each of these regions wide along the direction of the electric field. In Figure 1, the drain (D) of element T1 and the cathode (CA) of element T2 are connected to a common terminal with a potential of VD. In addition, in this semiconductor device 1, a roughly circular region on the semiconductor substrate is divided in the circumferential direction, and is divided into a part that operates as element T1 and a part that operates as element T2. As a result, in this semiconductor device 1, even when the breakdown voltage of elements T1 and T2 is set high, the overall size can be reduced.

[0018] Figure 2 is a cross-sectional view of the region where element T1 is formed (switching element region) in the semiconductor device 1, Figure 3 is a cross-sectional view of the region where element T2 is formed (protection element region), and Figure 4 is a top view of the semiconductor device 1. Figure 2 is a cross-sectional view in the AA direction in Figure 4, and Figure 3 is a cross-sectional view in the BB direction. In Figures 2 and 3, the semiconductor device 1 is formed on a p-type substrate (semiconductor substrate) 10 which is p-type (first conductivity type). In Figure 4, R1 is the switching element region, R2 is the protection element region, and R3 is the connection region connecting them.

[0019] In Figures 2 and 3, an n-type (second conductivity type) n-layer (first semiconductor region) 11 is broadly formed on the surface side of the p-type substrate 10 in the shape shown, and elements T1 and T2 in Figure 1 are both formed using this n-layer 11. In Figures 2 and 3, the right side of the n-layer 11 is the low-potential side (closer to ground potential), and the left side is the high-potential side (e.g., +600V or higher). In Figure 2 (switching element region), a p-type p-layer (second semiconductor region) 13, which is the body region of the MOSFET, is formed on the low-potential side (right side in the figure), and an n-type n-layer (first semiconductor region) 11 is formed on the higher-potential side. In addition, a higher-density and deeper n-type n-layer (embedded n-type layer: embedded semiconductor region) 11A is connected to the n-layer 11 on its high-potential side. Similarly, in Figure 3 (protection element region), a p-layer 16 is formed on the low-potential side (right side in the figure) corresponding to the p-layer 13, but its impurity concentration and depth do not need to be the same as those of the p-layer 13. On the higher-potential side, as in Figure 2, an n-layer 11 and an n-layer (embedded n-type layer: embedded semiconductor region) 11A are formed in the same way. As will be described later, the n-layer 11 and n-layer 11A in the switching element region (Figure 2) are connected to the n-layer 11 and n-layer 11A in the protection element region (Figure 3), respectively, but their impurity concentrations and depths do not need to match between the switching element region and the protection element region, and can be individually adjusted according to the characteristics of elements T1 and T2.

[0020] In FIG. 4, the overall shape of the n-layer 11A is circular (i.e., the same sector shape on both the switching element R1 side and the protection element region R2 side), but this shape does not necessarily have to be circular (the shapes on the switching element R1 side and the protection element region R2 side are the same). That is, this shape can be set appropriately according to the characteristics of the LDMOS and the specification of the diode. The same applies not only to the shape but also to its impurity concentration. Furthermore, the same applies to the impurity concentration of the n-layer 11.

[0021] Also, in FIGS. 2 and 3, on the left side (high potential side) surface of the n-layer 11, an n + layer (common contact region) 12, which is a high-concentration n-type layer, is formed. As shown in FIG. 4, the n + layers 12 in these figures are actually the same, and in FIGS. 2 and 3, cross-sections in different directions are shown.

[0022] In FIG. 2, the n + layer 12 on the n-layer 11 functions as a contact layer in the drain (D) region of the element T1 in FIG. 1. On the other hand, on the surface of the p-layer 13, an n + layer (third semiconductor region) 14, which is a high-concentration n-type, and a p + layer 15, which is a high-concentration p-type, are formed on the left and right sides, respectively. The p + layer 15 is formed as a contact layer to the p-layer 13 (second semiconductor region), and thereby the potential of the p-layer 13 is set to VBG in FIG. 1. The n + layer 14 functions as the source (S) region of the element T1, and its potential is set to VS in FIG. 1.

[0023] In FIG. 3, the n + layer 12 on the n-layer 11 functions as a contact layer in the cathode (CA) region of the element T2 in FIG. 1. That is, the n +Layer 12 is a common contact region for connecting to the drain (D) and cathode (CA) in Figure 1. In Figure 3, a p-type p-layer (fourth semiconductor region) 16 is formed on the surface of the p-type substrate 10 on the right side (low potential side), corresponding to the p-layer 13 in Figure 2, and in contact with the n-layer 11. As will be described later, in reality, the p-layer 13 and p-layer 16 are separated in terms of the operation of the device, but in Figures 2 and 3, their potential is in direct contact with the p-type substrate 10, so in Figure 1, VBG = VAN (=VS). Here, the potential of the p-type substrate 10 can be, for example, GND.

[0024] On the surface of the p layer 16, there is a higher concentration of p-type than the p layer 16. + Layer 17 is formed. The p layer 16 functions as the anode layer of the device T2, and its potential is given as VAN in Figure 1. + Layer 17 is formed for contact with the p layer 16, which will be the anode layer.

[0025] In Figures 2 and 3, an interlayer insulating layer 20 made of a silicon oxide film is formed on the semiconductor substrate on which the above structure is formed, and each wiring is connected to each of the above layers through openings formed in the interlayer insulating layer 20, thereby realizing the circuit configuration of Figure 1. First, n + The drain electrode (common electrode) 21 of element T1 is connected to layer 12. As described above, the drain electrode 21, whose potential is VD in the figure, also serves as the collector electrode of element T2. In Figure 2, n + A source electrode (second main electrode) 22 with a potential of VS is connected to layer 14, and to its right in the figure, p + A back gate electrode (second control electrode) 23, with a potential of VBG, is connected to layer 15. As described above, in this semiconductor device 1, VS, VBG, and VAN in Figure 1 are controlled independently.

[0026] Also, n +On the surface of layer 14 and the area to its left where the n layer 11 is exposed, a gate electrode (first control electrode) 25 is formed opposite to it via a gate oxide film 24 that is thinner than the interlayer insulating layer 20, with a potential of VG as shown in Figure 1. This structure forms a MOSFET element T1 that operates using a drain electrode 21, a source electrode 22, and a gate electrode 25 (and further a back gate electrode 23). In this MOSFET, when it is ON, the p layer 13 and n + When an ON current flows through the n-layer 11 up to layer 12, and a high voltage is applied to the drain electrode 21 when it is OFF, at least a portion of the n-layer 11 in this region becomes depleted.

[0027] Furthermore, in Figure 2, a silicon oxide film thicker than the gate oxide film 24 is formed directly beneath the left portion of the gate electrode 25. This portion functions as a field plate 30, which will be described later.

[0028] On the other hand, in Figure 3, p + An anode electrode (second electrode on the protection element side) 26, with a potential of VAN, is connected to layer 17. This forms element T2 in Figure 1. During normal use, in element T2 as well, VAN is set to a potential close to ground potential, and the drain electrode 21 side, which becomes the cathode electrode, has a high potential VD as described above, so element T2 is in the off state. For this reason, element T2 has little influence on the operation of element T1.

[0029] Furthermore, the anode electrode 26 is connected to a field plate (field plate 30, described later) facing the n-layer 11A via a silicon oxide film thicker than the gate oxide film 24 on its left side.

[0030] In Figure 2, the p layer 13 and n layer on the surface side + The n layer 11 between layers 12 becomes a region where breakdown voltage must be ensured (breakdown voltage ensuring region) because the electric field strength in the depletion layer formed when the device T1 is off increases. Here, in order to ensure breakdown voltage, the p layer 13 and n +Between layers 12, on the surfaces of n layer 11 and n layer 11A, multiple field plates 30 are arranged along the left-right direction in the figure (the direction in which an electric field distribution is generated during use) via a silicon oxide film thicker than the gate oxide film 24. A cross-section is shown in Figure 2, but as will be described later, each field plate 30 is n + The field plates are formed to concentrically surround layer 12 or the drain electrode 21, thereby ensuring that the surface potential of the n layer 11 directly beneath each field plate 30 is uniform. Furthermore, this surface potential is appropriately distributed from the field plate 30 on the highest potential side (left side in the figure) to the field plate 30 on the lowest potential side (right side in the figure) in Figure 2, by capacitive coupling between adjacent field plates 30, so as not to form regions with locally high electric field strength. The function of such field plates 30 is described, for example, in Japanese Patent No. 3275964. In other words, this structure makes it possible to increase the breakdown voltage in the breakdown voltage region.

[0031] In Figure 3, the p layer 16 and n on the surface side + The n-layer 11 between layers 12 also becomes a region where voltage breakdown should be ensured (voltage breakdown region) because the electric field strength in the depletion layer formed in element T2 increases when element T1 is off. Here as well, field plates 30 are arranged in the same way as above, and their function is the same as above. The planar structure of the field plates 30 in Figures 2 and 3 and their electrical connections will be described later.

[0032] In reality, the thick silicon oxide film in the region where the field plate 30 is formed is formed as, for example, a LOCOS oxide film. Therefore, the surface of the semiconductor layer (n layer 11, etc.) in this region is actually located below the surface of the p layer 13 directly beneath the gate electrode 25, and these surfaces are not on the same plane. In Figure 2, the surfaces of the semiconductor layers are simplified to form a single plane. The same applies to the cross-sectional views described later.

[0033] In the top view of Figure 4, among the components shown in Figures 2 and 3, the structure within the semiconductor layer is p-type substrate 10, n-layer 11, n-layer 11A, n + layer 12, p layer 13, p layer 16, n + Only layer 14 and gate electrode 25 are shown. Here, n + Only the circular region of the semiconductor device 1 centered on layer 12 is extracted, and a different semiconductor device may be provided on the p-type substrate 10 outside of it. The p-layer 13 and n-layer constituting the element T1 + Layer 14 and gate electrode 25 are formed only in the lower switching element region R1 in the figure, and the p-layer 16 constituting element T2 is formed only in the upper protection element region R2 in the figure. In this case, the n-layer 11 is formed continuously from the lower half (switching element region R1) to the connection region R3 and upper half (protection element region R2), but the p-layer 13 is formed in the lower half (switching element region R1) and the p-layer 16 is formed in the upper half (protection element region R2) in the figure, with the connection region R3 as the boundary. Here, the n-layer 11A is a circle centered on the n+ layer 12, that is, the n-layer 11A has the same planar shape and size on the switching element region R1 and protection element region R2 sides, but as mentioned above, in reality the n-layer 11A can be set individually on the switching element region R1 side and the protection element region R2 side, and the planar shape of the n-layer 11A does not need to be circular.

[0034] Furthermore, the current flowing through the n-layer 11 in element T1 is shown in Figure 4 as n + While the current flows from layer 12 through the region R1 below it, the current flowing through the n-layer 11 in element T2 is shown in Figure 4 as n + It flows from layer 12 through the upper region R2. Therefore, the VD of the drain (D) of element T1 and the cathode (CA) of element T2 in Figure 1 are common to n + By applying a voltage to layer 12, elements T1 and T2 can be operated independently, thereby realizing the circuit shown in Figure 1. In this case, the center of the circle in Figure 4 is the high-potential side, and the outer circumference of the circle is the low-potential side.

[0035] Here, when a surge voltage is mixed into VD and becomes excessive when off, in order to protect element T1 by element T2 in FIG. 1, it is necessary to cause breakdown in element T2 before breakdown occurs in the n layer 11 in element T1. For this purpose, in FIGS. 2 and 4, the shortest distance between the n layer 12 and the p layer 13 on the element T1 side is D11, and in FIGS. 3 and 4, the shortest distance between the n layer 12 and the p layer 16 on the element T2 side is D21. It is effective to set D11 > D21. + Or, in FIGS. 2 and 4, the shortest distance between the n layer 11A and the p layer 13 on the element T1 side is D12, and in FIGS. 3 and 4, the shortest distance between the n layer 11A and the p layer 16 on the element T2 side is D22. When D11 ≈ D21, it is effective to set D12 < D (END) + 22. Also, when D11 - D12 ≈ D21 - D22, it is effective to set D12 > D22. Alternatively, by making the impurity concentration of the n layer 11A in FIG. 2 (switching element region) lower than that of the n layer 11A in FIG. 3 (protection element region), element T2 can similarly be made to break down at a lower voltage than element T1. That is, by these settings, the breakdown voltages of elements T1 and T2 can be finely adjusted. Also, in FIG. 3, for example, when D21 is fixed, increasing D21 - D22 increases the breakdown voltage of element T2, and decreasing it decreases the breakdown voltage. Fixing D21 - D (END)

[0036] 22 and decreasing D22 (extending the p layer 16 to the left in FIG. 3) decreases the breakdown voltage. Also, increasing the impurity concentration of the n layer 11A decreases the breakdown voltage of element T2. Thus, the breakdown voltage of element T2 can be adjusted as appropriate.

[0037] The above distance settings (D11, etc.) can be adjusted accordingly if there is a depth (distance from the surface) in elements T1 and T2 that is particularly prone to breakdown. In particular, depending on the formation method of p layers 13 and 16 (combination of impurity diffusion and ion implantation), the depth profile of p layers 13 and 16 may not be a simple shape as shown in Figures 2 and 3, and in such cases, this situation occurs. Figure 5 is a cross-sectional view of the structure in which elements T1 and T2 are combined when the depth profile of p layers 13 and 16 differs from that in Figures 2 and 3. In Figure 5, n + Layer 12 is located in the center, with the right half corresponding to the cross-section of the switching element region R1 in Figure 2, and the left half corresponding to the cross-section of the protection element region R2 in Figure 3, and the vertical cross-section passing through the center in Figure 4.

[0038] In this structure, the left p layer 16 is shaped to protrude below the surface towards the n layer 11A. The right p layer 13 has a similar shape (dotted line in p layer 13 in the figure), but a new, shallow p layer is added on the surface side, so that the surface side of this structure is locally towards the center (n + The shape is such that it protrudes from the layer 12 side, and the depth direction profile differs significantly between p layer 16 and p layer 13. Specifically, in the left p layer 16, the internal edge (most n) is greater than the edge point PA on its surface. + The point PB, which is the end portion protruding towards layer 12, is spaced apart horizontally. On the other hand, in the right-hand p layer 13, the point PC, which is the end portion on its surface, and the end portion within it (most n + The horizontal distance between point PD (the end portion protruding towards layer 12) and the other point is smaller than the distance between PA and PB.

[0039] In Figure 4, the spacings D11, D21, D12, and D22 in the planar shape are shown, but in particular, in the case of the structure in Figure 5, it is preferable to set D12 and D22 based on internal points PB and PD rather than on the surface, as shown in the figure. That is, D12 is the shortest distance from point PD in p layer 13 to n layer 11A, and D22 is the shortest distance from point PB in p layer 16 to n layer 11A, and similarly to above, when D11 ≈ D21, D12<D22とすること、D11―D12≒D21―D22であるときに、D12> Using D22, etc., is effective.

[0040] Furthermore, Figure 6 shows a diagram corresponding to Figure 5 when the structure of the n layer (first semiconductor region) is different from that of Figures 2 and 3. In this case, the n layer (first semiconductor region) 81 is n + Formed on the layer 12 side, with a lower impurity concentration than the n layer 81 on the p layer 13 and 16 side - Layers 81A and 81B are formed, respectively. Also, in this case, n - Since layer 81A is formed to the outside of p layers 13 and 16, p layers 13 and 16 do not directly contact the p-type substrate 10. For this reason, VBG and VAN can be set independently in Figure 1. In this case, D11, D21, D15, and D25 can be set as shown in the figure. Here, D15 is n + The shortest distance between layer 12 and the n-layer 81A on the element T1 side, D25 is n + This is the shortest distance between layer 12 and n-layer 81B on the element T2 side.

[0041] In this case, when D11 ≈ D21, by setting D15 > D25, element T2 can be broken down before element T1, similar to the above.

[0042] Next, we will specifically explain the planar structure of the field plate 30 in Figures 2 and 3. Figure 7(a) is a plan view similar to Figure 4, with the planar structure of each field plate 30 added, n +Figure 7(b) is a diagram in which a drain electrode 21 has been added in place of layer 12, and is an enlarged view of only the portion relating to the three innermost field plates 30. As mentioned above, the field plate 30 has the same basic structure as, for example, the one described in Japanese Patent No. 3275964. For this reason, it is constructed by arranging multiple concentric annular field plates 30 around the drain electrode (common electrode) 21, spaced apart from each other in the radial direction.

[0043] As described above, in the voltage-bearing region (the region where multiple field plates 30 are arranged), the potential on the high-potential side (inner side) and the potential on the low-potential side (outer side) are distributed radially by capacitive coupling between adjacent field plates 30. In this case, the innermost field plate 30 is assigned the high-potential side potential (the potential of the drain electrode 21). Therefore, in Figures 2 and 3, the innermost (leftmost) field plate 30 overlaps with the upper part of the interlayer insulating layer 20 of the drain electrode 21 in a plan view and is connected to the drain electrode 21 by via wiring 21A that penetrates the interlayer insulating layer 20. This field plate 30 capacitively couples with the adjacent field plate 20 to its right by being in close proximity horizontally. The same applies to all the field plates 30 further to the right (low-potential side).

[0044] However, even if via wiring 21A is not provided and the drain electrode 21 and the innermost field plate 30 are insulated by the interlayer insulating layer 20, or if they are capacitively coupled to each other in the same way as between the field plates 30, the potential of the innermost field plate 30 can be determined in the same way. In Figures 2, 3, and 7, the drain electrode 21 and the innermost field plate 30 overlap in a plan view, but in this case, they do not need to overlap in a plan view. For example, the innermost field plate 30 may be formed outside the drain electrode 21, close to it so as to be capacitively coupled. In other words, the positional relationship and connection between the innermost field plate and the drain electrode can be appropriately set depending on the configuration of the electrodes and field plates. Note that in both Figure 2 (switching element region R1) and Figure 3 (protection element region R2), the leftmost field plate 30 and the drain electrode 21 are connected, but it is clear that this connection may be made in only one of the switching region R1 or element region R2.

[0045] As shown in Figure 7(b), the field plates 30, excluding the three outer (low-potential) ones, are concentric and annular, continuously formed across the switching element region R1, the protection element region R2, and the connection region R3 between them.

[0046] The potential applied to the outermost (low potential) field plate 30 can be the same as on the high potential side, as shown in Figure 3. Here, the outermost (right) field plate 30 is connected to the cathode electrode 26, which overlaps in a plan view, via via wiring 26A. On the other hand, in Figure 2, the gate electrode 25 is extended to the high potential side (left side) and faces the n layer 11 via an oxide film thicker than the gate oxide film 24, and this portion is essentially the field plate 30. These structures can also be set as appropriate, similar to the high potential side.

[0047] However, in Figure 2 (switching element region R1), the potential of the rightmost field plate 30 is VG, and in Figure 3 (protection element region R2), the potential of the rightmost field plate 30 is VAN. Although both are low potentials, generally VG ≠ VAN. For this reason, the three outer field plates 30 in Figure 7(a) are formed as field plate 30A in the switching element region R1 and as field plate 30B in the protection element region R2. As a result, in the switching element region R1, VD and VG are appropriately distributed radially using field plate 30A and the field plate 30 inside it to adjust the surface potential of the n layer 11, and in the protection element region R2, VD and VAN are appropriately distributed radially using field plate 30B and the field plate 30 inside it to adjust the surface potential of the n layer 11. In the connection region R3, field plate 30A and field plate 30B are separated, so the effect of the circumferential potential difference in this area is also small. The divided field plates 30 are located on the outermost periphery, but their number does not necessarily have to be three. Also, although the field plates 30 are not placed on the connection region R3 in Figure 7, they may also be placed on the connection region R3.

[0048] With the above configuration, the field plate 30 can be made to function in the same way as, for example, the one described in Japanese Patent No. 3275964, thereby increasing the withstand voltage in the withstand voltage region of the semiconductor device 1.

[0049] In Figure 4, p-layer 13 and p-layer 16 are completely separated. That is, they are separated radially from the inner side (high potential side) to the radially outer side (low potential side) in the connection region R3. However, the operation of elements T1 and T2 mainly takes place radially inside p-layer 13 and p-layer 16 in Figure 4. For this reason, p-layer 13 and p-layer 16 may be separated only radially inside (common contact region side), or they may be connected radially outside.

[0050] A modified version of the semiconductor device 1 described above will now be explained. Figure 8 is a circuit diagram corresponding to Figure 1, showing the configuration of this semiconductor device 2. In this semiconductor device 2, instead of the diode element T2, an npn transistor (bipolar transistor) element T3 is used as a protection element. Here, the collector (C: first electrode on the protection element side) of element T3 is shared with the drain (D) of element T1 instead of the cathode (CA) (potential VD), and the potential of the emitter (E: second electrode on the protection element side) is set to VISO instead of the anode (AN). VISO can be the potential of the outer periphery of the element, for example, as will be described later. However, since the p-type layer that forms the base (B) and the n-type layer that forms the emitter (E) are actually short-circuited by wiring, element T3 actually operates with two terminals. In semiconductor device 2, element T3 is normally in the off state, but when a large external noise such as a surge is introduced into VD, element T3 turns on, and the application of the surge to element T1 can be suppressed. This operation is similar to the breakdown in parasitic transistor operation. The characteristics of element T3, such as the on-voltage, will be described later. + The spacing between layer 18 and n-layer 11, the impurity concentration in p-layer 16 and n-layer 11, and VISO can be finely adjusted.

[0051] Figure 9 is a cross-sectional view of the element T3 side in this case, and corresponds to Figure 3. In this case as well, p layer 16, p + Similarly, layer 17 is formed. Here, p layer 16 functions as the base (B) layer of device T3, and p + Layer 17 is the contact layer. Here, in the p layer 16, the potential is set to n + A layer (fifth semiconductor region) 18 is formed, and this n + The emitter electrode 27 connected to layer 18 is p + By connecting to layer 17, the circuit configuration shown in Figure 8 is realized.

[0052] In order to protect element T1 with element T3, it is preferable to set element T3 to turn on before element T1 or the circuit connected to it is destroyed. Such characteristics, such as the on-voltage, can be adjusted by setting the impurity concentration of the p-layer 16. In this case, setting the distance between the n-layer 11 and the p-layers 13 and 16 (D11, D21), and the distance between the n-layer 11A and the p-layers 13 and 16 (D12, D22) is effective, as in the case of semiconductor device 1 described above, in order to maintain a high breakdown voltage while making breakdown in the n-layer 11 more likely to occur on the element T3 side than on the element T1 side. In this case, it is clear that the n-layer 11 may have the same shape as shown in Figures 5 and 6.

[0053] Figure 10 shows two different planar shapes of the semiconductor device 1 having the circuit configuration shown in Figure 1, when the positional relationship between the p-layer 13 and the p-type substrate 10 is changed. Figure 10(a) is the same as Figure 4, where both the p-layer 13 (potential VBG) and the p-layer 16 (potential VAN) are connected to the p-type substrate 10 (VBG=VAN). In Figure 10(b), the p-layer 16 (VAN) is connected to the p-type substrate 10, while the n-layer 11 can be interposed between the p-layer 13 (VBG) and the p-type substrate 10, allowing them to be separated.

[0054] Figure 11 shows the planar shape of the semiconductor device 2 having the circuit configuration shown in Figure 8, when the positional relationship between the p-layer 13 and the p-type substrate 10 is changed. In Figure 11(a), both the p-layer 13 (potential VBG) and the p-layer 16 (potential VISO) are connected to the p-type substrate 10 (VBG = VISO). In Figure 11(b), the p-layer 16 (potential VISO) is connected to the p-type substrate 10, while the p-layer 13 (potential VBG) and the p-type substrate 10 can be separated, similar to Figure 10(b). In Figure 11(c), the p-layer 13 (potential VBG) is connected to the p-type substrate 10, while the p-layer 16 (potential VISO) can be separated from the p-type substrate 10. In Figure 11(d), both the p-layer 13 (VBG) and the p-layer 16 (VISO) can be separated from the p-type substrate 10.

[0055] In Figures 10 and 11, except for Figures 10(a) and 11(a), the potential difference between p-layer 13 and p-layer 16 (the difference between VBG and VISO) varies depending on the setting, so a breakdown voltage between p-layer 13 and p-layer 16 is required. Figure 12 is a plan view illustrating the structure of Figure 11(d) from this perspective. Here, the distance between the p-type substrate 10 and p-layer 13 is denoted as DA, the distance between the p-type substrate 10 and p-layer 16 is denoted as DB, and the distance between p-layer 13 and p-layer 16 is denoted as DC. Here, during the operation of this semiconductor device, there are cases where the potential of the p-type substrate 10 is, for example, GND, and the potential of p-layer 13 VBG and the potential of p-layer 16 VISO are not limited to either positive or negative, so it is preferable that the distance DC between p-layer 13 and p-layer 16 be set such that distance DC ≥ distance DA and distance DC ≥ distance DB. Such requirements can also be applied to the semiconductor device 1 (Figure 10) in Figure 1.

[0056] In order to increase the breakdown voltage related to the switching element region R1 and the protection element region R2, and to achieve both the breakdown or turn-on on the element T2 and T3 side within the protection element region R2 being earlier than on the element T1 side within the switching element region R1, it is preferable to have a planar structure as shown in Figure 13. In Figure 13, this semiconductor device 2 is racetrack shaped (a shape in which semicircular parts are spaced apart vertically and connected by a straight line). Here, a structure corresponding to Figure 11(a) is shown. In this structure, the connection region R3 sandwiched between the switching element region R1 and the protection element region R2 is made longer than that of the semiconductor device 2 in Figure 11(a), so that the switching element region R1 and the protection element region R2 are spaced further apart. In this case, the p layer 13 and n + The distance D11 between layers 12 is between p layer 16 and n + It is easy to make the distance between layers 12 greater than D21. A similar structure can also be applied to semiconductor device 1 (Figure 10).

[0057] The above describes various planar structures that each component of semiconductor devices 1 and 2 can have. In contrast, semiconductor device 3, which is a second modified example described below, has a new structure added, particularly on its surface. This semiconductor device 3 will be described below.

[0058] In region F in Figure 7 (the portion sandwiched between p-layer 13 and p-layer 16, corresponding to the connection region R3 where p-layer 13 and p-layer 16 are in close proximity and facing each other), when the semiconductor device 3 is off, the depletion layer spreads from the interface between p-layer 13 and n-layer 11, and from the interface between p-layer 16 and n-layer 11. When the depletion layers spreading from both sides come into contact, electrical conductivity is established between p-layer 13 and p-layer 16 (punch-through). For this reason, widening the gap between p-layer 13 and p-layer 16 (length of connection region R3), as shown in the structure of Figure 13, is effective, but the size of the semiconductor device increases.

[0059] To suppress the occurrence of such punch-through, it is preferable to provide an inter-element field plate 40 extending circumferentially between the p-layer 13 and the p-layer 16 in region F of Figure 7. Figure 14 is a plan view showing the structure of such a semiconductor device 3, and here only the portion corresponding to region F and its surroundings in Figure 7 is shown.

[0060] Figure 14 shows the p-type substrate 10, the field plate 30, p-layer 13, p-layer 16, and inter-element field plate 40 in Figure 7. Figure 15 shows a cross-section in the HH direction in Figure 14. In Figure 15, the inter-element field plate 40, similar to the field plate 30, faces the n-layer 11 between p-layer 13 and p-layer 16 via an interlayer insulating layer 20 made of a thick silicon oxide film.

[0061] As shown in Figure 14, the inter-element field plate 40 is formed by extending one end to overlap with the p-layer 13 in a plan view and extending the other end to overlap with the p-layer 16. The inter-element field plate 40 is then connected to either the p-layer 13 (potential VBG) or the p-layer 16 (potential VISO). As a result, the depletion layer elongation is suppressed in the n-layer 11 between the p-layer 13 and p-layer 16 directly beneath the inter-element field plate 40, thereby suppressing punch-through.

[0062] Alternatively, the inter-element field plate 40 may be connected to the gate electrode 25 (potential VG). In this case, the circumferential end of the gate electrode 25 in Figure 4, etc., may be extended in the circumferential direction and connected to the inter-element field plate 40.

[0063] Furthermore, as shown in Figure 7, the outer field plate 30 is divided into a field plate 30A in the switching element region R1 and a field plate 30B in the protection element region R2. However, if an inter-element field plate 40 is provided, as shown in Figure 14, a field plate 30C separated from the field plates 30A and 30B may be provided on the same circumference between the field plates 30A and 30B. The field plate 30C may be capacitively coupled to the radially inner field plate 30 and the radially outer inter-element field plate 40, respectively.

[0064] The planar shape of the inter-element field plate 40 can be set as appropriate, as long as it includes at least the shape of the inter-element field plate 40 shown in Figure 14 and does not affect other electrodes (wirings), etc.

[0065] Figure 16 shows the overall planar shape of an example where the inter-element field plate 40 is connected to the p-layer 13 side as described above. A field plate is also formed on the p-layer 13 in the circumferential direction connecting the inter-element field plate 40. In this case, the electrical connection between the inter-element field plate 40 and the p-layer 13 can be made on the p-layer 13.

[0066] Figure 17 shows the overall planar shape of an example where the inter-element field plate 40 is integrated with the gate electrode 35, which is similarly provided along the circumferential direction, as described above. In this case, if the silicon oxide film directly beneath the portion that becomes the inter-element field plate 40 is formed as a LOCOS oxide film and is thicker than the gate oxide film 24, this structure can be obtained simply by changing the pattern of the gate electrode 25. Note that the field plate 30 is not shown in Figures 16 and 17.

[0067] In the semiconductor device described above, the portions constituting the switching element region R1 and the protection element region R2 were shaped to follow an arc. However, these do not necessarily have to follow an arc shape; they only need to follow the circumferential direction of the center (common contact region). Furthermore, in the example above, the angle of the switching element region and the angle of the protection element region (circumferential spread) viewed from the center were assumed to be the same, but these do not need to be the same.

[0068] Furthermore, in the above example, multiple field plates 30 were used in the voltage-bearing region. However, if voltage can be ensured without using such field plates, it is not necessary to provide field plates in the voltage-bearing region. In this case, the structure of the semiconductor device becomes simpler and less expensive. Alternatively, instead of multiple field plates 30 in the voltage-bearing region, well-known resistive field plates or shallow trench isolation may be used. The same applies to the inter-element field plates 40.

[0069] Furthermore, instead of an npn transistor, an n-channel MOSFET (LDMOS) similar to element T1 can be used as a protection element. Figure 18 shows the configuration of a semiconductor device 4 that is such a modified example (third modified example). The element (protection element) T4 used here is a MOSFET similar to element T1, and as shown in the figure, its source (S), gate (G), and back gate (BG) are connected. For example, if the interlayer insulating layer 20 directly beneath the rightmost field plate 30 in the figure, which is connected to the emitter electrode 27 in Figure 9, is made into a thinner gate oxide film 24 (Figure 2), then this field plate 30 becomes the gate (G) of element T4 in Figure 18, and this is p + Layer 17, n + This configuration can be easily realized by connecting layer 18 and emitter electrode 27. In other structures, the protective element T4 can be similarly realized by modifying the structure near the field plate.

[0070] Furthermore, in the planar views, including Figure 4, the portion that becomes element T1 and the portion that becomes element T2 (~T4) are both semicircular (the angle from the center of the arc shape they occupy is 180°) and have the same area. However, these areas do not need to be the same, and their areas can be set appropriately according to the required element characteristics. For example, the area of ​​element T1 may be larger than the area of ​​element T2 (~T4). In this case, the areas can be changed in this way by, for example, changing the angle on the element T1 side and the element T2 side. Also, in Figure 4, etc., one portion that becomes element T1 and one portion that becomes element T2 are combined on a single chip. However, if the angle in the portion that becomes element T1 and the portion that becomes element T2 in these planar structures is smaller than 180°, multiple combinations of these can be provided in the circumferential direction. In this case, the portion that becomes element T1 and the portion that becomes element T2 can be arranged alternately in the circumferential direction.

[0071] Furthermore, other layers can be added or removed as appropriate in the semiconductor layer. It is also clear that the same configuration can be applied even when all the p-type and n-type elements in the semiconductor are reversed in the above example. [Explanation of Symbols]

[0072] 1-4 Semiconductor Equipment 10 p-type substrate (semiconductor substrate) 11 n-layer (first semiconductor region) 11A n-layer (embedded n-type layer: embedded semiconductor region) 12 n + Layer (common contact area) 13. p-layer (second semiconductor region) 14 n + Layer (Third Semiconductor Region) Pages 15 and 17 + layer 16 p-layer (fourth semiconductor region) 18 n + Layer (5th semiconductor region) 20 interlayer insulating layer 21 Drain electrodes (common electrode, first main electrode, first electrode on the protection element side) 21A, 26A via wiring 22 Source electrode (second main electrode) 23. Back gate electrode (second control electrode) 24 Gate oxide film 25, 35 Electrode gate (first control electrode) 26 Anode electrode (second electrode on the protection element side) 27. Emitter electrode (second electrode on the protection element side) 30, 30A, 30B, 30C Field Plate 40-element field plate 81 n-layer (first semiconductor region) 81A, 81B n - layer AN Anode (Second electrode on the protection element side) B Bass BG Back gate (second control electrode) C Collector (Protection element side first electrode) CA cathode (first electrode on the protection element side) D drain (first main electrode: high-potential side electrode) E emitter (second electrode on the protection element side) G gate (first control electrode) R1 Switching element region R2 protection element area R3 Connection Area S Source (Second main electrode: Low-potential side electrode) T1 element (switching element) T2, T3, T4 elements (protection elements)

Claims

1. A semiconductor device is formed on a semiconductor substrate, comprising: a switching element whose on / off state is controlled by the potential of a control electrode between a first main electrode on the high-potential side and a second main electrode on the low-potential side; and a protection element that, when the switching element is off, bypasses the current between a first electrode on the high-potential side and a second electrode on the low-potential side of the protection element. A first semiconductor region of a second conductivity type, which is the opposite of the first conductivity type, is formed on the surface side of the semiconductor substrate of a first conductivity type, The first main electrode and the common electrode which also serves as the first electrode on the protection element side, A common contact region of the second conductivity type is formed locally on the first semiconductor region with a high impurity concentration and connected to the common electrode, It is equipped with, In a plan view, one circumferential region and another region centered on the common contact area are defined as the switching element region where the switching element is formed and the protective element region where the protective element is formed, respectively. In the switching element region, In a plan view, a second semiconductor region of the first conductivity type is locally formed at a location radially separated from the common contact region within the first semiconductor region, In a plan view, the third semiconductor region of the second conductivity type is locally formed within the second semiconductor region, A system was established, The second main electrode is connected to the third semiconductor region. In the aforementioned protective element region, In a plan view, a fourth semiconductor region of the first conductivity type is provided, which is locally formed at a location radially separated from the common contact region within the first semiconductor region. The second electrode on the protection element side is connected to the fourth semiconductor region. The semiconductor device is characterized in that the first semiconductor region is integrated with the switching element region and the protection element region, and in a plan view, the end of the second semiconductor region on the common contact region side and the end of the fourth semiconductor region on the common contact region side are spaced apart.

2. The semiconductor device according to claim 1, characterized in that the shortest distance between the common contact region and the fourth semiconductor region in the protection element region is set to be shorter than the shortest distance between the common contact region and the second semiconductor region in the switching element region.

3. The semiconductor substrate comprises a second conductive embedded semiconductor region formed deeper than the first semiconductor region on the common contact region side and connected to the first semiconductor region. The semiconductor device according to claim 1, characterized in that the shortest distance from the common contact region to the second semiconductor region is equal to the shortest distance from the common contact region to the fourth semiconductor region, and the shortest distance between the embedded semiconductor region and the second semiconductor region in the switching element region is set to be shorter than the shortest distance between the embedded semiconductor region and the fourth semiconductor region in the protection element region.

4. The semiconductor device according to claim 1 or 2, characterized in that a plurality of field plates, made of a conductor and facing the surface of the first semiconductor region via an insulating layer, are formed so as to surround the common electrode in a plan view, so as to capacitively couple with each other between the common electrode and the control electrode, and between the common electrode and the second electrode on the protection element side.

5. The fourth semiconductor region comprises a fifth semiconductor region of the second conductivity type formed locally within the fourth semiconductor region, The semiconductor device according to claim 1 or 2, characterized in that the second electrode on the protection element side is connected to the fifth semiconductor region.

6. The semiconductor device according to claim 5, characterized in that the shortest distance between the common contact region and the second semiconductor region in the switching element region is set to be equal to the shortest distance between the common contact region and the fourth semiconductor region in the protection element region.

7. The semiconductor device according to claim 1 or 2, characterized in that one of the second semiconductor region and the fourth semiconductor region is formed inside the first semiconductor region in a plan view.

8. The semiconductor device according to claim 1 or 2, characterized in that one of the second semiconductor region and the fourth semiconductor region in a plan view is connected to the semiconductor substrate on the radially outer side.

9. The second semiconductor region is formed inside the first semiconductor region in a plan view. The semiconductor device according to claim 7, characterized in that the distance between the outermost radial edge of the semiconductor substrate other than the portion in which the first semiconductor region is formed, which is not in direct contact with the semiconductor substrate, and the outermost radial edge of the first semiconductor region is less than or equal to the distance between the second semiconductor region and the fourth semiconductor region in the circumferential direction.

10. The semiconductor device according to claim 1 or 2, characterized in that, in a plan view, an inter-element field plate made of a conductor is formed on the surface of the first semiconductor region between the second semiconductor region and the fourth semiconductor region, where the second semiconductor region and the fourth semiconductor region are locally separated in the circumferential direction, via an insulating layer.

11. The semiconductor device according to claim 10, characterized in that the inter-element field plate is connected to the second semiconductor region, the fourth semiconductor region, or the control electrode with a conductive material.

Images