Transmitting circuit and communication device equipped therewith

Abstract

This reduces the gain fluctuation of the power amplification circuit included in the transmission circuit. [Solution] The transmitting circuit 100 includes an input terminal T1, an output terminal T2, a power amplifier circuit 105 that amplifies the high-frequency signal received at the input terminal T1, a balun 150, a power supply circuit 160, and an impedance adjustment circuit 170. The balun 150 includes an unbalanced line 153 whose first end is connected to the output terminal, and balanced lines 151 and 152 connected to the power amplifier circuit 105, and transmits the high-frequency signal amplified by the power amplifier circuit 105 to the output terminal T2. The power supply circuit 160 selects discrete power supply voltages according to the power of the high-frequency signal and supplies them to the power amplifier circuit 105. The impedance adjustment circuit 170 is connected to the second end of the unbalanced line 153 and changes the load impedance according to the power supply voltage supplied to the power amplifier circuit 105.

Description

[Technical Field]

[0001] This disclosure relates to a transmitting circuit and a communication device equipped therewith, and more specifically, to a technique for suppressing gain fluctuations in a power amplification circuit included in the transmitting circuit. [Background technology]

[0002] Japanese Patent Publication No. 2022-183043 (Patent Document 1) discloses a power amplifier that can adjust the impedance at the output by analogously changing the load impedance coupled to the output of the power amplifier in response to an envelope signal that changes in relation to the envelope of a radio frequency signal. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-183043 [Overview of the project] [Problems that the invention aims to solve]

[0004] Generally, power amplifier circuits require improved efficiency for input signals with wide modulation bandwidths. In particular, in recent years, development of communication systems using the sub-terahertz frequency band has progressed for the purpose of high-capacity and high-speed communication. In such systems, signal path losses tend to be greater compared to millimeter-wave and lower frequency bands, and the effects of reduced amplifier efficiency tend to be more pronounced.

[0005] In high-frequency bands such as subterahertz, the power (output) fluctuation period of the high-frequency signal to be output is extremely short, making it extremely difficult to analogously track the power supply voltage supplied to the power amplifier according to the envelope of the high-frequency signal. Therefore, in power amplifiers that amplify high-frequency signals in such high-frequency bands, a digital envelope tracker (digital ET) that switches between multiple power supply voltages is commonly used.

[0006] However, when using digital ET, the power supply voltage is switched discretely, which can cause the power amplifier gain to change significantly at the voltage switching timing, potentially leading to noise generation.

[0007] One method to reduce gain fluctuations during power supply voltage switching is to finely switch the power supply voltage. However, finely adjusting the power supply voltage level requires increasing the number of DC / DC converters used to set the voltage level. This necessitates a larger circuit area, resulting in a larger device size and potentially hindering miniaturization.

[0008] Alternatively, one could consider increasing the voltage level by changing the combination of outputs of multiple DC / DC converters without increasing the number of DC / DC converters. However, in that case, a switching circuit would be required to change the combination, which would increase losses in the switching circuit and potentially lead to a decrease in the efficiency of the power amplification circuit.

[0009] This disclosure is made to solve these problems, and its purpose is to reduce gain fluctuations in the power amplifier circuit included in the transmitting circuit. [Means for solving the problem]

[0010] The transmitting circuit according to this disclosure comprises an input terminal, an output terminal, an amplification circuit for amplifying the high-frequency signal received at the input terminal, a first balun, a power supply circuit, and an impedance adjustment circuit. The first balun includes an unbalanced line whose first end is connected to the output terminal, as well as a first balanced line and a second balanced line connected to the amplification circuit, and transmits the high-frequency signal amplified by the amplification circuit to the output terminal. The power supply circuit selects a discrete power supply voltage according to the power of the high-frequency signal and supplies it to the amplification circuit. The impedance adjustment circuit is connected to the second end of the unbalanced line of the first balun and changes the load impedance according to the power supply voltage supplied to the amplification circuit. [Effects of the Invention]

[0011] The transmitting circuit according to this disclosure is a transmitting circuit using a so-called digital ET, and an impedance adjustment circuit is provided in the unbalanced line of the balun connected to the output terminal. By changing the load impedance, the efficiency of the amplification circuit can be adjusted, and by selecting a load impedance that matches the supplied power supply voltage, the decrease in the gain of the amplification circuit can be suppressed. Therefore, the gain fluctuation of the power amplification circuit included in the transmitting circuit can be reduced. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram of a communication device to which the transmission circuit according to the embodiment is applied. [Figure 2] This figure shows the detailed configuration of the impedance adjustment circuit in Figure 1. [Figure 3] This figure shows the detailed structure of the balance. [Figure 4] This diagram illustrates the output gain resulting from differences in envelope tracking modes. [Figure 5] This diagram illustrates the change in balanced transmission line impedance when the frequency of the input high-frequency signal is varied, given a load impedance of 50Ω. [Figure 6] This figure illustrates the change in the pass-through characteristics (insertion loss) in the case of Figure 5. [Figure 7] It is a partial enlarged view of FIG. 6. [Figure 8] It is a diagram for explaining the change in the output impedance of the power amplifier circuit when the load impedance is changed. [Figure 9] It is a diagram for explaining the change in gain when the load impedance is changed. [Figure 10] It is a diagram for explaining the change in gain in the case of Modification 1 in which the power supply voltage level is changed. [Figure 11] It is a diagram showing the device arrangement in the communication device of the embodiment. [Figure 12] It is a diagram showing the device arrangement in the communication device of Modification 2.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and their description will not be repeated.

[0014] [Configuration of Communication Device] FIG. 1 is a schematic configuration diagram of a communication device 10 to which a transmission circuit 100 according to Embodiment 1 is applied. The communication device 10 is, for example, a mobile terminal such as a mobile phone, a smartphone or a tablet, or a personal computer having a communication function.

[0015] Referring to Figure 1, the communication device 10 comprises an antenna ANT, a transmitting circuit 100, a baseband signal processing circuit consisting of a BBIC (Baseband Integrated Circuit) 20 and an RFIC (Radio Frequency Integrated Circuit) 30. The transmitting circuit 100 includes an input terminal T1, an output terminal T2, a power amplification circuit 105, baluns 110 and 150, a power supply circuit 160, and an impedance adjustment circuit 170. The communication device 10 generally upconverts the intermediate frequency (IF) signal transmitted from the BBIC 20 to a high frequency (radio frequency RF) signal using the RFIC 30, amplifies the high frequency signal using the power amplification circuit 105, and radiates it from the antenna ANT.

[0016] RFIC30 is an example of a signal processing circuit that processes high-frequency signals. RFIC30 upconverts the intermediate frequency signal transmitted from BBIC20 into a high-frequency signal and outputs the generated high-frequency signal to the transmission circuit 100 via input terminal T1.

[0017] The power supply circuit 160 is an example of a so-called digital envelope tracker and can supply power supply voltages Vdd of multiple different voltage levels to the power amplifier circuit 105. The power supply circuit 160 includes a multilevel power converter (MPC) 161, a power supply selection circuit 162, and a digital ET 163.

[0018] The MPC161, although not shown in Figure 1, includes multiple DC / DC converters. The MPC161 converts the battery voltage VB supplied from an external battery into several different voltage levels and supplies them to the power selection circuit 162.

[0019] The digital ET163 receives the I and Q waveform signals of the transmitted signal from the BBIC20 and tracks the envelope of the transmitted signal using the digital ET mode. The digital ET163 generates a selection signal SEL corresponding to the voltage level of the envelope of the transmitted signal and outputs it to the power supply selection circuit 162.

[0020] The power supply selection circuit 162 selects a voltage corresponding to the selection signal SEL from multiple voltage levels supplied from the MPC 161 and generates a power supply voltage Vdd to be supplied to the power amplifier circuit 105. The generated power supply voltage Vdd is supplied to the power amplifier circuit 105. The power supply selection circuit 162 also functions as a circuit for controlling the impedance adjustment circuit 170. The power supply selection circuit 162 generates a control signal CNT corresponding to the selected voltage level and outputs it to the impedance adjustment circuit 170.

[0021] Each of the baluns 110 and 150 is a conversion element for converting between a pair of balanced and unbalanced transmission lines. In this embodiment, since the target is high-frequency signals in the sub-terahertz frequency band, merchant baluns are used as baluns 110 and 150.

[0022] While magnetic coupling transformers (MCTs) can be used in addition to baluns for converting between balanced and unbalanced transmission lines, in the sub-terahertz frequency band, miniaturization can increase magnetic coupling, potentially leading to increased losses and reduced bandwidth. Therefore, when dealing with high-frequency signals in the sub-terahertz frequency band, using a balun rather than an MCT can suppress the increase in losses.

[0023] Balun 110 is an input balun that converts the input signal Pin, which is input to an unbalanced line, into a pair of balanced lines. Power amplifier circuit 105 amplifies the high-frequency signal converted by balun 110 and outputs it to output balun 150. Balun 150 generates an output signal Pout by combining the high-frequency signals transmitted from power amplifier circuit 105 by converting the pair of balanced lines into an unbalanced line. The generated output signal Pout is radiated from antenna ANT via output terminal T2.

[0024] More specifically, the balun 110 includes lines 111 and 112 corresponding to a pair of balanced lines, and line 113 corresponding to an unbalanced line. If the wavelength of the center frequency of the high-frequency signal to be transmitted by the transmitting circuit 100 is λ, then lines 111 and 112 have a line length of 1 / 4 wavelength (λ / 4), and line 113 has a line length of 1 / 2 wavelength (λ / 2).

[0025] One end of the line 113 is connected to the input terminal T1, and the other end is an open end. The line 113 has a configuration in which a first part 1131 that connects to line 111 and a second part 1132 that connects to line 112 are connected in series. Each of the first part 1131 and the second part 1132 has a line length of λ / 4.

[0026] One end of the first section 1131 is open, and the other end is connected to one end of the second section 1132. The other end of the second section 1132 is connected to input terminal T1. The coupling of the first section 1131 and line 111 and the coupling of the second section 1132 and line 112 are in opposite phases. That is, the input signal Pin input to input terminal T1 is transmitted to line 111 and line 112 as signals in opposite phases.

[0027] One end of line 111 is connected to amplifier 120A in power amplification circuit 105, and the other end is connected to ground potential. Similarly, one end of line 112 is connected to amplifier 120B in power amplification circuit 105, and the other end is connected to ground potential.

[0028] The power amplification circuit 105 further includes amplifiers 140A and 140B, and matching networks (MN) 130A and 130B, in addition to amplifiers 120A and 120B. Amplifiers 140A and 140B are the main amplifiers in the power amplification circuit 105, while amplifiers 120A and 120B are drive amplifiers for driving amplifiers 140A and 140B, respectively.

[0029] Amplifier 120A is connected to amplifier 140A via matching circuit 130A. Similarly, amplifier 120B is connected to amplifier 140B via matching circuit 130B. The high-frequency signals amplified by amplifiers 120A and 120B are further amplified in amplifiers 140A and 140B and transmitted to balun 150.

[0030] In the power amplification circuit 105 of this embodiment, a two-stage amplifier is provided for each transmission line, but the circuit configuration of the amplifiers for each transmission line is not limited to this. For example, one amplifier may be provided for each transmission line, or a Doherty circuit having a carrier amplifier and a peak amplifier may be provided for each transmission line.

[0031] Matching circuits 130A and 130B are circuits for impedance matching and, although not shown, both include inductors and / or capacitors. Note that if impedance adjustment is not required, matching circuits 130A and 130B may not be provided.

[0032] The balun 150 includes a pair of transmission lines 151 and 152 corresponding to balanced transmission lines, and a transmission line 153 corresponding to an unbalanced transmission line. Transmission lines 151 and 152 have a length of 1 / 4 wavelength (λ / 4), and transmission line 153 has a length of 1 / 2 wavelength (λ / 2).

[0033] One end of line 151 is connected to the output terminal of amplifier 140A, and the other end is connected to ground potential. Similarly, one end of line 152 is connected to the output terminal of amplifier 140B, and the other end is connected to ground potential.

[0034] The track 153 has a configuration in which a first section 1531, which connects to track 151, and a second section 1532, which connects to track 152, are connected in series. Each of the first section 1531 and the second section 1532 has a track length of λ / 4.

[0035] The coupling of the first part 1531 and line 151 and the coupling of the second part 1532 and line 152 are in opposite phases. Since the input balun 110 converts them into high-frequency signals with opposite phases, the high-frequency signals transmitted to lines 151 and 152 are combined in phase at line 153.

[0036] One end of track 153 is connected to output terminal T2. The high-frequency signal synthesized on track 153 is radiated from antenna ANT via output terminal T2 as output signal Pout.

[0037] On the other hand, the other end of the line 153 is connected to an impedance adjustment circuit 170. The impedance adjustment circuit 170 is a circuit for adjusting the load impedance. The impedance adjustment circuit 170 is controlled by a control signal CNT from the power supply selection circuit 162, and the load impedance is changed according to the power supply voltage Vdd supplied to the power amplifier circuit 105.

[0038] [Configuration of Impedance Adjustment Circuit] Figure 2 shows the detailed configuration of the impedance adjustment circuit 170 in Figure 1. In this embodiment, the impedance adjustment circuit 170 is a variable resistor circuit that can adjust the load resistance and includes resistors R1 to R3 and switches TR1 to TR3.

[0039] Resistors R1 to R3 are connected in parallel between the other end of the line 153 of the balun 150 in Figure 1 and the ground potential. A switch TR1 is connected in series with resistor R1, a switch TR2 is connected in series with resistor R2, and a switch TR3 is connected in series with resistor R3.

[0040] Each of switches TR1 to TR3 is, for example, a semiconductor switch, controlled by a control signal CNT generated by a logic circuit 1621 included in the power selection circuit 162, to switch between conducting and not conducting. The load resistance may be switched by the alternative selection of one of resistors R1 to R3, or, in addition to or instead of this, by changing the combination of resistors R1 to R3.

[0041] The logic circuit 1621 changes the control signal CNT in response to the selection signal SEL generated by the digital ET163. More specifically, as will be described later, when the power supply voltage Vdd decreases, the logic circuit 1621 generates a control signal CNT that increases the resistance (i.e., impedance). Conversely, when the power supply voltage Vdd increases, the logic circuit 1621 generates a control signal CNT that decreases the resistance.

[0042] In Figure 2, a variable resistor circuit was used as an example for the impedance adjustment circuit 170. However, the impedance adjustment circuit 170 may have a different configuration as long as the impedance can be changed. For example, the impedance adjustment circuit 170 may be a variable capacitor whose capacitance value can be changed.

[0043] [Detailed structure of the balance] Figure 3 shows the detailed structure of the balun. In Figure 3, the output balun 150 is used as an example.

[0044] The balun 150 is formed on a dielectric substrate or a semiconductor substrate. In addition to the transmission lines 151 to 153, the balun 150 further includes terminals 155 to 157. The output of amplifier 140A is connected to terminal 155. The output terminal of amplifier 140B is connected to terminal 156. The power supply voltage Vdd is supplied to terminals 155 and 156.

[0045] Terminal 157 essentially corresponds to output terminal T2 in Figure 1. Although not shown in Figure 3, an antenna ANT is connected to terminal 157.

[0046] The balanced transmission lines 151 and 152 are strip-shaped flat plate electrodes with a roughly C-shape, and are arranged symmetrically so that the concave portions of the C-shape face each other. One end of transmission line 151 is positioned opposite terminal 155. Transmission line 151 and terminal 155 are capacitively coupled, and a capacitor C1 is formed between transmission line 151 and terminal 155.

[0047] Multiple vias GV1 are connected to the other end of track 151. Although not shown in Figure 3, vias GV1 are connected to ground potential.

[0048] Similarly, one end of the line 152 is positioned opposite terminal 156. Line 152 and terminal 156 are capacitively coupled, forming a capacitor C2 between them. Multiple vias GV2 are connected to the other end of line 152.

[0049] The unbalanced transmission line 153 is a strip-shaped flat electrode, positioned in the space between transmission lines 151 and 152, wound around the direction normal to the substrate. One end E1 of transmission line 153 is positioned opposite terminal 157. End E1 and terminal 157 are capacitively coupled, forming a capacitor C3 between them. Although not shown in Figure 3, the other end E2 of transmission line 153 is connected to the impedance adjustment circuit 170, as explained in Figure 2.

[0050] In the balun 150 example shown in Figure 3, the track widths of tracks 151 and 152 are wider than the track width of track 153. This allows impedance conversion to be performed in the balun 150.

[0051] Specifically, line 153 is connected to antenna ANT and is therefore set to a characteristic impedance of 50Ω. In contrast, the impedance of lines 151 and 152 is set to 20Ω. Since power amplification circuits 105 for amplifying high-frequency signals are connected to lines 151 and 152, the low impedance reduces transmission loss.

[0052] [Load impedance change process] Next, using Figure 4, we will explain the challenges of using digital ET and the load impedance change process in this embodiment. Figure 4 is a diagram illustrating the output gain due to differences in the envelope tracking mode of the transmitted signal. In Figure 4, the case where analog ET mode is used as the tracking mode is shown in the left column, and the case where digital ET is used is shown in the right column. In addition, in each mode, the temporal change of the power supply voltage is shown in the upper row, and the gain change is shown in the lower row.

[0053] In the upper graph of power supply voltage, the horizontal axis represents time, and the vertical axis represents voltage. The thick solid lines Vdd1 and Vdd2 represent the power supply voltage in each mode, while the thin solid lines WV1 and WV2 represent the output signal Pout, which is the high-frequency signal after modulation.

[0054] In the lower graph showing the gain change, the horizontal axis represents the gain and the vertical axis represents the output power. The thin solid lines, including lines LN11 to LN14, show the gain curve for each power supply voltage Vdd. The thick solid lines LN10 and LN15 show the gain progression in each tracking mode.

[0055] In analog ET mode, the power supply voltage is set to continuously change to follow the envelope of the input signal. The power supply voltage waveform in analog ET mode is an analog waveform, not a digital waveform.

[0056] In analog ET mode, the power supply voltage Vdd1 is always supplied that corresponds to the amplitude fluctuations of the input signal, resulting in the most efficient tracking. In this case, as shown by line LN10, the gain changes smoothly with respect to changes in output power.

[0057] On the other hand, in digital ET mode, multiple discrete voltage levels of the power supply voltage are set within a single frame. The power supply voltage has a digital waveform and forms a square wave. Specifically, in digital ET mode, based on the envelope signal, a voltage level corresponding to the voltage of the input signal in the target section of the frame is selected from among multiple different voltage levels. At this time, the voltage level is selected to track the envelope of the carrier wave modulated based on the transmitted information. More specifically, the voltage level corresponding to the envelope value of each symbol is selected by referring to the range of envelope values ​​associated with each of the multiple different voltage levels.

[0058] In the example shown in Figure 4, the voltage levels are set to those indicated by lines LN11, LN12, LN13, and LN14. In this case, when the input signal changes and the voltage level switches, the gain changes along the gain curve corresponding to that voltage level. Therefore, as shown by line LN15, the gain may change discontinuously at the voltage level switching points.

[0059] From the perspective of minimizing gain fluctuations, the analog ET mode is preferable. However, in analog ET mode, the power supply voltage must be continuously changed, so in the case of high frequency bands such as subterahertz, the power supply voltage may not be able to follow the envelope of the modulated high-frequency signal. Therefore, for high frequency bands such as subterahertz, it is necessary to use the digital ET mode. However, as mentioned above, the gain changes discontinuously and significantly when the voltage level is switched, which can be a source of noise.

[0060] Here, in general amplifiers, it is known that when the load impedance changes for the same input signal, the gain of the output signal fluctuates. More specifically, the gain increases as the load impedance increases.

[0061] For example, for a given power P, when the load impedance is R, the output power is V OUT1 Then, the following equation (1) holds.

[0062] P = (V OUT1 ) 2 / R …(1) For the same power P, when the load impedance is 2R, the output power is V OUT2 Then, the following equation (2) holds.

[0063] P = (V OUT2 ) 2 / 2R …(2) And from equations (1) and (2), the following relationship of equation (3) holds.

[0064] P = (V OUT1 ) 2 / R = (V OUT2 ) 2 / 2R …(3) When equation (3) is transformed, (V OUT2 ) 2 = (√2) 2 × (V OUT1 ) 2 Therefore, the voltage becomes √2 times, and as a result, the gain improves by 3 dB.

[0065] Therefore, in the transmission circuit 100 of the present embodiment, a configuration is adopted in which the impedance adjustment circuit 170 changes the load impedance in response to a change in the power supply voltage Vdd. More specifically, when the power supply voltage Vdd becomes low, the impedance adjustment circuit 170 is controlled so as to increase the load impedance. Thereby, the gain in the region where the voltage of the input signal is relatively low can be increased, and thus the gain fluctuation that occurs during the switching of the power supply voltage can be reduced.

[0066] Next, we will explain the simulation results for the load impedance modification process in this embodiment using Figures 5 to 9.

[0067] Figure 5 illustrates the change in balanced line impedance when the frequency of the input high-frequency signal is varied from 40 GHz to 300 GHz, given that the load impedance is the characteristic impedance of 50 Ω (line LN30). Figure (b) on the right is an enlarged view of the area around region AR1 in the Smith chart of Figure (a) on the left, showing the portion where the absolute value of the reflection coefficient Γ is less than 0.05.

[0068] In the example in Figure 5, the frequency band to be transmitted is 120 GHz to 140 GHz, and each parameter is set so that |Γ| < 0.05 within this range. Note that P1 is the impedance at 140 GHz, P2 is the impedance at 130 GHz, and P3 is the impedance at 120 GHz.

[0069] Figures 6 and 7 show the pass-through characteristics (insertion loss) in the state shown in Figure 5 (line LN31). Figure 7 is an enlarged view of Figure 6 near the frequency band BW1 (120GHz to 140GHz). As shown in Figures 6 and 7, the insertion loss is 0.5 to 0.6 dB across the entire frequency band BW1.

[0070] This state is considered the reference state when the power supply voltage Vdd is at its maximum. Figure 8 shows the change in the output impedance of the power amplifier circuit 105 (i.e., the balanced line impedance of the balun 150) when the power supply voltage Vdd is decreased while the load impedance is increased accordingly. In Figure 8, the left column is the Smith chart for the reference load impedance of 50Ω (line LN35). The power supply voltage Vdd at this time is defined as High.

[0071] The middle column shows the Smith chart when the power supply voltage Vdd is slightly reduced (Vdd = Mid) (line LN36), with the load impedance set to 200Ω. The right column shows the Smith chart when the power supply voltage Vdd is further reduced (Vdd = Low) (line LN37), with the load impedance set to 1000Ω.

[0072] As shown in Figure 8, increasing the load impedance as the power supply voltage Vdd decreases increases the balanced line impedance at the central frequency (130 GHz) by approximately 1.5 times. As a result, although the power of amplifiers 140A and 140B in the power amplification circuit 105 decreases slightly, the efficiency is improved.

[0073] Figure 9 illustrates the change in gain when the load impedance is changed, as shown in Figure 8. The left column of Figure 8 shows a graph for a comparative example where the load impedance is fixed with respect to the change in power supply voltage Vdd. The right column of Figure 8 shows a graph for an embodiment where the load impedance is changed with respect to the change in power supply voltage Vdd.

[0074] In each graph, the horizontal axis shows output power, and the vertical axis shows gain (left axis) and efficiency (right axis). In Figure 9, the solid lines LN40~LN42 and LN50~LN52 are graphs showing gain. In Figure 9, the dashed lines LN45~LN47 and LN55~LN57 are graphs showing efficiency.

[0075] Note that in each graph, the transmission signal frequency is 130 GHz. Lines LN40, LN45, LN50, and LN55 represent the case when the power supply voltage Vdd = 1.0V, while lines LN41, LN46, LN51, and LN56 represent the case when the power supply voltage Vdd = 2.0V. Furthermore, lines LN42, LN47, LN52, and LN57 represent the case when the power supply voltage Vdd = 4.0V.

[0076] Referring to Figure 9, the gains in the embodiment when the power supply voltage Vdd is 1.0V and 2.0V (lines LN50, LN51) are higher than the gains in the comparative example (lines LN40, LN41).

[0077] Furthermore, regarding efficiency, the increased load impedance results in higher peak efficiency (line LN55, LN56) for power supply voltages Vdd of 1.0V and 2.0V in the embodiment compared to the peak efficiency (line LN45, LN46) in the comparative example.

[0078] However, as the load impedance increases, the saturation power decreases (lines LN50, LN51, LN52), so the point at which the power supply voltage level is switched changes from 14.0 dBm to 12.4 dBm when the power supply voltage Vdd = 1.0 V, and from 17.6 dBm to 16.6 dBm when the power supply voltage Vdd = 2.0 V (lines LN49, LN59).

[0079] In this way, by increasing the load impedance in response to a decrease in the power supply voltage Vdd, the efficiency of the power amplifier circuit 105 at low voltage levels can be improved, and as a result, the gain can be increased. This reduces the gain fluctuation associated with changes in the power supply voltage Vdd, and thus reduces the noise caused by changes in the power supply voltage Vdd.

[0080] In the embodiments, "balun 150" and "balun 110" are examples of the "first balun" and "second balun" in this disclosure, respectively. In the embodiments, "amplifier 120A" and "amplifier 140A" are examples of the "first amplifier" in this disclosure. In the embodiments, "amplifier 120B" and "amplifier 140B" are examples of the "second amplifier" in this disclosure.

[0081] (Variation 1) In the example shown in Figure 9, the voltage level of the power supply voltage Vdd was the same in both the comparative example and the embodiment. In this case, as described above, the peak efficiency improved with increasing load impedance, but the point at which the power supply voltage Vdd was switched was lowered due to the decrease in saturation power.

[0082] In other words, by making the load impedance variable, there is more headroom in the amplifier's output power. Therefore, by increasing the voltage level of the power supply voltage Vdd during switching and thereby increasing the amplifier's saturation power, further efficiency improvements are possible.

[0083] Figure 10, similar to Figure 9, illustrates the change in gain in Modification 1, in addition to increasing the load impedance as the power supply voltage level decreases, by changing the voltage level of the power supply voltage Vdd. More specifically, in Modification 1, the maximum voltage level of the power supply voltage Vdd is maintained at 4.0V, while the relatively lower voltage levels of the power supply voltage Vdd are set to 1.6V and 2.4V.

[0084] The left column of Figure 10 shows the graph for the comparative example in Figure 9. The right column of Figure 10 shows the graph for the modified example 1. In the graph in the right column, the solid lines LN60 to LN62 represent the gain, and the dashed lines LN65 to LN67 represent the efficiency. Lines LN60 and LN65 represent the case when the power supply voltage Vdd = 1.6V, lines LN61 and LN66 represent the case when the power supply voltage Vdd = 2.4V, and lines LN62 and LN67 represent the case when the power supply voltage Vdd = 4.0V.

[0085] By setting the power supply voltage Vdd to 1.6V and 2.4V, the saturation power is increased, and the switching points for the power supply voltage Vdd are set to 14.0dBm and 17.6dBm, the same as in the comparative example. Furthermore, the peak efficiency at each power supply voltage Vdd is further improved (line LN69), and the gain is also increased (lines LN60, LN61). As a result, the gain fluctuation associated with switching the power supply voltage Vdd is further reduced.

[0086] Thus, by designing the power amplifier circuit 105 to increase the voltage level when switching the power supply voltage Vdd, in addition to increasing the load impedance in response to the decrease in the power supply voltage Vdd, the power amplifier circuit 105 can be operated with even greater efficiency. Therefore, noise caused by changes in the power supply voltage Vdd can be further reduced compared to the embodiment shown in Figure 9.

[0087] [Equipment layout in communication devices] The equipment layout in the communication device 10 according to the embodiment will be explained using Figure 11. Figure 11 is a side view of the communication device 10 described in Figure 1.

[0088] Referring to Figure 11, the communication device 10 includes a radiating element 220, a dielectric substrate 230, a system-in-package (SiP) module 60, and an amplifier module 240 on which a power amplification circuit 105 is formed. In Figure 10 and the side view of Figure 11 described later, the direction normal to the main surface of the dielectric substrate 230 is defined as the Z-axis, and the plane perpendicular to the Z-axis is defined as the XY plane. In Figure 10, the left-right direction of the figure is defined as the X-axis direction, and the depth direction is defined as the Y-axis direction.

[0089] The dielectric substrate 230 has two opposing main surfaces 231 (first surface) and 232 (second surface). The dielectric substrate 230 is a multilayer substrate made of low-temperature co-fired ceramics (LTCC), a multilayer resin substrate formed by laminating multiple resin layers made of epoxy, polyimide, or other resins, a multilayer resin substrate formed by laminating multiple resin layers made of liquid crystal polymer (LCP) having a lower dielectric constant, a multilayer resin substrate formed by laminating multiple resin layers made of fluororesin, or a multilayer ceramic substrate other than LTCC. Note that the dielectric substrate 230 does not necessarily have to be a multilayer structure and may be a single-layer substrate.

[0090] The radiating element 220 corresponds to the antenna ANT in Figure 1. The radiating element 220 is placed on the main surface 231 (the plane in the positive direction of the Z axis) of the dielectric substrate 230. In the example in Figure 11, the radiating element 220 is a flat patch antenna. Although Figure 11 shows an example where the radiating element 220 is exposed on the surface of the main surface 231, the radiating element 220 may also be placed in an inner layer of the dielectric substrate 230.

[0091] In the dielectric substrate 230, a ground electrode GND is positioned facing the radiating element 220 across the entire surface of a dielectric layer between the radiating element 220 and the main surface 232.

[0092] The amplifier module 240 includes semiconductor substrates 241 and 242. Semiconductor substrate 242 is located on the negative Z-axis principal surface of semiconductor substrate 241 and is electrically connected to semiconductor substrate 241. Semiconductor substrate 242 is molded on semiconductor substrate 241 with insulating resin 243.

[0093] The amplifier module 240 is mounted on the main surface 231 of the dielectric substrate 230. The semiconductor substrate 241 is electrically connected to the dielectric substrate 230 via columnar electrodes 260 and connecting electrodes 265 arranged in the molding resin 243, and solder bumps 266.

[0094] Semiconductor substrate 241 is a semiconductor substrate made of a Si-based substrate material such as SiGe (silicon germanium). On the other hand, semiconductor substrate 242 is a semiconductor substrate made of a material mainly composed of a compound of a group III element and a group V element (hereinafter also referred to as "a compound of group III and V") such as GaN (gallium nitride), GaAs (gallium arsenide), or InP (indium phosphide).

[0095] The semiconductor substrate 242 has amplifiers 120A, 120B, 140A, and 140B of the power amplification circuit 105 shown in Figure 1. On the other hand, the semiconductor substrate 241 has matching circuits 130A and 130B of the power amplification circuit 105, as well as baluns 110 and 150 and impedance adjustment circuit 170.

[0096] In addition to the RFIC 30, the SiP module 60 includes a PMIC (Power Management Integrated Circuit) 35 for power control. The PMIC 35 is a circuit that supplies the drive power to operate the power amplifier circuit 105 and corresponds to the power supply circuit 160 in Figure 1.

[0097] The high-frequency signal and power supply voltage Vdd from the SiP module 60 are transmitted to the amplifier module 240, respectively, by power supply wiring 251 and 252 located within the dielectric substrate 230. The output signal Pout, amplified by the transmitting circuit 100, is transmitted to the radiating element 220 by power supply wiring 267 located on the main surface 231 of the dielectric substrate 230.

[0098] Si-based materials are commonly used as semiconductor substrates for forming semiconductor devices used in amplifiers because they are relatively inexpensive and suitable for mass production. However, Si-based materials tend to have high losses in the subterahertz frequency band above 100 GHz, which can prevent them from achieving the characteristics required for semiconductor devices.

[0099] In contrast, III-V compounds such as GaN, GaAs, and InP have a higher material cost than Si-based materials, but they possess a higher power density. Therefore, III-V compound materials have the characteristic of having less loss compared to Si-based substrates, even in the sub-terahertz frequency band.

[0100] Therefore, by forming amplifiers 120A, 120B, 140A, and 140B, which carry relatively large currents within the amplifier module 240, on a semiconductor substrate 242 containing a low-loss III-V compound material, and forming the other circuits on a semiconductor substrate 241 containing a Si-based material or on a SiP module 60, it is possible to improve circuit efficiency while suppressing an increase in cost.

[0101] In Figure 11, an example was shown in which the impedance adjustment circuit 170 is formed on the semiconductor substrate 241, but the impedance adjustment circuit 170 may also be located on the SiP module 60.

[0102] In this embodiment, "semiconductor substrate 241" and "semiconductor substrate 242" are examples of "first substrate" and "second substrate" as defined in this disclosure.

[0103] (Modification 2) In Modification 2, a different arrangement configuration of the equipment on the dielectric substrate 230 will be described.

[0104] Figure 12 is a side view of the communication device 10A of the modified example 2. In the communication device 10A, multiple radiating elements 220A and 220B are arranged on the main surface 231 of the dielectric substrate 230, and furthermore, a SiP module 60A is arranged on the main surface 232 of the dielectric substrate 230.

[0105] In the communication device 10A, the dimensions of the dielectric substrate 230 in the X-axis direction are larger than those of the communication device 10 described in Figure 12. Furthermore, on the main surface 231, the radiating elements 220A and 220B are positioned in the positive and negative X-axis directions, respectively, compared to the amplifier module 240A.

[0106] The amplifier module 240A includes circuits for two radiating elements. Specifically, a semiconductor substrate 242A, on which an amplifier for radiating element 220A is formed, and a semiconductor substrate 242B, on which an amplifier for radiating element 220B is formed, are arranged on the semiconductor substrate 241. Although not shown in Figure 12, baluns and matching circuits for each radiating element are also arranged on the semiconductor substrate 241.

[0107] From the SiP module 60A, located on the main surface 232 of the dielectric substrate 230, high-frequency signals for the radiating elements 220A and 220B are supplied to the amplifier module 240A via power supply lines 251A and 251B, respectively. In addition, the power supply voltage Vdd for the radiating elements 220A and 220B is supplied to the semiconductor substrates 242A and 242B via power supply line 252.

[0108] Furthermore, in the communication device 10A, an impedance adjustment circuit 170A for the radiating element 220A and an impedance adjustment circuit 170B for the radiating element 220B are arranged on the SiP module 60A. The impedance adjustment circuits 170A and 170B are electrically connected to the semiconductor substrates 242A and 242B, respectively, by connecting wiring 253. Alternatively, the impedance adjustment circuits 170A and 170B may be arranged on the semiconductor substrate 241, as in Figure 11.

[0109] In the configuration shown in Figure 12, the amplifier, which carries a relatively large current within the amplifier module 240A, is formed on a semiconductor substrate 242 containing a low-loss III-V compound material, while the other circuits are formed on a semiconductor substrate 241 containing a Si-based material or on a SiP module 60A. This allows for improved circuit efficiency while suppressing cost increases.

[0110] In this embodiment, "semiconductor substrate 242A" and "semiconductor substrate 242B" are examples of the "second substrate" in this disclosure.

[0111] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the description of the embodiments above, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0112] 10, 10A Communication equipment, 20 BBIC, 30 RFIC, 35 PMIC, 60, 60A SiP module, 100 Transmitter circuit, 105 Power amplifier circuit, 110, 150 Balun, 111~113, 151~153 Transmission line, 1131, 1531 Part 1, 1132, 1532 Part 2, 120A, 120B, 140A, 140B Amplifier, 130A, 130B Matching circuit, 155~157 Terminals, 160 Power supply circuit, 161 MPC, 162 Power supply selection circuit, 1621 Logic circuit, 163 Digital ET, 170, 170A, 170B Impedance adjustment circuit, 220, 220A, 220B Radiating element, 230 Dielectric substrate, 231, 232 Main surface, 240, 240A Amplifier module, 241, 242, 242A, 242B Semiconductor substrate, 243 Resin, 251, 252, 251A, 251B, 267 Power supply wiring, 253 Connection wiring, 260 Columnar electrode, 265 Connection electrode, 266 Solder bump, ANT Antenna, C1~C3 Capacitor, E1, E2 End, GND Ground electrode, GV1, GV2 Via, R1~R3 ​​Resistor, T1 Input terminal, T2 Output terminal, TR1~TR3 Switch.

Claims

1. Input terminals, Output terminals, An amplification circuit that amplifies the high-frequency signal received at the aforementioned input terminal, A first balun that transmits a high-frequency signal amplified by the amplification circuit to the output terminal, including an unbalanced transmission line whose first end is connected to the output terminal, and a first balanced transmission line and a second balanced transmission line connected to the amplification circuit, A power supply circuit that selects a discrete power supply voltage according to the power of the high-frequency signal and supplies it to the amplification circuit, A transmitting circuit comprising an impedance adjustment circuit connected to the second end of the unbalanced line of the first balun, which changes the load impedance according to the power supply voltage supplied to the amplification circuit.

2. The transmitting circuit according to claim 1, wherein the impedance adjustment circuit is configured to increase the load impedance when the power supply voltage supplied to the amplification circuit becomes low.

3. The power supply circuit transmits a control signal to the impedance adjustment circuit to change the load impedance. The power supply circuit switches the control signal according to the selected power supply voltage, as described in claim 2.

4. The transmitting circuit according to any one of claims 1 to 3, wherein the impedance adjustment circuit includes a variable resistor circuit capable of adjusting the load resistance.

5. The aforementioned variable resistor circuit is Multiple resistors connected in parallel between the first balun and the ground potential, The transmitting circuit according to claim 4, wherein each of the plurality of resistors includes a switch connected in series with the resistor.

6. The transmitting circuit according to any one of claims 1 to 5, wherein the first balun is a merchant balun.

7. The system further comprises an unbalanced transmission line whose first end is connected to the input terminal, and a second balun including a first balanced transmission line and a second balanced transmission line connected to the amplification circuit. The transmitting circuit according to any one of claims 1 to 6, wherein the second balun is a merchant balun.

8. The aforementioned amplification circuit is A first amplifier amplifies the high-frequency signal from the first balanced line of the second balun and supplies it to the first balanced line of the first balun, The transmitting circuit according to claim 7, further comprising a second amplifier that amplifies the high-frequency signal from the second balanced line of the second balun and supplies it to the second balanced line of the first balun.

9. At least a portion of the transmission circuit is formed on a semiconductor substrate including a first substrate and a second substrate. The first substrate is a semiconductor substrate containing a material mainly composed of a Si-based substrate. The second substrate is a semiconductor substrate containing a material mainly composed of a compound of a group III element and a group V element, The amplification circuit is a transmitting circuit according to any one of claims 1 to 8, formed on the second substrate.

10. The impedance adjustment circuit is formed on the first substrate, as described in claim 9.

11. A transmitting circuit according to any one of claims 1 to 10, A radiating element connected to the output terminal, A communication device comprising a signal processing circuit that supplies a high-frequency signal to the aforementioned transmitting circuit.

12. The dielectric substrate further comprises a first surface and a second surface facing each other, The communication device according to claim 11, wherein the transmitting circuit, the signal processing circuit, and the radiating element are arranged on the first surface.

13. The dielectric substrate further comprises a first surface and a second surface facing each other, The amplification circuit and the radiating element are arranged on the first surface. The communication device according to claim 11, wherein the signal processing circuit is arranged on the second surface.

14. The system further comprises a SiP (System in Package) module with the aforementioned signal processing circuit built in, The impedance adjustment circuit is formed within the SiP module, as described in any one of claims 11 to 13.

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