Indication device

Abstract

Improve the pixel circuit. [Solution] The pixel circuit includes a light-emitting element, a first-conductivity drive transistor, a second-conductivity first switch transistor that connects and disconnects the gate and drain of the drive transistor, a second-conductivity second switch transistor that supplies a reset voltage to the gate of the drive transistor, a retaining capacitance including the gate electrode of the drive transistor, an interlayer insulating layer covering the gate electrode, and an intermediate conductor layer disposed on the interlayer insulating layer, and an auxiliary capacitance including a capacitive electrode disposed below the drive transistor, the semiconductor layer of the drive transistor, and an insulating layer between the capacitive electrode and the semiconductor layer of the drive transistor.

Description

Technical Field

[0001] This disclosure relates to a pixel circuit for controlling a light-emitting element.

Background Art

[0002] Since an OLED (Organic Light-Emitting Diode) element is a current-driven self-emitting element, it does not require a backlight and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and is expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a TFT (Thin Film Transistor), and generally, an LTPS (Low Temperature Poly-silicon) TFT is used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the driving transistor determines the light emission intensity of the OLED display device, such variations in electrical characteristics become a problem. Therefore, a correction circuit for correcting variations and fluctuations in the threshold voltage of the driving transistor is implemented in a general OLED display device.

[0005] In an OLED display device, image retention may occur, and this phenomenon is called image retention. For example, after displaying a black-and-white checkerboard pattern for a specific time and then attempting to display intermediate gradations across the entire screen, afterimages of checkerboards with different gradations are displayed for a while.

[0006] This is caused by the history effect of the driving transistor. The history effect refers to a phenomenon in a field-effect transistor where the drain current when the voltage between the gate and source changes from a high voltage to a low voltage and the drain current when the voltage changes from a low voltage to a high voltage are different.

[0007] In other words, the drain current when switching from black to an intermediate grayscale is different from the drain current when switching from white to an intermediate grayscale, resulting in a difference in the light emission intensity of the OLED display device. Furthermore, because this difference in drain current continues for several frames or more, it is perceived as an afterimage. This behavior of the drain current is called the current transient response characteristic due to the hysteresis effect. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2009-258227 [Overview of the Initiative]

[0009] One aspect of the present disclosure is a pixel circuit for controlling the emission of light-emitting elements, comprising: a light-emitting element; a drive transistor for controlling a drive current to the light-emitting element; a holding capacitor for holding a control voltage of the drive transistor; a first switch transistor for switching between connecting and disconnecting the gate and drain of the drive transistor; a second switch transistor for switching between the transmission of a data signal from a data line to the holding capacitor via the drive transistor and the first switch transistor between the data line and the drive transistor; and an auxiliary capacitor between the second switch transistor and the drive transistor for holding an auxiliary voltage corresponding to the data signal from the data line. After a first period in which both the second switch transistor and the first switch transistor are ON, a second period follows in which the second switch transistor is OFF and the first switch transistor is ON. During the first period, the auxiliary capacitor holds the auxiliary voltage corresponding to the data signal from the data line, and during the second period, it provides the holding capacitor with a potential corresponding to the held auxiliary voltage. The capacitance value of the auxiliary capacitor is 1 / 2 or more of the capacitance value of the holding capacitor.

[0010] Another aspect of the present disclosure is a pixel circuit for controlling the emission of light-emitting elements, comprising: a light-emitting element; a drive transistor for controlling a drive current to the light-emitting element; a holding capacitor for holding a control voltage of the drive transistor; a first switch transistor for switching between connecting and disconnecting the gate and drain of the drive transistor; a second switch transistor between a data line and the drive transistor for switching whether or not a data signal is transmitted from the data line to the holding capacitor via the drive transistor and the first switch transistor; and a first auxiliary capacitor and a second auxiliary capacitor between the second switch transistor and the drive transistor for holding an auxiliary voltage corresponding to a data signal from the data line. The first auxiliary capacitor is located between the node between the second switch transistor and the drive transistor and the anode power line for transmitting the anode power potential of the light-emitting element. The second auxiliary capacitor is located between the node and the anode electrode of the light-emitting element. A display device according to one aspect of the present disclosure includes a substrate and a plurality of pixel circuits on the substrate, each of which pixel circuits includes a light-emitting element, a drive transistor of a first conductivity type, a first switch transistor of a second conductivity type for connecting and disconnecting the gate and drain of the drive transistor, a second switch transistor of the second conductivity type for supplying a reset voltage to the gate of the drive transistor, a holding capacitance including a gate electrode of the drive transistor, an interlayer insulating layer covering the gate electrode, and an intermediate conductor layer disposed on the interlayer insulating layer, a capacitive electrode disposed below the drive transistor, a semiconductor layer of the drive transistor, and an auxiliary capacitance including an insulating layer between the capacitive electrode and the semiconductor layer of the drive transistor. [Brief explanation of the drawing]

[0011] [Figure 1] A schematic example of the configuration of an OLED display device is shown. [Figure 2] An example of the configuration of a pixel circuit according to one embodiment of this specification is shown. [Figure 3]The timing chart for the signals controlling the pixel circuit shown in Figure 2 over a single frame period is shown. [Figure 4] Figures 2 and 3 show the simulation results of the relationship between the Vth correction period and image retention in the pixel circuit shown. [Figure 5] Figures 2 and 3 show the simulation results of the relationship between the total auxiliary capacitance value and image retention in the pixel circuit shown. [Figure 6] These graphs show the simulation results of the pixel circuits shown in Figures 2 and 3 from a different perspective. [Figure 7] A schematic example of the pixel circuit structure as viewed in the stacking direction is shown. [Figure 8] Figure 7 schematically shows the cross-sectional structure along the VIII-VIII' section. [Figure 9] Figure 7 schematically shows the cross-sectional structure at the IX-IX' section. [Figure 10] This is a schematic plan view illustrating an example of a pixel circuit structure with one transistor omitted. [Figure 11] Other examples of pixel circuit configurations are shown. [Figure 12] Figure 11 is a schematic plan view showing an example of the device structure of a pixel circuit. [Figure 13] Figure 12 schematically shows the cross-sectional structure at the XIII-XIII' section. [Figure 14] This is a plan view showing an example of the device structure of a circuit obtained by removing the transistors from the pixel circuit shown in Figure 11. [Figure 15] Other examples of pixel circuit configurations are shown. [Figure 16] Figure 15 is a schematic plan view illustrating an example of the device structure of a pixel circuit. [Figure 17] Figure 16 schematically shows the cross-sectional structure along the XVII-XVII' section. [Figure 18] Figure 16 schematically shows the cross-sectional structure along the XVIII-XVIII' section. [Figure 19] Other examples of pixel circuit configurations are shown. [Figure 20] It is a plan view schematically showing an example of a device structure of a pixel circuit shown in FIG. 19. [Figure 21] It schematically shows a cross-sectional structure at the XX I-XX I' cutting line in FIG. 20.

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be specifically described with reference to the drawings. The same reference numerals are given to common configurations in each figure. For the sake of easy understanding, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0013] Hereinafter, a technique for improving drive current control in a light-emitting display device using a light-emitting element that emits light by a drive current, such as an OLED (Organic Light-Emitting Diode) display device, will be disclosed. More specifically, a technique for suppressing image retention in a light-emitting display device will be disclosed.

[0014] [Display Device Configuration] FIG. 1 schematically shows a configuration example of an OLED display device 10 which is a display device. The horizontal direction in FIG. 1 is the X-axis direction, and the vertical direction is the Y-axis direction perpendicular to the X-axis direction. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which an OLED element (light-emitting element) is formed, a sealing substrate 200 for sealing the organic light-emitting element, and a joining portion 300 for joining the TFT substrate 100 and the sealing substrate 200.

[0015] An inert gas such as dry nitrogen is enclosed between the TFT substrate 100 and the sealing substrate 200 and is sealed by the joining portion 300. A sealing structure portion of another structure, for example, a sealing structure portion using thin film sealing instead of the sealing substrate 200 may be used.

[0016] Scanning circuits 131, 132, a driver IC 134, and a demultiplexer 136 are arranged around the cathode electrode formation area 114 outside the display area 125 of the TFT substrate 100. The driver IC 134 is connected to an external device via an FPC (Flexible Printed Circuit) 135. Scanning circuits 131 and 132 drive the scan lines of the TFT substrate 100.

[0017] The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF). The driver IC 134 supplies power and timing signals (control signals) to the scanning circuits 131 and 132. Furthermore, the driver IC 134 supplies data signals to the demultiplexer 136.

[0018] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (where d is an integer greater than or equal to 2). The demultiplexer 136 drives d times the number of output pins of the driver IC 134 by switching the data line to which the data signal from the driver IC 134 is output d times within the scanning period.

[0019] The display area 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits that control the light emission of each of the plurality of pixels. In a color OLED display device, each OLED element emits light of one of the following colors, for example, red, blue, or green. The plurality of pixel circuits constitute a pixel circuit array.

[0020] As described later, each pixel circuit includes a drive TFT (driver transistor) and a holding capacitor that holds the signal voltage that determines the drive current of the drive TFT. The data signal transmitted by the data line is corrected for the threshold voltage Vth of the drive transistor and stored in the holding capacitor. The voltage of the holding capacitor determines the gate voltage (Vgs) of the drive TFT. The corrected control voltage of the holding capacitor changes the conductance of the drive TFT analogously, supplying a forward bias current corresponding to the light emission gradation to the OLED element.

[0021] A pixel circuit in one embodiment of this specification further includes an auxiliary capacitor that holds an auxiliary voltage for correcting the voltage held by the retaining capacitor. The auxiliary capacitor supplies a potential to the retaining capacitor after the data signal is written from the data line to the pixel circuit, thereby correcting the voltage held by the retaining capacitor. The auxiliary capacitor makes it possible to more appropriately correct the control voltage held by the retaining capacitor with respect to the threshold voltage Vth of the drive transistor.

[0022] [Pixel circuit] Figure 2 shows an example of a pixel circuit configuration 400 according to one embodiment of this specification. The pixel circuit 400 includes a holding capacitor that holds a control voltage that controls the amount of current of the drive transistor. The control voltage held by the holding capacitor is also called the drive voltage of the drive transistor. The holding capacitor holds a control voltage corresponding to the data signal (potential) transmitted from the driver IC 134 via the data line. The control voltage is a voltage that has been corrected (Vth correction) for the threshold voltage Vth of the drive TFT with respect to the data signal, and is sometimes called the corrected data voltage.

[0023] The pixel circuit 400 further includes an auxiliary capacitor that holds an auxiliary voltage corresponding to the data signal from the data line. The auxiliary voltage is a value corresponding to the data signal and is sometimes called the data voltage. The auxiliary capacitor is located between the data line and the drive transistor in the pixel circuit. The auxiliary capacitor provides a potential corresponding to the auxiliary voltage to the holding capacitor via the diode-connected drive transistor. This ensures that the Vth correction of the control voltage held by the holding capacitor is maintained.

[0024] The pixel circuit 400 corrects the data signal supplied from the driver IC 134 and controls the light emission of the OLED element using the corrected signal. The pixel circuit 400 includes eight transistors (TFTs) M1 to M8, each having a gate, source, and drain. In this example, transistors M1 to M8 are P-type TFTs, and all transistors except the driving transistor M3 are switch transistors. Note that transistor M8 may be omitted.

[0025] The pixel circuit 400 further includes a holding capacitor Cst, as well as a first auxiliary capacitor Cd1 and a second auxiliary capacitor Cd2. The holding capacitor Cst is connected between the anode power supply that provides the power supply potential VDD and the gate (node ​​N1) of the drive transistor M3. It holds the gate-source voltage (also called the gate voltage or control voltage) of the drive transistor M3.

[0026] One end of the auxiliary capacitor Cd1 is connected to node N3 between the source / drain of the switch transistor M2 and the source / drain of the drive transistor M3, and the other end is connected to a power line that transmits the anode power supply potential. The auxiliary capacitor Cd1 maintains the auxiliary voltage between the source / drain of the switch transistor M2 and the anode power supply. Transistor M2 is a second switch transistor that switches whether or not a data signal is transmitted to the holding capacitor.

[0027] One end of the auxiliary capacitor Cd2 is connected to node N3 between the source / drain of the switch transistor M2 and the source / drain of the drive transistor M3, and the other end is connected to the anode electrode of the OLED element E1. The auxiliary capacitor Cd2 maintains an auxiliary voltage between the source / drain of the switch transistor M2 and the anode electrode of the OLED element E1.

[0028] Transistor M3 is a drive transistor that controls the amount of current supplied to the OLED element E1. The drive transistor M3 controls the amount of current supplied from the anode power supply to the OLED element E1 according to the voltage held by the retaining capacitance Cst. The cathode of the OLED element E1 is connected to a cathode power supply that provides the cathode potential VEE.

[0029] Transistors M1 and M6 control the illumination of the OLED element E1. Transistor M1 has one source / drain connected to the anode power supply and switches the current supply to the drive transistor M3, which is connected to the other source / drain, ON / OFF. Transistor M6 has one source / drain connected to the drain of the drive transistor M3 and switches the current supply to the OLED element E1, which is connected to the other source / drain, ON / OFF. Transistors M1 and M6 are controlled by the illumination control signal Em input to the gate from the scanning circuit 131 or 132, respectively.

[0030] Transistor M7 operates to supply a reset potential to the anode of the OLED element E1. When transistor M7 is turned ON by a selection signal S2 or S3 input to its gate from the scanning circuit 131 or 132, it supplies a reset potential Vrst from the reset power supply to the anode of the OLED element E1. The reset potential may be, for example, below the GND potential. The other end of the reset power supply is connected to GND.

[0031] Transistor M5 controls whether or not a reset potential is supplied to the gate of the drive transistor M3. When transistor M5 is turned ON by a selection signal S1 input to the gate terminal from the scanning circuit 131 or 132, it supplies a reset potential Vrst to the gate of the drive transistor M3 from a reset power supply connected to one of its source or drain terminals. The other end of the reset power supply is connected to GND. Note that the reset potential to the anode electrode of the OLED element E1 and the reset potential to the gate of the drive transistor M3 may be different.

[0032] Transistor M2 is a selection transistor for selecting the pixel circuit 400 that supplies the data signal. The gate voltage of transistor M2 is controlled by the selection signal S2 supplied from the scanning circuit 131 or 132. When selection transistor M2 is ON, it supplies the data signal Vdata supplied from the driver IC 134 via the data line to auxiliary capacitors Cd1 and Cd2.

[0033] In this example, the source / drain of transistor M2 is connected between the data line and the source (node ​​N2) of the drive transistor M3. Furthermore, transistor M8 is connected between the source / drain (node ​​N3) of the selection transistor M2 and the source (node ​​N2) of the drive transistor M3. Transistor M8 is the third switch transistor. Transistor M4 is connected between the drain and gate of the drive transistor M3. Transistor M4 is the first switch transistor.

[0034] Transistors M4 and M8 are controlled by a selection signal S3 supplied from the scanning circuit 131 or 132. Transistor M4 operates to compensate for the threshold voltage Vth of the drive transistor M3. Transistor M4 switches the connection between the gate and drain of the drive transistor M3 between connected and disconnected. When transistor M4 is ON, the drive transistor M3 constitutes a diode-connected transistor. When transistor M4 is OFF, the drive transistor M3 is in its normal state.

[0035] The data signal Vdata from the data line is supplied to the holding capacitor Cst via ON transistors M2 and M8, the diode-connected drive transistor M3, and the ON transistor M4. At this time, Vth correction is performed. Also during this period, the data signal Vdata from the data line is supplied to auxiliary capacitors Cd1 and Cd2 via the ON transistor M2.

[0036] After transistor M2 is turned OFF, the potential of node N3 due to the auxiliary voltages of auxiliary capacitors Cd1 and Cd2 is supplied to the retaining capacitor Cst via the ON transistor M8, the diode-connected driving transistor M3, and the ON transistor M4. This further corrects the Vth of the control voltage held by the retaining capacitor Cst.

[0037] The retaining capacitor Cst holds the gate-source voltage of the drive transistor M3 and controls the amount of current that the drive transistor M3 supplies to the OLED element E1. As described above, the retaining capacitor Cst holds a voltage corrected according to the threshold voltage Vth of the drive transistor M3.

[0038] As described above, the auxiliary capacitors Cd1 and Cd2 allow for continued Vth correction of the control voltage of the retaining capacitor Cst after transistor M2 is turned OFF. This enables more appropriate Vth correction and effectively reduces image retention.

[0039] In the example shown in Figure 2, two auxiliary capacitors Cd1 and Cd2 are included in the pixel circuit 400. This allows for a larger capacitance value to maintain the auxiliary voltage in the pixel circuit 400, enabling more effective Vth correction. In other configuration examples, if the required capacitance value can be secured, one of the two auxiliary capacitors Cd1 and Cd2 may be omitted. When writing the auxiliary voltage to the auxiliary capacitor, a data signal is applied to one end and a predetermined fixed potential is applied to the other end. The fixed potential is not particularly limited.

[0040] Figure 3 shows the timing chart of the signals that control the pixel circuit 400 shown in Figure 2 during one frame period. Figure 3 shows the timing chart for selecting the Nth row and writing the data signal Vdata to the pixel circuit 400. Specifically, Figure 3 shows the light emission control signal Em, selection signal S1, selection signal S2, selection signal S3, and data signal Vdata. Note that selection signal S2 may be the same as the selection signal S1_N+1 for the (N+1)th row.

[0041] At time T1, the light emission control signal Em changes from Low to High. At time T1, transistors M1 and M6 are OFF. At time T1, selection signals S1, S2, and S3 are High. In accordance with these control signals, transistors M2, M4, M5, M7, and M8 are OFF. These transistor states are maintained until time T2, after time T1. The potential of node N1 is at the signal potential of the previous frame.

[0042] At time T2, selection signal S1 changes from High to Low. At time T2, the light emission control signal Em and selection signals S2 and S3 are High. Transistor M5 turns ON in response to the change in selection signal S1. Transistors M1, M2, M4, M6~M8 are OFF.

[0043] When transistor M5 is turned ON, the potential of node N1 changes to the reset potential Vrst. The reset potential is applied to node N1 from time T2 to time T3. Because the reset potential is applied to node N1 every frame, the gate potential of the drive transistor M3 also becomes the same every frame, thus reducing the effects of hysteresis.

[0044] At time T3, selection signal S1 changes from Low to High. Furthermore, selection signals S2 and S3 change from High to Low. The light emission control signal Em is High. Transistor M5 turns OFF in response to the change in selection signal S1. Transistors M2 and M7 turn ON in response to the change in selection signal S2. Transistors M4 and M8 turn ON in response to the change in selection signal S3. Transistors M1 and M6 remain OFF.

[0045] When transistor M7 is turned ON, a reset potential Vrst is applied to the anode of the OLED element E1 and one end of the auxiliary capacitor Cd2. Since transistor M4 is ON, the drive transistor M3 is diode-connected.

[0046] Since transistors M2 and M8 are ON, the data signal Vdata from the data line is written to the retaining capacitor Cst via transistors M2, M8, M3, and M4. The voltage written to the retaining capacitor Cst is a voltage that has been corrected for the threshold voltage Vth of the drive transistor M3 relative to the data signal Vdata.

[0047] Furthermore, because transistor M2 is ON, the data signal Vdata from the data line is written to auxiliary capacitors Cd1 and Cd2 via transistor M2. Auxiliary capacitor Cd1 holds the voltage between the anode power supply potential (fixed potential) and the data signal, and auxiliary capacitor Cd2 holds the voltage between the data signal and the reset power supply potential (fixed potential). During the period from time T3 to time T4, the data signal Vdata is written from the data line to the pixel circuit 400 and its Vth correction is performed.

[0048] At time T4, the selection signal S2 changes from Low to High. At time T4, the light emission control signal Em and selection signal S1 are High, and the selection signal S3 is Low. Transistors M2 and M7 turn OFF in response to the change in selection signal S2. Transistors M8 and M4 are ON, and transistors M1, M2, M5~M7 are OFF.

[0049] Since transistors M8 and M4 are ON, the Vth correction of the control voltage held by the holding capacitor Cst continues due to the auxiliary voltage (data voltage) held by auxiliary capacitors Cd1 and Cd2. From time T4 to time T5, the control signal and the state of the transistors are maintained. For example, auxiliary capacitors Cd1 and Cd2 have the capacitance values ​​necessary to maintain the potential of node N3 at substantially the same potential as the potential due to the data signal Vdata during this period.

[0050] At time T5, the selection signal S3 changes from Low to High. Time T5 coincides with the time when the selection signal S2 in row (N+m) changes from High to Low, where m is an integer greater than or equal to 2. In response to this change in selection signal S3, transistors M4 and M8 turn OFF. The other switch transistors remain OFF. At time T5, the Vth correction of the control voltage of the holding capacitance Cst by auxiliary capacitances Cd1 and Cd2 is completed.

[0051] At time T6, the light emission control signal Em changes from High to Low, and transistors M1 and M6 change from OFF to ON. The selection signals S1, S2, and S3 are High, and transistors M2, M4, M5, M7, and M8 remain OFF. The drive transistor M3 controls the drive current supplied to the OLED element E1 based on the corrected data voltage held in the retaining capacitor Cst. In other words, the OLED element E1 emits light.

[0052] According to the pixel circuit operation described above, Vth correction can be performed during the period from time T3 to time T5. This period is longer than the period from time T3 to time T4, which is the period when the selection signal S2 is low and data signals are written to the pixel circuit from the data line. By adjusting time T5 in the circuit design, a Vth correction period suitable for the display device can be set. The set Vth correction period is longer than the data writing period.

[0053] In the example shown in Figure 3, the data writing period is from time T3 to T4. The Vth correction period is from time T3 to T5. The data writing period is the period when transistor M2 is ON and data signals are supplied to the pixel circuit from the data line. The Vth correction period is the period when a potential is supplied to the retaining capacitor Cst via the diode-connected drive transistor M3, and Vth correction is performed at the control voltage of the retaining capacitor Cst.

[0054] In the example shown in Figure 3, the data writing period is included in the Vth correction period. That is, during the period from time T3 to T4, data writing and Vth correction are performed simultaneously. In the period from time T4 to T5, after this period, no data writing is performed, and only Vth correction by the auxiliary capacity is performed. In this way, including the data writing period in the Vth correction period allows for more appropriate Vth correction.

[0055] In other configuration examples, the data writing period may end before the Vth correction period without overlapping with it. For example, in the timing chart shown in Figure 3, the data writing period may be the period from time T2 to T3. This period is the reset period, where the selection signal S1 is low and the reset potential is applied to the gate of the drive transistor M3. Transistor M8 is OFF, and the data signal from the data line is applied to the auxiliary capacitors Cd1 and Cd2 without being applied to the holding capacitor Cst.

[0056] [Conditions for auxiliary capacity] Examples of conditions for auxiliary capacitors Cd1 and Cd2 are described below. As explained with reference to Figures 2 and 3, during the Vth correction period when the selection signal S3 is Low, it is desirable that the potential of node N2 be maintained at the data signal potential Vdata. If the total auxiliary capacitance value (Cd1 + Cd2) is small, the potential of node N2 will drop rapidly, causing the correction mechanism to stop. Therefore, by including an auxiliary capacitor with a sufficiently large total auxiliary capacitance value Cd in the pixel circuit, the charge retention effect at node N2 suppresses potential fluctuations at node N2 during the correction period, allowing the correction operation to continue.

[0057] Figure 4 shows the simulation results of the relationship between the Vth correction period and image retention in the pixel circuit shown in FIGS. 2 and 3. In the graph of FIG. 4, the horizontal axis represents the Vth correction period, and the vertical axis represents an exponent indicating the image retention intensity. When the exponent is a positive value, it is negative-type image retention, and when the exponent is a negative value, it is positive-type image retention. The farther the exponent is from 0, the greater the image retention. The data writing period (1H period) is 4.2 μs, and the capacitance value of the holding capacitance Cst is 80 fF. The data writing period is also called the horizontal selection period.

[0058] The different lines in the graph show the simulation results of different total auxiliary capacitance values Cd of the two auxiliary capacitances Cd1 and Cd2. Line 421 shows the data of the pixel circuit with the total capacitance value of the auxiliary capacitance being 0. Line 422 shows the data of the pixel circuit with the total capacitance value of the auxiliary capacitance being 40 fF. Line 423 shows the data of the pixel circuit with the total capacitance value of the auxiliary capacitance being 80 fF. Line 424 shows the data of the pixel circuit with the total capacitance value of the auxiliary capacitance being 160 fF or 240 fF.

[0059] The image retention intensity index is defined as follows. After displaying a black-and-white checkerboard pattern for a certain period of time, when the drain current when switching from black to a middle gray level is I1, and the drain current when switching from white to a middle gray level is I2, the image retention intensity index can be defined as follows. Image retention intensity index = 2.0 * (I1 - I2) / (I1 + I2)

[0060] From this definition, when I1 > I2, that is, when the image retention intensity index is positive, the current (luminance) of the pixel that was displaying black becomes larger than the pixel (luminance) that was displaying white, resulting in an afterimage with the luminance reversed from the original black-and-white checkerboard pattern. Therefore, this is defined as negative-type image retention, and when I1 < I2, it is defined as positive-type image retention.

[0061] Range 430 corresponds to an image retention intensity index ranging from -2.0E-03 to 2.0E-03. This range 430 represents a range where the effect of image retention can be ignored, as determined by the inventors' experimental results. Image retention is dependent on the bias history of the driving TFT, and the image retention intensity index is known to increase approximately proportionally to the stress time in monochrome display.

[0062] It is generally known that afterimages become visible when the brightness difference between adjacent areas is approximately ±1%. However, in this simulation, the monochrome display stress time is about 1 / 10th of the test conditions for the actual product, so the image retention strength index is also small. The range 430 mentioned above was determined considering the difference between the display conditions of the display panel and the simulation conditions.

[0063] As shown in Figure 4, when the total auxiliary capacitance value Cd is 40 fF or more, the image retention intensity can be included within the range of 430 by appropriately setting the Vth correction period. Furthermore, when the total auxiliary capacitance value Cd is 80 fF or more, the image retention intensity can be reduced to zero by appropriately setting the Vth correction period.

[0064] As mentioned above, since the retention capacity is 80 fF, the image retention intensity can be kept within the range of 430 by setting the total auxiliary capacity to be 1 / 2 or more of the retention capacity. Furthermore, the image retention intensity can be set to zero by setting the total auxiliary capacity to be equal to or greater than the retention capacity.

[0065] As shown in Figure 4, if both Cd and the correction period are excessive, the image retention intensity index becomes too large in the negative direction. To properly reduce image retention, it is important to set the length of the correction period appropriately. The correction period will be explained below.

[0066] Figure 5 shows the simulation results of the relationship between the total auxiliary capacitance value and image retention in the pixel circuit shown in Figures 2 and 3. In the graph in Figure 5, the horizontal axis represents the total auxiliary capacitance value, and the vertical axis represents the image retention strength. The data writing period (1H period) is 4.2 μs, and the capacitance value of the retention capacitance Cst is 80 fF.

[0067] The different lines in the graph represent the simulation results for different Vth correction periods. Line 441 shows the data for a pixel circuit with a Vth correction period of 12.6 μs. Line 442 shows the data for a pixel circuit with a Vth correction period of 21.0 μs. Line 443 shows the data for a pixel circuit with a Vth correction period of 29.4 μs. Line 444 shows the data for a pixel circuit with a Vth correction period of 42.0 μs.

[0068] As shown in Figure 5, when the Vth correction period is between 21.0 μs and 42 μs, the image retention intensity can be included within range 430 by appropriately setting the total auxiliary capacitance value. Since the data writing period (1H period) is 4.2 μs, the image retention intensity can be included within range 430 by setting the Vth correction period to between 5H and 10H.

[0069] Figure 6 is a graph showing the simulation results of the pixel circuit shown in Figures 2 and 3 from a different perspective. The horizontal axis represents (Cd / Cst) × (correction period / data writing period). 3 The graph shows the image retention intensity on the vertical axis. Cd represents the total auxiliary volume value, and Cst represents the retention volume value. Note that different combinations of Cd and correction period may show the same value on the horizontal axis and different values ​​on the vertical axis. In Figure 6, the range 440 shown by the rectangle represents the range of the image retention intensity index from -2.0E-03 to 2.0E-03. As can be seen from the graph in Figure 6, the image retention intensity can be included within the desired range above by satisfying the following conditions. 100 ≤ (Cd / Cst) × (Correction period / Data writing period) 3 ≤700

[0070] [Device Structure] The following describes an example of the device structure of a pixel circuit. Figure 7 is a schematic plan view showing an example of the device structure of a pixel circuit as seen in the stacking direction. Figure 7 shows the polysilicon layer and the conductor layer in the pixel circuit. The white rectangles indicate the contact areas of different conductor layers. The contact areas are conductors formed within via holes that penetrate the insulating layer in the stacking direction.

[0071] Transmission lines M1S1, M1S2, M1S3, and M1E transmit selection signals S1, S2, and S3, and light emission control signal Em, respectively. These are contained within the first metal layer, which is a conductive layer. In the example in Figure 7, these extend in the X-axis direction. In the example in Figure 7, selection signal S1 is common to selection signal S2 in the previous row.

[0072] As explained with reference to Figure 2, the pixel circuit includes transistors M1 to M8. The channels of the transistors are contained within the polysilicon layer p-Si. In Figure 7, the polysilicon layer p-Si is shown with the same pattern. The gate electrodes of transistors M1 to M8 are contained within the first metal layer. In Figure 7, the gate electrode of the driving transistor M3 is indicated by the code M1G.

[0073] The conductor portion MCP covers the entire gate electrode M1G of the drive transistor M3. The conductor portion MCP is connected to the power line M2V, which transmits the anode power supply potential VDD, via a contact hole. The conductor portion MCP is contained within the intermediate conductor layer above the first metal layer. A portion of the conductor portion MCP is contained within the retaining capacitance Cst. The intermediate conductor layer further includes transmission lines MCV and MCV2, which extend in the X-axis direction and transmit the reference potential Vrst. Transmission lines M2V and M2D extend in the Y-axis direction and transmit the anode power supply potential VDD and the data signal Vdata, respectively. These are contained within the second metal layer above the intermediate conductor layer. The second metal layer is a conductor layer.

[0074] The capacitive electrode M3C is located in the third metal layer, which is above the second metal layer. The third metal layer is a conductive layer. The capacitive electrode M3C is connected to the source / drain of transistors M2 and M8 via the contact portion M2C of the second metal layer. The capacitive electrode M3C is the common electrode for auxiliary capacitors Cd1 and Cd2 in the pixel circuit shown in Figure 2.

[0075] The capacitive electrode M3C covers at least a portion of the power line M2V that transmits the anode power supply potential VDD. The auxiliary capacitance Cd1 is formed between the capacitive electrode M3C and the power line M2V. Furthermore, the anode electrode RE of the OLED element covers at least a portion of the capacitive electrode M3C. The anode electrode RE is above the third metal layer containing the capacitive electrode M3C. The auxiliary capacitance Cd2 is formed between the capacitive electrode M3C and the anode electrode RE.

[0076] Figure 8 schematically shows the cross-sectional structure at the VIII-VIII' section in Figure 7. Figure 8 mainly shows transistors M1 and M2 and auxiliary capacitor Cd2. A stacked structure of the pixel circuit is formed on a substrate SUB made of polyimide or glass. An underlayer UC, for example, a silicon nitride layer, is formed on the substrate SUB. A polysilicon layer p-Si is stacked on the underlayer UC. Furthermore, a gate insulating layer GI is stacked so as to cover the polysilicon layer p-Si. The gate insulating layer GI is formed of, for example, silicon oxide or silicon nitride.

[0077] The first metal layer is laminated on the gate insulating layer GI. Specifically, the transmission line M1E for transmitting the light emission control signal Em, and the transmission lines M1S1, M1S2, and M1S3 for transmitting the selection signals S1, S2, and S3, respectively, are shown. In Figure 8, the transmission line M1S2 corresponds to the gate electrode of transistor M2. The first metal layer can be formed from, for example, a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof.

[0078] An interlayer insulating layer (IMD) is laminated so as to cover the first metal layer. The interlayer insulating layer (IMD) can be formed from, for example, silicon oxide or silicon nitride. The intermediate conductor layer is laminated on the interlayer insulating layer (IMD). Specifically, the reference potential transmission line (MCV) and the conductor portion (MCP) that constitutes part of the holding capacitance are shown. The intermediate conductor layer can be made of, for example, a high melting point metal such as W, Mo, or Ta, or an alloy thereof, or it can have an Al single layer or a Ti / Al / Ti laminated structure.

[0079] An interlayer insulating layer (ILD) is laminated to cover the intermediate conductor layer. The interlayer insulating layer (ILD) can be formed from, for example, silicon oxide or silicon nitride. A second metal layer is formed on the interlayer insulating layer (ILD). Figure 8 shows the transmission line M2V for the anode power supply potential VDD, the transmission line M2D for the data signal Vdata, and the contact portion M2C. The transmission lines M2V, M2D, and the contact portion M2C are in contact with the polysilicon layer P-Si through via holes that penetrate the interlayer insulating layer (ILD) and the gate insulating layer GI.

[0080] A passivation layer PAS and a planarization layer PLN1 on top of it are formed to cover the underlying layers. These can be made of organic or inorganic insulators. A third metal layer containing a capacitive electrode M3C is formed in the planarization layer PLN1. The capacitive electrode M3C is in contact with the contact portion M2C through via holes that penetrate the planarization layer PLN1 and the passivation layer PAS.

[0081] A planarization layer PLN2 is formed to cover the underlying layer. The planarization layer PLN2 can be made of an organic or inorganic insulator. The anode electrode RE of the OLED element is formed on the planarization layer PLN2. The anode electrode RE has, for example, an ITO / Ag / ITO structure or an IZO / Ag / IZO structure.

[0082] A portion of the anode electrode RE faces the capacitive electrode M3C across the planarization layer PLN2, forming an auxiliary capacitance Cd2. By forming this auxiliary capacitance Cd2 between the anode electrode RE and the capacitive electrode M3C of the third metal layer, the capacitance value that holds the auxiliary voltage for correcting the Vth of the retained capacitance Cst can be effectively increased.

[0083] Figure 9 schematically shows the cross-sectional structure at the IX-IX' cut line in Figure 7. Figure 9 shows the cross-sectional structure of the drive transistor M3 and its surroundings. The gate electrode M1G of the drive transistor M3 covers the channel of the polysilicon layer p-Si with the gate insulating layer GI in between, and controls the amount of current flowing through the channel.

[0084] The conductor portion MCP of the intermediate conductor layer faces the gate electrode M1G across the interlayer insulating layer IMD. Furthermore, the conductor portion MCP faces the transmission line M2V of the anode power supply potential VDD across the interlayer insulating layer IMD. A retaining capacitance Cst is formed between the gate electrode M1G and the transmission line M2V, which face each other across the conductor portion MCP.

[0085] The contact portion MB of the second metal layer penetrates the interlayer insulating layer ILD, the opening in the conductor portion MCP, and the gate insulating layer GI to contact the gate electrode M1G. The contact portion MB connects the gate electrode M1G of the drive transistor M3 to the source / drain of transistor M4.

[0086] The transmission line M2V of the anode power supply potential VDD of the second metal layer faces the capacitive electrode M3C of the third metal layer, with the passivation layer PAS and the planarization layer PLN1 in between. The auxiliary capacitance Cd1 is formed between the transmission line M2V and the capacitive electrode M3C. As shown in Figure 8, the auxiliary capacitance Cd2 is formed between the anode electrode RE and the capacitive electrode M3C.

[0087] As described above, by configuring an auxiliary capacitance between the anode power line and the capacitive electrode, and also between the capacitive electrode and the anode electrode, the auxiliary capacitance value required to properly correct the Vth of the control voltage of the drive transistor can be achieved in a small area.

[0088] [Other configuration examples] The following describes different configurations of the pixel circuit. The transistor M8 can be omitted from the pixel circuit 400 shown in Figure 2. Figure 10 is a schematic plan view showing an example of the structure of the pixel circuit with transistor M8 omitted. The following mainly explains the differences from the structure shown in Figure 7.

[0089] As shown in Figure 10, the pixel circuit includes an electrode portion M2E1 of the second metal layer that straddles the transmission line M1S3. The electrode portion M2E1 is connected to the source / drain of transistor M2 by a contact portion M2C, and further connected to the source / drain of transistors M1 and M3 by a contact portion M2C2. This eliminates the need for transistor M8. Compared to the structure in Figure 10, the structure in Figure 7 can omit the electrode portion M2E1 that straddles the transmission line M1S3. Transistor M8 increases the number of circuit elements, but the device structure can be made simpler.

[0090] Figure 11 shows another example of a pixel circuit configuration. The main difference from the pixel circuit 400 in Figure 2 will be explained. Pixel circuit 500 includes N-type transistors M12, M14, M15, M17, and M18. These correspond to the P-type transistors M2, M4, M5, M7, and M8 in pixel circuit 400 shown in Figure 2. Transistors M1, M3, and M6, through which the drive current of the OLED element E1 passes, are P-type polysilicon transistors exhibiting high mobility.

[0091] The selection signals S1, S2, and S3 that control the pixel circuit 500 show changes in the opposite direction to the time changes shown in Figure 3. That is, the High and Low signals in Figure 3 are reversed. The change in the light emission control signal Em is the same as the change shown in Figure 3. The N-type transistor is, for example, an oxide semiconductor transistor. Compared to polysilicon transistors, oxide semiconductor transistors can reduce leakage current. By reducing the leakage current of transistor M12, the voltage drop of the auxiliary capacitor can be suppressed. Also, by reducing the leakage current of transistors M14 and M15, the voltage drop of the retaining capacitor can be suppressed. Note that some of the N-type transistors in Figure 11 may be P-type transistors.

[0092] Figure 12 is a schematic plan view showing an example of the device structure of the pixel circuit 500 shown in Figure 11. The main difference from the example structure shown in Figure 7 will be explained. As mentioned above, the P-type transistors M2, M4, M5, M7, and M8 in the example structure in Figure 7 are replaced with N-type transistors 12, M14, M15, M17, and M18, respectively. The P-type transistors are polysilicon TFTs, and the N-type transistors are oxide semiconductor TFTs. Oxide semiconductors are, for example, InGaZnO and ZnO.

[0093] In Figure 12, the oxide semiconductor layer OX contains the channels of transistors M12, M14, M15, M17, and M18. Electrodes M2E5, M2E6, and M2E7 of the second metal layer interconnect the source / drain of transistors with different conductivity types, respectively. Specifically, electrode M2E5 connects the P-type transistor M1 and the N-type transistor M18. Electrode M2E6 connects the P-type transistors M3 and M6 and the N-type transistor M14. Electrode M2E7 connects the P-type transistor M6 and the N-type transistor M17.

[0094] The transmission lines MDS1, MDS2, and MDS3, which transmit the selection signals S1, S2, and S3, are included in the fourth metal layer. The fourth metal layer is a conductor layer. As will be described later, the fourth metal layer is the layer between the intermediate metal layer and the second metal layer.

[0095] Figure 13 schematically shows the cross-sectional structure at the XIII-XIII' section in Figure 12. The main points to explain are the differences from the structural example shown in Figure 8. The oxide semiconductor layer OX and the gate insulating layer GI2 are stacked between the interlayer insulating layer ILD and the passivation layer PAS. The oxide semiconductor layer OX is formed on the interlayer insulating layer ILD and covered by the gate insulating layer GI2.

[0096] The electrode M2E5 of the second metal layer interconnects the source / drain of the polysilicon transistor M1 and the source / drain of the oxide semiconductor transistor M12. Specifically, the electrode M2E5 of the second metal layer contacts the source / drain of the P-type transistor M1 via via holes penetrating the passivation layer PAS, the gate insulating layer GI2, the interlayer insulating layer ILD, the interlayer insulating layer IMD, and the gate insulating layer GI. Furthermore, the electrode M2E5 of the second metal layer contacts the source / drain of the N-type transistor M12 via via holes penetrating the passivation layer PAS and the gate insulating layer GI2.

[0097] The transmission lines MDS1, MDS2, and MDS3, which transmit the selection signals S1, S2, and S3, are contained in the fourth metal layer. The fourth metal layer can be formed from a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof. The fourth metal layer is formed between the gate insulating layer GI2 and the passivation layer PAS. The fourth metal layer is a metal layer (conductor layer) between the intermediate conductor layer and the second metal layer.

[0098] Similar to the pixel circuit 400 shown in Figure 2, the transistor M18 can be omitted from the pixel circuit 500 shown in Figure 11. Figure 14 is a plan view showing an example of the device structure of the pixel circuit 500 with transistor M18 removed. Electrode M2E8 is used instead of electrode M2E5 in the structural example shown in Figure 12.

[0099] Electrode M2E8 is contained in the second metal layer and interconnects the source / drain of P-type transistor M1 and the source / drain of N-type transistor M12 across the conductor MCP and transmission line MDS3. By implementing transistor M18 in the pixel circuit 500, the device structure of the pixel circuit can be made simpler.

[0100] Figure 15 shows another example of a pixel circuit configuration. The main differences from the pixel circuit 400 in Figure 2 will be explained. The pixel circuit 600 includes a third auxiliary capacitor Cd3 and a second capacitive electrode SH, in addition to the configuration of the pixel circuit 400 in Figure 2. One end of the third auxiliary capacitor Cd3 is connected to the second capacitive electrode SH, and the other end is connected to node N2. A fixed potential may be applied to the second capacitive electrode SH. Other configurations are the same as those of the pixel circuit 400.

[0101] Figure 16 is a plan view showing an example of the device structure of the pixel circuit in Figure 15. Figure 17 schematically shows the cross-sectional structure at the XVII-XVII' section in Figure 16. Figure 18 schematically shows the cross-sectional structure at the XVIII-XVIII' section in Figure 16. Below, we will mainly explain the differences from the structural examples described with reference to Figures 7 to 9.

[0102] The structural examples shown in Figures 16 to 18 include a second capacitive electrode SH between the substrate SUB and the underlying insulating film UC. As shown in Figure 16, in a plan view, the second capacitive electrode SH is positioned below the drive transistor M3, and at least a portion of the second capacitive electrode SH overlaps with the drive transistor M3.

[0103] The potential of the second capacitive electrode SH may be a fixed potential, for example, the ground potential. The polysilicon layer p-Si constituting the drain of the drive transistor M3 and the second capacitive electrode SH form a third auxiliary capacitance Cd3. Although the structural examples shown in Figures 16 to 18 include the capacitive electrode M3C, the capacitive electrode M3C may be omitted.

[0104] Because the total capacitance of the auxiliary capacitor can be increased, an appropriate capacitance value can be secured even when the pixel size is reduced due to increased resolution, thus effectively controlling afterimages. Furthermore, the current drift of the drive transistor caused by the generation of fixed charges in the polyimide, which is a problem when using a polyimide film as the substrate, is shielded by the second capacitance electrode layer, thereby stabilizing the drive transistor. As a result, brightness drift during the initial panel startup and afterimages, especially afterimages caused by prolonged stress, can be suppressed.

[0105] Figure 19 shows another example of a pixel circuit configuration. The main differences from the pixel circuit 500 in Figure 11 will be explained. The pixel circuit 700 includes a third auxiliary capacitor Cd3 and a second capacitance electrode SH, in addition to the configuration of the pixel circuit 500 in Figure 11. One end of the third auxiliary capacitor Cd3 is connected to the second capacitance electrode SH, and the other end is connected to node N2. A fixed potential may be applied to the second capacitance electrode SH. Other configurations are the same as those of the pixel circuit 500.

[0106] Figure 20 is a plan view schematically showing an example of the device structure of the pixel circuit shown in Figure 19. Figure 21 schematically shows the cross-sectional structure at the XXI-XXI' cutting line in Figure 20. Below, we will mainly explain the differences from the structural examples described with reference to Figures 12 and 13.

[0107] The structural examples shown in Figures 20 and 21 include a second capacitive electrode SH between the substrate SUB and the underlying insulating film UC. As shown in Figure 20, in a plan view, the second capacitive electrode SH is positioned below the drive transistor M3, and at least a portion of the second capacitive electrode SH overlaps with the drive transistor M3.

[0108] The potential of the second capacitive electrode SH may be a fixed potential, for example, the ground potential. The polysilicon layer p-Si constituting the drain of the drive transistor M3 and the second capacitive electrode SH form the capacitance Cd3. Although the structural examples shown in Figures 20 and 21 include the capacitive electrode M3C, the capacitive electrode M3C may be omitted.

[0109] Furthermore, bottom gate wirings MCS2 and MCS3 are added to make the oxide semiconductor transistors M12, M17, and M18 dual-gate TFTs. The bottom gate wirings MCS2 and MCS3 are located between the interlayer insulating layer IMD and the interlayer insulating layer ILD. In the example structure shown in the figure, in a plan view, the bottom gate wiring MCS2 and the top gate wiring MDS2 overlap, and the bottom gate wiring MCS3 and the top gate wiring MDS3 overlap. The top gate wiring MDS2 and the bottom gate wiring MCS2, and the top gate wiring MDS3 and the bottom gate wiring MCS3 are connected, for example, outside the display area, and the top gate and bottom gate are driven at the same potential.

[0110] According to this structural example, the Vth drift of oxide semiconductor transistors caused by the generation of fixed charges in polyimide, which is a problem when using a polyimide film as the substrate, can be shielded by the bottom gate wiring, thereby stabilizing the characteristics. By using a dual-gate structure for the oxide semiconductor transistor, the short-channel effect can be suppressed. This makes it possible to shorten the channel of the oxide semiconductor transistor, improves its driving capability, and enables the layout of high-resolution pixels.

[0111] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0112] 10 OLED display device, 100 TFT substrate, 114 cathode electrode formation area, 125 display area, 131 scanning circuit, 134 driver IC, 136 demultiplexer, Cst retention capacitance, E1 OLED element, GI gate insulating layer, ILD interlayer insulating layer, IMD interlayer insulating layer, M1-M8, M12, M14, M15, M17, M18 transistors, N1, N2, N3 nodes, N1S node potential, p-Si polysilicon film, PNL1, PNL2 planarization layer, PAS passivation layer, SUB substrate, UC underlayer, SH second capacitance electrode

Claims

1. A display device, circuit board and Multiple pixel circuits on the aforementioned substrate, Includes, Each pixel circuit of the aforementioned plurality of pixel circuits is Light-emitting element and A first-conductivity type drive transistor, A first switch transistor of second conductivity type connects and disconnects the gate and drain of the aforementioned drive transistor, The second switch transistor of the second conductivity type supplies a reset voltage to the gate of the drive transistor, A retaining capacitance comprising the gate electrode of the drive transistor, an interlayer insulating layer covering the gate electrode, and an intermediate conductor layer disposed on the interlayer insulating layer, An auxiliary capacitor comprising a capacitive electrode disposed beneath the drive transistor, a semiconductor layer of the drive transistor, and an insulating layer between the capacitive electrode and the semiconductor layer of the drive transistor, A display device, including a display device.

2. A display device according to claim 1, The first switch transistor has a dual gate structure, The first switch transistor is, The bottom gate electrode on the interlayer insulating layer, The oxide semiconductor layer covering the bottom gate electrode, The bottom gate electrode and the oxide semiconductor layer are separated by a second interlayer insulating layer, A gate insulating layer covering the oxide semiconductor layer, On the gate insulating layer, a top gate electrode overlaps with the bottom gate electrode in a plan view, A display device, including a display device.

3. A display device according to claim 2, The top gate electrode and the bottom gate electrode are given the same potential. Display device.

4. A display device according to claim 2, The intermediate conductor layer and the bottom gate electrode of the aforementioned holding capacitance are contained in the same high-melting-point metal layer. Display device.

5. A display device according to claim 1, The substrate is made of polyimide. Display device.

6. A display device according to claim 1, Between the power supply line and the drive transistor, the third switch transistor of the first conductivity type, A fourth switch transistor of the first conductivity type between the drive transistor and the light-emitting element, It further includes, The first conductivity type is P-type, and the second conductivity type is N-type. Display device.

7. A display device according to claim 1, A fifth switch transistor having a dual gate structure and the second conductivity type, A sixth switch transistor having a dual gate structure and the second conductivity type, A seventh switch transistor having a dual-gate structure and the second conductivity type, which supplies a reset voltage to the anode of the light-emitting element, It further includes, The fifth switch transistor and the sixth switch transistor are connected in series between the data line and the source of the drive transistor. The first conductivity type is P-type, and the second conductivity type is N-type. Display device.

8. A display device according to claim 1, The aforementioned intermediate conductor layer and the bottom gate electrode of the first switch transistor are composed of the same metal layer. Display device.

9. A display device according to claim 1, The capacitance electrode of the auxiliary capacitor of each pixel circuit is connected to the capacitance electrode of the auxiliary capacitor of the adjacent pixel circuit. Display device.

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