Composite electronic components

Abstract

This mitigates the problem of insufficient coupling between the capacitor and the bump. [Solution] A composite electronic component according to one embodiment of the present invention includes a capacitor including a body containing a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and external electrodes disposed on the body, and a bump disposed on the lower side of the body and connected to the external electrodes, wherein the bump includes a bump body containing a conductive metal, a Ni plating layer disposed on the bump body, a compound layer disposed on the Ni plating layer, and a Sn plating layer disposed on the compound layer, and the Ni plating layer may have irregularities on one or more surfaces among the surface adjacent to the bump body and the surface adjacent to the compound layer.

Description

[Technical Field]

[0001] This invention relates to a composite electronic component. [Background technology]

[0002] Multilayer ceramic capacitors (MLCCs) are chip-type capacitors that are mounted on printed circuit boards of various electronic products, such as video equipment like liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones and mobile phones, on-board chargers (OBCs) in electric vehicles, and DC-DC converters, to charge or discharge electricity.

[0003] Because the dielectric layers contained in multilayer ceramic capacitors have piezoelectric and electrostrictive properties, when a DC or AC voltage is applied to a multilayer ceramic capacitor, a piezoelectric phenomenon may occur between the internal electrodes, causing vibrations.

[0004] Such vibrations are transmitted via the external electrodes of the multilayer ceramic capacitor to the printed circuit board on which the multilayer ceramic capacitor is mounted, generating vibrational noise. This vibrational noise falls within the audible frequency range of 20 to 20,000 Hz, which is unpleasant to humans, and such vibrational noise that causes discomfort to humans is called acoustic noise.

[0005] Conventionally, methods to reduce acoustic noise have included making the upper and lower covers of the main unit different in thickness, or connecting an interposer containing ceramic material to the bottom of the capacitor, or connecting a metal bump to the bottom of the capacitor.

[0006] In particular, in conventional structures such as the one described in Patent Document 1, where a metal bump is bonded to the bottom of the capacitor, the Sn plating layer of the capacitor and the Sn plating layer of the metal bump may melt and form an Sn bulk during the reflow process for bonding the capacitor and the metal bump. This makes uniform soldering difficult, and it can be difficult to ensure sufficient bonding strength between the Ni plating layer of the metal bump and the Sn bulk. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2022-081609 [Overview of the project] [Problems that the invention aims to solve]

[0008] One of the various objectives of this invention is to alleviate the problem of insufficient coupling force between the capacitor and the bump.

[0009] However, the object of the present invention is not limited to the above-described content and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0010] A composite electronic component according to one embodiment of the present invention includes a capacitor including a body containing a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and external electrodes disposed on the body, and a bump disposed on the lower side of the body and connected to the external electrodes, wherein the bump includes a bump body containing a conductive metal, a Ni plating layer disposed on the bump body, a compound layer disposed on the Ni plating layer, and a Sn plating layer disposed on the compound layer, and the Ni plating layer may have irregularities on one or more surfaces among the surface adjacent to the bump body and the surface adjacent to the compound layer. [Effects of the Invention]

[0011] One of the various effects of the present invention is to improve the interfacial bonding force between the capacitor and the bump.

[0012] However, the diverse and significant advantages and effects of the present invention are not limited to the above-described content, and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Brief Description of the Drawings

[0013] [Figure 1] It schematically shows a perspective view of a composite electronic component according to an embodiment of the present invention. [Figure 2] It schematically shows a cross-sectional view taken along the line I-I' of FIG. 1. [Figure 3] It schematically shows a cross-sectional view taken along the line II-II' of FIG. 1. [Figure 4] It schematically shows an enlarged view of the P1 region of FIG. 2 according to an example. [Figure 5] It schematically shows an enlarged view of the P1 region of FIG. 2 according to another example. [Figure 6] It schematically shows an enlarged view of the P1 region of FIG. 2 according to still another example. [Figure 7] It is a schematic diagram showing a method for measuring the 10-point average roughness (Rz) of the first bump compound layer according to an example.

Modes for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be deformed into several other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to an ordinary technician. Therefore, the shape and size of elements in the drawings may be enlarged or reduced (or emphasized or simplified) for a clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0015] For the sake of clearly explaining the present invention in the drawings, parts not related to the explanation are omitted. Also, the sizes and thicknesses of the illustrated components are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited by the illustration. Further, components having the same functions within the scope of the same concept can be described using the same reference numerals. Additionally, throughout the specification, when a certain part "includes" a certain component, it means that other components can be further included rather than excluding other components, unless otherwise stated to the contrary.

[0016] In the drawings, the first direction can be defined as the stacking direction or the thickness direction, the second direction as the length direction, and the third direction as the width direction.

[0017] FIG. 1 schematically shows a perspective view of a composite electronic component according to an embodiment of the present invention. FIG. 2 schematically shows a cross-sectional view taken along the line I-I' of FIG. 1. FIG. 3 schematically shows a cross-sectional view taken along the line II-II' of FIG. 1. FIG. 4 schematically shows an enlarged view of the P1 region of FIG. 2 according to an example. FIG. 5 schematically shows an enlarged view of the P1 region of FIG. 2 according to another example. FIG. 6 schematically shows an enlarged view of the P1 region of FIG. 2 according to still another example. FIG. 7 is a schematic diagram showing a method for measuring the 10-point average roughness (Rz) of a first bump compound layer according to an example.

[0018] Hereinafter, referring to FIGS. 1 to 7, a composite electronic component 1000 according to an embodiment of the present invention and various examples thereof will be described in detail.

[0019] A composite electronic component 1000 according to one embodiment of the present invention includes a capacitor 100 including a body 110 with a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer, and external electrodes 130 and 140 arranged on the body, and bumps 230 and 240 arranged on the lower side of the body and connected to the external electrodes, wherein the bumps include bump bodies 231 and 241 containing a conductive metal, Ni plating layers 232 and 242 arranged on the bump bodies, compound layers 234 and 244 arranged on the Ni plating layers, and Sn plating layers 233 and 243 arranged on the compound layers, and the Ni plating layers may have irregularities on one or more surfaces among the surfaces adjacent to the bump bodies and the surfaces adjacent to the compound layers.

[0020] The capacitor 100 may include a main body 110 and external electrodes 130 and 140 positioned on the main body.

[0021] The main body 110 may include a dielectric layer 111 and internal electrodes 121 and 122, and the dielectric layer 111 and internal electrodes 121 and 122 may be arranged alternately in a first direction. That is, in the present invention, the first direction may mean the stacking direction of the dielectric layer 111 and internal electrodes 121 and 122.

[0022] There are no particular restrictions on the specific shape of the main body 110, but as shown in Figure 1, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedral.

[0023] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction perpendicular to the first direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction perpendicular to the first and second directions.

[0024] On the other hand, as margin regions where internal electrodes 121 and 122 are not placed overlap on the dielectric layer 111, steps are created due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface and the third to sixth surfaces and / or the second surface and the third to sixth surfaces may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 and the third to sixth surfaces 3, 4, 5, and 6 and / or the corners connecting the second surface 2 and the third to sixth surfaces 3, 4, 5, and 6 may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 may be rounded by performing a separate process to round the corners connecting the first face with the third to sixth faces and / or the corners connecting the second face with the third to sixth faces.

[0025] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the composite electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0026] The dielectric layer 111 can be formed by manufacturing a ceramic slurry containing ceramic powder, an organic solvent, and a binder, applying the slurry onto a carrier film and drying it to form a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained, but for example, barium titanate (BaTiO3) based powder can be used as the ceramic powder. To give a more specific example, barium titanate (BaTiO3) based powder is BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1)、Ba(Ti 1-y Cay )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) and Ba(Ti 1-y Zr y )O3 (0 < y < 1) may be one or more of them, and the relative permittivity powder of the CaZrO3 substrate is (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x < 1, 0 < y < 1).

[0027] The average thickness td of the dielectric layer 111 is not particularly limited.

[0028] When aiming at miniaturization and high capacitance of the composite electronic component 1000, the average thickness td of the dielectric layer 111 can be 0.35 μm or less, and in order to improve the reliability of the composite electronic component 1000 under high temperature and high pressure, the average thickness td of the dielectric layer 111 can be 3 μm or more.

[0029] The average thickness td of the dielectric layer 111 can mean the average thickness of one or more of the plurality of dielectric layers.

[0030] The average thickness td of the dielectric layer 111 can be measured by scanning images of the cross-sections (LT cross-sections) of the main body 110 in the first and second directions using a scanning electron microscope (SEM). For example, the average thickness td of the dielectric layer 111 can be the average of the thicknesses measured at the 1 / 4, 2 / 4, and 3 / 4 points, which are four equal parts of the dielectric layer in the length direction, using the point where the center line in the length direction of the capacitance formation section and the center line in the thickness direction of the dielectric layer meet, as a reference, from the images of the dielectric layer extracted from the images scanned with a scanning electron microscope (SEM) of the cross-sections in the first and second directions (LT) cut in the center of the width direction of the main body 110. The average thickness of the dielectric layer can be further generalized by extending such measurements to the two upper and two lower dielectric layers that are equally spaced, using the point where the center line in the length direction of the capacitance formation section and the center line in the thickness direction meet, as a reference.

[0031] Using the dielectric layer at the point where the central line in the length direction and the central line in the thickness direction of the main body intersect as a reference, and considering a total of five dielectric layers (two above and two below), five points are established at equal intervals, two to the left and two to the right of the aforementioned reference point, and the thickness of each point can be measured to determine the average value.

[0032] The main body 110 may include a capacitance forming section Ac which is disposed inside the main body 110 and includes first internal electrodes 121 and second internal electrodes 122 which are arranged alternately with the dielectric layer 111, and cover sections 112 and 113 which are formed on the upper and lower parts of the capacitance forming section Ac in a first direction.

[0033] The capacitance-forming portion Ac, which contributes to the capacitance formation of the capacitor, can be formed by repeatedly stacking multiple first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between, and can represent a region where the first internal electrodes 121 and second internal electrodes 122 overlap in a first direction. Furthermore, the first internal electrode 121 may be positioned at the uppermost end of the capacitance-forming portion Ac in the first direction, and the second internal electrode 122 may be positioned at the lowermost end in the first direction.

[0034] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively. That is, in one embodiment, one end of the first internal electrode 121 in the second direction can be in contact with the third surface 3, and one end of the second internal electrode 122 in the second direction can be in contact with the fourth surface 4.

[0035] Referring to Figure 2, the first internal electrode 121 can be connected to the first external electrode 130, and the second internal electrode 122 can be connected to the second external electrode 140.

[0036] The first internal electrode 121 may be connected to the first external electrode 130 but not to the second external electrode 140, and the second internal electrode 122 may be connected to the second external electrode 140 but not to the first external electrode 130. That is, the first internal electrode 121 may be formed at a certain distance apart on the fourth surface 4, and the second internal electrode 122 may be formed at a certain distance apart on the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 may be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0037] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, Ti, and alloys thereof, but the present invention is not limited thereto.

[0038] The average thickness te of the internal electrodes 121 and 122 is not particularly limited and may vary depending on the purpose. To miniaturize the composite electronic component 1000, the average thickness te of the internal electrodes 121 and 122 can be 0.35 μm or less, and to improve the reliability of the composite electronic component 1000 under high temperature and high pressure, the average thickness te of the internal electrodes 121 and 122 can be 3 μm or more.

[0039] The average thickness te of internal electrodes 121 and 122 can mean the average thickness of one or more internal electrodes among multiple internal electrodes.

[0040] The average thickness te of the internal electrodes 121 and 122 can be measured by scanning images of the cross-sections (LT cross-sections) of the main body 110 in the first and second directions using a scanning electron microscope (SEM). For example, the average thickness te of the internal electrodes 121 and 122 can be the average of the thicknesses measured at the 1 / 4, 2 / 4, and 3 / 4 points, which are four equal parts of the internal electrode lengthwise, based on the point where the center line in the lengthwise direction and the center line in the thickness direction of the capacitance forming section meet, and the internal electrode layer adjacent to it, extracted from images of the internal electrodes scanned with a scanning electron microscope (SEM) at the center of the widthwise direction of the main body 110. The average thickness of the internal electrodes can be further generalized by extending such measurement to the two upper and two lower internal electrodes that are equally spaced based on the point where the center line in the lengthwise direction and the center line in the thickness direction of the capacitance forming section meet, and the internal electrode layer adjacent to it.

[0041] The average thickness te of the internal electrodes 121 and 122 can be calculated by taking an image of the internal electrode layers extracted from a scanning electron microscope (SEM) of a cross-section in the length and thickness direction (LT) of the main body 110 cut in the width direction, and using the first internal electrode layer at the point where the center line in the length direction and the center line in the thickness direction of the main body intersect as a reference, and then measuring the thickness of each of the five internal electrode layers (two layers on top and two layers on the bottom), five points are set at equal intervals around the reference point where the center line in the length direction and the center line in the thickness direction of the main body intersect, and the average thickness can be calculated.

[0042] Referring to Figures 2 and 3, cover portions 112 and 113 can be arranged on the upper and lower surfaces of the volume forming portion Ac in the first direction.

[0043] The cover portions 112 and 113 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0044] The cover portions 112 and 113 can contain the same material as the dielectric layer 111. That is, the cover portions 112 and 113 can contain ceramic materials, for example, barium titanate (BaTiO3) based ceramic materials.

[0045] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. For example, the thickness of each of the cover portions 112 and 113 may be 20 μm or less.

[0046] The average thickness of the cover portions 112 and 113 can represent the size in the first direction, and may be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0047] Referring to Figure 3, margin portions 114 and 115 may be arranged on the side surface of the volume-forming portion Ac.

[0048] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0049] As shown in Figure 3, margin portions 114 and 115 refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the main body 110 in the width-thickness (WT) direction.

[0050] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0051] The margin portions 114 and 115 may be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0052] On the other hand, the widths of the margin portions 114 and 115 do not need to be particularly limited. For example, the average width of the margin portions 114 and 115 may be 20 μm or less.

[0053] The average width of the margin portions 114 and 115 can represent the average size in the third direction of the region where the internal electrode is separated from the fifth surface and the average size in the third direction of the region where the internal electrode is separated from the sixth surface, and can be the average of the sizes in the third direction of the margin portions 114 and 115 measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0054] The external electrodes 130 and 140 may be placed on the main body 110, specifically on the third surface 3 and the fourth surface 4 of the main body 110.

[0055] The external electrodes 130 and 140 may include a first external electrode 130 positioned on the third surface 3 of the main body 110 and a second external electrode 140 positioned on the fourth surface 4 of the main body 110.

[0056] On the other hand, it is not necessary to limit the external electrodes 130 and 140 to those arranged only on the third surface 3 and fourth surface 4 of the main body. Referring to Figures 1 and 2, the first external electrode 130 can be arranged extending from the third surface 3 of the main body 110 to a portion of the first surface 1, second surface 2, fifth surface 5, and sixth surface 6, and the second external electrode 140 can be arranged extending from the fourth surface to a portion of the first surface 1, second surface 2, fifth surface 5, and sixth surface 6.

[0057] The external electrodes 130 and 140 may include electrode layers 131 and 141 that are positioned on the main body 110 and connected to the internal electrodes 121 and 122.

[0058] Specifically, the first internal electrode 130 may include a first electrode layer 131 disposed on the main body 110 and connected to the first internal electrode 121, and the second internal electrode 140 may include a second electrode layer 141 disposed on the main body 110 and connected to the second internal electrode 122.

[0059] The first electrode layer 131 and the second electrode layer 141 are connected to the internal electrodes 121 and 122, respectively, and can play a role in ensuring the electrical connectivity between the external electrodes 130 and 140 and the internal electrodes 121 and 122.

[0060] The first electrode layer 131 and the second electrode layer 141 may contain a conductive metal. The conductive metal is not particularly limited and can be any material with excellent electrical conductivity. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof. To ensure electrical conductivity and bonding strength through alloy formation with the Ni internal electrode, the electrode layers 131 and 141 may contain Cu.

[0061] More specific examples of the first electrode layer 131 and the second electrode layer 141 include the fact that the electrode layers may be fired electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0062] The first electrode layer 131 and the second electrode layer 141 may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Furthermore, the electrode layers may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0063] A plating layer can be placed on the electrode layers 131 and 141. The plating layer can improve the airtightness and mountability of the composite electronic component 1000, and can also improve the bonding strength with the bumps 230 and 240, which will be described later. The specific structure of the plating layer will be described later.

[0064] Referring to Figure 2, the bumps 230 and 240 are positioned on the underside of the capacitor 100 and can be connected to the external electrodes 130 and 140. The bumps 230 and 240 are positioned on the underside of the capacitor 100 and can play a role in reducing or absorbing vibrations transmitted from the substrate to the capacitor 100.

[0065] Bumps 230 and 240 can contain components that do not melt during the solder reflow process, and can form multiple layers to facilitate adhesion with the capacitor 100.

[0066] According to one embodiment of the present invention, the bumps 230 and 240 may include bump bodies 231 and 241 containing a conductive metal. The type of conductive metal included in the bump bodies 231 and 241 is not particularly limited, but the bump bodies 231 and 241 may include Cu as the conductive metal to improve vibration absorption characteristics.

[0067] On the other hand, the bumps 230 and 240 according to one embodiment can perform the function of electrodes themselves and therefore can have excellent electrical conductivity. Specifically, the bump bodies 231 and 241 can be made substantially of conductive metals only. For example, the bump bodies 231 and 241 can contain Cu and O, but the O content in the bump bodies 231 and 241 may be at a level of 0.01 at% or less relative to Cu.

[0068] In conventional methods for connecting capacitor 100 with bumps 230 and 240, a method can be used in which a Sn plating layer is formed on capacitor 100 and bumps 230 and 240, and then melted through a reflow process. In this case, the Sn plating layer formed on the capacitor and the Sn plating layer formed on the bumps are melted to form a bulk, thereby allowing capacitor 100 and bumps 230 and 240 to be joined. However, in the reflow process, it is difficult to uniformly melt the Sn plating layers formed on capacitor 100 and bumps 230 and 240, and the bonding strength between the bulk Sn plating layer and the Ni plating layer contained in bumps 230 and 240 may be insufficient, making it difficult to form a sufficient bonding strength between capacitor 100 and bumps 230 and 240.

[0069] Therefore, in one embodiment of the present invention, the bumps 230 and 240 include bump bodies 231 and 241 containing a conductive metal, Ni plating layers 232 and 242 disposed on the bump bodies 231 and 241, compound layers 234 and 244 disposed on the Ni plating layers 232 and 242, and Sn plating layers 233 and 243 disposed on the compound layers 234 and 244, and the Ni plating layers 232 and 242 have irregularities on one or more surfaces among the surfaces adjacent to the bump bodies 231 and 241 and the surfaces adjacent to the compound layers 234 and 244, thereby improving the bonding force between the electrode layers forming the bumps 230 and 240, and improving the bonding force between the bumps 230 and 240 and the capacitor 100.

[0070] On the other hand, in the present invention, the meaning of a specific surface being "uneven" can mean that the surface has a surface roughness sufficient to maintain interlayer bonding strength even after undergoing a heat treatment process at approximately 270°C, such as a reflow process. Specifically, the meaning of a specific surface being "uneven" can mean that the ten-point average roughness (Rz) of the specific surface is 1.3 μm or more.

[0071] The compound layers 234 and 244 may be layers formed by the reaction of a portion of the Ni plating layer 232 and the Sn plating layer 233. In one embodiment, the compound layers 234 and 244 may contain an intermetallic compound (IMC) containing Ni and Sn.

[0072] The external electrodes 130 and 140 of the capacitor 100 may include electrode layers 131 and 141 that are in contact with one end of the internal electrodes 121 and 122, Ni plating layers 132 and 142 placed on the electrode layers 131 and 141, and Sn plating layers 133 and 143 placed on the Ni plating layers 132 and 142.

[0073] The Ni plating layers 132 and 142 can play a role in relieving interlayer stress in the external electrodes 130 and 140 and improving airtightness.

[0074] The Sn plating layers 133 and 143 improve mounting characteristics and can play a role in forming a bond with the bumps 230 and 240. Specifically, the Sn plating layers 133 and 143 of the external electrodes 130 and 140 can come into contact with the Sn plating layers 233 and 243 of the bumps 230 and 240.

[0075] In the following, with reference to Figures 4 to 6, various embodiments in which the Ni plating layers 232 and 242 have irregularities on one or more surfaces adjacent to the bump bodies 231 and 241 and the compound layers 234 and 244 will be described in detail. However, the present invention is not intended to be limited to the embodiments shown in Figures 4 to 6.

[0076] Referring to Figure 4, the Ni plating layer 232 can have irregularities on the surface adjacent to the bump body 231.

[0077] The method for forming the surface of the Ni plating layer 232 adjacent to the bump body 231 to have irregularities is not particularly limited. For example, the surface of the bump body 231 can be etched by physical or chemical means to form irregularities on the surface of the Ni plating layer 232 adjacent to the bump body 231. More specifically, chemical etching (etching) and physical polishing (grinding, polishing) using abrasive materials can be used.

[0078] Between the Ni plating layer 232 and the Sn plating layer 233, a compound layer 234 can be formed by the reaction of a portion of the Ni plating layer 232 and the Sn plating layer 233, so the bonding strength between the Ni plating layer 232 and the Sn plating layer 233 can be relatively good. On the other hand, a certain partial alloy can be formed between the bump body 231 and the Ni plating layer 232 by the components of the bump body 231, but unless a separate intermetallic compound is formed, it may be difficult to ensure sufficient bonding strength between the bump body 231 and the Ni plating layer 232, and the low bonding strength between the bump body 231 and the Ni plating layer 232 may make it difficult to maintain the bond between the capacitor 100 and the bumps 230 and 240 during the reflow process of the composite electronic component.

[0079] However, in one embodiment, when there are irregularities on the surface adjacent to the Ni plating layer 232 bump body 231, the above-mentioned problem caused by the low bonding force between the Ni plating layer 232 bump body 231 can be mitigated, and as a result, sufficient bonding force can be ensured between the capacitor 100 and the bumps 230 and 240.

[0080] Referring to Figure 4, the ten-point average roughness of the Ni plating layer 232 adjacent to the bump body 231 may be greater than the ten-point average roughness of the compound layer 234 adjacent to the surface. In this case, even if irregularities are formed only on the surface of the bump body 231, sufficient bonding force can be ensured between the capacitor 100 and the bumps 230 and 240, so an additional irregularity formation process does not need to be performed.

[0081] Referring to Figure 5, the Ni plating layer 232 can have irregularities on the surface adjacent to the compound layer 234.

[0082] The structure in which the Ni plating layer 232 has irregularities on the surface adjacent to the compound layer 234 can be induced by forming the surface irregularities of the Ni plating layer 232 first, followed by the formation of the compound layer 234. In this case, the internal bonding force of the bumps 230 and 240 can be improved by preventing the separation of the Ni plating layer 232 and the compound layer 234.

[0083] There are no particular limitations on the method for making the Ni plating layer 232 have irregularities on the surface adjacent to the compound layer 234. For example, after forming the Ni plating layer 232 on the bump body 231 and before forming the Sn plating layer 233, the surface of the Ni plating layer 232 can be etched by physical or chemical means to form irregularities on the surface of the Ni plating layer 232 adjacent to the compound layer 234. More specifically, chemical etching methods (etching) and physical polishing methods (grinding, polishing) using abrasive materials can be used.

[0084] Referring to Figure 6, the Ni plating layer 232 can have irregularities on the entire surface adjacent to the bump body 231 and the surface adjacent to the compound layer 234.

[0085] There are no particular limitations on how the Ni plating layer 232 is made to have irregularities on the entire surface adjacent to the bump body 231 and the surface adjacent to the compound layer 234.

[0086] Before forming the Ni plating layer 232, the surface of the bump body 231 can be etched by physical or chemical means to create irregularities on the surface of the Ni plating layer 232 adjacent to the bump body 231. After this, by adjusting conditions such as the plating time of the Ni plating layer 232, it is possible to form a Ni plating layer 232 with irregularities on the entire surface adjacent to the bump body 231 and the surface adjacent to the compound layer 234, as shown in Figure 6. On the other hand, the compound layer 234 can be formed by forming a Sn plating layer 233 on the Ni plating layer 232 and undergoing a reflow process, or by undergoing a separate heat treatment process.

[0087] The compound layer 234 formed on the Ni plating layer 232, which has irregularities on the entire surface adjacent to the bump body 231 and the surface adjacent to the compound layer 234, can have irregularities on the entire surface adjacent to the Ni plating layer 232 and the surface adjacent to the Sn plating layer 233. The compound layer 234 can be formed by adjusting the temperature or process time during the reflow process or heat treatment process so that it has irregularities on the entire surface adjacent to the Ni plating layer 232 and the surface adjacent to the Sn plating layer 233. In this way, when the compound layer 234 is formed with irregularities on the entire surface adjacent to the Ni plating layer 232 and the surface adjacent to the Sn plating layer 233, irregularities are formed at all interfaces of the bump body 231, the Ni plating layer 232, the compound layer 234, and the Sn plating layer 233, resulting in an even more pronounced improvement in the bonding strength between the bumps 230, 240 and the capacitor 100.

[0088] Referring to Figure 6, the compound layer 234 can be formed thinly along the irregularities of the Ni plating layer 232. In one embodiment, the compound layer 234 can be positioned to cover the Ni plating layer 232. This further enhances the effect of improving the coupling force between the bumps 230, 240 and the capacitor 100.

[0089] A specific configuration in which the compound layer 234 is arranged to cover the Ni plating layer 232 is, for example, one in which the connectivity of the compound layer 234 is 95% or more. In this case, the connectivity of the compound layer 234 can mean the ratio of the sum of the lengths in the second direction of each compound layer 234 formed in a particular region to the length in the second direction of the particular region. The particular region is a cross-section in the first and second directions polished to the center of the third direction of the composite electronic component, and is a region obtained by dividing the compound layer 230 located on the upper or lower surface of the bumps 230, 240 into five equal parts, which can mean the 2 / 5 region, 3 / 5 region, and 4 / 5 region, but is not limited to this, and can be selected from the compound layer 230 located on the side surface of the bumps 230, 240.

[0090] On the other hand, the ten-point mean roughness (Rz) in this specification can be calculated by adding the absolute value of (Yv1+Yv2+Yv3+Yv4+Yv5), which is the distance from the average line m of the top five peaks from the highest peak of the sampled portion relative to the reference length l, to the distance from the average line m of the bottom five valleys from the lowest valley bottom of the sampled portion relative to the reference length l, as shown in Figure 7, and dividing by 5.

[0091] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0092] Furthermore, the expression "one embodiment" used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct features of each embodiment. However, the above-presented embodiments do not preclude their implementation in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a contradictory or contrary explanation of that matter in the other embodiment.

[0093] The terms used in this disclosure are used solely to illustrate one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0094] 1000 Composite Electronic Components 100 Capacitors 110 Main Unit 111 Dielectric layer 121, 122 Internal electrode 112, 113 Cover section 114, 115 Margin section 130, 140 external electrode 131, 141 electrode layer 132, 142, 232, 242 Ni plating layer 133, 143, 233, 243 Sn plating layer 234, 244 compound layer 230, 240 bump

Claims

1. A capacitor comprising a dielectric layer, a body including internal electrodes arranged alternately with the dielectric layer, and external electrodes arranged on the body, The main body includes a bump positioned on the lower side and connected to the external electrode, The bump comprises a bump body containing a conductive metal, a Ni plating layer disposed on the bump body, a compound layer disposed on the Ni plating layer, and a Sn plating layer disposed on the compound layer. The Ni plating layer has irregularities on one or more surfaces, including the surface adjacent to the bump body and the surface adjacent to the compound layer, in a composite electronic component.

2. The composite electronic component according to claim 1, wherein the ten-point average roughness of the surface having irregularities of the Ni plating layer is 1.3 μm or more.

3. The composite electronic component according to claim 1, wherein the ten-point average roughness of the Ni plating layer adjacent to the bump body is greater than the ten-point average roughness of the compound layer adjacent to the surface.

4. The composite electronic component according to claim 1, wherein the ten-point average roughness of the Ni plating layer adjacent to the compound layer is greater than the ten-point average roughness of the surface adjacent to the bump body.

5. The composite electronic component according to claim 1, wherein the Ni plating layer has irregularities on the entire surface adjacent to the bump body and the surface adjacent to the compound layer.

6. The composite electronic component according to claim 5, wherein the compound layer has irregularities on the entire surface adjacent to the Ni plating layer and the surface adjacent to the Sn plating layer.

7. The composite electronic component according to claim 5, wherein the compound layer covers the Ni plating layer.

8. The composite electronic component according to claim 5, wherein the connectivity of the compound layer is 95% or more.

9. The composite electronic component according to any one of claims 1 to 8, wherein the compound layer comprises an intermetallic compound containing Ni and Sn.

10. The external electrode includes an electrode layer in contact with one end of the internal electrode, a Ni plating layer disposed on the electrode layer, and a Sn plating layer disposed on the Ni plating layer. The composite electronic component according to any one of claims 1 to 8, wherein the Sn plating layer of the external electrode and the Sn plating layer of the bump are in contact.

11. The aforementioned bump body comprises Cu, a composite electronic component according to any one of claims 1 to 8.

12. The bump body includes Cu and O, The composite electronic component according to any one of claims 1 to 8, wherein the content of O relative to Cu is 0.01 at% or less.

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