Integrated scaling and stretching platform for optimizing monolithic and / or heterogeneous integration on a single semiconductor die.

Abstract

A single monolithic die is provided, containing a first circuit manufactured based on a first technology node. [Solution] The die area of ​​a single monolithic die is smaller than the die area of ​​another monolithic die having a second circuit manufactured based on a first technology node, the first circuit being the same as the second circuit, and the first circuit being an SRAM circuit, a logic circuit, a combination of an SRAM and a logic circuit, or a main functional block circuit.

Description

[Technical Field]

[0001] The present invention relates to a monolithic semiconductor die, and more particularly to an optimized monolithic semiconductor die based on an integrated scaling and stretching platform that can effectively reduce the size of SRAM circuits and logic circuits within the monolithic semiconductor die without reducing the minimum shape. [Background technology]

[0002] IT systems are rapidly evolving in all kinds of businesses and companies, including factories, healthcare, and transportation. System-on-a-chip (SOC) or artificial intelligence (AI) is now the cornerstone of IT systems, enabling smarter factories, improved patient outcomes, and enhanced safety in autonomous vehicles. Data from manufacturing equipment, sensors, and machine vision systems can easily reach one petabyte per day. Therefore, handling such petabyte-scale data requires high-performance computing (HPC), SOCs, or AI chips.

[0003] Generally, AI chips can be classified into Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), and Application Specific IC (ASIC). Originally, GPUs were designed for graphics processing applications through parallel processing, but they have increasingly been used for AI learning. The learning speed and efficiency of GPUs are generally said to be 10 to 1000 times that of general-purpose CPUs. FPGAs have logic blocks that interact with each other, and engineers can design them to support specific algorithms and are suitable for AI inference. Although FPGAs have the disadvantages of being large in size, slow in speed, and high in power consumption, they are preferred over ASIC design because the time to market is short, the cost is low, and the flexibility is high. Due to the high flexibility of FPGAs, any part of the FPGA can be partially programmed according to requirements. The inference speed and efficiency of FPGAs are 10 to 100 times that of general-purpose CPUs. On the other hand, ASICs are generally more efficient than FPGAs because they directly adjust the circuit. In the case of customized ASICs, the learning / inference speed and efficiency can be 10 to 1000 times that of general-purpose CPUs. However, unlike FPGAs, which are easy to customize according to the evolution of AI algorithms, ASICs tend to gradually become obsolete as new AI algorithms are developed.

[0004] Regardless of whether it's a GPU, FPGA, or ASIC (or similar SOC, CPU, NPU, etc.), logic circuits and SRAM circuits are the main circuits, and their combination accounts for approximately 90% of the AI ​​chip size. The remaining 10% of the AI ​​chip can include input / output pad circuits. However, scaling process / technology nodes for manufacturing AI chips are increasingly necessary to provide better efficiency and performance, and to enable AI machines to learn efficiently and quickly. While improvements in integrated circuit performance and cost have been achieved primarily through process scaling techniques following Moore's Law, scaling by technology nodes ("λ" or "F") and minimum shapes from 28nm to 3-5nm has encountered many technical difficulties, dramatically increasing the R&D and equipment investment costs in the semiconductor industry.

[0005] For example, achieving the scaling of SRAM devices to increase recording density, reducing the operating voltage (VDD) to lower standby power consumption, and improving yield—all necessary for realizing high-capacity SRAM—is becoming increasingly difficult. When miniaturizing to 28nm (or less), the manufacturing process becomes a challenge. Figure 1A shows a 6-transistor (6-T) SRAM cell architecture, consisting of two cross-coupling inverters. (PMOS pull-up transistors PU-1, PU-2, NMOS pull-down transistors PD-1, PD-2) and two access transistors (NMOS passgate transistors PG-1 and PG-2). The high-level voltage VDD is coupled to the PMOS pull-up transistors PU-1, PU-2, and the low-level voltage VSS is coupled to the NMOS pull-down transistors PD-1, PD-2. When the word line (WL) is activated (i.e., when a row in the array is selected), the access transistors turn on and connect the storage nodes (node 1 / node 2) to the bit lines (BL, BL bar) running vertically. Figure 1B is a "bar graph" showing the arrangement and connection of the six transistors of the SRAM. The bar graph usually includes only the active regions (vertical gray bars) and the gate lines (horizontal white bars). Of course, some are directly connected to the six transistors, while on the other hand, some are connected to the word line (WL), bit lines (BL and BL bar), high-level voltage VDD, low-level voltage VSS, etc., and the number of contacts is still large.

[0006] When the minimum feature size becomes small, λ 2 or F 2Some of the reasons why the total area of ​​an SRAM cell represented by can be dramatically increased can be explained as follows. Conventional 6T-SRAM connects six transistors with multiple wirings, and its first wiring layer M1 connects the gate level (hereinafter referred to as "gate") of the transistor to the diffusion level (generally referred to as "diffusion") of the source and drain regions. Without increasing the die size with M1 alone, it is necessary to add a second wiring layer M2 and / or a third wiring layer M3 to facilitate signal transmission (word lines (WL) and / or bit lines (BL and BL bars), etc.), and a structural via 1 made of a certain seed conductive material is formed to connect M2 to M1. Thus, a vertical structure formed through a contact (Con) connection from diffusion to M1, namely "diffusion-contact-M1", exists. Similarly, another structure that connects the gate to M1 with a contact structure can be formed as "gate-contact-M1". Also, when it is necessary to form a connection structure that connects from the M1 wiring to the M2 wiring through via 1, we will call it "M1-via 1-M2". More complex wiring structures from the gate level to the M2 wiring can be described as "gate-contact-M1-via1-M2". Furthermore, multilayer wiring systems may have structures such as "M1-via1-M2-via2-M3" or "M1-via1-M2-via2-M3-via3-M4". Since the gates and diffuses of the two access transistors (NMOS pass gate transistors PG-1 and PG-2 in Figure 1A) are connected to word lines (WL) and / or bit lines (BL and BL bars) located in the second wiring layer M2 or the third wiring layer M3, in conventional SRAM, such metal connections must first pass through wiring layer M1. In other words, in state-of-the-art SRAM wiring systems, gates or diffuses may not be able to connect directly to M2 without bypassing the M1 structure. As a result, the space required between one M1 trace and another increases the die size, and in some cases, this wiring connection may extend beyond the M1 region, hindering the intention of efficient channeling that directly uses M2.Furthermore, it is difficult to form a self-aligning structure between via 1 and the contact, and at the same time, both via 1 and the contact are connected to their own independent wiring systems.

[0007] Furthermore, as shown in Figure 2A, in conventional 6T-SRAM cells, at least one NMOS transistor and one PMOS transistor are placed in adjacent regions of a p-type substrate and a portion of an n-type well, which are formed in close proximity. This creates a junction structure called an n+ / p / n / p+ parasitic bipolar device, extending from the n+ region of the NMOS transistor to the p-type well, the adjacent n-type well, and further to the p+ region of the PMOS transistor. If large noise occurs at the n+ / p junction or p+ / n junction, an unusually large current may flow abnormally through this n+ / p / n / p+ junction, potentially causing some CMOS circuits to stop working or the entire chip to malfunction. This abnormal phenomenon, called latch-up, negatively impacts CMOS operation and therefore needs to be avoided. To improve resistance to latch-up, which is a weakness of CMOS, one method is to increase the distance from the n+ region to the p+ region. However, increasing the distance from the n+ region to the p+ region to avoid the latch-up problem also increases the size of the SRAM cell.

[0008] Even when the manufacturing process is miniaturized to 28nm or less (the so-called "minimum shape", "λ", "F"), due to the above-mentioned problems such as interference between the sizes of the contacts and between the layouts of the metal wires connecting the word lines (WL), bit lines (BL and BL bars), high-level voltage VDD, low-level voltage VSS, etc., as shown in Figure 2B, when the minimum shape becomes smaller, λ 2 or F 2 The total area of ​​the SRAM cells represented by this formula increases dramatically (Non-Patent Literature 1).

[0009] A similar situation occurs with the scaling of logic circuits. Scaling logic circuits to increase recording density, reducing the operating voltage (Vdd) to decrease standby power consumption, and improving yield—all necessary for realizing high-capacity logic circuits—are becoming increasingly difficult to achieve. Standard cells are fundamental elements commonly used in logic circuits. Standard cells may contain basic logic function cells (inverter cells, NOR cells, NAND cells, etc.). Similarly, even when manufacturing processes are miniaturized to below 28nm, interference between contact size and metal wire layout causes λ to become smaller as the minimum shape decreases. 2 or F 2 The total area of ​​the standard cell, as shown, increases dramatically. Figure 3A is a bar graph showing the arrangement and connections of PMOS and NMOS transistors in a 5nm (UHD) standard cell from a semiconductor company (Samsung). The bar graph mainly shows the active region (horizontal bars) and gate line (vertical white bars). Hereafter, the active region will be called a "fin". Of course, some are directly coupled to the PMOS or NMOS transistor, while others are coupled to the input terminal, output terminal, high-level voltage Vdd, low-level voltage VSS (or ground "GND"), etc., leaving many contacts. In particular, each transistor has two active regions or fins (shown as horizontal dark gray bars), which form the transistor channel, allowing the W / L ratio to be maintained within an acceptable range.

[0010] The area size of the inverter cell is equal to X×Y, where X = 2×Cpp, Y = Cell_Height, and Cpp is the distance of the Contacted Poly Pitch. It can be seen that for the PMOS / NMOS of this standard cell, some active regions or fins (shown as thin gray horizontal bars and called "dummy fins") are not utilized, and the potential reason is considered to be related to the latch-up problem between PMOS and NMOS. Therefore, the latch-up distance between PMOS and NMOS in Figure 3A is 3×Fp, where Fp is the fin pitch. Based on the available data regarding Cpp (54nm) and Cell_Height (216nm) of the Samsung 5nm (UHD) standard cell, the cell area is 23328nm 2 (or 933.12λ 2 , where lambda (λ) is the minimum feature size such as 5nm). Figure 3B shows the Samsung 5nm (UHD) standard cell and its dimensions. As shown in Figure 3B, the latch-up distance between PMOS and NMOS is 15λ, Cpp is 10.8λ, and the height of the cell is 43.2λ.

[0011] Figure 3C shows the scaling trend of the area size (2Cpp×cell Height) by process technology node in three semiconductor manufacturing factories. As the technology node becomes smaller (e.g., from 22nm to 5nm), it is obvious that the area size of the conventional standard cell (2Cpp×Cell_Height) represented by λ 2 increases dramatically. In the conventional standard cell, the smaller the technology node, the larger the area size represented by λ 2 . The reason for such a sharp increase in λ 2 is considered to be that as λ becomes smaller, it is difficult for the sizes of gate contacts / source contacts / drain contacts to be proportionally reduced in both SRAM and logic circuits, the latch-up distance between PMOS and NMOS is difficult to be proportionally reduced, and metal layers interfere when λ becomes smaller, etc.

[0012] From another perspective, SOCs, AIs, Network Processing Units (NPUs), GPUs, CPUs, FPGAs, and other components are currently monolithically integrated, incorporating as many circuits as possible. However, as shown in Figure 4A, maximizing the die area of ​​each monolithic die is limited by the maximum reticle size of the lithography stepper, which is difficult to expand due to the state-of-the-art existing photolithography exposure equipment. For example, as shown in Figure 4B, current i193 and EUV lithography steppers have their maximum reticle sizes, so the Scanner Maximum Field Area (SMFA) of a monolithic SOC die is 26mm x 33mm or 858mm. 2 (https: / / en.wikichip.org / wiki / mask) However, for AI applications, high-end consumer GPUs are 500-600mm 2 It appears to be operating in this way. As a result, within the limitations of SMFA, it is becoming more difficult, or even impossible, to configure two or more major functional blocks, such as GPUs and FPGAs (for example), on a single monolithic die. Also, the most widely used 6-transistor CMOS SRAM cells are quite large in order to also sufficiently enlarge the eSRAM size for both major blocks. Furthermore, there is a need to expand the capacity of external DRAM, but discrete PoP (Package-on-Package, e.g., HBM to In SOC (State-of-Chip) or POD (Package DRAM on SOC Die), limitations remain, such as poor signal routing between dies and packages, making it difficult to achieve the desired performance. [Prior art documents] [Non-patent literature]

[0013] [Non-Patent Document 1] J. Chang et al., "15.1 A5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assisted Circuitry Schemes for High-Density and Low-VMIN Applications," 2020 IEEE International Semiconductor Circuits Conference (ISSCC), 2020, pp. 238-240. [Overview of the project] [Problems that the invention aims to solve]

[0014] Therefore, in order to solve the above problems and realize more powerful and efficient SOCs and AI single chips of the near future, it is necessary to propose an optimal monolithic / heterogeneous integration structure for a single semiconductor die that optimizes the dimensions of the standard cells / SRAM cells of a monolithic SOC die within the limitations of SMFA without reducing the technology node or minimum shape λ. [Means for solving the problem]

[0015] Embodiments of the present invention provide a first monolithic die comprising a first circuit manufactured based on a first technology node, wherein the die area of ​​the first monolithic die is smaller than the die area of ​​a second monolithic die having a second circuit manufactured based on the first technology node, the first circuit being identical to the second circuit, and the first circuit being an SRAM circuit, a logic circuit, a combination of an SRAM and a logic circuit, or a major functional block circuit.

[0016] According to another aspect of the present invention, the second circuit occupies an area between 20% and 90% of the die area of ​​the second monolithic die.

[0017] According to another aspect of the present invention, the first circuit is the Ynm of the first monolithic die. 2 The second circuit occupies the second monolithic die at Xnm 2 It occupies a certain area, and X > Y.

[0018] According to another aspect of the present invention, Y is between 20% and 90% of X.

[0019] A further embodiment of the present invention provides a first monolithic die comprising a first circuit formed on the first monolithic die and a second circuit formed on the first monolithic die, wherein the first monolithic die has a first scanner maximum exposure area, the first circuit occupies a first portion of the first scanner maximum exposure area, the second circuit occupies a second portion of the first scanner maximum exposure area, the scanner maximum exposure area of ​​the first monolithic die is the same as the second scanner maximum exposure area of ​​the second monolithic die, the second monolithic die has the first circuit, and the area of ​​the first circuit in the second monolithic die is between 50% and 90% of the second scanner maximum exposure area of ​​the second monolithic die.

[0020] According to another aspect of the present invention, the first circuit is an SRAM circuit, a combination of an SRAM circuit and a logic circuit, or a main functional block circuit.

[0021] According to another aspect of the present invention, the first circuit is selected from the group consisting of GPU, CPU, TPU, NPU, and FPGA.

[0022] According to another aspect of the present invention, the maximum exposure area of ​​the first scanner or the maximum exposure area of ​​the second scanner is 26 mm × 33 mm or 858 mm 2 The following applies:

[0023] Yet another embodiment of the present invention provides a first monolithic die comprising a first circuit manufactured by performing a predetermined manufacturing process based on a first technology node, wherein the die area of ​​the first monolithic die is smaller than the die area of ​​a second monolithic die comprising a second circuit made based on the first technology node without performing the predetermined manufacturing process.

[0024] According to another aspect of the present invention, the first circuit is the same as the second circuit.

[0025] According to another aspect of the present invention, the second circuit occupies an area between 20% and 90% of the die area of ​​the second monolithic die.

[0026] According to another aspect of the present invention, the first circuit is the Ynm of the first monolithic die. 2 The second circuit occupies the second monolithic die at Xnm 2 It occupies a certain area, and X > Y.

[0027] According to another aspect of the present invention, Y is 20% to 90% of X.

[0028] According to another aspect of the present invention, the first circuit is an SRAM circuit, a logic circuit, a combination of an SRAM and a logic circuit, or a main functional block circuit.

[0029] A further embodiment of the present invention provides a monolithic die comprising: a first processing circuit formed on the monolithic die, comprising a plurality of first logic core circuits, each first logic core circuit corresponding to a first cache memory; and a second processing circuit formed on the monolithic die, comprising a plurality of second logic core circuits, each second logic core circuit corresponding to a second cache memory; wherein the scanner maximum exposure area of ​​the monolithic die is defined by a specific technology node.

[0030] According to another aspect of the present invention, the maximum scanner exposure area of ​​the monolithic die is 26 mm × 33 mm or 858 mm². 2 The following applies:

[0031] According to another aspect of the present invention, the primary function performed by the first processing unit circuit is different from the primary function performed by the second processing unit circuit.

[0032] According to another aspect of the present invention, the first or second processing unit circuit is selected from the group consisting of GPU, CPU, TPU, NPU, and FPGA.

[0033] According to another aspect of the present invention, the monolithic die further comprises a third cache memory, the third cache memory being configurable and utilized by the first and second processing circuits during the operation of the monolithic die.

[0034] According to another aspect of the present invention, the first cache memory, the second cache memory, and the third cache memory are composed of SRAM.

[0035] A further embodiment of the present invention provides a monolithic die comprising: a first processing unit circuit formed on the monolithic die, comprising a plurality of first logic core circuits, each first logic core circuit corresponding to a first cache memory; and a second processing unit circuit formed on the monolithic die, comprising a plurality of second logic core circuits, each second logic core circuit corresponding to a second cache memory, wherein the primary function performed by the first processing unit circuit is different from the primary function performed by the second processing unit circuit.

[0036] According to another aspect of the present invention, the first or second processing unit circuit is selected from the group consisting of GPU, CPU, TPU, NPU, and FPGA.

[0037] According to another aspect of the present invention, the monolithic die further comprises a third cache memory, the third cache memory being shared and utilized by the first and second processing circuits during the operation of the monolithic die.

[0038] A further embodiment of the present invention provides a monolithic die, the monolithic die comprising a first processing unit circuit formed on the monolithic die, comprising a plurality of first logic core circuits, each first logic core circuit comprising a first processing unit circuit corresponding to a low-level cache memory and a high-level cache memory utilized by the first processing unit circuit, wherein the sum of the total size of the low-level cache memory and the size of the high-level cache memory is at least 64 MB.

[0039] According to another aspect of the present invention, the maximum scanner exposure area of ​​the monolithic die is defined by a photolithography exposure tool used in the technical processing node.

[0040] According to another aspect of the present invention, the maximum scanner exposure area of ​​the monolithic die is 26 mm × 33 mm or 858 mm². 2 The following applies:

[0041] According to another aspect of the present invention, the low-level cache memory includes an L1 cache and an L2 cache, wherein the size of the L2 cache is larger than the size of the L1 cache.

[0042] According to another aspect of the present invention, the high-level cache memory includes an L3 cache shared and utilized by a plurality of first logic core circuits.

[0043] According to another aspect of the present invention, the monolithic die is a second processing unit circuit formed on the monolithic die, comprising a plurality of second logic core circuits, each second logic core circuit further comprising a second processing unit circuit corresponding to a second cache memory, the high-level cache memory including an L4 cache shared and utilized by the first and second processing unit circuits.

[0044] According to another aspect of the present invention, the L4 cache is shared and utilized by the first processing unit circuit and the second processing unit circuit, depending on the setting of the mode register.

[0045] A further embodiment of the present invention provides a method for manufacturing a monolithic die having a set of CMOS circuits, the method comprising: performing a first set of steps to re-examine the dimensions of a plurality of transistors in the set of CMOS circuits of a monolithic die based on a conventional technology node; and performing a second set of steps to wire the plurality of transistors to other metal layers in the monolithic die based on a conventional technology node, wherein the new size of the monolithic die manufactured by the first set of steps and the second set of steps is smaller than the original size of another monolithic die having the same set of CMOS circuits manufactured based on a conventional technology node without performing the first set of steps and the second set of steps.

[0046] According to another aspect of the present invention, the size of a new monolithic die produced by the first set of steps and the second set of steps is less than 50% of the original size of another monolithic die.

[0047] According to another aspect of the present invention, the size of a novel monolithic die produced by a first set of processes and a second set of processes is less than 35% of the original size of another monolithic die when the conventional technology node is 5 nm.

[0048] A further embodiment of the present invention provides a method for manufacturing a monolithic die having a scanner maximum exposure area defined by a conventional technology node, the method comprising: performing a first set of steps to re-examine the dimensions of a plurality of transistors in a monolithic die based on a conventional technology node; and performing a second set of steps to wire the plurality of transistors to other metal layers in the monolithic die based on a conventional technology node, wherein the SRAM capacity of the monolithic die manufactured by the first set of steps and the second set of steps is greater than the capacity of a monolithic die manufactured based on a conventional technology node without performing the first set of steps and the second set of steps.

[0049] According to another aspect of the present invention, a monolithic die having a scanner maximum exposure area defined by a conventional technology node comprises a first processing circuit and a second processing circuit, wherein the primary function performed by the first processing circuit is different from the primary function performed by the second processing circuit.

[0050] A further embodiment of the present invention provides a platform for reconfiguring the memory architecture of a chip system, the chip system comprising a first monolithic die connected to a first DRAM memory having a first predetermined capacity, the first monolithic die comprising a first logic circuit and a first SRAM memory. The platform comprises a second monolithic die connected to a second DRAM memory having a second predetermined capacity, the second monolithic die comprising a second logic circuit and a second SRAM memory. The first monolithic die has a scanner maximum exposure area based on a target technology node, the second monolithic die has a scanner maximum exposure area based on a target technology node, the first logic circuit is the same as the second logic circuit, the area of ​​the first logic circuit in the first monolithic die is larger than the area of ​​the second logic circuit in the second monolithic die, the capacity of the first SRAM memory is smaller than the capacity of the second SRAM memory, and the second predetermined capacity of the second DRAM memory is smaller than the first predetermined capacity of the first DRAM memory.

[0051] According to another aspect of the present invention, the second DRAM memory is externally mounted on the second monolithic die, and the second DRAM memory and the second monolithic die are enclosed in a single package. Furthermore, the second DRAM memory is an embedded DRAM chip. Furthermore, the first DRAM memory is externally mounted on the first monolithic die, and the first DRAM memory and the first monolithic die are enclosed in another single package. Furthermore, the first DRAM memory is an embedded DRAM chip.

[0052] According to another aspect of the present invention, the combined area of ​​the first logic circuit and the first SRAM memory accounts for at least 80% to 90% of the maximum scanner exposure area of ​​the first monolithic die, and the combined area of ​​the second logic circuit and the second SRAM memory accounts for at least 80% to 90% of the maximum scanner exposure area of ​​the second monolithic die. The second DRAM memory is an embedded DRAM chip externally attached to the second monolithic die, and the second DRAM memory and the second monolithic die are encapsulated in a single package.

[0053] The advantages and spirit of the present invention can be understood from the following description together with the accompanying drawings. These and other objectives of the present invention will undoubtedly become clear to those skilled in the art by reading the following detailed description of preferred embodiments shown in various figures and drawings. [Brief explanation of the drawing]

[0054] [Figure 1A] This is a circuit diagram for a standard 6T-SRAM. [Figure 1B] This is a bar graph corresponding to the 6T-SRAM in Figure 1A, with the active region represented by vertical bars and the gate lines by horizontal bars. [Figure 2A] This is a diagram showing cross-sections of the structures of conventional NMOS and PMOS. [Figure 2B] This figure shows the total area of ​​SRAM cells for different process dimensions λ (or F) using currently available manufacturing processes, in units of λ² (or F²). [Figure 3A] This bar graph shows the arrangement and connections of PMOS and NMOS transistors in a standard cell. [Figure 3B] This bar graph shows the arrangement and connections of PMOS and NMOS transistors in a standard cell, along with dimensional information. [Figure 3C] This shows the scaling trends in area size by process technology node in three semiconductor manufacturing plants. [Figure 4A] This figure shows a monolithic SOC die with a scanner maximum exposure area (SMFA) limited by the maximum reticle size of the lithography stepper. [Figure 4B] This figure shows a monolithic SOC die with a scanner maximum exposure area (SMFA) limited by the maximum reticle size of the lithography stepper. [Figure 5] This figure shows a top view of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) according to the present invention. [Figure 6] This figure shows a cross-section of the pad oxide layer, the pad nitride layer on the substrate, and the STI (shallow trench isolation) oxide 1 formed on the substrate. [Figure 7] This figure shows the true gate (TG) and dummy shield gate (DSG) formed on the active region. [Figure 8] This figure shows the process of depositing spin-on dielectric (SOD), depositing a well-designed gate mask layer, and etching. [Figure 9] This diagram shows the nitride layer on top of a dummy shield gate (DSG), with the DSG, a portion of the dielectric insulator corresponding to the DSG, and the p-type substrate 102 corresponding to the DSG removed. [Figure 10] This figure shows the process of removing the gate mask layer, etching the SOD, and depositing two oxide layers to form STI oxide 2. [Figure 11] This figure shows the process of depositing three oxide layers, etching them to form oxide 3 spacers, forming lightly doped drains (LDDs) on a p-type substrate, depositing a nitride layer, etching back to form nitride spacers, and removing the dielectric insulator. [Figure 12] This figure shows a unique silicon electrode being grown using Selective Epitaxy Growth (SEG) technology. [Figure 13] This figure shows the process of depositing three layers of CVD-STI oxide, etching them back, removing the intrinsic silicon electrodes, and forming the source (n+ source) and drain (n+ drain) of an mMOSFET. [Figure 14] This figure shows the process of depositing an oxide spacer and etching it to form a contact hole opening. [Figure 15A]This diagram shows the process of depositing an SOD layer to fill voids in a substrate and then flattening the surface using chemical mechanical polishing (CMP). [Figure 15B] This is a top view of Figure 15A. [Figure 16] This figure shows the photoresistive layer formed on top of the structure in Figure 15B. [Figure 17] This figure shows an anisotropic etching technique that removes the nitride cap layer within the exposed gate expansion region, exposing the conductive metal gate layer. [Figure 18A] This figure shows the state after the photoresistive layer and SOD layer have been removed to form an aperture region above both the source region and the drain region, thereby forming a spacer. [Figure 18B] This is a top view of Figure 18A. [Figure 19A] This diagram shows how the layers of the metal wiring network are formed. [Figure 19B] Figure 19A is a top view, showing that the gate is connected to the source region through a single layer of metal. [Figure 20] These are a series of top views and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to one embodiment of the present disclosure. [Figure 21] These are a series of top views and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to one embodiment of the present disclosure. [Figure 22] These are a series of top views and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to one embodiment of the present disclosure. [Figure 23] These are a series of top views and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to one embodiment of the present disclosure. [Figure 24-1] These are a top view and a cross-sectional view showing another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 24-2] These are a top view and a cross-sectional view showing another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 25A]This diagram shows cross-sections of PMOS and NMOS transistors used in SRAM cells. [Figure 25B] This diagram shows cross-sections of PMOS and NMOS transistors used in SRAM cells. [Figure 26A] Figures 25A and 25B are top views showing the combined structure of the new PMOS52 and the new NMOS51. [Figure 26B] This figure shows a cross-section of a new combination of PMOS52 and NMOS51 along the cutting line (Y-axis) in Figure 26A. [Figure 27] This figure shows a cross-section of one combination of conventional PMOS and NMOS transistors. [Figure 28A] Figures 25A and 25B are top views showing another combination structure of the novel PMOS 52 and novel NMOS 51. [Figure 28B] This figure shows a cross-section of a new combination of PMOS52 and NMOS51 along the cutting line (X-axis) in Figure 28A. [Figure 29] This figure shows a cross-section of another combination of conventional PMOS and NMOS transistors. [Figure 30] This is a top view showing another combination structure of PMOS and NMOS transistors used in a new SRAM cell. [Figure 31A] Figure 2 shows a bar graph. [Figure 31B] This is a bar graph showing the dimensions of the new 6T SRAM. [Figure 31C] This is a bar graph of a novel 6T SRAM having contacts according to the present invention. [Figure 32] The SRAM cell area (represented by λ²) is shown from three different semiconductor manufacturing plants A, B, and C, and across different technology nodes of the present invention. [Figure 33A] This is a bar graph showing the dimensions of the new 6T SRAM. [Figure 33B]This is a bar graph of a novel 6T SRAM having contacts according to the present invention. [Figure 34A] The area (expressed in λ²) of standard cells from three different semiconductor manufacturing plants A, B, and C, and across different technology nodes of the present invention, is shown. [Figure 34B] The Cpp, fin pitch, and Cell Height are shown from three different semiconductor manufacturing plants and across different technology nodes of the present invention. [Figure 35] This figure shows the integrated scaling and stretching platform proposed by the present invention. [Figure 36A] This invention illustrates different embodiments of a monolithic die based on the integrated scaling and stretching platform proposed by the present invention. [Figure 36B] This invention illustrates different embodiments of a monolithic die based on the integrated scaling and stretching platform proposed by the present invention. [Figure 36C] This invention illustrates different embodiments of a monolithic die based on the integrated scaling and stretching platform proposed by the present invention. [Figure 36D] This invention illustrates different embodiments of a monolithic die based on the integrated scaling and stretching platform proposed by the present invention. [Figure 36E] This invention illustrates different embodiments of a monolithic die based on the integrated scaling and stretching platform proposed by the present invention. [Modes for carrying out the invention]

[0055] As mentioned above, in conventional SRAM cells or logic cells, even when the minimum shape or technology node was miniaturized to 28nm or less, the size of the transistor did not decrease proportionally. Hereinafter, "technology node" refers to a specific semiconductor manufacturing process announced by a semiconductor manufacturing plant (such as N5 and N7 announced by Taiwan Semiconductor Manufacturing Company), or related data announced by a third party (such as wikichip, https: / / en.wikichip.org / ). Different nodes often mean different circuit generations and architectures. Generally, the smaller the technology node, the smaller the shape, and the faster and more power-efficient the smaller the transistor that can be manufactured. The term "minimum shape" is synonymous with the term "technology node." In the semiconductor industry, the terms "contact polypitch (or Cpp)" and "fin pitch" are commonly used. "Fin width" refers to the width of the bottom surface of the fin structure of a FinFet transistor or tri-gate transistor.

[0056] This invention discloses a miniaturized transistor structure that precisely controls the linear dimensions of the source, drain, and gate of a miniaturized transistor, making these linear dimensions as small as the minimum shape, lambda (λ). Therefore, when two adjacent transistors are connected via the drain / source, the distance between the gate edges of the two adjacent transistors can be reduced to 2λ. Furthermore, the linear dimensions of the contact holes in the source, drain, and gate can be less than λ, such as 0.6λ to 0.8λ.

[0057] Figure 5 shows an example of a miniaturized metal oxide layer semiconductor field-effect transistor (mMOSFET) 100 according to the present invention. As shown in Figure 5, the mMOSFET 100 includes: (1) a gate structure 101 having a length G(L) and a width G(W); (2) a source 103 on the left side of the gate structure 101 having a length S(L) and a width S(W) which are the linear dimensions from the edge of the gate structure 101 to the edge of the isolation region 105; (3) a drain 107 on the right side of the gate structure 101 having a length D(L) and a width D(W) which are the linear dimensions from the edge of the gate structure 101 to the edge of the isolation region 105; (4) a contact hole 109 formed by self-alignment technique in the central part of the source 103 having opening lengths and widths denoted as CS(L) and CS(W), respectively; and (5) similarly, a contact hole 111 formed by self-alignment technique in the central part of the drain 107 having opening lengths and widths denoted as CD(L) and CD(W), respectively. Lengths G(L), D(L), and S(L) can be precisely controlled within the range of the minimum shape λ. Furthermore, the length and width of the openings denoted as CS(L) and CS(W), or the length and width of the openings denoted as DS(L) and DS(W), may be less than λ, for example, 0.6λ to 0.8λ.

[0058] The manufacturing process of the mMOSFET 100 is briefly described below. A detailed description of the structure of the mMOSFET 100 and its manufacturing process is presented in U.S. Patent Application No. 17 / 138,918, filed on 31 December 2020, entitled "Miniaturized Transistor with Controlled Source / Drain and Contact Aperture Dimensions and Related Manufacturing Methods," the entirety of U.S. Patent Application No. 17 / 138,918 is incorporated herein by reference.

[0059] As shown in Figure 6, a pad oxide layer 302 is formed on the substrate 102, and a pad nitride layer 304 is deposited. The active region of the mMOSFET is defined, and a portion of the silicon material outside the active region is removed to create a trench structure. One oxide layer is deposited in the trench structure and etched back to form a shallow trench isolation (STI oxide 1) 306 below the original horizontal plane of the silicon substrate (hereinafter referred to as HSS).

[0060] The pad oxide layer 302 and pad nitride layer 304 are removed to form a dielectric insulator 402 on the HSS. Next, as shown in Figure 7, the gate layer 602 and nitride layer 604 are deposited on the HSS, and the gate layer 602 and nitride layer 604 are etched to form a dummy shield gate with a desired linear distance from the true gate and true gate (TG) of the mMOSFET. A (DSG) is formed. As shown in Figure 7, the length of the true gate and the dummy shield gate is λ, the length of the dummy shield gate is also λ, and the distance between the edges of the true gate and the dummy shield gate is also λ. Of course, for the purpose of mitigation, these lengths and distances can be made larger than λ depending on the requirements.

[0061] Next, spin-on dielectric (SOD) 702 is deposited, and the SOD 702 is etched back. As shown in Figure 8, a well-designed gate mask layer 802 is formed using photolithography masking techniques. Then, as shown in Figure 9, anisotropic etching techniques are used to remove the nitride layer 604 on the dummy shield gate (DSG), removing the gate layer of the DSG, a portion of the dielectric insulator 402 corresponding to the DSG, and the p-type substrate 102 corresponding to the DSG.

[0062] Furthermore, as shown in Figure 10, the gate mask layer 802 is removed, the SOD 702 is etched, and the STI oxide 2 1002 is deposited, followed by etching back. Next, as shown in Figure 11, the oxide 3 layer is deposited, etching back is performed to form the oxide 3 spacer 1502, a low-concentration doped drain (LDD) 1504 is formed on the p-type substrate 102, a nitride layer is deposited, etching back is performed to form the nitride spacer 1506, and the dielectric insulator 402 is removed.

[0063] Furthermore, as shown in Figure 12, the intrinsic silicon electrode 1602 is grown using selective epitaxial growth (SEG) technique. Next, as shown in Figure 13, a CVD-STI oxide 3 layer 1702 is deposited and etched back to remove the intrinsic silicon 1602, forming the source region (n+source) 1704 and drain region (n+drain) 1706 of the mMOSFET. The source region (n+source) 1704 and drain region (n+drain) 1706 are formed between the true gate (TG) and the CVD-STI oxide 3 layer 1702 in the position originally occupied by the dummy shield gate (DSG), and thus the length and width of the source region (n+source) 1704 (or drain region (n+drain) 1706) become small, λ. The opening of the source region (n+source) 1704 (or drain region (n+drain) 1706) can be less than λ, for example, 0.8λ. Such openings can be reduced by further forming oxide spacers 1802, as shown in Figure 14.

[0064] Furthermore, the novel miniaturized transistor allows the first metal wiring (M1 layer) to directly connect the gate, source, and / or drain regions through self-aligned miniaturized contacts, without the need for conventional contact hole opening masks or metal O transition layers for M1 connection. Following Figure 13, a layer of SOD1901 is deposited to fill the voids on the substrate, including the opening of the source region (n+source) 1704 (or drain region (n+drain) 1706). The surface is then flattened using CMP as shown in Figure 15A. Figure 15B is a top view of Figure 15A, showing multiple fingers in the horizontal direction.

[0065] Furthermore, using a well-designed mask, the photoresistivity layer 1902, which forms several stripe patterns along the X-axis in Figure 15(b), is applied in another space of length GROC(L) along the Y-axis in Figure 15(b) to expose the gate extension region, resulting in the top view shown in Figure 16. As shown in Figure 16, this is the most aggressive design rule with GROC(L) = λ. Next, anisotropic etching techniques are used to remove the nitride cap layer within the exposed gate extension region, exposing the conductive metal gate layer (Figure 17).

[0066] Subsequently, the photoresistive layer 1902 and the SOD layer 1901 are removed so that their opening regions at the top of both the source region 1704 and the drain region 1706 are exposed again. Next, a well-designed thickness layer of oxide 1904 is deposited, and then anisotropic etching techniques are used to form spacers on the four sidewalls of the opening regions of the source region 1704 and the drain region 1706 and the exposed gate extension region 1903. Thus, naturally formed contact hole openings are created in the exposed gate extension region, source region 1704, and drain region 1706, respectively. Figure 18A is a cross-sectional view of such a transistor structure. Figure 18B is a top view of such a transistor structure as shown in Figure 18A. The vertical length CRMG(L) of the opening in the exposed gate extension region 1903 is smaller than the length GROC(L), which may be λ.

[0067] Finally, a well-designed thickness layer of metal 1905 is formed to fill all the aforementioned contact hole openings and create a smooth plane according to the wafer surface topography. Next, as shown in Figure 19(a), photolithography masking techniques are used to create all the connections between those contact hole openings to realize the required metal-1 wiring network. Figure 19B is a top view of the mMOSFET shown in Figure 19A. Thus, this metal-1 layer provides contact filling and plug connections for both the gate and source / drain, and also functions as direct wiring to connect all the transistors. In particular, it eliminates the need for the use of expensive and highly controlled conventional contact hole masks and the subsequent extremely difficult contact hole opening drilling process, which is considered the most difficult challenge when further miniaturizing the horizontal shape of billions of transistors. Furthermore, it eliminates the need for complex and integrated processing steps (for example, steps that are always required in some state-of-the-art technologies that create metal-zero structures) to insert metal plugs into the contact hole openings or CMP processing to realize metal studs.

[0068] Furthermore, conventional SRAM cells or standard cells may not allow gate or diffusion to connect directly to M2 without bypassing the M1 structure (or M1 to connect to M3 without bypassing the M2 structure, or M1 to connect to Mx without bypassing the M2~Mx-1 structure, etc.). The present invention discloses a novel wiring structure in which either the gate region or the diffusion (source / drain) region is directly and self-aligned to the M2 wiring layer without a transition layer M1, through a single vertical conductive plug consisting of contact A and via 1A, which are formed at other locations on the same die during the construction phase of contact and via 1, respectively. As a result, the space required between one M1 wiring and another M1 wiring, and blocking problems in some wiring connections can be reduced. The novel wiring structure in which the gate region and diffusion (source / drain) region are directly and self-aligned to the M2 wiring layer without a transition layer M1 is briefly described below.

[0069] Figures 20A and 20C show cross-sectional and top views of the transistor up to the construction stage where multiple openings are formed on both the gate expansion region and the diffusion region, where Figure 20A is a top view of the transistor construction stage, and Figures 20B and 20C are two cross-sectional views of the transistor construction stage along the cutting lines C1B1 and C1B2 shown in Figure 20A, respectively. As shown in Figures 20B and 20C, the transistor structure 100 is formed by a shallow trench isolator (STI) 105 and has a defined extent. The transistor structure 100 has a gate terminal 102, a transistor channel region 103 below the gate terminal 102, and a source / drain region 104. The gate terminal 102 comprises a gate dielectric layer 102a, a gate conductive layer 102b formed on the gate dielectric layer 102a, and a silicon region (or seed region) 102c formed on the gate conductive layer 102b. The silicon region 102c can be made of polycrystalline or amorphous silicon. The gate terminal 102 further includes a capping layer (e.g., a nitride layer) on the upper surface of the silicon region 102c, and further includes at least one spacer (e.g., a nitride spacer 102s1 and a thermal oxide spacer 102s2) on the sidewalls of the gate dielectric layer 102a, the gate conductive layer 102b, and the silicon region 102c. The first dielectric layer 120 is formed on the semiconductor substrate 101 so as to at least cover the active region of the transistor structure 100, which includes the gate terminal 102, the source / drain region 104, and the STI 105.

[0070] Multiple openings (such as openings 107a and 107b) are formed in the first dielectric layer 120 to expose the upper surface portion 11 of the silicon 102c region and the upper surface portion 12 of the source / drain region 104. In some embodiments, openings 107a and 107b are formed by partially removing the first dielectric layer 120 using a photolithography process to expose the silicon region 102c of the source / drain region 104 and the silicon region of the drain terminal. In one example, each of the openings 107a and 107b may be equal in size to the minimum shape (e.g., the critical size of the transistor structure 100 of the device 10). Of course, the size of the openings 107a and 107b may be larger than the minimum shape. The bottoms of the openings 107a and 107b (i.e., the exposed upper portions 11 and 12) are each made of either polycrystalline / amorphous silicon or highly doped crystalline silicon with high conductivity. The exposed silicon regions 102c of the gate terminal and the exposed silicon regions of the source / drain terminals are seed regions for growing pillars based on seed regions using selective epitaxial growth (SEG) technology.

[0071] Next, as shown in Figures 21A to 21C, a highly doped conductive silicon plug (or conductive pillar) is grown by SEG on the exposed upper surface portion 11 and the exposed upper surface portion 12 as a base, forming the first conductive pillar portion 131a and the third conductive pillar portion 131b. Then, a first dielectric underlayer 140 is formed on the first dielectric layer 120, making the upper surface 140s of the first dielectric underlayer 140 substantially coplanar with the upper surfaces of the first conductive pillar portion 131a and the third conductive pillar portion 131b. The “exposed heads” (or exposed upper surfaces) of the first conductive pillar portion 131a and the third conductive pillar portion 131b can be used as seed portions for the subsequent SEG process. Furthermore, each of the first conductor pillar portion 131a and the third conductor pillar portion 131b has a seed region or seed pillar on its upper portion, which can be used for subsequent selective epitaxial growth. Subsequently, a second conductor pillar portion 132a is formed on the first conductor pillar portion 131a by a second selective epitaxial growth, and a fourth conductor pillar portion 132b is formed on the third conductor pillar portion 131b. Figure 21A is a top view showing the structure after the second conductor pillar portion 132a and the fourth conductor pillar portion 132b have been formed on the first conductor pillar portion 131a and the third conductor pillar portion 131b according to one embodiment of the present disclosure. Figure 21B is a cross-sectional view taken along the cutting line C1E1 drawn in Figure 21A. Figure 21B is a cross-sectional view taken along the cutting line C1E2 drawn in Figure 21A.

[0072] Furthermore, as shown in Figures 22A to 22C, a first conductive layer 150, such as copper (Cu), aluminum (Al), tungsten (W), or other suitable conductive material, can be deposited on the upper surface 140s of the first dielectric underlayment 140. Subsequently, a second dielectric underlayment 160 is deposited on the first conductive layer 150. The first conductive layer 150 and the second dielectric underlayment 160 are patterned to define an open cavity 109, and the first conductive pillar 130A penetrates the open cavity 109 without contacting the first conductive layer 150 and the second dielectric underlayment 160. Figure 22A is a top view showing the structure after the first conductive layer 150 and the second dielectric underlayment 160 have been formed on the first dielectric layer 120 according to one embodiment of the present disclosure. Figure 22B is a cross-sectional view taken along the cutting line C1F1 drawn in Figure 22A. Figure 22C is a cross-sectional view taken along the cutting line C1F2 shown in Figure 22A.

[0073] Furthermore, as shown in Figures 23A to 23C, the upper dielectric layer 170 is deposited so as to cover the second dielectric underlayer 160 and the first dielectric underlayer 140, filling the opening hollow 109. The upper surface 170s of the upper dielectric layer 170 is located below the upper surface 130t of the first conductor pillar 130A (including the first conductor pillar portion or sub-pillar 131a and the second conductor pillar portion or sub-pillar 132a) and the second conductor pillar 130B (including the third conductor pillar portion or sub-pillar 131b and the fourth conductor pillar portion or sub-pillar 132b). Subsequently, the upper conductive layer 180 is formed on the upper dielectric layer 170, and the first conductor pillar 130A connects to the upper conductive layer 180 but is cut off from the first conductive layer 150. In this example, Figure 23A is a top view showing the structure after a conductive layer 180 has been formed on the upper dielectric layer 170 according to one embodiment of the present disclosure. Figure 23A is a top view, and Figure 23B is a cross-sectional view taken along the cutting line C1H1 drawn in Figure 23A. Figure 23C is a cross-sectional view taken along the cutting line C1H2 drawn in Figure 23A.

[0074] As described above, the exposed silicon region 102c of the gate terminal and the exposed silicon region of the source / drain terminals are seed regions for growing pillars based on seed regions using selective epitaxial growth (SEG) technology. Furthermore, each of the first conductor pillar portion 131a and the third conductor pillar portion 131b also has a seed region or seed pillar on its upper portion, and such seed region or seed pillar can be used for subsequent selective epitaxial growth. In addition, in this embodiment, if there is a seed portion or seed pillar on the upper portion of the conductive terminal and a conductor pillar portion configured according to selective epitaxial growth technology, it is also possible to directly connect the M1 wiring (a single-seed conductive terminal) or conductive layer to the MX wiring layer in a self-aligned manner through a single vertical conductive or conductive plug (without connecting to conductive layers M2, M3, ... MX-1). Note that the seed portion or seed pillar is not limited to silicon, but can be any material that can be used as a seed configured for subsequent selective epitaxial growth.

[0075] The conductor pillar may be a metal conductor pillar, or a composite conductor pillar consisting of a metal conductor pillar and its upper seed portion or seed pillar. As shown in Figures 24A to 24C, the highly doped N+ polycrystalline silicon pillars 131a, 132a, 131b, and 132b in Figures 23A to 23C can be removed and replaced with a tungsten pillar 330w, a TiN layer 330n, and a highly doped silicon pillar. As shown in Figures 24B to 24C, the first conductor pillar includes a metal pillar portion 330A (including a tungsten pillar 330w and a TiN layer 330n) and a highly doped silicon pillar 410a, and the second conductor pillar includes a metal pillar portion 330B (including a tungsten pillar 330w and a TiN layer 330n) and a highly doped silicon pillar 410b. The highly doped silicon pillars 410a and 410b are seed regions or seed pillars of a conductor pillar configured for subsequent metal connections, as shown in Figures 24B and 24C, and the first conductive layer 450 is formed on the first dielectric underlayer 240 and electrically connected to the highly doped silicon pillars 410a and 410b. Furthermore, the highly doped silicon pillars 410a and 410b are seed regions or seed pillars of a conductor pillar configured to follow a SEG process for growing another silicon pillar thereon. In this example, Figure 24A is a top view, and Figure 24B is a cross-sectional view taken along the cutting line C4B1 drawn in Figure 24A. Figure 24C is a cross-sectional view taken along the cutting line C4B2 drawn in Figure 24A. Thus, the conductor pillar may include a tungsten pillar and a first highly doped silicon pillar, i.e., the conductor pillar has seed regions or seed pillars on its upper portion.

[0076] The highly doped silicon pillars 410a and 410b are seed regions or seed pillars of a conductive pillar configured to follow the SEG process to grow another silicon pillar on its upper portion, so that the conductive pillar can have a seed region or seed pillar on its upper portion, thereby achieving borderless contact. As shown in Figures 24D to 24F, even if the width of the metallic conductive layer (e.g., the first metallic underlayment 550a or the second metallic underlayment 550b) is the same as the width of the contact plug below (it may be as small as the minimum shape), misalignment tolerances of the photolithography masking may prevent the metallic conductive layer 550a or 550b from completely covering the contact (as shown in Figures 24E and 24F), but there is no concern that the resistance between the metallic conductive layer and the contact will become too high due to insufficient contact area. The invention here is to further use SEG to grow some extra highly doped silicon material (side pillars 520) for attaching the vertical walls of the metallic conductive layers 550a and 550b. In this example, Figure 24D is a top view, and Figure 24E is a cross-sectional view taken along the cutting line C51 drawn in Figure 24D. Figure 24F is a cross-sectional view taken along the cutting line C52 drawn in Figure 24D.

[0077] Furthermore, the present invention discloses a novel CMOS structure in which the n+ and p+ regions of the source and drain areas of NMOS and PMOS transistors are completely isolated by an insulator, which not only enhances resistance to latch-up problems but also increases the insulation distance to the silicon substrate, separating the junctions of the NMOS and PMOS transistors and reducing the surface distance between the junctions (e.g., 3λ), thereby reducing the size of the SRAM cell or standard cell. Below, a brief description is given of the novel CMOS structure in which the n+ and p+ regions of the source and drain areas of NMOS and PMOS transistors are completely isolated by an insulator. A detailed description of the novel combination structure of PMOS and MNOS is presented in U.S. Patent Application No. 17 / 318,097, filed on 12 May 2021, entitled "Complementary MOSFET Structure Having Local Insulators on Silicon Substrate for Reduced Leakage and Prevention of Latch-up," the entirety of U.S. Patent Application No. 17 / 318,097 is incorporated herein by reference.

[0078] Refer to Figures 25A and 25B. Figure 25A is a cross-section of a PMOS transistor 52, and Figure 25B is a cross-section of an NMOS transistor 51. A gate structure 33 having a gate dielectric layer 331 and a gate conductive layer 332 (gate metal, etc.) is formed on the horizontal plane or above the original surface of a semiconductor substrate (silicon substrate, etc.). A dielectric cap 333 (a composite of an oxide layer and a nitride layer, etc.) is located on the gate conductive layer 332. Furthermore, a spacer 34 containing a composite of an oxide layer 341 and a nitride layer 342 is used on the sidewall of the gate structure 33. A trench is formed in the silicon substrate, and all or at least part of the source region 35 and the drain region 36 are located within the corresponding trenches. The source (or drain) region in the PMOS transistor 32 may include a P+ region or other suitable doping profile region (such as a gradual or stepwise change between the P- region and the P+ region). Furthermore, a local insulator 48 (such as a nitride or other high dielectric constant dielectric material) is located in one trench below the source region, and another local insulator 48 is located in another trench below the drain region. Such local insulators 48 are located below the horizontal silicon surface (HSS) of the silicon substrate and can be called local insulators (LISS) 48 to the silicon substrate. The LISS 48 can be a composite of thick nitride or dielectric layers. For example, the local insulator or LISS 48 may comprise a composite local insulator including an oxide layer (referred to as oxide 3V layer 481) covering at least a portion of the sidewalls of the trench and another oxide layer (oxide 3B layer 482) covering at least a portion of the bottom wall of the trench. The oxide 3V layer 481 and oxide 3B layer 482 can be formed by thermal oxidation. The composite local insulator 48 further includes a nitride layer 483 (referred to as nitride 3) provided on top of the oxide 3B layer 482 and in contact with the oxide 3V layer 481. It is mentioned that the nitride layer 483 or nitride 3 can be replaced with any suitable insulating material, as long as the oxide 3V layer remains to the maximum extent as designed.Furthermore, the STI (shallow trench isolation) regions in Figures 25A and 25B may comprise a composite STI 49 including an STI-1 layer 491 and an STI-2 layer 492, where the STI-1 layer 491 and the STI-2 layer 492 may each be composed of a thick oxide material by different processes.

[0079] Furthermore, the source (or drain) region in Figures 25A and 25B may comprise a composite source region 55 and / or drain region 56. For example, as shown in Figure 25(a), in the PMOS transistor 52, the composite source region 55 (or drain region 56) comprises at least a low-concentration doped drain (LDD) 551 and a high-concentration P+ doped region 552 within a trench. It is noteworthy that the low-concentration doped drain (LDD) 551 abuts against an exposed silicon surface having a uniform (110) crystal orientation. In contrast to the edge of the gate structure, labeled TEC (thickness of the etched transistor body, well defined to form a sharp edge with an effective channel length) in Figure 25A, the vertical boundary of the exposed silicon surface has a suitable recessed thickness. The exposed silicon surface is substantially aligned with the gate structure. The exposed silicon surface may also be the terminal surface of the transistor channel.

[0080] The low-concentration doped drain (LDD) 551 and the high-concentration P+ doped region 552 are formed based on selective epitaxial growth (SEG) technique (or other suitable technique which may be atomic layer deposition ALD or selective growth ALD-SALD), and silicon is grown from exposed TEC areas used as crystal seeds to form a novel, well-organized (110) lattice, throughout the LISS region where there is no seeding effect on altering the (110) crystal structure of the newly formed crystal in the composite source region 55 or drain region 56. Such a newly formed crystal (including the low-concentration doped drain (LDD) 551 and the high-concentration P+ doped region 552) may be named TEC-Si, as shown in Figure 25A. In one embodiment, the TEC is aligned with or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewall of the LDD 551 opposite the TEC may be aligned with or substantially aligned with the sidewall of the spacer 34. Similarly, the TEC-Si (including the LDD region and the highly doped n+ region) of the composite source / drain region of the NMOS transistor 51 is shown in Figure 25B. The composite source (or drain) region may further comprise several tungsten (or other suitable metallic material) plugs 553 formed by horizontal connections to the TEC-Si portion to complete the entire source / drain region, as shown in Figures 25A and 25B. As shown in Figure 25A, the active channel current flowing through the future metal wiring, such as a metal layer 1, passes through the LDD 551 and the highly doped conductive region 552 to the tungsten 553 (or other metallic material) which is directly connected to metal 1 by good metal-to-metal resistive contacts with much lower resistance than conventional silicon-to-metal contacts.

[0081] Figure 26A, a top view, shows one of the combination structures of the novel PMOS 52 and the novel NMOS 51, and Figure 26B shows a cross-section of the combination of the novel PMOS 52 and the novel NMOS 51 along the cutting line (Y axis) in Figure 26A. As shown in Figure 26B, since a composite local insulator (or LISS 48) exists between the bottom of the p+ source / drain region of the PMOS and the n-type N-well, another composite local insulator (or LISS 48) also exists between the bottom of the N+ source / drain region of the NMOS and the p-type P-well or substrate. In this novel CMOS structure shown in Figure 26B, the advantage is clearly demonstrated that the bottoms of the n+ region and the p+ region are completely isolated by the insulator. In other words, the possible latch-up path from the bottom of the p+ region of the PMOS to the bottom of the n+ region of the NMOS is completely blocked by the LISS. On the other hand, in conventional CMOS structures, as shown in Figure 27, the n+ region and the p+ region are not completely isolated by an insulator. Therefore, the possible latch-up paths from the n+ / p junction through the p-well / n-well junction to the n / p+ junction have lengths a, b, and c (where "circle X" refers to the letter "X" enclosed in a circle). (Figure 27). Therefore, from the standpoint of device layout, the edge distance (Xn+Xp) secured between the NMOS and PMOS in Figure 26B can be smaller than that in Figure 27. For example, the secured edge distance (Xn+Xp) can be around 2 to 5λ, for example, around 3λ.

[0082] Another combination structure of the novel PMOS52 and novel NMOS51 is shown in Figure 28A, a top view, and Figure 28B is a cross-section of the novel PMOS52 and novel NMOS51 combination along the cutting line (X-axis) in Figure 28A. As shown in Figure 28B, the path from the n+ / p junction through the p-well (or p-substrate) / n-well junction to the n / p+ junction is significantly longer. Possible latch-up paths from the LDD-n / p junction through the p-well / n-well junction to the n / LDD-p junction are length circles 1, 2 (length of the bottom wall of one LISS region), 3, 4, 5, 6, 7 (length of the bottom wall of another LISS region), and 8, shown in Figure 28B. On the other hand, in the conventional CMOS structure combining the PMOS and NMOS structures shown in Figure 29, the possible latch-up paths from the n+ / p junction through the p-well / n-well junction to the n / p+ junction are limited to (as shown in Figure 29) lengths d, e, f, and g. The possible latch-up paths in Figure 28B are longer than those in Figure 29. Therefore, from a device layout perspective, the edge distance (Xn+Xp) secured between the NMOS and PMOS in Figure 28B can be smaller than that in Figure 29. For example, the secured edge distance (Xn+Xp) can be around 2-5λ, for example, around 3λ.

[0083] Furthermore, in currently available SRAM cells and standard cells, the metal wires for the high-level voltage VDD and low-level voltage VSS (or ground) are located above the original silicon surface of the silicon substrate, and such a distribution can interfere if there is not enough space between other word lines (WL), bit lines (BL, BL bars), or other connecting metal wires. The present invention discloses a novel SRAM structure in which the metal wires for the high-level voltage VDD and / or low-level voltage VSS can be located below the original silicon surface of the silicon substrate, thereby avoiding interference between the contact size, word lines (WL), bit lines (BL and BL bars), and the layout of the metal wires connecting the high-level voltage VDD and low-level voltage VSS, etc., even when the size of the SRAM cell is reduced. As shown in Figure 30, in the drain region of the PMOS 52, a metal material 553 such as tungsten is directly coupled to an N-type well electrically coupled to VDD. On the other hand, in the source region of the NMOS 51, the metal material 553 such as tungsten is directly coupled to a P-type well or P-type substrate electrically coupled to ground. Therefore, the openings for the source / drain region, which are originally used for electrical coupling between the source / drain region and metal layer 2 or metal layer 3 for VDD or ground connection, may be omitted in novel SRAM cells and standard cells. A detailed description of the structure and its manufacturing process is presented in U.S. Patent Application No. 16 / 991,044, filed on 12 August 2020, entitled “Transistor Structure and Associated Inverter,” the entirety of which U.S. Patent Application No. 16 / 991,044 is incorporated herein by reference.

[0084] As described above, the new SRAM cells and standard cells have at least the following advantages: (1) The linear dimensions of the source, drain, and gate of the transistors in the SRAM can be precisely controlled, making these linear dimensions as small as the minimum shape, lambda (λ). Therefore, when two adjacent transistors are connected through the drain / source, the length of the transistors can be as small as 3λ, and the distance between the gate edges of the two adjacent transistors can be as small as 2λ. Of course, considering tolerances, the length of the transistors must be 3λ to 6λ or more, and the distance between the gate edges of the two adjacent transistors must be 3λ to 5λ or more. (2) Without using conventional contact hole opening masks or metal 0 transition layers for connecting M1, the first metal wiring (M1 layer) is directly connected to the gate, source, and / or drain regions via self-aligned miniaturized contacts. (3) The gate region and / or diffusion (source / drain) region are directly connected to the M2 wiring layer in a self-aligned manner without connecting the M1 layer. This reduces the space required between one M1 wiring and another, and also reduces blocking problems in some wiring connections. Furthermore, a similar structure can be applied even when the lower metal layer and the upper metal layer are directly connected by a conductor pillar, but the conductor pillar is not electrically connected to any intermediate metal layer between the lower and upper metal layers. (4) The n+ and p+ regions of the source and drain areas of NMOS and PMOS transistors are completely insulated by an insulator, which not only increases resistance to latch-up problems but also increases the insulation distance to the silicon substrate, separating the junctions of NMOS and PMOS transistors and the surface distance between the junction points. (For example, 3λ to 10λ, for example, 6 or 8λ) can be reduced. (5) Metal wires for the high-level voltage VDD and / or low-level voltage VSS of SRAM cells and standard cells can be placed beneath the original silicon surface of the silicon substrate, so that even if the size of SRAM cells and standard cells is reduced, interference between the contact size, word lines (WL), bit lines (BL and BL bars), high-level voltage VDD and low-level voltage VSS, etc., and the layout of metal wires can be avoided. Furthermore, the openings for the source / drain region, which are originally used for electrical coupling between the source / drain region and metal layer 2 or metal layer 3 for VDD or ground connection, may be omitted in new SRAM cells and standard cells.

[0085] Figure 31A is a copy of Figure 1B, showing a "bar graph" representing the layout and connections between the six transistors of the SRAM, while Figure 31B is a bar graph with dimensions according to the advantages of the present invention. Figure 31B is a bar graph of a novel 6T SRAM with dimensions according to the advantages of the present invention. As shown in Figure 31B, the length dimension of the transistors is small, 3λ (enclosed by a dotted rectangle), and the distance between the gate edges of two adjacent transistors can be small, 2λ. Furthermore, the insulation distance to the silicon substrate for separating the junctions of the NMOS and PMOS transistors can be reduced to 3λ (enclosed by a dashed rectangle). The insulation distance to the silicon substrate for separating the junctions of two PMOS transistors can be reduced to between 1.5 and 2.5λ, for example, 2λ (enclosed by a dashed rectangle). Furthermore, Figure 31B shows that Cpp is small, 3λ, and the two fin pitches Fp_1 and Fp_2 are small, 4λ and 3λ, respectively.

[0086] In Figure 31B, the dimensions of the active region (vertical lines) can be reduced to approximately λ, and the same applies to the gate lines (horizontal lines). Furthermore, in Figure 31B, for the upper left transistor corresponding to the PG transistor in Figure 31A, the horizontal distance between the edge of the active region and the boundary of the SRAM cell or bit cell is set to 1.5λ (enclosed by a dotted rectangle) to avoid interference between the two contact holes that are later formed in the active region and the gate region, respectively. The transistor in the lower right corner of Figure 31B, corresponding to another PG transistor in Figure 31A, is treated similarly. Therefore, in the case of the bar graph in Figure 31B, the horizontal length (x direction) of the SRAM cell is 15λ, and the vertical length (y direction) of the SRAM cell or bit cell is 6λ. Consequently, the total area of ​​the SRAM cells or bit cells in Figure 31B is 90λ. 2 And it gets smaller.

[0087] As shown in Figure 31C, in the proposed SRAM cell, several source / drain contacts (for connecting to one layer of metal) can be formed in the active region. The size of the source / drain contacts may be as small as λ×λ, regardless of the size of the technology node or (or minimum shape). Similarly, several source / drain contacts and gate contacts (for directly connecting to two layers of metal without connecting to one layer of metal, as previously described) can be formed on the gate or polyline, and the size of the gate contacts can also be as small as λ×λ.

[0088] Figure 32 shows the SRAM cell area (λ) across different technology nodes in three different semiconductor manufacturing plants A, B, and C. 2 This shows (represented by) (data collected from publicly available literature). With shape miniaturization technology, SRAM cell size (λ 2 It can be seen that the (represented by) is also increasing. With the design and its derivative designs described in the present invention, the SRAM cell area spanning different technology nodes can remain flat or low-sensitivity to the technology node, that is, from the 28nm technology node to the 5nm technology node, the SRAM cell area according to the present invention is 84λ2 ~10²λ 2 It can be maintained within this range. Taking the technology node or minimum shape = 5nm as an example, the area of ​​the newly proposed SRAM cell is approximately 1 / 8 (1 / 8) of the area of ​​the conventional 5nm SRAM cell shown in Figure 32, which is 100λ. 2 It may be to that extent.

[0089] Of course, it is not necessary to utilize all the improved techniques proposed in the novel SRAM cell structure of the present invention; even just one of the proposed techniques can reduce the area of ​​the SRAM cell structure compared to transient SRAM cells. For example, by reducing the active region according to the present invention (or simply connecting the gate / source / drain contacts ("CTs") to a second metal layer), the area of ​​the SRAM can be reduced to 84λ at a 5nm technology node. 2 ~700λ 2 Within the range, the technology node 7nm is 84λ 2 ~450λ 2 Within the range, from technology nodes 10nm to over 7nm, 84λ 2 ~280λ 2 Within the range, from technology nodes 20nm to over 10nm, 84λ 2 ~200λ 2 Within the range, from technology nodes 28nm to over 20nm, 84λ 2 ~150λ 2 It will be within the range. For example, by reducing the area of ​​the active region, the area of ​​the SRAM in a 5nm technology node can be reduced to 160λ. 2 ~240λ 2 Within this range (or further if more tolerance is required), the SRAM area is 107λ in the 16nm technology node. 2 ~161λ 2 (And even more tolerances if needed.)

[0090] The area (λ) of a conventional SRAM shown in Figure 2B 2Compared to the linear dimensions of the conventional SRAM in Figure 3, the linear dimensions of the present invention are 0.9 (or less, e.g., 0.85, 0.8, or 0.7) times, and the area of ​​the present invention may be at least 0.81 (or less, e.g., 0.72, 0.64, or 0.5) times the area of ​​the conventional SRAM in Figure 2B. Thus, in another embodiment, when the minimum shape is 5 nm, the area of ​​the SRAM cell is 84λ 2 ~672λ 2 It is within the range. When the minimum shape is 7nm, the area of ​​the SRAM cell is 84λ 2 ~440λ 2 It is within the range. When the minimum shape is between 10nm and over 7nm, the area of ​​the SRAM cell is 84λ 2 ~300λ 2 It is within the range. When the minimum shape is between 16nm and over 10nm, the area of ​​the SRAM cell is 84λ 2 ~204λ 2 It is within the range. When the minimum shape is between 22nm and over 16nm, the area of ​​the SRAM cell is 84λ 2 ~152λ 2 It is within the range. When the minimum shape is between 28nm and over 22nm, the area of ​​the SRAM cell is 84λ 2 ~139λ 2 It is within the range.

[0091] Similarly, the transistor, CMOS, latch-up design, and / or wiring structures described above can also be applied to logic circuits that use standard cells as basic elements. Figures 33A and 33B propose a novel standard cell (cell area: 2Cpp × Cell_Height), where Cpp may be as small as 4λ and Cell_Height as 24λ. Note that in Figure 33A, two active fins are used for both the PMOS and NMOS. However, the fin pitch may be as small as 3λ. The width of the active region and fins is small at λ, and the width of the gate line (or polyline) is also the same. Its dimensions can be easily formed regardless of the size of currently available technology nodes (or minimum shapes). Thus, the cell area of ​​the proposed standard cell (2Cpp × Cell_Height) is 192λ 2 That is the case.

[0092] As shown in Figure 33B, several source / drain contacts (for connecting to one layer of metal) can be formed in the active region. The size of the source / drain contacts may be as small as λ×λ, regardless of the size of the technology node or (or minimum shape). Similarly, gate contacts (for connecting directly to two layers of metal without connecting to one layer of metal, as described earlier) can be formed on the gate or polyline, and the size of the gate contacts can also be as small as λ×λ. In other words, the linear dimensions of the transistor's source, drain, gate, and contacts in a standard cell can be precisely controlled, and these linear dimensions can be made as small as the minimum shape, lambda (λ). In this embodiment, the distance between two gate lines or polylines is small, 3λ.

[0093] Furthermore, as mentioned above, since the bottom surface of the source / drain structure can be separated from the substrate, the isolation between n+ and n+ or p+ and p+ can be kept within a reasonable range. As a result, the distance between two adjacent active regions can be reduced to 2λ (indicated by the dotted line on the left in Figure 33B). Moreover, in this invention, since the n+ and p+ regions of the source and drain regions in the NMOS and PMOS transistors are completely isolated by an insulator, the latch-up distance between the PMOS and NMOS can be reduced to 8λ (indicated by the dotted line on the right in Figure 33B), regardless of the size or (minimum shape) of the technology node.

[0094] As described above, according to the present invention, the area size of a standard cell (2Cpp × Cell Height) capable of housing an inverter is 192λ 2 And so, such λ 2As shown in Figure 34A, the area size in units of is approximately the same from at least the 22nm technology node to 5nm. Compared to conventional practices in other semiconductor manufacturing plants, the proposed standard cell (2Cpp × cell height) has an area of ​​about 1 / 3.5 that of a conventional 5nm standard cell.

[0095] Of course, it is not necessary to utilize all the improved techniques proposed in the novel standard cell of the present invention; using just one of the proposed techniques can reduce the area of ​​the standard cell structure compared to the transitional standard cell. For example, the area (2 Cpp × cell height) of the standard cell according to the present invention is 190λ at ​​a 5 nm technology node. 2 ~600λ 2 Within the range, 190λ at ​​the 7nm technology node 2 ~450λ 2 or 190λ 2 ~250λ 2 Within the range of 190λ at ​​technology nodes between 10nm and 14nm 2 ~250λ 2 It could be within the range of, for example.

[0096] Furthermore, in another embodiment, the present invention is also applicable to different cell sizes such as 3Cpp×Cell_Height or 5Cpp×Cell_Height. Two NOR cells, NAND cells, or inverter cells may be embedded in a 3Cpp×Cell_Height cell size, and two NOR cells or two NAND cells may be embedded in a 5Cpp×Cell_Height cell size. Also, (regardless of whether the cell size is 3Cpp×Cell_Height or 5Cpp×Cell_Height), the proposed standard cell area size is λ 2 It can be concluded that they are nearly identical, at least from the 22nm to the 5nm technology node.

[0097] Figure 34B shows the Cpp, fin pitch, and Cell_Height values ​​for different technology nodes from three different semiconductor manufacturing plants, along with the present invention implemented with some of the proposed transistor structures and wiring with extra tolerances. The Cpp and fin pitch values ​​of the present invention are applicable not only to SRAM cells but also to standard cells (shown in Figures 31B and 33A). Of course, it is not necessary to utilize all the proposed improvements in a new die; just one of the proposed techniques can reduce the area of ​​the SRAM cell or standard cell structure compared to a transitional SRAM cell. Therefore, compared to other available semiconductor manufacturing plants, the Cpp value according to the present invention may be 45 nm or less (e.g., within the range of 45-20 nm or 40-20 nm) at the 5 nm technology node, 50 nm or less (e.g., within the range of 50-28 nm or 45-28 nm) at the 7 nm technology node, 50 nm or less (e.g., within the range of 50-40 nm or 45-40 nm) at the 10 nm technology node, and 67 nm or less (e.g., within the range of 67-64 nm) at the technology node between 14 nm and 16 nm. Furthermore, the fin pitch value according to the present invention may be 20 nm or less (e.g., within the range of 20 nm to 15 nm) at the 5 nm technology node, 24 nm or less (e.g., within the range of 24 nm to 21 nm) at the 7 nm technology node, and 32 nm or less (e.g., within the range of 32 nm to 30 nm) at the 10 nm technology node.

[0098] Furthermore, the Cpp value may be 45 nm or less (for example, within the range of 45 nm to 20 nm) if the second fin width is 5 nm or less, or the Cpp value may be 50 nm or less (for example, within the range of 50 nm to 28 nm) if the second fin width is 7 nm or less and 5 nm or more, or the Cpp value may be 50 nm or less if the second fin width is 10 nm or less and 7 nm or more. (For example, within the range of 50nm to 40nm), or the Cpp value may be 67nm or less (for example, within the range of 67nm to 64nm) if the second fin width is 14nm to 16nm.

[0099] As described above, Figure 35 discloses this innovation of an Integrated Scaling and / or Stretching Platform (ISSP) in monolithic die design. First, the proposed novel transistors, CMOS, wiring structures, etc., reduce the area of ​​the original circuit on die A by 2 to 3 times, so that major functional blocks such as the CPU or GPU can be reduced to a significantly smaller size. This allows more SRAM or major functional blocks to be formed on a single monolithic die. Taking the 5nm technology node as an example, as shown in Figure 32, the SRAM cell size of 6T can be reduced to approximately 100F 2 (F is the smallest shape that can be made on a silicon wafer) It is possible to reduce it to this size. In other words, if F = 5nm, the SRAM cell will be approximately 2500nm 2 While it can occupy a large area, the cutting edge cell area is approximately 800F according to the paper. 2 (~8x reduction). Furthermore, the 8-finger CMOS inverter (dimensions 2Cpp × Cell_Height, shown in Figures 33A and 33B) is 700F at the 5nm process node shown in Figure 34A. 2 Over 900F 2 In contrast to the publicly announced CMOS inverters up to that point, the 200F 2 This requires consuming the die area.

[0100] In other words, die A has a first die area (Ynm) based on the technology node (such as 7nm or 5nm). 2 When a die A has circuits that occupy (such as SRAM circuits, logic circuits, a combination of SRAM and logic circuits, or major functional block circuits such as CPU, GPU, FPGA), with the help of the present invention, the total area of ​​die A with the same circuits can be reduced even if die A is still manufactured by the same technology node. Furthermore, the new die area occupied by the same circuits in die A becomes smaller than the initial die area, for example, Ynm 2 This will be between 20% and 90% (or 30% and 70%).

[0101] For example, as shown in Figure 35, the original SOC die 3510 is 26 x 33 mm 2 The scanner has a maximum exposure area (SMFA) of 65%, 25%, and 10% of the die area, with the original SRAM, original logic circuitry, and input / output pads occupying 65%, 25%, and 10%, respectively. When the SRAM is reduced to 1 / 5.3 and the logic circuitry to 1 / 3.5, the new reduced die 3520 is 26x33mm 2 This results in a die area that is 1 / 3.4 the size of SMFA. Therefore, 26 x 33 mm 2 More SOC dies can be produced in the same SMFA (e.g., 2.4 times the number of dies). From another perspective, based on the proposed Integrated Scaling and / or Stretching Platform (ISSP), it is easily possible to combine a scaled-down die 3520 within the same SMFA with more SRAM (e.g., 5.7 times the amount of the original SRAM) to create a new monolithic die 3530, or to combine a scaled-down die 3520 within the same SMFA with a more major functional block (e.g., a new CPU, a new GPU, a new FPGA, etc.) to create another new monolithic die 3530.

[0102] Therefore, more SRAM will be formed on the monolithic die. Currently, major processing units (such as CPUs or GPUs) have several levels of cache. There is usually one L1 cache and one L2 cache (collectively referred to as "low-level caches") per CPU or GPU core unit, and the L1 cache is divided into L1i and L1d, which are used to store instructions and data respectively, the L2 cache does not distinguish between instructions and data, and the L3 cache (which may also be one of the "high-level caches") is shared by multiple cores and usually does not distinguish between instructions and data either. There is usually one L1 / L2 cache per CPU or GPU core, and the area must be increased by the same size as the number of CPU or GPU cores increases. Generally, the larger the cache capacity, the higher the hit rate. For high-speed operation, these low-level or high-level caches are generally composed of SRAM. Therefore, based on our integrated scaling and / or stretching platform, L1 / L2 caches ("low-level caches") and L3 caches ("high-level caches") can be increased within a monolithic single die, within the scanner maximum field area (SMFA) limited by the photolithography exposure system.

[0103] For example, as shown in Figure 36A for a single monolithic die 3610, an XPU3610 (e.g., a GPU) with multiple cores may have a high level of cache of 64MB or more of SRAM (e.g., 128, 256, 512MB or more) on an SMFA (e.g., 26mm x 33mm or 858mm). 2It has, for example. Furthermore, it is possible to improve performance by inserting additional logical GU cores of the GPU (GU core 1 to GU core 2N, e.g., 64, 128, 256 or more cores) into the same SMFA. In another embodiment, a memory controller with high-bandwidth I / O is also present. Each monolithic die includes an I / O bus (such as high-bandwidth I / O), and each CPU or GPU core is electrically coupled to the I / O bus, as are their caches and SRAMs.

[0104] Alternatively, other major functional blocks other than the terminated major functional block, such as a Network Processing Unit (NPU), a Tensor Processing Unit (TPU), or an FPGA, which have also been miniaturized according to the present invention, can be integrated together on another monolithic die 3620 as shown in Figure 36B. In Figure 36B, XPU3621 and YPU3622 represent processing units having major functional blocks, which may be an NPU, GPU, CPU, FPGA, or TPU. For example, XPU3621 may be a CPU and YPU3622 may be a GPU. The major functional blocks of XPU3621 may be the same as or different from those of YPU3622. The XPU3621 and YPU3622 each have multiple logical cores, each with a low-level cache (L1 / L2 cache, etc.; L1 is 128K, L2 is 512K or 1M), while a large high-level cache (32MB, 64MB or more L3 cache, etc.) is shared between the XPU3621 and YPU3622. Each monolithic die includes an I / O bus (high-bandwidth I / O, etc.), and each logical core is electrically coupled to the I / O bus, as are their caches or SRAMs.

[0105] Therefore, a single monolithic die of the present invention (which may have a scanner maximum exposure area) may have two (or more) main functional blocks or different circuits. A conventional monolithic die has a first circuit or first main functional block that occupies 20% to 90%, 30% to 80%, 50% to 90%, or 60% to 90% of the scanner maximum exposure area of ​​a conventional monolithic die (for example, as shown on the left side of Figure 35, the logic circuit corresponding to the circuit occupies about 25% to 30%, the SRAM circuit corresponding to the circuit occupies about 50% to 65%, and the combination of SRAM and logic circuit corresponding to another circuit occupies about 80% to 90%). However, a single monolithic die of the present invention having the same scanner maximum exposure area (i.e., made on the same technology node as a conventional monolithic die such as 5nm or 7nm) may not only include the same first circuit or first main functional block, but may also include another second circuit or second main functional block (as shown on the right side of Figure 35). In another embodiment, the area of ​​the second circuit in the monolithic die of the present invention is the same as the area of ​​the first circuit in the monolithic die of the present invention.

[0106] According to the present invention, the first circuit or first major functional block in a conventional monolithic die can be reduced by 20% to 90% (for example, 30% to 80%, in Figures 32 and 34A, the SRAM circuit can be reduced to 1 / 8 and the logic circuit to 1 / 3.5). In particular, GPUs are well-suited for AI training but not so well for AI inference. FPGAs, on the other hand, have interacting logic blocks and can be designed by engineers to support specific algorithms, making them suitable for AI inference. Both GPUs and FPGAs may be formed within a monolithic die based on an Integrated Scaling and / or Stretching Platform (ISSP). Such a monolithic die excels in parallel processing, learning speed, and efficiency. It also possesses excellent AI inference capabilities with a short time to market, low cost, and high flexibility.

[0107] In another embodiment, a shared high-level cache 3633 (e.g., an L3 cache) between the XPU3631 and YPU3632 can be configured for a single monolithic die 3630, as shown in Figure 36C, by setting a separate mode register (not shown), or by making it adaptively configurable during the operation of the monolithic die. For example, in one embodiment, by setting the mode register, one-third of the high-level cache 3633 can be used by the XPU3631 and two-thirds can be used by the YPU3632. The capacity of such a shared high-level cache 3633 (e.g., an L3 cache) for the XPU3631 or YPU3632 can also be dramatically changed based on the operation of the Integrated Scaling and / or Stretching Platform (ISSP). In yet another embodiment, as shown in Figure 36D, for a single monolithic die 3640, the high-level cache includes an L3 cache 3643 and an L4 cache 3644, with each of the XPU3641 and YPU3642 having a corresponding L3 cache (e.g., 8MB or more) 3643 shared by its own core, and an L4 cache 3644 (e.g., 32MB or more) shared by the XPU3641 and YPU3642. In this example as well, each monolithic die includes an I / O bus (e.g., high-bandwidth I / O), each logical core is electrically coupled to the I / O bus, and their caches or SRAM are similarly electrically coupled to the I / O bus.

[0108] Of particular importance is that, because the area of ​​the eSRAM design according to the present invention is much smaller, it is possible to design a shared SRAM (or embedded SRAM, “eSRAM”) with a slightly larger capacity on the die. Because more and smarter shared eSRAMs can be used, it may be more efficient to connect external DRAM to this eSRAM within the monolithic die with a limited SMFA corresponding to a specific technology node, potentially reducing the required capacity of external DRAM. Thus, the present invention discloses a platform for reconfiguring the memory architecture of a conventional chip system. In a conventional chip system, there is a first monolithic die (e.g., a GPU) connected to a first DRAM memory having a first predetermined capacity (e.g., 1 GB), the first monolithic die having a scanner maximum exposure area (SMFA) based on a target technology node (e.g., 5 nm), and including a first logic circuit and a first SRAM memory, the combined area of ​​the first logic circuit and the first SRAM memory occupies at least 80-90% of the scanner maximum exposure area of ​​the first monolithic die.

[0109] Based on the present invention, a novel platform having a completely novel memory architecture comprises a second monolithic die connected to a second DRAM memory, the second monolithic die including a second logic circuit and a second SRAM memory, and the second monolithic die having the same SMFA based on the same target technology node. Here, the second logic circuit is identical or substantially identical to the first logic circuit (for example, both are the same GPU or NPU), but according to the present invention, the area of ​​the second logic circuit can be reduced, so that the area of ​​the first logic circuit on the first monolithic die is larger than the area of ​​the second logic circuit on the second monolithic die. Furthermore, because the area of ​​the SRAM structure according to the present invention is very small and there is a lot of extra chip area remaining on the second monolithic die, a larger capacity SRAM can be designed on the die, and thus the capacity of the second SRAM memory on the second monolithic die is much higher than the capacity of the first SRAM memory on the first monolithic die. Since the SRAM capacity of the second monolithic die is large, the capacity of the DRAM connected to the second monolithic die can be reduced so that the capacity of the second DRAM memory becomes smaller than the capacity of the first DRAM memory.

[0110] In another embodiment shown in Figure 36E for a single monolithic die 3650, one good approach is to mount a single large Direct Wide Bus (DWB) on a monolithic die (expandable up to the maximum allowable reticle size) connected to another monolithic die of external DRAM or other embedded DRAM ("eDRAM"). The DWB was filed on June 18, 2020, as "MEMORY SYSTEM AND MEMORY This is presented in U.S. Patent Application No. 16 / 904,597, titled "CHIP," the entirety of which is incorporated herein by reference. The DWB has 128 bits, 256 bits, 512 bits, 1024 bits, or more, and can transmit dates in parallel. In Figure 36E, the embedded DRAM ("eDRAM") 3656 may be located on a separate die packaged with a monolithic die 3650 having at least two main functional blocks (XPU 3651 and YPU 3652) and high-capacity SRAM (e.g., L3 cache 3653 and L4 cache 3654). The external DRAM 3657 is separate from package 3655 but communicates with the single monolithic die 3650 via the DWB. Furthermore, the single monolithic die 3650 with a limited SMFA corresponding to a particular technology node also includes a memory controller and physical layer compatible with the DWB.

[0111] In summary, the monolithic / non-uniform integration on a single die that enabled the success of Moore's Law is now facing limitations, particularly due to the limitations of photographic printing technology. On the one hand, scaling the smallest shape printed on the die is extremely costly, and on the other hand, die size is limited by the maximum exposure area of ​​the scanner. However, the increasing and diversifying functionality of processing units is making integration on monolithic dies difficult. Furthermore, the presence of eSRAM on the die for each major function and external DRAM acting only for each individual die function is somewhat redundant and does not constitute an optimized and desirable solution. Based on the proposed Integrated Scaling and / or Stretching Platform (ISSP), monolithic dies and SOC dies can (a) reduce the size of a single major functional block such as FPGA, TPU, NPU, CPU, or GPU significantly, (b) form more SRAM or more functional blocks on a monolithic die, and (c) GPU and FPGA Two or more key functional blocks, such as (or other combinations thereof), that are also reduced through this ISSP can be integrated together on the same monolithic die. Furthermore, more levels of cache can be present within the monolithic die. Such an integrated monolithic die can be combined with another die based on heterogeneous integration (e.g., eDRAM).

[0112] While the present invention has been described with reference to embodiments, it should be understood that the present invention is not limited to the disclosed embodiments, but rather is intended to encompass various modifications and equivalent arrangements that fall within the spirit and scope of the appended claims. [Explanation of Symbols]

[0113] 100 Transistor mmMOSFET 101 Gate structure 102 p type substrate 103 Source 104 Source / Drain Area 105 Quarantine area 107 Drain 109, 111 Contact holes 120 First dielectric layer 150 First conductive layer 160 Second dielectric underlayer 170 Upper dielectric layer 180 Upper conductive layer 302 Pad oxide layer 304 Pad Nitride Layer 402 Dielectric Insulator 602 Gate Layer 604 Nitride layer 702 Spin-on Dielectrics 802 Gate Mask Layer 1502 Oxide 3 Spacer 1504 Low-concentration doped drain 1602 Intrinsic Silicon Electrode 1702 CVD-STI oxide 3 layer 1704 Source Area 1706 Drain area 1802 Oxide Spacer 1901 SOD 1902 Photoresistance layer 1901 SOD layer 1903 Gate Expansion Area

Claims

1. It is a monolithic die, Initially, a semiconductor substrate having a surface, A first processing unit circuit formed on the semiconductor substrate, comprising a plurality of first logic cores, each first logic core circuit corresponding to a low-level cache memory, The system comprises a high-level cache memory used by the first processing unit circuit, One of the plurality of first logical cores is A first transistor formed on the semiconductor substrate, A second transistor adjacent to the first transistor is formed on the semiconductor substrate, The semiconductor substrate is formed and has an STI (Shallow Trench Isolation) region surrounding the first transistor and the second transistor, A monolithic die in which the first transistor has a gate region and a first conductive region having a first vertical sidewall, and the second transistor has a gate region and a second conductive region having a second vertical sidewall, the second vertical sidewall facing the first vertical sidewall.

2. The monolithic die according to claim 1, wherein the STI region has a top surface that is higher than the initial surface.

3. The monolithic die according to claim 2, wherein the first vertical side wall of the first conductive region is in contact with the STI region, and the second vertical side wall of the second conductive region is in contact with the STI region.

4. The maximum exposure area of ​​the scanner for the monolithic die is 26 mm x 33 mm or 858 mm. ２ The monolithic die according to claim 1 is as follows:

5. The monolithic die according to claim 1, further comprising a second processing circuit formed on the monolithic die, wherein the second processing circuit comprises a plurality of second logic core circuits, and each second logic core circuit corresponds to a second cache memory.

6. The monolithic die according to claim 5, wherein the primary function performed by the first processing unit circuit is different from the primary function performed by the second processing unit circuit, and the first processing unit circuit or the second processing unit circuit is selected from the group consisting of a GPU, a CPU, a TPU, an NPU, and an FPGA.

7. The monolithic die according to claim 1, wherein a first local insulator is provided below the first conductive region, and the bottom surface of the first conductive region is insulated from the semiconductor substrate by the first local insulator.

8. The monolithic die according to claim 7, wherein the first conductive region includes an LDD region and a highly doped region extending from the side of the LDD region, and the edge of the LDD region is substantially aligned with the edge of the gate conductive region.

9. The monolithic die according to claim 8, having a metal plug that contacts most of the side surface of the high-concentration doped region of the drain region.

10. The monolithic die according to claim 9, wherein a hole is provided between the gate region and the STI region of the first transistor, and the metal plug is filled into the hole.

11. The monolithic die according to claim 1, wherein a voltage source extends along the bottom surface of the STI region and is electrically connected to the bottom surface of the first conductive region or the second conductive region.

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