Wiring board
The dual-substrate wiring board with resin and glass substrates addresses thermal stress-induced connection failures by leveraging differential thermal expansion, enhancing connection reliability.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- IBIDEN CO LTD
- Filing Date
- 2024-12-09
- Publication Date
- 2026-06-19
Smart Images
Figure 2026100451000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a wiring board.
Background Art
[0002] Patent Document 1 discloses a wiring circuit board having a glass substrate, an insulating resin layer formed on the glass substrate, and a wiring group laminated on the insulating resin layer. A semiconductor element is connected to one surface of the wiring circuit board, and an external printed board is connected to the other surface via connection elements such as solder balls and conductive bumps.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In the wiring circuit board disclosed in Patent Document 1, connection failures due to thermal stress may occur in the connection via the connection elements to the printed board, which is an external element, and sufficient connection quality may not be obtained between the external elements.
Means for Solving the Problems
[0005] The wiring board of the present invention includes a first substrate having a first surface and a second surface opposite to the first surface, and comprising a first core substrate and a first build-up portion including a first insulating layer and a first conductor layer alternately laminated on both sides of the first core substrate; and a second substrate having a third surface and a fourth surface opposite to the third surface, and comprising a second core substrate and a second build-up portion including a second insulating layer and a second conductor layer alternately laminated on both sides of the second core substrate. The second surface of the first substrate and the third surface of the second substrate are connected via a conductive connecting element, the fourth surface of the second substrate is configured as a component mounting surface, the first surface of the first substrate is configured as a substrate connection surface, the second core substrate includes a glass substrate, the first core substrate includes a resin substrate, the thermal expansion coefficient of the first substrate is greater than that of the second substrate, and the thermal expansion coefficient of the first substrate is 7 ppm or more and 15 ppm or less.
[0006] According to embodiments of the present invention, a wiring board with good quality in relation to connections with external substrates can be provided. [Brief explanation of the drawing]
[0007] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2A] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 2B] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 2C] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 3A] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 3B] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 3C] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 3D] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 4A] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 4B] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Modes for carrying out the invention]
[0008] A wiring board according to an embodiment of the present invention will be described with reference to the drawings. Figure 1 shows a cross-sectional view of wiring board 1, which is an example of a wiring board according to the embodiment. Note that wiring board 1 is merely an example of a wiring board according to the embodiment. For example, the laminated structure of the wiring board according to the embodiment, and the number of conductor layers and insulating layers included in the wiring board according to the embodiment are not limited to the laminated structure of wiring board 1 in Figure 1, and the number of conductor layers and insulating layers included in wiring board 1. Also, in the drawings referenced in the following description, certain parts may be enlarged to facilitate understanding of the disclosed embodiment, and the size and length of each component may not be depicted in the exact proportions between them.
[0009] The wiring board of the embodiment includes two substrates (a first substrate and a second substrate). The first substrate and the second substrate are composed of a core substrate and a build-up portion consisting of insulating layers and conductive layers alternately laminated on both sides of the core substrate. The illustrated example wiring board 1 includes a first substrate 10 and a second substrate 20. The first substrate 10 has two main surfaces perpendicular to its thickness direction: a first surface 10F and a second surface 10S opposite to the first surface 10F. The second substrate 20 has two main surfaces perpendicular to its thickness direction: a third surface 20F and a fourth surface 20S opposite to the third surface 20F. The second substrate 20 is positioned so that its third surface 20F faces the second surface 10S of the first substrate 10 and is connected to the first substrate 10 via a connecting element BP. In the illustrated example wiring board 1, the first substrate 10 and the second substrate 20 have substantially the same shape and dimensions in plan view. Here, "planar shape" refers to the shape that can be perceived when the wiring board 1 is viewed from a line of sight parallel to its thickness direction (i.e., viewed from above).
[0010] In the wiring board 1, the first substrate 10 comprises a first core substrate 100 which includes a resin substrate 101 and a first core conductor layer 102 formed in contact with two surfaces perpendicular to the thickness direction of the resin substrate 101. The first core substrate 100 has one surface 100f and the other surface 100s opposite to the surface 100f. One layer of first insulating layer 11 and one layer of first conductor layer 12 are laminated on both sides of the first core substrate 100 (one surface 100f and the other surface 100s), respectively, and a total of two layers of first insulating layer 11 and a total of two layers of first conductor layer 12 constitute a first build-up portion 10B included in the first substrate 10.
[0011] The second substrate 20 includes a second core substrate 200 made of a glass substrate 201. The second core substrate 200 has one surface 200f and the other surface 200s opposite to the first surface 200f. Five layers of second insulating layers 21 and five layers of second conductive layers 22 are laminated on both sides of the second core substrate 200 (one surface 200f and the other surface 200s), resulting in a total of 10 layers of second insulating layers 21 and 10 layers of second conductive layers 22, which constitute the second build-up portion 20B included in the second substrate 20.
[0012] Regarding the description of the wiring board of the embodiment, in the description of the components of the first board 10, the side of the first core board 100 closer to the resin substrate 101 is referred to as "bottom," "inside," or "lower side" or "inside," while the side further from the resin substrate 101 is referred to as "top," "outside," or "upper side" or "outside." The surface of each element constituting the first board 10 that faces the resin substrate 101 is also referred to as the "bottom surface," and the surface facing away from the resin substrate 101 is also referred to as the "top surface." Furthermore, in the description of the components of the second board 20, the side of the second core board 200 closer to the glass substrate 201 is referred to as "bottom" or "lower side," while the side further from the glass substrate 201 is referred to as "top" or "upper side." Therefore, the surface of each element constituting the second board 20 that faces the glass substrate 201 is referred to as the "bottom surface," and the surface facing away from the glass substrate 201 is also referred to as the "top surface."
[0013] The first core conductor layer 102, which is formed in contact with both sides of the resin substrate 101 that constitutes the first core substrate 100 of the first substrate 10, is connected by through conductors 103 that penetrate the resin substrate 101 in the thickness direction. The first core substrate 100 may include a plurality of through conductors 103. Each of the first insulating layers 11 that constitute the first substrate 10 has a via conductor 13 formed thereon that penetrates the first insulating layer 11 in the thickness direction and connects conductors (first conductor layers 12 to each other, or the first conductor layer 12 and the first core conductor layer 102) that are facing each other across the first insulating layer 11. The glass substrate 201 that constitutes the second core substrate 200 of the second substrate 20 has a through conductor 203 formed thereon that penetrates the glass substrate 201 in the thickness direction. The second core substrate 200 may include a plurality of through conductors 203. Each of the second insulating layers 21 constituting the second substrate 20 has a via conductor 23 formed therein that penetrates the second insulating layer 21 in the thickness direction and connects opposing conductors (two second conductor layers 22, or a second conductor layer 22 and a through conductor 203) that are sandwiched between the second insulating layer 21. The through conductor 103 included in the first core substrate 100 is also referred to as the first through conductor 103, and the through conductor 203 included in the second core substrate 200 is also referred to as the second through conductor 203. Furthermore, the via conductor 13 formed in the first insulating layer 11 is also referred to as the first via conductor 13, and the via conductor 23 formed in the second insulating layer 21 is also referred to as the second via conductor 23.
[0014] The first through-conductor 103 includes a conductive film 113 that covers the inner wall of a through-hole 101a formed in the resin substrate 101, and a filler 123, for example, an insulating resin, that fills the region (cavity) defined by the conductive film 113. That is, the first through-conductor 103 includes a conductive film 113 responsible for conductivity and a filler 123 that fills the inside of the conductive film 113. The conductive film 113 constituting the first through-conductor 103 is formed integrally with the first core conductor layer 102. The second through-conductor 203 is formed by filling a through-hole 201a formed in the glass substrate 201 with a conductor. In the illustrated example, the end face of the second through-conductor 203 in the extending direction is formed substantially flush with the surface of the glass substrate 201, and constitutes one surface 200f and the other surface 200s of the second core substrate 200.
[0015] The first via conductor 13 is formed by filling a through-hole 11a formed in the first insulating layer 11 with a conductor. The first via conductor 13 is integrally formed with a first conductor layer 12 that contacts the surface of the first insulating layer 11 on the side opposite to the first core substrate 100 through which the first via conductor 13 passes. The second via conductor 23 is formed by filling a through-hole 21a formed in the second insulating layer 21 with a conductor. The second via conductor 23 is integrally formed with a second conductor layer 22 that contacts the surface of the second insulating layer 21 on the side opposite to the second core substrate 200 through which the second via conductor 23 passes.
[0016] The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 are formed using an arbitrary insulating resin. Examples of the insulating resin include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, and thermoplastic resins such as fluororesin, liquid crystal polymer (LCP), ethylene fluoride (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 may contain inorganic fillers (not shown) such as silica and alumina. The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 may contain reinforcing materials (core materials) such as glass fibers and aramid fibers. In the illustrated example, the resin substrate 101 contains a reinforcing material 101s.
[0017] As the glass material used for the glass substrate 201 constituting the second core substrate 200, for example, soda lime glass, borosilicate glass, or alkali-free glass can be used. These glasses may contain elements such as magnesium, calcium, manganese, aluminum, lead, iron, chromium, potassium, sulfur, antimony, boron, etc. as additives. In the wiring substrate of the embodiment, the core substrate included in the first substrate is composed of an insulating resin having a relatively large coefficient of thermal expansion, and the core substrate included in the second substrate is composed of a glass material having a relatively small coefficient of thermal expansion.
[0018] Examples of conductors that make up the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the second through conductor 203, the conductor film 113 of the first through conductor 103, and the first core conductor layer 102 include copper and nickel, and preferably copper is used. In the example shown in FIG. 1, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, the second through conductor 203, and the first core conductor layer 102 are each shown as a single layer, but may be configured as a multilayer structure. The first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, the second through conductor 203, and the first core conductor layer 102 may have a multilayer structure including, for example, a metal foil layer (preferably a copper foil), a metal film layer (preferably a copper film formed by electroless plating or sputtering), and a plating film layer (preferably an electrolytic copper plating film). For example, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, and the second through conductor 203 may have a two-layer structure including a metal film layer and a plating film layer. The first core conductor layer 102 may have a five-layer structure including a metal foil layer, a metal film layer, and a plating film layer.
[0019] Each conductor layer (the first conductor layer 12, the second conductor layer 22, the first core conductor layer 102) constituting the wiring substrate 1 is patterned so as to have a predetermined conductor pattern. The first conductor layer 12 forming the first surface 10F of the first substrate 10 is formed in a pattern having a plurality of conductor pads 12fp. The first conductor layer 12 forming the second surface 10S of the first substrate 10 is formed in a pattern having a plurality of conductor pads 12sp. The second conductor layer 22 forming the third surface 20F of the second substrate 20 is formed in a pattern having a plurality of conductor pads 22fp. The second conductor layer 22 forming the fourth surface 20S of the second substrate 20 is formed in a pattern having a plurality of conductor pads 22sp.
[0020] On the first substrate 10, a solder resist layer 10Rf, formed using, for example, a photosensitive polyimide resin or epoxy resin, is laminated on the outermost first conductor layer 12 on one side 100f of the first core substrate 100. An opening 10Rfa is formed in the solder resist layer 10Rf, and a conductor pad 12fp is exposed through the opening 10Rfa. That is, the first side 10F of the first substrate 10 includes the surface of the solder resist layer 10Rf and the surface of the conductor pad 12fp exposed through the opening 10Rfa. On the other side 100s of the first core substrate 100, a solder resist layer 10Rs is laminated on the outermost first conductor layer 12. An opening 10Rsa is formed in the solder resist layer 10Rs, and a conductor pad 12sp is exposed through the opening 10Rsa. In other words, the second surface 10S of the first substrate 10 includes the surface of the solder resist layer 10Rs and the surface of the conductor pad 12sp exposed from the opening 10Rsa.
[0021] A solder resist layer 20Rf is laminated on the outermost second conductor layer 22 on one side 200f of the second core substrate 200. An opening 20Rfa is formed in the solder resist layer 20Rf, and a conductor pad 22fp is exposed through the opening 20Rfa. That is, the third side 20F of the second substrate 20 includes the surface of the solder resist layer 20Rf and the surface of the conductor pad 22fp exposed through the opening 20Rfa. A solder resist layer 20Rs is laminated on the outermost second conductor layer 22 on the other side 200s of the second core substrate 200. An opening 20Rsa is formed in the solder resist layer 20Rs, and a conductor pad 22sp is exposed through the opening 20Rsa. That is, the fourth side 20S of the second substrate 20 includes the surface of the solder resist layer 20Rs and the surface of the conductor pad 22sp exposed through the opening 20Rsa.
[0022] As described above, the first core substrate 100 constituting the first substrate 10 includes a resin substrate 101 made of an insulating resin with a relatively large coefficient of thermal expansion, and the second core substrate 200 constituting the second substrate 20 includes a resin substrate 101 made of a glass material with a relatively small coefficient of thermal expansion. As a result, the overall coefficient of thermal expansion of the first substrate 10 and the overall coefficient of thermal expansion of the second substrate 20 are different. Specifically, in the wiring board of the embodiment, the coefficient of thermal expansion of the first substrate 10 is greater than that of the second substrate 20.
[0023] The fourth surface 20S of the second substrate 20, which constitutes the outermost surface of the wiring board 1, is configured as a component mounting surface to which external electronic components D are connected. In the illustrated example, the second substrate 20 has a component mounting area EA, and the conductor pad 22sp is formed within the component mounting area EA. The conductor pad 22sp is connected to the connection pad Dp of the external electronic component D when the wiring board 1 is used. When mounting the external electronic component D onto the wiring board 1, a conductive bonding material SB, such as solder, is placed on the upper surface of the exposed conductor pad 22sp, and the conductor pad 22sp is electrically and mechanically connected to the connection pad Dp of the external electronic component D via this bonding material SB. Examples of electronic components D that can be mounted on the wiring board 1 include, for example, semiconductor integrated circuit devices and active components such as transistors.
[0024] On the wiring board 1, the first surface 10F of the first substrate 10, which is opposite to the fourth surface 20S of the second substrate 20 (the component mounting surface), is the connection surface (substrate connection surface) that connects to the external substrate DD when the wiring board 1 is mounted on an external substrate DD, which is, for example, the motherboard of any electrical device. Therefore, in the use of the wiring board 1, the conductor pad 12fp is connected to the connection pad DDP of the external substrate DD. In the connection between the wiring board 1 and the external substrate DD, a conductive bonding element SBP, such as solder, is placed on the surface of the exposed conductor pad 12sp, and the conductor pad 12sp is electrically and mechanically connected to the connection pad DDP of the external substrate DD via this bonding element SBP.
[0025] Multiple conductor pads 22sp exposed on the fourth surface 20S, which is the component mounting surface of the second substrate 20, are also referred to as component mounting pads 22sp. Multiple conductor pads 12fp exposed on the first surface 10F, which is the substrate connection surface of the first substrate 10, are also referred to as substrate connection pads 12fp. In the illustrated example, on the second substrate 20, the minimum pitch of the multiple component mounting pads 22sp constituting the component mounting surface 20S (i.e., the distance between the centers of two adjacent component mounting pads 22sp) is smaller than the minimum pitch of the multiple conductor pads 22fp constituting the third surface 20F. Also, on the first substrate 10, the minimum pitch of the multiple substrate connection pads 12fp constituting the substrate connection surface 10F is larger than the minimum pitch of the multiple conductor pads 12sp constituting the second surface 10S. In other words, the wiring that may be included in the wiring board 1 can, in its use, enable rewiring that fans out from the connection pads Dp, which have a relatively narrow pitch, of the external electronic component D mounted on the component mounting surface 20S, to the connection pads DDP, which have a relatively wide pitch, of the external board DD. Accordingly, the pitch of the multiple second through-conductors 203 included in the second core board 200 may be smaller than the pitch of the multiple first through-conductors 103 included in the first core board 100. In order to realize a configuration in which the pitch of the second through-conductors 203 is smaller than the pitch of the first through-conductors 103, the diameter of the second through-conductors 203 may be smaller than the diameter of the first through-conductors 103. Here, "diameter" refers to the straight-line distance between the two furthest apart points on the outer edges of the through-conductors 103 and 203 in a plan view.
[0026] As described above with respect to the prior art, when a substrate containing a glass substrate with a relatively small coefficient of thermal expansion is connected to an external substrate, it is thought that connection failures may occur due to the difference in the coefficient of thermal expansion between the external substrate and the glass substrate. Specifically, when the coefficient of thermal expansion of the external substrate is relatively large, the difference between the coefficient of thermal expansion of the substrate containing the glass substrate and the coefficient of thermal expansion of the external substrate is large, and it is thought that thermal stress caused by this difference may concentrate at the connection point, resulting in connection failures. In contrast, the wiring board of the embodiment has a configuration in which a second substrate 20, which includes a second core substrate 200 containing a glass substrate 201, is connected to an external substrate DD via a first substrate 10. As described above, the coefficient of thermal expansion of the second substrate 20 as a whole is different from the coefficient of thermal expansion of the first substrate 10 as a whole, and the coefficient of thermal expansion of the first substrate 10 is larger than that of the second substrate 20. Therefore, the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the first substrate 10 may be smaller than the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the second substrate 20, and the difference between the thermal expansion coefficient of the second substrate 20 and the thermal expansion coefficient of the first substrate 10 may also be smaller than the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the second substrate 20. In such cases, the thermal stress that may be applied to the connection between the first substrate 10 and the external substrate DD, and the connection between the second substrate 20 and the first substrate 10, can be mitigated compared to the case where the second substrate 20 is directly connected to the external substrate DD. It is considered that the occurrence of connection failures caused by thermal stress in the connection between the second substrate 20 and the external substrate DD can be suppressed.
[0027] The thermal expansion coefficient of the second substrate 20, which includes a second core substrate 200 made of a glass substrate 201, is, for example, 4 ppm or more and 12 ppm or less. The thermal expansion coefficient of the first substrate 10, which has a first core substrate 100 including a resin substrate 101, is 7 ppm or more and 15 ppm or less. From the viewpoint of avoiding connection failure due to thermal stress caused by the difference in thermal expansion coefficients at the connection portion as described above, it is preferable that the difference between the thermal expansion coefficient of the first substrate 10 and the thermal expansion coefficient of the second substrate 20 is 2 ppm or more and 6 ppm or less.
[0028] Furthermore, it is preferable that the dimension of the second build-up portion 20B in the thickness direction on the second substrate 20 is larger than the dimension of the first build-up portion 10B in the thickness direction on the first substrate 10. It is believed that the stress applied to the second substrate 20 when an external electronic component D is mounted on the component mounting surface 22sp is absorbed by the second substrate 20 before it reaches the connection between the second substrate 20 and the first substrate 10, thereby suppressing the occurrence of defects at the connection between the second substrate 20 and the first substrate 10.
[0029] As described above, the conductors constituting the second substrate 20 (second conductor layer 22, second via conductor 23, second through conductor 203) may constitute rewiring that fans out from the component mounting pad 22sp constituting the component mounting surface 20S to the conductor pad 22fp constituting the third surface 20F. Similarly, the conductors constituting the first substrate 10 (first conductor layer 12, first via conductor 13, first through conductor 103) may constitute rewiring that fans out from the conductor pad 12sp constituting the second surface 10S to the board connection pad 12fp constituting the first surface 10F. Consequently, the second via conductor 23 may be formed to have a finer pitch than the first via conductor 13, and therefore, the thickness of the second insulating layer 21 constituting the second substrate 20 may be smaller than the thickness of the first insulating layer 11 constituting the first substrate 10. In such cases, from the viewpoint of increasing the thickness of the second build-up portion 20B of the second substrate 20 in order to alleviate the stress when mounting the external electronic component D as described above, it is preferable that the number of layers of the second insulating layer 21 constituting the second build-up portion 20B is greater than the number of layers of the first insulating layer 11 constituting the first build-up portion 10B of the first substrate 10. Accordingly, it is preferable that the number of layers of the second conductor layer 22 constituting the second build-up portion 20B is greater than the number of layers of the first conductor layer 12 constituting the first build-up portion 10B of the first substrate 10.
[0030] The conductive pads 22fp constituting the third surface 20F of the second substrate 20 are mechanically and electrically connected to the conductive pads 12sp constituting the second surface 10S of the first substrate 10 via conductive connecting elements BP. The space between the third surface 20S of the second substrate 20 and the second surface 10F of the first substrate 10 (specifically, between the solder resist layer 20Rf and the solder resist layer 10Rs) may be filled with an underfill material (not shown), such as epoxy resin or polyimide resin.
[0031] Next, with reference to Figures 2A to 2C, 3A to 3D, and 4A to 4B, the manufacturing method for the wiring board 1 shown in Figure 1 will be explained. Unless otherwise specified, each component formed in the manufacturing method described below may be formed using the materials exemplified as the materials for the corresponding components in the description of the wiring board 1 in Figure 1. Furthermore, in Figures 2A to 4B, the metal foil layer, metal film layer, and plating film layer, which are components of each conductor layer, are not depicted; instead, each conductor layer is depicted as a single layer, similar to Figure 1.
[0032] Manufacturing the wiring board 1 includes manufacturing the first board 10, manufacturing the second board 20, and connecting the first board 10 and the second board 20. First, Figures 2A to 2C will be shown to explain the manufacturing of the first board 10.
[0033] As shown in Figure 2A, the first core substrate 100 is formed. For example, a resin substrate 101 made of an insulating resin such as epoxy resin, and a laminate (e.g., a double-sided copper-clad laminate) having metal foil (not shown) provided on both sides of the resin substrate 101 are prepared. Through holes 101a are formed in the prepared laminate, for example by drilling. Subsequently, a metal film layer (not shown) is formed on the inner wall surface of the through holes 101a and the upper surface of the metal foil by electroless plating, and a plating film layer (not shown) is formed on the metal film layer by electroplating using the metal film layer as a power supply layer. As a result, a conductive film 113 is formed having a metal film layer and a plating film layer, covering the inner wall surface of the through holes 101a.
[0034] Next, the inside of the conductive film 113 is filled with a filler 123, for example, epoxy resin, to form a first through-conductor 103 composed of the conductive film 113 and the filler 123. After the filler 123 has solidified, a metal film layer and a plating film layer are further formed on the entire surface where the filler 123 and the plating film layer are exposed, and a first core conductor layer 102 having a predetermined conductor pattern is formed by a subtractive method. A first core substrate 100 having one surface 100f and the other surface 100s is obtained.
[0035] Next, as shown in Figure 2B, a first insulating layer 11 is formed to cover the first core conductor layer 102 and the resin substrate 101 exposed from the pattern of the first core conductor layer 102. The first insulating layer 11 is formed by thermocompression bonding a film-like insulating resin, such as epoxy resin or phenolic resin, to the surface of the first core substrate 100 (on one surface 100f and on the other surface 100s). Subsequently, a first via conductor 13 penetrating the first insulating layer 11 and a first conductor layer 12 on the first insulating layer 11 are integrally formed. Specifically, through holes 11a are formed in the first insulating layer 11 at the positions where the first via conductor 13 is to be formed, for example, by irradiation with carbon dioxide laser light. The first conductor layer 12 and the first via conductor 13 are formed by forming a metal film layer (not shown) on the inner surface of the through hole 11a and the upper surface of the first insulating layer 11 by electroless plating or sputtering, and by forming a plated film layer (not shown) by electroplating using a plating resist having appropriate openings and using the metal film layer as a power supply layer. The first conductor layer 12 on one side 100f of the first core substrate 100 is formed in a pattern including a conductor pad 12fp. The first conductor layer 12 on the other side 100s of the first core substrate 100 is formed in a pattern including a conductor pad 12sp.
[0036] Next, as shown in Figure 2C, a solder resist layer 10Rf is formed on the outermost first conductor layer 12 and first insulating layer 11 on one side 100f of the first core substrate 100, having an opening 10Rfa that exposes the conductor pad 12fp. On the other side 100s of the first core substrate 100, a solder resist layer 10Rs is formed on the outermost first conductor layer 12 and first insulating layer 11, having an opening 10Rsa that exposes the conductor pad 12sp. The manufacturing of the first substrate 10, having a first side 10F and a second side 10S opposite to the first side 10F, is completed. The thermal expansion coefficient of the manufactured first substrate 10 is, for example, 7 ppm or more and 15 ppm or less.
[0037] Next, the manufacturing of the second substrate 20 will be described with reference to Figures 3A to 3D. First, as shown in Figure 3A, the second core substrate 200 is formed. In forming the second core substrate 200, first, a glass substrate 201 containing, for example, soda-lime glass, borosilicate glass, or alkali-free glass is prepared, and through holes 201a are formed in the glass substrate 201. In forming the through holes 201a, for example, a modified area is formed in the position where the through holes 201a are to be formed in the glass substrate 201 by irradiation with laser light, and the through holes 201a can be formed by removing the modified area with, for example, an etching solution containing an aqueous solution of hydrogen fluoride. As the laser light that forms the modified area, helium-neon lasers, argon ion lasers, excimer lasers, and various YAG lasers can be used.
[0038] Next, the interior of the formed through-hole 201a is completely filled with a conductor, and the conductor is formed to completely cover two surfaces of the glass substrate 201 that are perpendicular to the thickness direction. In forming the conductor, a metal film layer (not shown) is formed on the inner wall surface of the through-hole 201a and on the two surfaces of the glass substrate 201, for example by electroless plating, and then a plating film layer (not shown) is formed on the metal film layer by electroplating using the metal film layer as a power supply layer. A second through-conductor 203 having a metal film layer and a plating film layer is formed, and the two surfaces of the glass substrate 201 are covered with a two-layer structure of conductors consisting of a metal film layer and a plating film layer. Subsequently, the conductor layers covering both sides of the glass substrate 201 are removed, for example by CMP (chemical mechanical polishing). As shown in Figure 3A, a second core substrate 200 is formed, having one surface 200f and the other surface 200s, composed of the surface of the glass substrate 201 and the surface (end face) of the second through-conductor 203.
[0039] Next, as shown in Figure 3B, a second insulating layer 21 is formed covering one surface 200f and the other surface 200s of the second core substrate 200, and then a second conductor layer 22 is formed on top of the second insulating layer 21. Simultaneously with the formation of the second conductor layer 22, a second via conductor 23 is formed integrally with the second conductor layer 22.
[0040] The second insulating layer 21 is formed, for example, by thermocompression bonding of a film-like insulating resin (e.g., epoxy resin) onto the surface of the second core substrate 200 (one surface 200f and the other surface 200s). Through holes 21a are formed in the second insulating layer 21 at the positions where the second via conductor 23 is to be formed, for example by irradiation with carbon dioxide laser light. The second conductor layer 22 and the second via conductor 23 are formed by forming a metal film layer (not shown) on the inner surface of the through holes 23a and the upper surface of the second insulating layer 21 by electroless plating or sputtering, and by forming a plating film (not shown) by electroplating using a plating resist with appropriate openings and using the metal film layer as a power supply layer.
[0041] Next, as shown in Figure 3C, the same process as the formation of the second insulating layer 21 and the integral formation of the second via conductor 23 and the second conductor layer 22 described above is repeated a desired number of times on the upper side of one surface 200f and the other surface 200s of the second core substrate 200. As shown, a second build-up section 20B is formed, comprising a total of 10 layers of the second insulating layer 21 and a total of 10 layers of the second conductor layer 22. The outermost second conductor layer 22 on the side of one surface 200f is formed in a pattern including a conductor pad 22fp. The outermost second conductor layer 22 on the other surface 200s is formed in a pattern including a conductor pad 22sp.
[0042] Next, as shown in Figure 3D, a solder resist layer 20Rf is formed on the outermost second conductor layer 22 and second insulating layer 21 on one side 200f of the second core substrate 200, having an opening 20Rfa that exposes the conductor pad 22fp. On the other side 200s of the second core substrate 200, a solder resist layer 20Rs is formed on the outermost second conductor layer 22 and second insulating layer 21, having an opening 20Rsa that exposes the conductor pad 22sp. The manufacturing of the second substrate 20, having a first side 20F and a second side 20S opposite to the first side 20F, is completed. The thermal expansion coefficient of the manufactured second substrate 20 is, for example, 4 ppm or more and 12 ppm or less.
[0043] Next, Figures 4A and 4B will be referenced to explain how to connect the first substrate 10 and the second substrate 20. First, as shown in Figure 4A, connecting elements BP, such as solder bumps, are formed on the conductive pads 12sp that constitute the second surface 10S of the first substrate 10.
[0044] Next, as shown in Figure 4B, the second substrate 20 is connected to the first substrate 10 via a connecting element BP. Specifically, the second substrate 20 is positioned so that its third surface 20F faces the second surface 10S of the first substrate 10, and the conductor pads 22fp exposed within the opening 20Rsa of the solder resist layer 20Rs constituting the third surface 20F are connected to the connecting element BP. The manufacturing of the wiring board 1 is then completed. After the connection of the first substrate 10 and the second substrate 20, an underfill material (not shown) may be filled into the gap between the third surface 20F of the second substrate 20 and the second surface 10S of the first substrate 10, which are mutually connected via the connecting element BP. [Explanation of Symbols]
[0045] 1 Wiring board 10. First board 20 Second board 10B First Build-up Section 20B Second Build-up Section 11. Insulating layer (first insulating layer) 21. Insulating layer (second insulating layer) 12 Conductor layer (First conductor layer) 22 Conductor layer (second conductor layer) 13 Via conductor (first via conductor) 23 Via conductor (2nd via conductor) 100 First Core Board 101 Resin substrate 102 First core conductor layer 200 Second Core Board 201 Glass Substrate 103 Through-conductor (First through-conductor) 203 Through-conductor (Second through-conductor) 12fp Conductor Pads (Board Connection Pads) 12sp, 22fp conductor pads 22sp Conductor Pad (Component Mounting Pad) BP connection element EA component mounting area
Claims
1. A first substrate having a first surface and a second surface opposite to the first surface, and comprising a first core substrate and a first build-up portion including a first insulating layer and a first conductive layer alternately laminated on both sides of the first core substrate, A second substrate having a third surface and a fourth surface opposite to the third surface, and comprising a second core substrate and a second build-up portion including a second insulating layer and a second conductive layer alternately laminated on both sides of the second core substrate, A wiring board including, The second surface of the first substrate and the third surface of the second substrate are connected via a conductive connecting element. The fourth surface of the second substrate is configured as a component mounting surface. The first surface of the first substrate is configured as a substrate connection surface, The second core substrate includes a glass substrate, The first core substrate includes a resin substrate, The thermal expansion coefficient of the first substrate is greater than that of the second substrate. The thermal expansion coefficient of the first substrate is 7 ppm or more and 15 ppm or less.
2. The wiring board according to claim 1, wherein the difference between the thermal expansion coefficient of the first substrate and the thermal expansion coefficient of the second substrate is 2 ppm or more and 6 ppm or less.
3. The wiring board according to claim 1, wherein the thickness of the first build-up portion is smaller than the thickness of the second build-up portion.
4. The wiring board according to claim 1, wherein the number of conductor layers constituting the second build-up portion is greater than the number of conductor layers constituting the first build-up portion.
5. The wiring board according to claim 1, wherein the shape and dimensions of the first board and the second board in a plan view are substantially equal.
6. A wiring board according to claim 1, wherein the first core board includes a first through conductor, the second core board includes a second through conductor, and the diameter of the second through conductor is smaller than the diameter of the first through conductor.
7. A wiring board according to claim 1, wherein the third surface includes a plurality of conductor pads, the fourth surface includes a plurality of component mounting pads, and the minimum pitch of the plurality of component mounting pads is smaller than the minimum pitch of the plurality of conductor pads.