Semiconductor equipment

Abstract

To improve the reliability of solder connections in response to temperature changes during package assembly. [Solution] The package has a package structure that can be mounted on a mounting substrate 200, and includes a semiconductor chip 20 having a first surface 20a and a second surface 20b opposite to the first surface 20a, and a plurality of connection terminal portions 60 for making an electrical connection between the semiconductor chip 20 and the mounting substrate 200, wherein a resin layer 40 with a thickness of 100 μm or more is formed between the second surface 20b of the semiconductor chip 20 and the connection terminal portions 60, and the resin layer 40 is configured to include one or more base portions 42 that are individually arranged on and protrude in the thickness direction of the resin layer 40, and the base portions 42 have a thickness of 33% or more of the thickness of the resin layer 40.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In recent years, in order to cope with the miniaturization and high integration of semiconductor chips, flip-chip mounting with a semiconductor device as a CSP (Chip Scale Package) has been actively adopted.

[0003] Since the package size of CSP is about the same as that of a semiconductor chip, it is small and the productivity of the wafer-level process is good. On the other hand, the solder connection reliability of the package mounting is low. In the package mounting of CSP, the reason for the low solder connection reliability is that the linear expansion coefficient of silicon (2.6 to 4.2 ppm / °C) that constitutes the chip body in the semiconductor chip that is the mother body of CSP and the linear expansion coefficient of the mounting substrate such as a motherboard on which CSP is mounted (15 to 20 ppm / °C) have a large difference. Therefore, due to the thermal expansion difference with respect to temperature changes such as temperature cycles, the stress applied to the connection terminal portion and its periphery becomes large.

[0004] Patent Document 1 discloses a semiconductor device aimed at enhancing the reliability of an external terminal (connection portion) against distortion due to the thermal expansion difference between a semiconductor chip and a printed circuit board by interposing a low-elasticity and thick stress relaxation layer laminated on an insulating film on the semiconductor chip between the semiconductor chip and wiring and a land.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the semiconductor device described in Patent Document 1, the stress relaxation layer is a single layer with substantially uniform thickness, and all connection parts are located on the stress relaxation layer. Therefore, in the semiconductor device described in Patent Document 1, when strain occurs, the entire stress relaxation layer deforms to absorb the stress, resulting in a limited stress relaxation effect. Consequently, the semiconductor device described in Patent Document 1 has room for improvement in terms of solder connection reliability.

[0007] The present invention has been made in view of the above circumstances, and specifically aims to provide a semiconductor device that can improve the reliability of solder connections with respect to temperature changes during package mounting. [Means for solving the problem]

[0008] The above problem can be solved by any of the following means (1) to (15).

[0009] (1) A semiconductor device having a package structure that can be mounted on a mounting substrate, comprising: a semiconductor chip having a first surface and a second surface opposite to the first surface; and a plurality of connection terminals for making an electrical connection between the semiconductor chip and the mounting substrate, wherein a resin layer having a thickness of 100 μm or more is formed between the second surface of the semiconductor chip and the connection terminals, and the resin layer comprises one or more base portions that are provided projecting in the thickness direction of the resin layer and on which the connection terminals are individually arranged, and the base portions have a thickness of 33% or more of the thickness of the resin layer.

[0010] (2) The semiconductor device according to (1) above, wherein the resin layer further has a base portion disposed on the semiconductor chip side, and the base portion is disposed between the base portion and the semiconductor chip.

[0011] (3) The semiconductor device according to (1) or (2) above, wherein the base portion is formed to correspond to at least one of the connection terminal portions arranged on the outer periphery of the resin layer in a plan view.

[0012] (4) The semiconductor device according to any one of (1) to (3) above, wherein the base portion is formed in correspondence with the connection terminal portion which is located at the position furthest from the center of the semiconductor chip in a plan view.

[0013] (5) The semiconductor device according to any one of (1) to (3) above, wherein the base portion is formed in correspondence with the connection terminal portion located at the position furthest from the center of the semiconductor chip in a plan view, and at least one of the connection terminal portions adjacent to the connection terminal portion located at the position furthest from the center of the semiconductor chip.

[0014] (6) The semiconductor device according to any one of (1) to (5) above, wherein the resin layer further has a mound portion on which a plurality of connection terminal portions are arranged, a bridge portion is formed between the base portion and the mound portion adjacent to the base portion, the bridge portion has a terminal forming surface of the mound portion and a wiring forming surface continuous with the terminal forming surface of the base portion, and wiring connected to the connection terminal portion arranged on the base portion is laid to connect to the connection terminal portion arranged on the base portion by passing through the terminal forming surface of the mound portion and the wiring forming surface of the bridge portion.

[0015] (7) The semiconductor device according to (6) above, wherein the bridge portion is formed to extend in a direction intersecting the direction of the principal stress applied to the base portion, and the wiring connected to the connection terminal portion located on the base portion is laid along the extending direction of the bridge portion.

[0016] (8) The semiconductor device according to any one of (1) to (5) above, wherein the wiring connected to the connection terminal portion located on the base portion is laid through the inside of the base portion and connected to the connection terminal portion to be connected.

[0017] (9) The wiring connected to the connection terminal portion located on the base portion is laid along the outer surface of the base portion, as described in any one of (1) to (5) above.

[0018] (10) The thickness of the pedestal portion is such that the thickness of the pedestal portion disposed on the outer peripheral side of the semiconductor chip is greater than the thickness of the pedestal portion disposed on the central side of the semiconductor chip in a plan view. The semiconductor device according to any one of (1) to (9) above.

[0019] (11) The resin layer is formed of a photosensitive material. The semiconductor device according to any one of (1) to (10) above.

[0020] (12) The connection terminal portion is formed of solder. The semiconductor device according to any one of (1) to (11) above.

[0021] (13) The resin layer has an elastic modulus of 10 GPa or more and 20 GPa. The semiconductor device according to any one of (1) to (12) above.

[0022] (14) The package structure is a chip size package or a fan out package. The semiconductor device according to any one of (1) to (13) above.

[0023] (15) The semiconductor chip is an image sensor. The semiconductor device according to (1) or (14) above.

Advantages of the Invention

[0024] The semiconductor device according to an embodiment of the present invention can reduce the solder stress associated with temperature changes during package mounting and enhance the solder connection reliability.

Brief Description of the Drawings

[0025] [Figure 1] It is a cross-sectional schematic view showing a state where the semiconductor device according to an embodiment of the present invention is mounted on a mounting substrate. [Figure 2] It is a cross-sectional schematic view of the semiconductor device of the present embodiment. [Figure 3A] It is a cross-sectional schematic view showing the form of the resin layer. [Figure 3B] It is a cross-sectional schematic view showing another form of the resin layer. [Figure 4A]This is a partially shown schematic cross-sectional diagram illustrating the state of the resin layer before distortion occurs due to temperature changes. [Figure 4B] This is a partially shown schematic cross-sectional diagram illustrating the state of the resin layer after deformation occurs due to temperature changes. [Figure 5A] This is a plan view of a semiconductor device having a resin layer according to Embodiment 1. [Figure 5B] Figure 5A is a schematic cross-sectional view taken along line AA. [Figure 6A] This is a plan view of a semiconductor device having a resin layer of form 2. [Figure 6B] Figure 6A is a schematic cross-sectional view taken along line BB. [Figure 7A] This is a plan view of a semiconductor device having a resin layer of form 3. [Figure 7B] Figure 7A is a schematic cross-sectional view taken along the CC line. [Figure 8A] This is a plan view of a semiconductor device having a resin layer of form 4. [Figure 8B] Figure 8A is a schematic cross-sectional view taken along the line DD. [Figure 9A] This is a plan view of a semiconductor device having a resin layer according to form 5. [Figure 9B] Figure 9A is a schematic cross-sectional view taken along the line E1-E1. [Figure 9C] Figure 9A is a schematic cross-sectional view taken along the line E2-E2. [Figure 10A] This is a plan view of a semiconductor device having a resin layer of form 6. [Figure 10B] Figure 10A is a schematic cross-sectional view taken along the line F1-F1. [Figure 10C] Figure 10A is a schematic cross-sectional view taken along the line F2-F2. [Figure 11A] This is a schematic plan view showing wiring configuration 1 in the semiconductor device of this embodiment. [Figure 11B] This is a schematic cross-sectional view obtained by cutting along the line passing through A1-B1-D1-E3 in Figure 11A. [Figure 11C] Figure 11A is a schematic diagram of a combined cross-section obtained by cutting along the line passing through A1-B1-C1. [Figure 12A] This is a schematic plan view showing wiring configuration 2 in the semiconductor device of this embodiment. [Figure 12B] This is a schematic cross-sectional view obtained by cutting along the line passing through A2-B2-C2 in Figure 12A. [Figure 13A] This is a schematic plan view showing wiring configuration 3 in the semiconductor device of this embodiment. [Figure 13B] This is a schematic cross-sectional view obtained by cutting along the cutting line passing through A3-B3-C3 in Figure 13A. [Figure 14] This table shows the model conditions obtained from the simulation of the example. [Figure 15] This table shows the material properties obtained from simulations of the examples. [Figure 16] Figure (a) is a plan view showing a 1 / 8 scale model of the semiconductor device used in the simulation, and Figure (b) is a side view of the model shown in Figure (a). [Figure 17A] This table shows the simulation results for the example. [Figure 17B] This table shows the simulation results for the example. [Figure 17C] This table shows the simulation results for the example. [Figure 17D] This table shows the simulation results for the example. [Figure 18A] This is a schematic plan view showing the structure of the semiconductor devices of Samples 1 to 8 of the embodiment. [Figure 18B] Figure 18A is a schematic cross-sectional view taken along the GG line. [Figure 19A] This is a schematic plan view showing the structure of the semiconductor devices of Samples 9 to 20 in the examples. [Figure 19B] Figure 19A is a schematic cross-sectional view taken along line HH. [Figure 20A] This is a schematic plan view showing the structure of the semiconductor devices of Samples 21 to 26 of the embodiment. [Figure 20B] This is a schematic cross-sectional view taken along line II in Figure 20A. [Figure 21A]This is a schematic plan view showing the structure of the semiconductor devices of Sample 27 and Sample 28 in the embodiment. [Figure 21B] Figure 21A is a schematic cross-sectional view taken along the JJ line. [Figure 22A] This is a schematic plan view showing the structure of the semiconductor device with a resin layer in Sample 29 of the embodiment. [Figure 22B] Figure 22A is a schematic cross-sectional view taken along the KK line. [Figure 23A] This is a schematic plan view showing the structure of the semiconductor device with a resin layer in Sample 30 of the example. [Figure 23B] Figure 23A is a schematic cross-sectional view taken along the line LL. [Modes for carrying out the invention]

[0026] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Furthermore, the embodiments described below are merely illustrative, and various modifications are possible from such embodiments.

[0027] In the following, "upper part" or "top" may include not only things that are directly above and in contact, but also things that are above but not in contact. Similarly, "lower part" or "bottom" may include not only things that are directly below and in contact, but also things that are below but not in contact.

[0028] A singular expression includes plural expressions unless the context clearly indicates that it is singular. Furthermore, when a part is said to "include," "possess," or "have" a component, it does not exclude other components, but rather may include other components unless otherwise specified.

[0029] Unless explicitly stated otherwise, the steps constituting the method shall be performed in the appropriate order. This order is not necessarily limited to the order in which the steps are described. All examples or illustrative terms are used solely to illustrate the technical idea and are not limited in scope to the claims.

[0030] In the following explanations, when ordinal numbers such as "1st" and "2nd" are used, they are for convenience only and do not prescribe any particular order unless otherwise specified.

[0031] The semiconductor device 1 shown in each embodiment of the present invention can be a wafer-level package (CSP) in which the semiconductor chip 20 is composed of a solid-state image sensor (COMS image sensor) as its package structure. Furthermore, the semiconductor device 1 can be a fan-out package.

[0032] A semiconductor device 1 according to an embodiment of the present invention will be described with reference to the drawings.

[0033] For the sake of explanation, we will set an XYZ Cartesian coordinate system for the semiconductor device 1. The direction parallel to the X-axis within a predetermined plane is defined as the X-axis direction. The direction parallel to the Y-axis perpendicular to the X-axis within a predetermined plane is defined as the Y-axis direction. The direction parallel to the Z-axis perpendicular to both the X-axis and the Y-axis is defined as the Z-axis direction. In this invention, the predetermined plane is an XY plane parallel to the horizontal plane, and the Z-axis is a perpendicular direction perpendicular to the predetermined plane and is the axis in the thickness direction of the semiconductor device 1.

[0034] As shown in Figures 1 and 2, the semiconductor device 1 is composed of a transparent substrate 10, a semiconductor chip 20, an insulating layer 30, a resin layer 40, wiring 50, a connection terminal portion 60, and a protective layer 70. As shown in Figure 1, the semiconductor device 1 can be mounted on a mounting substrate 200 via the connection terminal portion 60.

[0035] The transparent substrate 10 is formed from a light-transmitting inorganic or organic material. Typical examples include glass, germanium, silicon, and acrylic.

[0036] As shown in Figure 2, the transparent substrate 10 has a first surface 10a which is the incident surface of light, and a second surface 10b which is opposite to the first surface 10a. The transparent substrate 10 is joined to the semiconductor chip 20 via a joint 2 made of a sealing material (DAM agent) or the like, with the second surface 10b and the first surface 20a facing each other. In Figure 1, the first surface 10a of the transparent substrate 10 is the top surface of the transparent substrate 10, and the second surface 10b of the transparent substrate 10 is the bottom surface of the transparent substrate 10.

[0037] The semiconductor chip 20 has a chip body made of silicon or the like. The semiconductor chip 20 has a first surface 20a which is the incident surface of light, and a second surface 20b which is opposite to the first surface 20a. An IC circuit pattern or the like is formed on the first surface 20a. In Figure 2, the first surface 20a of the semiconductor chip 20 is the top surface of the chip body, and the second surface 20b of the semiconductor chip 20 is the bottom surface of the chip body.

[0038] The semiconductor chip 20 has a light-receiving area in which multiple pixels that convert incident light into electrical signals are arranged in rows vertically and horizontally, and can be configured as a CMOS image sensor with an on-chip lens (microlens) 21, as well as a color filter, photodiode, pixel circuit, etc. (not shown) mounted on it.

[0039] An electrode 22 is formed on the first surface 20a of the semiconductor chip 20, and through holes (vias) 23 are formed from the second surface 20b to the electrode 22 so that electrical conductivity with the electrode 22 is possible. The through holes 23 can be formed by known processing methods such as deep reactive ion etching (DRIE).

[0040] An insulating layer 30 is formed on the second surface 20b of the semiconductor chip 20, the side surface, and the side surface of the through hole 23. The insulating layer 30 is formed by known thin-film formation methods such as vapor deposition, sputtering, and CVD, and at least the portion formed on the surface facing the electrode 22 at the bottom of the through hole 23 is removed.

[0041] A resin layer 40 for arranging the connection terminal portion 60 is formed on at least a portion of the insulating layer 30.

[0042] As shown in Figure 2, the resin layer 40 can be composed of a base portion 41, a pedestal portion 42, and a hill portion 43. The resin layer 40 can be configured to include at least the pedestal portion 42 from the above configuration. In Figures 2, 3A, 3B, etc., the boundaries of the resin layer 40 are shown with dotted lines for the sake of clarity in the explanation, but in reality, it is formed integrally from the same material.

[0043] The base portion 41 is positioned on the semiconductor chip 20 side of the resin layer 40. A base portion 42 or a mound portion 43 can be formed on the connection terminal portion 60 side of the base portion 41. The thickness of the base portion 41 can be made thinner than the thickness of the base portion 42, or zero. In that case, the base portion 42 or the mound portion 43 can be formed directly on the insulating layer 30.

[0044] The base portion 42 has a convex shape such as a cone (partially), a square pyramid (partially), or a cylinder, and has a terminal forming surface 42a, and is formed at a position corresponding to the formation position of the connection terminal portion 60. The connection terminal portions 60 are individually arranged on the terminal forming surface 42a of the base portion 42. Therefore, the base portion 42 has a one-to-one relationship with each connection terminal portion 60. From the viewpoint of effectively absorbing distortion due to temperature changes and improving the solder connection reliability of the connection terminal portion 60, the base portion 42 has a thickness of 33% or more of the thickness of the resin layer 40.

[0045] The mound portion 43 is formed adjacent to the base portion 42, and multiple connection terminal portions 60 are arranged on it. The mound portion 43 has a convex shape with a terminal forming surface 43a on which multiple connection terminal portions 60 are arranged. The number and position of the connection terminal portions 60 arranged on the mound portion 43 can be arbitrarily set according to the specifications of the semiconductor device 1.

[0046] Between the base portion 42 and other adjacent base portions 42 or hill portions 43, gap portions 45 are formed so that the base portions 42 can be individually independent.

[0047] As shown in Figure 3A, if the base portion 41 is not formed below the base portion 42, the thickness T2 of the base portion 42 corresponds to the thickness T of the resin layer 40. Therefore, the heights of the resin layer 40 and the base portion 42 shown in Figure 3A are the same. Also, as shown in Figure 3B, if the resin layer 40 is composed of a base portion 41, a base portion 42, and a hill portion 43, the base portion 42 and the hill portion 43 can be formed above the base portion 41, respectively. Therefore, the thickness T of the resin layer 40 corresponds to the height obtained by adding the thickness T1 of the base portion 41 to the thickness T2 of the base portion 42, and the height obtained by adding the thickness T1 of the base portion 41 to the thickness T3 of the hill portion 43, as shown in Figure 3B. The thickness of the resin layer 40 can be measured with a micrometer after the resin layer 40 is formed during the manufacturing process, or after the package is completed, the package can be cut and measured using the ranging function of a microscope. The resin layer 40 is formed by appropriately combining the base portion 41, the pedestal portion 42, and the mound portion 43, as shown in Figures 3A and 3B, but the thickness refers to the total thickness of the resin layer 40.

[0048] The resin layer 40 can be made of a photosensitive material applicable to various semiconductor packages such as solder resist, or an insulating resin such as epoxy resin. From the viewpoint of ease of formation, it is preferable to form the resin layer 40 with a photosensitive material. Furthermore, it is preferable that the resin layer 40 contains a non-conductive filler, such as an inorganic filler having a spherical or flattened shape such as silica, in addition to the photosensitive material or insulating resin. The content of the non-conductive filler in the resin layer 40 can be adjusted to achieve the best solder connection reliability of the semiconductor device 1. By adjusting the content of the filler, it is possible to adjust the coefficient of thermal expansion and elastic modulus of the resin layer 40 itself. Therefore, the semiconductor device 1, by having a resin layer 40 with a filler content adjusted to achieve the best solder connection reliability, becomes a package with excellent solder connection reliability.

[0049] When a photosensitive resin material is used, the resin layer 40 can be formed by molding it into the desired shape so that the base portion 42 is formed, and then exposing and developing it. When an insulating resin such as epoxy resin is used, the resin layer 40 can be formed to the required thickness, and then unnecessary parts can be removed so that the base portion 42 is formed. Alternatively, the resin layer 40 can be formed simultaneously with the base portion 42 when the resin layer 40 is formed using a mold or the like.

[0050] When using an insulating resin as the resin layer 40, materials having an elastic modulus of 10 GPa or more and 20 GPa or less can be used. Semiconductor encapsulants can be used as materials that satisfy the aforementioned elastic modulus. Furthermore, if the resin layer 40 is made too thin, its effect in absorbing strain decreases, and if it is made too thick, the wafer may not fit into the stocker or the wafer may warp. For this reason, a thickness of 100 μm or more and 800 μm or less is desirable (due to stocker requirements), and a thickness of 800 μm or less is desirable to suppress warping. The elastic modulus can be, for example, the storage modulus that can be measured by dynamic viscoelasticity measurement. Alternatively, the elastic modulus can be the Young's modulus measured by bending tests, tensile tests, etc., using a universal testing machine.

[0051] Figure 4A shows the semiconductor device 1 before thermal shrinkage. Figure 4B shows the semiconductor device 1 after thermal shrinkage. The dashed line in Figure 4B represents the external shape of the semiconductor device 1 before thermal shrinkage. As shown in Figure 4B, when the entire device shrinks due to thermal shrinkage, the amount of shrinkage of the mounting substrate 200 is greater than the amount of shrinkage of the transparent substrate 10 and semiconductor chip 20 due to the difference in thermal expansion, so stress is applied to the connection terminal portion 60. However, in this embodiment, the individually formed base portions 42 tilt and deform individually, which effectively relieves this stress. In other words, the semiconductor device 1 of this embodiment can effectively absorb the stress associated with thermal shrinkage and maintain the connection state of the connection terminal portion 60.

[0052] Next, examples of the form of the resin layer 40 will be given. In Forms 1 to 6, the resin layer 40 is configured to have a base portion 41, but it may also be configured without a base portion 41. Also, for the sake of explanation, the semiconductor device 1 shown in Figures 5A to 10B is simplified by schematically illustrating only the semiconductor chip 20, resin layer 40, and connection terminal portion 60. Note that the resin layer 40 is not limited to the shapes of Forms 1 to 6 shown below.

[0053] (Form 1) Figure 5A is a plan view of a semiconductor device 1 having a resin layer 40 of form 1. Figure 5B is a schematic cross-sectional view taken along line AA of Figure 5A. Form 1 is a configuration in which multiple base portions 42 are formed corresponding to all connection terminal portions 60 arranged on the resin layer 40, as shown in Figures 5A and 5B. In form 1, since a base portion 42 is formed one-to-one for each connection terminal portion 60, it can be flexibly deformed according to the stress applied to each connection terminal portion 60.

[0054] (Form 2) Figure 6A is a plan view of a semiconductor device 1 having a resin layer 40 of form 2. Figure 6B is a schematic cross-sectional view taken along line BB of Figure 6A. Form 2 is a form in which a base portion 42 is formed corresponding to a connection terminal portion 60 located at the position furthest from the center of the semiconductor chip 20 in a plan view. As shown in Figure 6A, the base portion 42 is formed corresponding to the connection terminal portions 60 located at the four corners of the resin layer 40, which are the positions furthest from the center of the semiconductor chip 20 in a plan view, among the connection terminal portions 60 arranged on the resin layer 40. Since Form 2 forms the base portion 42 corresponding to the connection terminal portions 60 at the four corners, which are the most stressed parts of the semiconductor device 1, stress due to distortion caused by thermal shrinkage and the like can be effectively reduced.

[0055] (Form 3) Figure 7A is a plan view of a semiconductor device 1 having a resin layer 40 of form 3. Figure 7B is a schematic cross-sectional view taken along the CC line of Figure 7A. Form 3 is a form in which a base portion 42 is formed corresponding to a connection terminal portion 60 located at the position furthest from the center of the semiconductor chip 20 in a plan view, and to connection terminal portions 60 adjacent to these connection terminal portions 60. As shown in Figure 7A, the base portion 42 is formed corresponding to the connection terminal portions 60 located at the four corners of the resin layer 40, among the connection terminal portions 60 located on the resin layer 40. Furthermore, as shown in Figure 7A, the base portion 42 is formed corresponding to the connection terminal portions 60 adjacent to the connection terminal portions 60 located at the four corners of the resin layer 40. In other words, in form 3, the base portion 42 is formed corresponding to three connection terminal portions 60 located near the four corners of the resin layer 40. In the third configuration, the base portion 42 is formed in accordance with the connection terminal portions 60 at the four corners and the surrounding connection terminal portions 60, which are the areas where the semiconductor device 1 is most susceptible to stress. This effectively reduces stress caused by distortion due to thermal contraction and other factors.

[0056] (Form 4) Figure 8A is a plan view of a semiconductor device 1 having a resin layer 40 of form 4. Figure 8B is a schematic cross-sectional view taken along the DD line of Figure 8A. As shown in Figures 8A and 8B, form 4 has a connection terminal portion 60 located at the position furthest from the center of the semiconductor chip 20 in a plan view, and a base portion 42 corresponding to the connection terminal portions 60 adjacent to these connection terminal portions 60. As shown in Figure 8A, the base portion 42 is formed to correspond to the connection terminal portions 60 located at the four corners of the resin layer 40, among the connection terminal portions 60 located on the resin layer 40. Furthermore, as shown in Figure 8A, the base portion 42 is formed to correspond to the connection terminal portions 60 adjacent to the connection terminal portions 60 located at the four corners of the resin layer 40. In other words, in form 4, base portions 42 are formed corresponding to the four connection terminal portions 60 located near the four corners of the resin layer 40. Since form 4 forms the base portions 42 corresponding to the connection terminal portions 60 at the four corners and the surrounding connection terminal portions 60, which are the areas in the semiconductor device 1 that are most susceptible to stress, stress due to distortion caused by thermal shrinkage and the like can be effectively reduced.

[0057] (Form 5) Figure 9A is a plan view of a semiconductor device 1 having a resin layer 40 of form 5. Figure 9B is a schematic cross-sectional view taken along the line E1-E1 in Figure 9A. Figure 9C is a schematic cross-sectional view taken along the line E2-E2 in Figure 9A. Form 5 is a form in which a base portion 42 is formed corresponding to a connection terminal portion 60 located at the position furthest from the center of the semiconductor chip 20 in a plan view, and a connection terminal portion 60 located on the outer periphery 44 of the resin layer 40 that is aligned in a straight line with these connection terminal portions 60. As shown in Figures 9A and 9B, the base portion 42 is formed corresponding to the connection terminal portions 60 located at the four corners of the resin layer 40. Furthermore, as shown in Figures 9A and 9B, the base portion 42 is formed corresponding to the connection terminal portions 60 located on the outer periphery 44 of the resin layer 40 that are aligned with the connection terminal portions 60 located at the four corners of the resin layer 40. In other words, in the configuration shown in Figure 9A, a base portion 42 is formed for each of the connection terminal portions 60 that are arranged in a row at the top and bottom of the outer peripheral portion 44. As shown in Figures 9A and 9C, the hill portion 43 forms connection terminal portions 60 other than those located on the base portion 42. In configuration 5, since the base portion 42 is formed in accordance with the connection terminal portions 60 located on the outer peripheral portion 44 of the resin layer 40, which includes the connection terminal portions 60 at the four corners where the semiconductor device 1 is most susceptible to stress, stress due to distortion caused by thermal shrinkage and the like can be effectively reduced.

[0058] Figure 10A is a plan view of a semiconductor device 1 having a resin layer 40 of form 6. Figure 10B is a schematic cross-sectional view taken along the line F1-F1 in Figure 10A. Figure 10C is a schematic cross-sectional view taken along the line F2-F2 in Figure 10A. Form 6 is a form in which a base portion 42 is formed corresponding to the connection terminal portion 60 located at the position furthest from the center of the semiconductor chip 20 in a plan view, and the connection terminal portions 60 arranged along the outer periphery 44 of the resin layer 40 including these connection terminal portions 60. As shown in Figures 10A and 10B, the base portion 42 is formed corresponding to the connection terminal portions 60 located at the four corners of the resin layer 40, among the connection terminal portions 60 arranged on the resin layer 40. Furthermore, as shown in Figure 10A, the base portion 42 is also individually formed for the connection terminal portions 60 located on the outer periphery 44 of the resin layer 40, other than the four corners. As shown in Figures 10A and 10C, the hill portion 43 has connection terminal portions 60 other than the connection terminal portion 60 located on the base portion 42.

[0059] In Embodiments 5 and 6, the "outer periphery 44" refers to a frame-shaped region whose outline is represented by a dashed line as shown in Figures 9A and 10A, and means the outer peripheral portion of the resin layer 40 in the formation region of the connection terminal portion 60 of the resin layer 40. The outer periphery 44 can be configured to include at least the formation region of the connection terminal portion 60 located on the outermost periphery in the formation region of the connection terminal portion 60 of the resin layer 40. In this embodiment, the outer periphery 44 is the region enclosed by the dashed line in Figure 9A, etc.

[0060] In semiconductor device 1, the connection terminal portion 60, which is furthest from the center of the semiconductor chip 20 in a plan view, is most susceptible to stress. Therefore, it is preferable that the base portion 42 be formed to correspond to the connection terminal portion 60, which is furthest from the center of the semiconductor chip 20 in a plan view, as shown in embodiments 1 to 6 described above.

[0061] Furthermore, the thickness of the base portion 42 relative to the thickness of the resin layer 40 may be approximately uniform for all base portions 42, or it may differ for each base portion 42. The thickness of the base portion 42 varies depending on the specifications of the package structure of the semiconductor device 1, and can be set appropriately according to the stress applied to the connection terminal portion 60. In addition, from the viewpoint of improving solder connection reliability, it is preferable to make the thickness of the base portion 42 located on the outer periphery of the semiconductor chip 20 thicker than the thickness of the base portion 42 located on the center side of the semiconductor chip 20 in a plan view.

[0062] Furthermore, the semiconductor device 1 can also have a connection terminal portion 60, which is located at the position furthest from the center of the semiconductor chip 20 where stress is most likely to occur, formed as a dummy terminal portion without electrical connection. When a dummy terminal portion is formed in the semiconductor device 1, it is effective to form a base portion 42 corresponding to the connection terminal portion 60 furthest from the center of the semiconductor chip 20, excluding the dummy terminal portion.

[0063] Returning to Figures 1 and 2, the connection terminals 60 located in the resin layer 40 are each connected to the electrodes 22 of the semiconductor chip 20 via the wiring 50.

[0064] The wiring 50 can be formed by laminating a single or multiple layers of metal materials such as copper (Cu), aluminum (Al), or gold (Au). The wiring 50 can be formed by known wiring formation methods such as photolithography. The wiring 50 can be formed on the terminal formation surface 42a or terminal formation surface 43a between the connection terminal portion 60 and the resin layer 40.

[0065] Next, examples of wiring configurations 50 will be given. Wiring 50 can be laid as shown in the following configurations 1 to 3. Note that wiring 50 is not limited to the configurations shown in configurations 1 to 3, and can also be laid in other ways.

[0066] (Laying type 1) Figure 11A is a schematic plan view showing wiring configuration 1 of the semiconductor device 1. Figure 11B is a schematic cross-sectional view obtained by cutting along the cutting line passing through A1-B1-D1-E3 in Figure 11A. Figure 11C is a schematic combined cross-sectional view obtained by cutting along the cutting line passing through A1-B1-C1 in Figure 11A. The wiring 50 can be laid in the wiring configuration 1 shown in Figures 11A, 11B, and 11C. In wiring configuration 1, as shown in Figure 11A, a bridge portion 80 is formed in a groove-shaped gap portion 45 formed between the base portion 42 and the hill portion 43. The connection terminal portion 60 is arranged on the base portion 42 and the hill portion 43, respectively, as shown in Figures 11A and 11B.

[0067] As shown in Figures 11A and 11C, the bridge portion 80 has a wiring-forming surface 81 that connects the terminal-forming surface 42a of the base portion 42 and the terminal-forming surface 43a of the hill portion 43. As shown in Figure 11C, the height position of the wiring-forming surface 81 is approximately the same as the height of the terminal-forming surfaces 42a and 43a in the thickness direction (Z-axis direction) of the resin layer 40. Therefore, the wiring-forming surface 81 of the bridge portion 80 is approximately flush with the terminal-forming surfaces 42a and 43a.

[0068] The bridge section 80 is formed to extend in a direction that intersects, preferably perpendicular to, the direction of the principal stress V (the direction of the thick arrow in Figure 11A) applied to the base section 42 on which the wiring 50 is laid. As a result, the bridge section 80 does not hinder the deformation of the base section 42 when stress is applied to the base section 42. Therefore, the base section 42 can deform in accordance with the stress. Note that the entire bridge section 80 does not need to extend in a direction that intersects the direction of the principal stress V applied to the base section 42. For example, the above effect can be achieved if a portion of the bridge section 80 relatively close to the base section 42 (specifically, a certain region including the connection portion with the base section 42 and its vicinity) extends in a direction that intersects the direction of the principal stress V.

[0069] In installation configuration 1, the wiring 50 is laid so as to connect to the connection terminal portion 60 located on the base portion 42, passing through the terminal forming surface 43a of the hill portion 43 and the wiring forming surface 81 of the bridge portion 80. The wiring 50 is laid along the extending direction of the bridge portion 80. In installation configuration 1, the wiring 50 laid is less likely to break because the bridge portion 80 can deform in accordance with the stress deformation of the base portion 42.

[0070] (Laying type 2) Figure 12A is a schematic plan view showing wiring configuration 2 of the semiconductor device 1. Figure 12B is a schematic cross-sectional view obtained by cutting along the cutting line passing through A2-B2-C2 in Figure 12A. The wiring 50 can be laid in the wiring configuration 2 shown in Figures 12A and 12B. In wiring configuration 2, the wiring 50 is laid to connect to the connection terminal portion 60 along the uneven shape of the outer surface of the base portion 42, and is an example in which the bridge portion 80 of wiring configuration 1 is not used. In addition to the outer surface of the base portion 42, the wiring 50 can also be laid through the outer surfaces of other components of the resin layer 40, such as the base portion 41 and the hill portion 43.

[0071] (Laying type 3) Figure 13A is a schematic plan view showing wiring configuration 3 of the semiconductor device 1. Figure 13B is a schematic cross-sectional view obtained by cutting along the cutting line passing through A3-B3-C3 in Figure 13A. The wiring 50 can be laid in the wiring configuration 3 shown in Figures 13A and 13B. In wiring configuration 3, the wiring 50 is laid so as to penetrate the inside of the base portion 42 and connect to the connection terminal portion 60. In wiring configuration 3, the wiring 50 and the connection terminal portion 60 are electrically connected through a through hole 42b formed in the base portion 42. The through hole 42b is formed after the base portion 42 is formed, from the terminal formation surface 42a side toward the patterned wiring 50, after the wiring 50 is patterned in the insulating layer 30 before the base portion 42 is formed. The wiring 50 is electrically connected to the connection terminal portion 60 through a through electrode formed in the through hole 42b by plating or other means, or a columnar electrode such as a copper pin inserted into the through hole 42b.

[0072] Returning to Figures 1 and 2, multiple connection terminals 60 are formed in the resin layer 40.

[0073] The connection terminal portion 60 is formed of a conductive material such as solder. The connection terminal portion 60 is positioned on the terminal forming surface 42a of the base portion 42 of the resin layer 40, or on the terminal forming surface 43a of the raised portion 43, and is electrically connected to the wiring 50. The shape and size of the connection terminal portion 60 can be appropriately determined according to the specifications of the semiconductor device 1. In its basic configuration, the connection terminal portion 60 is a terminal that electrically connects the semiconductor device 1 and the mounting substrate 200, but it may also include a portion of dummy terminals that function as structural connecting members but do not have an electrical connection.

[0074] The protective layer 70 is formed to cover the exposed portions of the insulating layer 30 and the wiring 50. The protective layer 70 can be formed using the same material as the resin layer 40 by a known forming method. The protective layer 70 can be formed in advance so as not to cover the contact portion between the wiring 50 and the connection terminal portion 60. Alternatively, the protective layer 70 may be formed to cover the insulating layer 30 and the wiring entirely, and then the contact portion between the wiring 50 and the connection terminal portion 60 may be removed.

[0075] As described above, the semiconductor device 1 according to the present invention has a package structure that can be mounted on a mounting substrate 200 and includes a semiconductor chip 20 having a first surface 20a and a second surface 20b opposite to the first surface 20a, and a plurality of connection terminal portions 60 for making an electrical connection between the semiconductor chip 20 and the mounting substrate 200. Between the second surface 20b of the semiconductor chip 20 and the connection terminal portions 60, a resin layer 40 with a thickness of 100 μm or more is formed. The resin layer 40 is configured to include one or more base portions 42 on which the connection terminal portions 60 are individually arranged and which protrude in the thickness direction of the resin layer 40, and the base portions 42 have a thickness of 33% or more of the thickness of the resin layer 40.

[0076] With this configuration, the semiconductor device 1 has a base portion 42 formed in the resin layer 40, on which the connection terminal portions 60 are individually arranged. Therefore, when thermal contraction occurs due to temperature changes during a temperature cycle, the base portion 42 deforms individually according to the applied stress. As a result, the semiconductor device 1 effectively reduces distortion due to temperature changes, and the reliability of solder connections when mounted on the mounting substrate 200 can be improved. [Examples]

[0077] Next, embodiments of the present invention will be described, but the present invention is not limited to the following embodiments.

[0078] The following simulations were conducted to verify the solder connection reliability in the semiconductor device of the present invention. The simulations were performed as follows.

[0079] (Specifications, software, and analysis methods) The analysis was performed using Marc®, a nonlinear finite element method analysis software manufactured by MSC Software Corporation, employing the finite element method (FEM).

[0080] (Simulation conditions) The simulation conditions, namely "model conditions" and "material properties," were as shown in Table 1 of Figure 14 and Table 2 of Figure 15. The shape and configuration of each part of the simulation model are as shown in Figure 16. The simulation model for each sample was a 1 / 8 scale cut of a package mounted on a circuit board, as shown in subdivisions (a) and (b) of Figure 16, in a plan view. The number of samples simulated was 30.

[0081] Figures 17A to 17D show the simulation results for this embodiment. For samples 9 to 30, the lifetime improvement rate was calculated when a sample with the same resin layer thickness was used as a reference from samples 1 to 8 shown in Table A of Figure 17A. In the characterization of samples 9 to 30 shown in Tables B to D of Figures 17B to 17D, samples with a solder lifetime of 1.0455 times or more than the reference were marked with "○", and samples with a lifetime of less than 1.0455 times were marked with "×". This evaluation criterion is because if the lifetime cycle count of a sample is less than 1.0455 times the lifetime cycle count of the reference, it falls within the 2σ interval of the standard deviation of the reference's cycle count, and therefore may be judged as being within the range of variation in the reference's cycle count.

[0082] The structure of each sample was as follows. Figures 18A, 19A, 20A, 21A, 22A, and 23A show a plan view of the entire package structure before the sample was cut to 1 / 8 size. Figures 18B, 19B, 20B, 21B, 22B, and 23B show schematic cross-sectional views of the corresponding package structure.

[0083] As shown in Figures 18A and 18B, Samples 1 to 8 have a raised section 43 in the resin layer 40 where the connection terminals 60 are located. In other words, in Samples 1 to 8, all connection terminals 60 are arranged on a single raised section 43. Furthermore, Samples 1 to 8 were used as references for Samples 9 to 30, which have the same thickness of resin layer 40.

[0084] The resin layers of samples 9 to 20 had a structure corresponding to the aforementioned form 1 (see Figures 4A and 4B), as shown in Figures 19A and 19B. That is, in samples 9 to 20, all connection terminals 60 were placed on the base portion 42.

[0085] The resin layers of samples 21 to 26 had a structure corresponding to the aforementioned form 2 (see Figures 5A and 5B), as shown in Figures 20A and 20B. That is, in samples 21 to 26, the connection terminals 60 located at the four corners of the resin layer 40 furthest from the center of the semiconductor chip 20 in a plan view were placed on the base portion 42.

[0086] Samples 27 and 28 have a structure corresponding to the aforementioned form 4 (see Figures 8A and 8B), as shown in Figures 21A and 21B. That is, in Samples 27 and 28, the four corner connection terminals 60 located at the positions furthest from the center of the semiconductor chip 20 in a plan view, and the three connection terminals 60 adjacent to each of the four corner connection terminals 60, are individually placed on the base portion 42.

[0087] As shown in Figures 22A and 22B, the resin layer of sample 29 has a structure in which the connection terminals 60, which are arranged around the entire circumference of the outer periphery 44 of the resin layer 40, are each placed on a base portion 42.

[0088] As shown in Figures 23A and 23B, sample 30 has a structure in which a connection terminal portion 60 is located at the position furthest from the center of the semiconductor chip 20 in a plan view, and three adjacent connection terminal portions 60 are formed to form a raised portion 43. In other words, the resin layer 40 of sample 30 is divided into corners near the four corners and the rest of the layer, but the entire layer is formed of raised portions 43.

[0089] The evaluation results for each sample are shown in Tables A to D in Figures 17A to 17D.

[0090] As shown in Figure 17B, for samples 9 to 12 of samples 9 to 20, the base thickness was less than 100 μm, resulting in a life cycle below the evaluation criteria and unsatisfactory results. In contrast, for samples 13 to 20, the base thickness was 100 μm or more, and the base thickness was 33% or more of the resin layer thickness, so it was confirmed that the life cycle exceeded the evaluation criteria and good results were obtained.

[0091] Of the samples 21 to 26 shown in Figure 17C, samples 21 and 22 did not yield satisfactory results because the thickness of the base portion was less than 33% of the thickness of the resin layer, resulting in a life cycle that fell below the evaluation criteria. In contrast, samples 23 to 26 had a base portion thickness of 100 μm or more, and the thickness of the base portion was 33% or more of the thickness of the resin layer, so it was confirmed that they yielded satisfactory results because their life cycle exceeded the evaluation criteria.

[0092] Of the samples 27 to 30 shown in Figure 17D, sample 30 had a connection terminal located furthest from the center of the semiconductor chip in a plan view, and three adjacent connection terminals were grouped together on a raised section. As a result, its life cycle fell below the evaluation criteria, and a good result was not obtained. In contrast, samples 27 to 29 had connection terminals located furthest from the center of the semiconductor chip in a plan view, and base sections were formed corresponding to each of these connection terminals. Furthermore, the thickness of the base sections was 100 μm or more, and the thickness of the base sections was 33% or more of the thickness of the resin layer. As a result, it was confirmed that the life cycle exceeded the evaluation criteria, and a good result was obtained.

[0093] As described above, the semiconductor device of this embodiment is effective in extending the solder life cycle when mounted on a mounting board and improving the reliability of solder connections by having a base portion thickness of 100 μm or more, and a base portion thickness of 33% or more of the resin layer thickness, and by forming a base portion corresponding to each individual connection terminal. [Explanation of Symbols]

[0094] 1 Semiconductor device, 2 joints, 10 transparent substrates, 10a First surface of the transparent substrate, 10b Second surface of the transparent substrate, 20 semiconductor chips, 20a The first surface of a semiconductor chip, 20b Second surface of the semiconductor chip, 21 on-chip lenses, 22 electrodes, 23 through holes, 30 insulating layer, 40 resin layers, 41 base, 42 Base section, 42a Terminal forming surface of the base portion, 43 Hill, 43a Terminal forming surface of the hill portion, 44 Outer periphery, 45 Gap, 50 wiring, 60 Connection terminal section, 70 protective layer, 80 Bridge section, 81 Wiring formation surface, 200 mounted circuit boards, T Resin layer thickness, Thickness of the T1 base, Thickness of the T2 base, T3 thickness of the hill section, V: Direction of principal stress.

Claims

1. A semiconductor device having a package structure that can be mounted on a mounting substrate, A semiconductor chip having a first surface and a second surface opposite to the first surface, It includes a plurality of connection terminals for making an electrical connection between the semiconductor chip and the mounting substrate, A resin layer with a thickness of 100 μm or more is formed between the second surface of the semiconductor chip and the connection terminal portion. The resin layer is configured to include one or more base portions that are provided projecting in the thickness direction of the resin layer, with the connection terminal portions being individually arranged therein. The base portion has a thickness of 33% or more of the thickness of the resin layer, wherein the semiconductor device is provided.

2. The resin layer further has a base portion that is disposed on the semiconductor chip side, The semiconductor device according to claim 1, wherein the base is disposed between the pedestal and the semiconductor chip, or is disposed adjacent to it in a planar direction perpendicular to the thickness direction.

3. The semiconductor device according to claim 1, wherein the base portion is formed to correspond to at least one of the connection terminal portions arranged on the outer peripheral side of the resin layer in a plan view.

4. The semiconductor device according to claim 3, wherein the base portion is formed in correspondence with the connection terminal portion which is located at the position furthest from the center of the semiconductor chip in a plan view.

5. The semiconductor device according to claim 3, wherein the base portion is formed in correspondence with the connection terminal portion located at the position furthest from the center of the semiconductor chip in a plan view, and at least one of the connection terminal portions adjacent to the connection terminal portion located at the position furthest from the center of the semiconductor chip.

6. The resin layer further has a mound portion on which a plurality of connection terminal portions are arranged, A bridge section is formed between the base section and the hill section adjacent to the base section. The bridge portion has a wiring forming surface that is continuous with the terminal forming surface of the hill portion and the terminal forming surface of the base portion. The semiconductor device according to claim 1, wherein the wiring connected to the connection terminal portion arranged on the base portion is laid so as to pass through the terminal forming surface of the hill portion and the wiring forming surface of the bridge portion and connect to the connection terminal portion arranged on the base portion.

7. The bridge portion is formed to extend in a direction intersecting the direction of the principal stress applied to the base portion. The semiconductor device according to claim 6, wherein the wiring connected to the connection terminal portion arranged on the base portion is laid along the extending direction of the bridge portion.

8. The semiconductor device according to claim 1, wherein the wiring connected to the connection terminal portion arranged on the base portion is laid through the inside of the base portion and connected to the connection terminal portion to be connected.

9. The semiconductor device according to claim 1, wherein the wiring connected to the connection terminal portion located on the base portion is laid along the outer surface of the base portion.

10. The semiconductor device according to claim 1, wherein the thickness of the base portion is greater when the base portion is located on the outer periphery side of the semiconductor chip than when the base portion is located on the central side of the semiconductor chip in a plan view.

11. The semiconductor device according to claim 1, wherein the resin layer is formed of a photosensitive material.

12. The semiconductor device according to claim 1, wherein the connection terminal portion is formed of solder.

13. The semiconductor device according to claim 1, wherein the resin layer has an elastic modulus of 10 GPa or more and 20 GPa.

14. The semiconductor device according to claim 1, wherein the package structure is a chip-size package or a fan-out package.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor chip is an image sensor.

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