Electro-optical devices and electronic equipment

Abstract

To provide an electro-optical device and electronic equipment that can improve the light-shielding properties against light incident on a semiconductor layer. [Solution] The electro-optic apparatus comprises a substrate, a transistor including a gate electrode and a semiconductor layer disposed between the substrate and the gate electrode and extending in a first direction, and a first light-shielding portion that blocks the incidence of light onto the semiconductor layer, wherein the semiconductor layer has a drain region, a channel region and a source region aligned along the first direction, and the first light-shielding portion has two first parts spaced apart at the boundary between the drain region and the channel region, extending in the first direction in a plan view in the thickness direction of the substrate and sandwiching the boundary, and a second part located between the two first parts in a plan view and connecting the two first parts, wherein the second part, the drain region, the boundary, and the channel region are aligned in the first direction in a plan view.

Description

Technical Field

[0006] ,

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In an electronic device such as a projector, an electro-optical device such as a liquid crystal display device capable of changing optical characteristics for each pixel is used.

[0003] The liquid crystal display device described in Patent Document 1 includes a pixel electrode, a transistor, and a scanning line. The scanning line is connected to the gate electrode of the transistor via a contact. Further, the scanning line is provided so as to shield the periphery of the channel region of the transistor. Specifically, the scanning line is provided above the transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Since the scanning line having light shielding properties in Patent Document 1 is provided above the transistor, it has been difficult for only the scanning line to sufficiently suppress the incidence of light from the side of the periphery of the channel region.

Means for Solving the Problems

[0006] <00One embodiment of the electro-optical apparatus of the present invention comprises a substrate, a transistor including a gate electrode and a semiconductor layer disposed between the substrate and the gate electrode and extending in a first direction, and a first light-shielding portion that blocks the incidence of light onto the semiconductor layer, wherein the semiconductor layer has a drain region, a channel region and a source region aligned along the first direction, and the first light-shielding portion has two first parts spaced apart at the boundary between the drain region and the channel region, extending in the first direction in a plan view in the thickness direction of the substrate and sandwiching the boundary, and a second part located between the two first parts in a plan view and connecting the two first parts, wherein the second part, the drain region, the boundary, and the channel region are aligned in the first direction in a plan view.

[0007] One embodiment of the electronic device of the present invention comprises an electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of an electro-optical apparatus according to an embodiment. [Figure 2] This is a cross-sectional view of the AA line of the electro-optical apparatus shown in 1. [Figure 3] Figure 1 is an equivalent circuit diagram showing the electrical configuration of the element substrate. [Figure 4] Figure 2 is a plan view showing a portion of the element substrate in the display area. [Figure 5] This is a cross-sectional view along the line A1-A1 in Figure 4. [Figure 6] This is a cross-sectional view along the line A2-A2 in Figure 4. [Figure 7] This is a plan view showing the semiconductor layers of the transistor in Figure 5. [Figure 8] Figure 5 is an enlarged view of the first light-shielding section. [Figure 9] This is a plan view corresponding to the line B1-B1 in Figure 5. [Figure 10] This is a plan view corresponding to the line B2-B2 in Figure 5. [Figure 11]It is a view of the first light-shielding portion in the Y1 direction. [Figure 12] It is a view corresponding to the B3-B3 line in FIG. 9. [Figure 13] It is a plan view showing the gate electrode shown in FIG. 5. [Figure 14] It is a cross-sectional view showing the first light-shielding portion of the first modification. [Figure 15] It is a plan view of the first light-shielding portion shown in FIG. 14. [Figure 16] It is a perspective view showing a personal computer which is an example of an electronic device. [Figure 17] It is a plan view showing a smartphone which is an example of an electronic device. [Figure 18] It is a schematic view showing a projector which is an example of an electronic device.

Embodiments for Carrying Out the Invention

[0012] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device of an active matrix driving method. The electro-optical device 100 includes a device substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. As shown in FIG. 2, the device substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in the Z1 direction in this order. Note that viewing from the Z1 direction or the Z2 direction, which is the direction in which these are overlapped, is referred to as "plan view". Also, although the shape of the electro-optical device 100 in plan view shown in FIG. 1 is a rectangle, it may be a polygon other than a rectangle or a circle.

[0013] The device substrate 2 shown in FIG. 2 includes a first substrate 21 having translucency, a laminate 22 having translucency, a plurality of pixel electrodes 25 having translucency, and a first alignment film 29 having translucency. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in the Z1 direction in this order. Note that "translucency" means transmittance with respect to visible light, and preferably means that the transmittance of visible light is 50% or more. Also, as will be described in detail later, the device substrate 2 includes a light-shielding first light-shielding portion 6, a light-shielding second light-shielding portion 7, and a light-shielding third light-shielding portion 8 shown in FIGS. 5 and 6. Note that "light-shielding property" means light-shielding property with respect to visible light, and preferably means that the transmittance of visible light is less than 50%, and more preferably 10% or less.

[0014] The first substrate 21 shown in Figure 2 corresponds to the "substrate". The first substrate 21 is a translucent and insulating flat plate, and is composed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of translucent insulating films. Various wirings and the like are also provided on the laminate 22. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, transparent conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown in the figure, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in a plan view. The first alignment film 29 is translucent and insulating. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. The first alignment film 29 is arranged to cover the plurality of pixel electrodes 25. The material of the first orientation film 29 is, for example, polyimide and silicon dioxide.

[0015] The opposing substrate 3 is positioned opposite the element substrate 2. The opposing substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second orientation film 34. Although not shown in the figures, the opposing substrate 3 also has a light-shielding border that surrounds a plurality of pixel electrodes 25 in a plan view.

[0016] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a translucent and insulating plate, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 is translucent and insulating and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode placed on a plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes, for example, transparent conductive materials such as ITO, IZO, and FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide.

[0017] The sealing member 4 is placed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins, such as epoxy resin. The sealing member 4 may also include a gap material made of an inorganic material such as glass.

[0018] The liquid crystal layer 5 is located within a region enclosed by the element substrate 2, the opposing substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optic layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0019] As shown in Figure 1, the element substrate 2 has multiple scan line drive circuits 11, signal line drive circuits 12, and multiple external terminals 13. Some of the multiple external terminals 13 are connected to wiring (not shown) that is routed from the scan line drive circuits 11 or signal line drive circuits 12. In addition, the multiple external terminals 13 include terminals to which a constant potential Vcom is applied. These terminals are electrically connected to a common electrode 33 of the opposing substrate 3 via wiring and conductive material (not shown). Thus, a constant potential Vcom is supplied to the common electrode 33.

[0020] The electro-optical device 100 has a display area A10 for displaying an image and a peripheral area A20 located outside the display area A10 in a plan view. The display area A10 is provided with a plurality of pixels P arranged in a matrix. A plurality of pixel electrodes 25 are arranged one-to-one for the plurality of pixels P. The aforementioned common electrode 33 is provided in common for the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a plan view. A scan line drive circuit 11 and a signal line drive circuit 12 are arranged in the peripheral area A20.

[0021] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Figure 2, an image is displayed by modulating the light LL between the time it is incident on the opposing substrate 3 and the time it is emitted from the element substrate 2. Alternatively, an image may be displayed by modulating the light incident on the element substrate 2 while it is emitted from the opposing substrate 3.

[0022] Furthermore, the electro-optical device 100 is applied to, for example, a color display device such as a personal computer and a smartphone, which will be described later. When applied to such a display device, a color filter is appropriately used for the electro-optical device 100. Also, the electro-optical device 100 is applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light bulb. In this case, a color filter is omitted for the electro-optical device 100.

[0023] 1B. Electrical configuration of the element substrate 2 Figure 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 in Figure 1. As shown in Figure 3, the element substrate 2 has a plurality of transistors 23, n scan lines 241, m signal lines 242, and n constant potential lines 243. n and m are integers greater than or equal to 2. Transistors 23 are arranged corresponding to each intersection of the n scan lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, source, and drain.

[0024] Each of the n scan lines 241 extends in the X1 direction, and the n scan lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scan lines 241 is electrically connected to the gate of a corresponding set of transistors 23. The n scan lines 241 are electrically connected to the scan line drive circuit 11 shown in Figure 1. Scan signals G1, G2, ..., and Gn are supplied to the 1 to n scan lines 241 sequentially from the scan line drive circuit 11.

[0025] Each of the m signal lines 242 shown in Figure 3 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the source of the corresponding set of transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in Figure 1. Image signals S1, S2, ..., and Sm are supplied in parallel from the signal line drive circuit 12 to the 1 to m signal lines 242.

[0026] The n scan lines 241 and m signal lines 242 shown in Figure 3 are electrically insulated from each other and arranged in a grid pattern in a plan view. The region enclosed by two adjacent scan lines 241 and two adjacent signal lines 242 corresponds to a pixel P. Each pixel P is provided with a transistor 23, a pixel electrode 25, and a capacitive element 24. The pixel electrode 25 is provided in a one-to-one relationship with the transistor 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0027] Each of the n constant potential lines 243 extends in the X1 direction, and the n constant potential lines 243 are arranged at equal intervals in the Y2 direction. Furthermore, the n constant potential lines 243 are electrically insulated from the n scan lines 241 and the m signal lines 242, and are spaced apart from them. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitive element 24. Each capacitive element 24 is a holding capacitor for maintaining the potential of the pixel electrode 25. The capacitive elements 24 are provided in a one-to-one ratio with respect to the transistor 23. The other of the two electrodes of each capacitive element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitive element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0028] As scanning signals G1, G2, ..., and Gn become sequentially active and n scanning lines 241 are selected sequentially, the transistor 23 connected to the selected scanning line 241 turns ON. Then, image signals S1, S2, ..., and Sm, whose magnitudes correspond to the grayscale to be displayed, are taken up via m signal lines 242 to the pixel P corresponding to the selected scanning line 241 and applied to the pixel electrode 25. As a result, a voltage corresponding to the grayscale to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in Figure 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. In addition, the applied voltage is maintained by the capacitive element 24. Light is modulated by this change in the orientation of the liquid crystal molecules, making grayscale display possible.

[0029] 1C. Structure of element substrate 2 Figure 4 shows a portion of the element substrate 2 in the display area A10 of Figure 2.

[0030] As shown in Figure 4, the display area A10 has multiple aperture areas A11 and a light-shielding area A12. The multiple aperture areas A11 are arranged in a matrix in a plan view. The shape of the light-shielding area A12 in a plan view is a frame shape located between the multiple aperture areas A11. Each aperture area A11 is the area where the pixel electrode 25 is placed and is a light-transmitting area. On the other hand, the transistor 23 is placed in the light-shielding area A12. Although not shown in Figure 4, the light-shielding area A12 also has multiple wirings such as the scan line 241, signal line 242, and constant potential line 243 shown in Figure 3, as well as a capacitive element 24.

[0031] Figure 5 is a cross-sectional view along the line A1-A1 in Figure 4. Figure 6 is a cross-sectional view along the line A2-A2 in Figure 4.

[0032] As shown in Figures 5 and 6, the element substrate 2 has a first substrate 21, which is a "substrate," and a laminate 22. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. The insulating layers 221 to 229 are translucent and insulating. The materials of each insulating layer 221 to 229 are, for example, inorganic materials containing silicon, such as silicon oxide and silicon oxynitride.

[0033] The laminate 22 contains a transistor 23, a scan line 241, a signal line 242, a first light-shielding section 6, a second light-shielding section 7, and a third light-shielding section 8. Furthermore, the laminate 22 contains relay electrodes 244, 245, 246, 247, 248, and 249.

[0034] As described above, the first substrate 21 is composed of, for example, a glass substrate or a quartz substrate. A third light-shielding portion 8 is placed on the first substrate 21. The third light-shielding portion 8 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. The third light-shielding portion 8 has a longitudinal shape along the Y1 direction, which is the extending direction of the semiconductor layer 231 of the transistor 23. The first substrate 21 may have a recess that opens in the Z1 direction. In this case, the third light-shielding portion 8 may be placed in the recess.

[0035] A transistor 23 is placed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is placed on the insulating layer 221. The semiconductor layer 231 is placed between the first substrate 21 and the gate electrode 232 and extends in the Y1 direction, which is the "first direction". The gate electrode 232 is placed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. The region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0036] Figure 7 is a plan view of the semiconductor layer 231 of transistor 23 in Figure 5. Transistor 23 has an LDD (Lightly Doped Drain) structure. As shown in Figures 5 and 7, the semiconductor layer 231 extends in the Y1 direction in a plan view of the first substrate 21 in the thickness direction. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The low-concentration drain region 231d is the region between the drain region 231a and the channel region 231c, and corresponds to the "boundary." The channel region 231c is located between the drain region 231a and the source region 231b. Therefore, the drain region 231a, the channel region 231c, and the source region 231b are arranged in this order along the Y1 direction. Also, the low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The regions excluding the channel region 231c are doped with impurities to enhance conductivity. The impurity concentration in the low-concentration drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the low-concentration source region 231e is lower than the impurity concentration in the source region 231b.

[0037] Having such an LDD structure makes it possible to mitigate the electric field between the source region 231b and the drain region 231a. Specifically, by providing a low-concentration drain region 231d, which is a region with a low impurity concentration, at the edge of the drain region 231a, the generation of hot carriers can be suppressed, and thus the reliability of the transistor 23 can be improved. This is particularly effective in miniaturizing the transistor 23. Note that, for example, the transistor 23 does not necessarily have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. In this case, the "boundary" is the boundary between the drain region 231a and the channel region 231c. Also, as shown in Figure 7, the semiconductor layer 231 overlaps the third light-shielding portion 8 in a plan view.

[0038] The gate electrode 232 shown in Figure 5 is formed, for example, by doping polysilicon with impurities that enhance conductivity. The gate electrode 232 may also be formed using conductive materials such as metals, metal oxides, and metal compounds. In a plan view, the gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231. Furthermore, the gate electrode 232 has portions that overlap and portions that do not overlap with the semiconductor layer 231 in a plan view. Therefore, in the example shown in Figure 6, the upper surface of the gate electrode 232 has a stepped surface. The gate insulating film 233 is composed of a silicon oxide film formed, for example, by thermal oxidation or CVD (chemical vapor deposition).

[0039] As shown in Figures 5 and 6, a first light-shielding section 6 and a second light-shielding section 7 are positioned on the top and sides of the transistor 23. Each of the first light-shielding section 6 and the second light-shielding section 7 is composed of, for example, a multi-layer laminate. Each of the first light-shielding section 6 and the second light-shielding section 7 is formed, for example, using the damascene method. The first light-shielding section 6 and the second light-shielding section 7 are provided to suppress the incidence of light onto the semiconductor layer 231. The first light-shielding section 6 is electrically connected to the drain region 231a of the semiconductor layer 231. The second light-shielding section 7 is electrically connected to the gate electrode 232. As shown in Figure 6, the second light-shielding section 7 is directly connected to the third light-shielding section 8, and the second light-shielding section 7 is electrically connected to the third light-shielding section 8. The third light-shielding section 8 functions as a back gate. By providing the first light-shielding section 6, the second light-shielding section 7, and the third light-shielding section 8, the incidence of light into the low-concentration drain region 231d, which is the "boundary," can be suppressed. If the low-concentration drain region 231d is not provided, the first light-shielding section 6, the second light-shielding section 7, and the third light-shielding section 8 suppress the incidence of light into the boundary portion between the drain region 231a and the channel region 231c, which is the "boundary."

[0040] As shown in Figure 5, a relay electrode 244 is placed in the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole that penetrates the insulating layers 222 and 223. The relay electrode 244 and the contact 271 are integrally formed from the same material, but they may be formed from different materials.

[0041] As shown in Figure 5, a scan line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scan line 241 is electrically connected to the gate electrode 232 via the second light-shielding portion 7. The relay electrode 245 is electrically connected to the first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224. Note that contacts 272 and 273 are, for example, contact plugs that fill holes penetrating the insulating layer 224.

[0042] Intermediate electrodes 247 and 248 are arranged on the insulating layer 225. Intermediate electrode 247 is electrically connected to intermediate electrode 246 via a contact 275 that penetrates the insulating layer 225. The contact 275 is, for example, integrally formed with intermediate electrode 246 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225. Intermediate electrode 248 is electrically connected to intermediate electrode 245 via a contact 274 that penetrates the insulating layer 225. The contact 274 is integrally formed with intermediate electrode 248 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225.

[0043] A signal line 242 is placed on the insulating layer 226. The signal line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the signal line 242 is electrically connected to the source region 231b via contact 276, relay electrode 247, contact 275, relay electrode 246, contact 273, relay electrode 244, and contact 271. The contact 276 is integrally formed with the signal line 242 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0044] As shown in Figure 6, a relay electrode 249 is placed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer. The contact 277 is integrally formed with the relay electrode 249 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0045] A capacitive element 24 is placed on the insulating layer 227. The capacitive element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. Electrode 2401 is placed on the insulating layer 227. Electrode 2402 is placed on the insulating layer 228. The dielectric layer 2403 is placed between electrodes 2401 and 2402. Electrode 2401 also serves as the constant potential line 243 in Figure 2. Electrode 2402 is also electrically connected to the intermediate electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. Therefore, as shown in Figure 5 or Figure 6, electrode 2402 is electrically connected to the drain region 231a via contact 278, intermediate electrode 249, contact 277, intermediate electrode 248, contact 274, intermediate electrode 245, contact 272 and the first light-shielding portion 6. The contact 278 is integrally formed with the electrode 2402 and has a trench structure provided along the inner wall surface of the holes formed in the insulating layers 227 and 228.

[0046] As shown in Figure 6, the pixel electrode 25 is placed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229. The contact 279 is integrally formed with the pixel electrode 25 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 229.

[0047] Each of the aforementioned scanning line 241, signal line 242, electrode 2401, electrode 2402, and relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single layers or laminates. For example, they are composed of a laminate of an aluminum film and a titanium nitride film.

[0048] Furthermore, each of the aforementioned contacts 271 to 279 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), as well as metal nitrides and metal silicides. Each of the contacts 271 to 279 may be single-layer or multi-layer. Also, each of the contacts 271 to 279 may be integrally formed with the electrode or wiring to be connected, or may be formed separately. Each of the contacts 271 to 279 may be a trench structure or a contact plug.

[0049] Note that the configuration of the element substrate 2 shown in Figures 5 and 6 is just one example. For example, it may include other capacitive elements besides the capacitive element 24. Also, although the scan line 241, signal line 242, and capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.

[0050] 1D. First light-shielding section 6 and second light-shielding section 7 Figure 8 is an enlarged view of the first light-shielding section 6 shown in Figure 5. Figure 9 is a plan view corresponding to the line B1-B1 in Figure 5. Figure 10 is a plan view corresponding to the line B2-B2 in Figure 5. Figure 11 is a view of the first light-shielding section 6 in the Y1 direction.

[0051] As shown in Figures 9 and 10, the first light-shielding portion 6 three-dimensionally covers the transistor 23. The first light-shielding portion 6 has two first parts 61, a second part 62, a third part 63, and a fourth part 64. In Figures 9 and 10, hatching is applied to the first light-shielding portion 6 for ease of understanding. In Figure 9, different types of hatching are applied to the first part 61, the second part 62, and the fourth part 64. In Figure 10, different types of hatching are applied to the first part 61, the second part 62, and the third part 63.

[0052] As shown in Figure 9, the two first portions 61 are spaced apart from each other and are provided so as to sandwich the low-concentration drain region 231d, which corresponds to the "boundary." Specifically, the two first portions 61 are provided on both sides of the low-concentration drain region 231d in the width direction. Also, each of the two first portions 61 is spaced apart from the low-concentration drain region 231d. Furthermore, the two first portions 61 extend along the Y1 direction, which is the "first direction" in which the semiconductor layer 231 extends, when viewed in a plan view in the thickness direction of the first substrate 21. In a plan view, each first portion 61 extends from the low-concentration drain region 231d to the drain region 231a.

[0053] Furthermore, as shown in Figure 8, each first portion 61 is provided from the insulating layer 221 to the top of the insulating layer 223. Each first portion 61 overlaps the low-concentration drain region 231d and the drain region 231a when viewed from the direction along the X-axis, which is the width direction of the semiconductor layer 231. Each first portion 61 is provided so as to cover the low-concentration drain region 231d and the drain region 231a when viewed from the direction along the X-axis.

[0054] As shown in Figure 9, the second portion 62 is located between the two first portions 61 in a plan view and connects the two first portions 61. The second portion 62 extends in the direction along the X-axis. The second portion 62 is located in the Y2 direction, which is opposite to the Y1 direction with respect to the semiconductor layer 231. The second portion 62, the drain region 231a, and the channel region 231c are aligned in the Y1 direction in this order. The channel region 231c is positioned most in the Y1 direction. In this embodiment, the second portion 62 is in contact with the drain region 231a. The second portion 62 also protrudes in the Z2 direction.

[0055] Furthermore, as shown in Figure 8, the length of the second portion 62 along the Z-axis is equal to the length of each first portion 61 along the Z-axis. The second portion 62 extends from the insulating layer 221 to the top of the insulating layer 223. Also, as shown in Figure 11, the second portion 62 overlaps with the semiconductor layer 231 when viewed in the Y1 direction. The second portion 62 covers the semiconductor layer 231 when viewed in the Y1 direction.

[0056] As shown in Figure 10, the third portion 63 is located in the region between the two first portions 61 and the second portion 62. In a plan view, the third portion 63 overlaps the drain region 231a and the low-concentration drain region 231d. In particular, the third portion 63 covers the low-concentration drain region 231d in a plan view. Also, as shown in Figure 8, the third portion 63 is provided on the insulating layer 223. In the Z-axis, the third portion 63 is located above the semiconductor layer 231 and the gate electrode 232.

[0057] As shown in Figure 9, the fourth portion 64 is located between the two first portions 61 in a plan view and is positioned in the Y1 direction relative to the second portion 62. The fourth portion 64 is in contact with the second portion 62. The length of the fourth portion 64 along the X axis is the same as the length of the second portion 62 along the X axis. In a plan view, the fourth portion 64 overlaps with a portion of the drain region 231a.

[0058] As shown in Figure 8, the fourth portion 64 is located in the Z-axis direction between the third portion 63 and the semiconductor layer 231 and is in contact with the drain region 231a. The fourth portion 64 is provided on the insulating layers 222 and 223.

[0059] As shown in Figures 9 and 10, the second light-shielding section 7 has two fifth sections 71 and a sixth section 72. In Figures 9 and 10, hatching is applied to the second light-shielding section 7 for ease of understanding. In Figure 9, different types of hatching are applied to the fifth section 71 and the sixth section 72. In Figure 10, different types of hatching are applied to the fifth section 71 and the sixth section 72.

[0060] As shown in Figures 9 and 10, the two fifth portions 71 are spaced apart from each other and extend in the Y1 direction in a plan view. In a plan view, the two fifth portions 71 are located on either side of the gate electrode 232 and the channel region 231c. The two fifth portions 71 are also spaced apart from the two first portions 61 and are located outside the two first portions 61. Furthermore, as shown in Figure 6, each fifth portion 71 extends in the Z-axis from the third light-shielding portion 8 to the scan line 241. Each fifth portion 71 is in contact with the third light-shielding portion 8 and the scan line 241.

[0061] As shown in Figures 9 and 10, the sixth portion 72 is located between the two fifth portions 71 and is in contact with them. The sixth portion 72 extends in the direction along the X-axis. As shown in Figures 6 and 8, the sixth portion 72 is provided in the Z-axis from the gate electrode 232 to the scan line 241. The sixth portion 72 is in contact with the gate electrode 232 and the scan line 241. Therefore, the second light-shielding portion 7 also serves as a contact plug connecting the gate electrode 232 and the scan line 241.

[0062] As described above, the first light-shielding portion has two first portions 61 and a second portion 62. The two first portions 61 extend in the Y1 direction in a plan view, are spaced apart from the low-concentration drain region 231d, which is the "boundary" between the drain region 231a and the channel region 231c, and sandwich the low-concentration drain region 231d in a plan view. The second portion 62 is located between the two first portions 61 in a plan view and connects the two first portions 61. Furthermore, the second portion 62, the drain region 231a, the low-concentration drain region 231d, and the channel region 231c are aligned in the Y1 direction in a plan view. Therefore, the second portion 62 is located in the Y2 direction of the semiconductor layer 231.

[0063] The provision of the first light-shielding portion 6 effectively suppresses the incidence of light into the low-concentration drain region 231d, which is the "boundary," compared to the conventional configuration. In particular, the two first portions 61 sandwich the low-concentration drain region 231d in a plan view, and the second portion 62 is located in the Y2 direction relative to the semiconductor layer 231. Therefore, the first light-shielding portion 6 effectively suppresses the incidence of light into the low-concentration drain region 231d from the side, especially from the Y1 direction.

[0064] Furthermore, each of the two first portions 61 is provided from the upper layer to the lower layer of the semiconductor layer 231 along the Z-axis. Specifically, the two first portions 61 are provided from the lower insulating layer 221 to the upper insulating layer 223 of the insulating layer 222 on which the semiconductor layer 231 is provided. As a result, the first portions 61 can suppress the incidence of light from the direction along the X-axis, which is to the side of the low-concentration drain region 231d, and also from directions intersecting the X, Y, and Z axes.

[0065] Similarly, the second portion 62 is provided in the Z-axis direction from the upper layer to the lower layer of the semiconductor layer 231. Specifically, the second portion 62 is provided from the lower insulating layer 221 to the upper insulating layer 223 of the insulating layer 222 on which the semiconductor layer 231 is provided. Therefore, the second portion 62 can suppress the incidence of light from the Y1 direction, which is to the side of the low-concentration drain region 231d, and also from directions intersecting the X, Y, and Z axes.

[0066] Furthermore, when viewed in the Y1 direction, which is the "first direction," the second portion 62 overlaps with the semiconductor layer 231. Therefore, the second portion 62 can suppress the incidence of light from the Y1 direction, which is to the side of the low-concentration drain region 231d.

[0067] Furthermore, the first light-shielding portion 6 has a third portion 63 that overlaps the low-concentration drain region 231d in a plan view. The provision of the third portion 63 makes it possible to suppress the incidence of light from above the low-concentration drain region 231d.

[0068] Furthermore, the first light-shielding portion 6 has a fourth portion 64 located between the third portion 63 and the drain region 231a in the direction along the Z axis and connected to the drain region 231a. Because of this fourth portion 64, the first light-shielding portion 6 is at the drain potential. Therefore, the first light-shielding portion 6 can be brought close to the low-concentration drain region 231d. Thus, the light-shielding performance of the first light-shielding portion 6 with respect to the low-concentration drain region 231d can be improved.

[0069] The fourth section 64 is connected to the second section 62. Therefore, the second section 62 is in close proximity to the fourth section 64. Thus, the second section 62 can be brought close to the low-concentration drain region 231d, further improving the light-shielding performance of the first light-shielding section 6.

[0070] Note that the first light-shielding portion 6 does not necessarily have to be at the drain potential.

[0071] In this embodiment, a second light-shielding portion 7 is also provided. The second light-shielding portion 7 is electrically connected to the gate electrode 232. The second light-shielding portion 7 has two fifth portions 71 and a sixth portion 72. The two fifth portions 71 extend in the Y1 direction in a plan view, are spaced apart in the low-concentration drain region 231d, and sandwich the low-concentration drain region 231d in a plan view. The sixth portion 72 is located between the two fifth portions 71 in a plan view, connects the two fifth portions 71, and is connected to the gate electrode 232.

[0072] The provision of this second light-shielding section 7 makes it possible to suppress the incidence of light into the low-concentration drain region 231d from the Y2 direction and from above.

[0073] Furthermore, the second light-shielding portion 7 does not necessarily have to have two fifth portions 71 that are arranged to sandwich the low-concentration drain region 231d in a plan view.

[0074] Figure 12 is a diagram corresponding to the line B3-B3 in Figure 9. As shown in Figures 9 and 12, the two fifth portions 71 are located outside the two first portions 61 relative to the semiconductor layer 231 in a plan view. Viewed along the X-axis, the fifth portion 71 and the first portion 61 overlap. And, viewed downward from the gate electrode layer 232, that is, in a plan view, the low-concentration drain region 231d is surrounded by the first light-shielding portion 6 and the second light-shielding portion 7. Therefore, the incidence of light onto the low-concentration drain region 231d from the side, specifically from all directions in the XY plane, can be effectively suppressed. As a result, malfunctions caused by the photocurrent of the transistor 23 can be suppressed more effectively than in the conventional method.

[0075] Furthermore, the two fifth portions 71 are located outside the two first portions 61 relative to the semiconductor layer 231 in a plan view. Therefore, in the direction along the X-axis, the distance between the fifth portions 71 and the low-concentration drain region 231d is longer than the distance between the first portions 61 and the low-concentration drain region 231d. Because the fifth portions 71 are further away from the low-concentration drain region 231d than the first portions 61, the risk of the gate potential of the fifth portions 71 affecting the low-concentration drain region 231d is reduced. Specifically, it is possible to suppress the increase in off-leak current caused by the gate potential approaching regions other than the channel region 231c of the semiconductor layer 231. Therefore, it is possible to suppress the deterioration of display quality due to the occurrence of black spots, etc. Off-leak current is the leakage current that flows when the transistor 23 is turned off.

[0076] Note that the fifth part 71 and the first part 61 do not need to overlap when viewed along the X-axis.

[0077] Furthermore, each of the two first portions 61 and the two fifth portions 71 is a straight line along the Y1 direction, which is the direction in which the semiconductor layer 231 extends when viewed from above. Therefore, compared to the case where they are bent or curved, the light-shielding region A12 in which the first light-shielding portion 6 and the second light-shielding portion 7 are located can be narrowed. As a result, the aperture region A11 can be expanded, i.e., the aperture ratio can be improved.

[0078] Furthermore, the fifth part 71 and the first part 61 may each be bent or curved in plan view.

[0079] Furthermore, as shown in Figure 5, a third light-shielding portion 8 is positioned between the first substrate 21 and the semiconductor layer 231. The third light-shielding portion 8 is the gate potential. As shown in Figure 7, the third light-shielding portion 8 overlaps the low-concentration drain region 231d in a plan view. By positioning the third light-shielding portion 8 below the semiconductor layer 231, the incidence of light from below the semiconductor layer 231 into the low-concentration drain region 231d can be suppressed. Therefore, the first light-shielding portion 6, the second light-shielding portion 7, and the third light-shielding portion 8 can effectively suppress the incidence of light from all directions into the low-concentration drain region 231d of the semiconductor layer 231.

[0080] Furthermore, as shown in Figure 5, the connection portion 70 of the second light-shielding portion 7 with the gate electrode 232 is located on the drain region 231a side of the gate electrode 232 in a plan view. By arranging the connection portion 70 in this way, the light-shielding region A12 in which the second light-shielding portion 7 is located can be narrowed. As a result, the opening region A11 can be expanded, i.e., the aperture ratio can be improved.

[0081] Figure 13 is a plan view showing the gate electrode 232 shown in Figure 5. As shown in Figure 13, the gate electrode 232 has a first gate portion 2321 and a second gate portion 2322. In a plan view, the second gate portion 2322 is located further from the drain region 231a than the first gate portion 2321. The length of the second gate portion 2322 along the X axis is shorter than the length of the first gate portion 2321 along the X axis. The first gate portion 2321 is located at the intersection of the light-shielding region A12. The aforementioned second light-shielding portion 7 is connected to the first gate portion 2321.

[0082] With this configuration of the gate electrode 232 and the arrangement of the second light-shielding portion 7, it is easy to narrow the light-shielding region A12. Therefore, it is possible to enlarge the aperture region A11, that is, to improve the aperture ratio.

[0083] Furthermore, for example, the first light-shielding portion 6 is manufactured as follows. First, the portions of the insulating layers 221, 222, and 223 corresponding to the fourth portion 64 and parts of the first portion 61 and second portion 62 in the same layer are removed by etching. Next, the portions of the insulating layer 223 corresponding to the third portion 63 and the remaining parts of the first portion 61 and second portion 62 in the same layer are removed by etching. Next, the portions of the insulating layers 221, 222, and 223 that were removed by etching are filled with a material such as tungsten. As a result, the first light-shielding portion 6 is manufactured.

[0084] 2. Variations The embodiments illustrated above can be modified in various ways. Specific examples of modifications that can be applied to the aforementioned embodiments are given below. Two or more embodiments arbitrarily selected from the following examples can be combined as appropriate, to the extent that they do not contradict each other.

[0085] 2-1. First variation Figure 14 is a cross-sectional view showing the first light-shielding portion 6A of the first modified example. Figure 15 is a plan view of the first light-shielding portion 6A shown in Figure 14. As shown in Figures 14 and 15, in the first light-shielding portion 6A of the first modified example, the second portion 62A is spaced apart from the semiconductor layer 231 and does not contact the semiconductor layer 231. Therefore, the second portion 62A is spaced apart from the fourth portion 64 and does not contact the semiconductor layer 231.

[0086] Thus, in this modified example, the fourth portion 64 is spaced apart from the second portion 62A. With this configuration of the first light-shielding portion 6A, the area that is opened by etching during manufacturing can be reduced compared to the first light-shielding portion 6 of the first embodiment. Therefore, the possibility of insufficient filling and voids caused by dishing during damascene processing can be reduced. Furthermore, with the configuration of the first light-shielding portion 6A, the area that is opened by etching is smaller compared to the first light-shielding portion 6, i.e., the aspect ratio is larger. As a result, the etching rate of the first portion 61, the second portion 62A and the fourth portion 64 can be reduced. Therefore, the amount of over-etching of the semiconductor layer 231 can be reduced. Consequently, the risk of penetrating the semiconductor layer 231 during etching when forming the first light-shielding portion 6A can be reduced.

[0087] 2-2. Other variations In the embodiments described above, an active-matrix electro-optical device 100 is exemplified, but the device is not limited thereto, and the driving method of the electro-optical device 100 may be, for example, a passive-matrix method.

[0088] The driving method for the "electro-optical device" is not limited to a longitudinal electric field method, but may also be a transverse electric field method. An example of a transverse electric field method is the IPS (In Plane Switching) mode. Examples of longitudinal electric field methods include the TN (Twisted Nematic) mode, VA (Vertical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode.

[0089] In the above description, the second light-shielding section 7 is connected to the third light-shielding section 8, but it does not have to be connected. Also, the third light-shielding section 8 may be omitted.

[0090] 2.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0091] Figure 16 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main unit 2010 in which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0092] Figure 17 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has operation buttons 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to the operation of the operation buttons 3001. The control unit 3002 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0093] Figure 18 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. Electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b, corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0094] The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is the light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator, such as a light bulb, that modulates the monochromatic light supplied from the illumination optical system 4001 according to the displayed image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0095] The electronic device described above comprises the aforementioned electro-optical device 100 and control units 2003, 3002, or 4005. Because the aforementioned electro-optical device 100 has excellent light-shielding properties in the semiconductor layer 231, instability in the operation of the transistor 23 is suppressed. Therefore, the risk of display malfunctions is suppressed. Furthermore, by including the electro-optical device 100, the light resistance of the panel can be improved, thereby increasing the brightness of the electronic device. Thus, by including the electro-optical device 100, the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000 can be enhanced.

[0096] Furthermore, the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices, but include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of Sale) terminals. In addition, electronic devices to which the present invention is applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0097] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added.

[0098] Furthermore, while the above description described a liquid crystal display device as an example of the electro-optical device of the present invention, the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to image sensors and the like. [Explanation of Symbols]

[0099] 2...Element substrate, 3...Opposite substrate, 5...Liquid crystal layer, 6...First light-shielding section, 7...Second light-shielding section, 8...Third light-shielding section, 21...First substrate (substrate), 22...Laminate, 23...Transistor, 25...Pixel electrode, 61...First part, 62...Second part, 63...Third part, 64...Fourth part, 71...Fifth part, 72...Sixth part, 100...Electro-optical device, 221-229...Insulating layer, 231...Semiconductor layer , 231a...Drain region, 231b...Source region, 231c...Channel region, 231d...Low-density drain region, 231e...Low-density source region, 232...Gate electrode, 233...Gate insulating film, 241...Scan line, 242...Signal line, 243...Constant potential line, 2010...Main body, A10...Display region, A11...Aperture region, A12...Light-shielding region, A20...Peripheral region, P...Pixel.

Claims

1. circuit board and A transistor comprising a gate electrode and a semiconductor layer disposed between the substrate and the gate electrode and extending in a first direction, A first light-shielding portion that blocks the incidence of light onto the semiconductor layer, Equipped with, The semiconductor layer has a drain region, a channel region, and a source region arranged along the first direction, The first light-shielding portion is, The two first portions are spaced apart at the boundary between the drain region and the channel region, and extend in the first direction in a plan view in the thickness direction of the substrate, flanking the boundary. In the plan view, it has a second portion located between the two first portions and connecting the two first portions, The second portion, the drain region, the boundary portion, and the channel region are aligned in the first direction in the plan view. An electro-optical apparatus characterized by the following features.

2. Each of the two first parts is provided from the upper layer to the lower layer of the semiconductor layer. The electro-optical apparatus according to claim 1.

3. The second part is provided from the upper layer to the lower layer of the semiconductor layer, The electro-optical apparatus according to claim 1.

4. Viewed in the first direction, the second portion overlaps the semiconductor layer, The electro-optical apparatus according to claim 1.

5. The first light-shielding portion has a third portion that overlaps the boundary portion in the plan view, The electro-optical apparatus according to claim 1.

6. The first light-shielding portion is located between the third portion and the drain region and has a fourth portion connected to the drain region. The electro-optical apparatus according to claim 5.

7. The fourth part is connected to the second part, The electro-optical apparatus according to claim 6.

8. The fourth part is separated from the second part. The electro-optical apparatus according to claim 6.

9. The gate electrode is further equipped with a second light-shielding portion electrically connected to the gate electrode, The second light-shielding portion is, The boundary portion is spaced apart, and in the plan view, it extends in the first direction and encloses the boundary portion, The device has a sixth portion located between the two fifth portions in the plan view, connecting the two fifth portions and connected to the gate electrode, The electro-optical apparatus according to claim 1.

10. The two fifth portions are located, in the plan view, outside the semiconductor layer compared to the two first portions. The electro-optical apparatus according to claim 1.

11. An electro-optical apparatus according to any one of claims 1 to 10, An electronic device characterized by having a control unit that controls the operation of the electro-optical device.

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