Apparatus and system for offset cross field effect transistors - Patents.com

Abstract

A disclosed integrated circuit for an offset cross field effect transistor can include a first transistor including a first channel oriented in a first direction, an oxide layer adjacent to the first transistor, and a second transistor adjacent to the oxide layer. The second transistor can include a second channel oriented in a direction orthogonal to the first direction, and the first and second channels can be laterally offset such that the second channel does not cross the first channel. Various other devices, systems, and methods are also disclosed.

Description

[Background technology]

[0001] Non-planar transistors may enable scaling of semiconductor devices beyond planar transistor designs.

[0002] The accompanying drawings illustrate several exemplary embodiments and variations and constitute a part of this specification, and together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a diagram of an exemplary pair of offset cross field effect transistors. [Figure 2] FIG. 1 is a diagram of an exemplary transistor. [Figure 3] FIG. 2 is a diagram of an exemplary transistor connected to a power source. [Figure 4] FIG. 2 is a diagram of an exemplary pair of transistors, each connected to a power source. [Figure 5] FIG. 2 is a diagram of an exemplary pair of transistors separated by an air gap. [Figure 6] 6 is another view of the exemplary pair of transistors of FIG. 5. [Figure 7] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 8] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 9] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 10] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 11] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 12]FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 13] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 14] FIG. 1 is a layer diagram of an exemplary layout using offset cross field effect transistors. [Figure 15] FIG. 1 is a flow diagram of an exemplary method for fabricating an offset cross field effect transistor. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments and variations described herein are susceptible to various modifications and alternative forms, specific embodiments and variations have been shown by way of example in the drawings and are described in detail herein. However, the exemplary embodiments and variations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] The present disclosure is generally directed to devices, systems and methods for offset cross field effect transistors.

[0006] In some embodiments, the cross field effect transistor (or "XFET") is a vertically stacked gate-all-around (GAA) transistor, where an upper vertical GAA transistor is formed vertically on top of a lower GAA transistor with at least an isolation oxide layer between the two GAA transistors. In addition, the upper GAA transistor has one or more conductive channels positioned orthogonal to one or more conductive channels of the lower GAA transistor. Thus, the direction of current flow of the upper GAA transistor through one or more upper channels is orthogonal to the direction of current flow of one or more lower channels of the lower GAA transistor.

[0007] In some embodiments, an offset intersecting field effect transistor (or "TFET") is an XFET that is laterally offset such that one or more upper channels of an upper GAA transistor do not intersect one or more lower channels of a lower GAA transistor. Thus, the one or more upper channels and one or more lower channels of a TFET can form a "T" shape. In some variations, the channels of the TFET can be formed from nanosheets. Thus, the upper channel nanosheet(s) and the lower channel nanosheet can be offset from one another.

[0008] In some embodiments, the upper channel nanosheet(s) can be moved away from the lower channel local interconnect so that the metal sidewall contact can be full width when passing through the upper channel nanosheet. The upper channel local interconnect can clear the upper channel nanosheet before contacting the lower lower channel local interconnect. In some variations, instead of a contact from the upper channel local interconnect to the lower channel local interconnect, there can be a contact from the upper channel to the lower channel gate, both over-field.

[0009] In some embodiments, one or more of the TFET designs described herein may enable both upper-channel to lower-channel gate-to-gate structures and upper-channel and lower-channel local interconnect structures, which can reduce device resistance and / or capacitance. Additionally, in embodiments in which the upper-channel local interconnect clears the lower-channel nanosheet before contacting the lower-channel interconnect, there may be lower-resistance contact between the upper-channel local interconnect connection and the lower-channel local interconnect connection. Furthermore, these embodiments may have more reliable yields, higher device reliability, and / or less process resistance variation. Additionally, one or more of the TFET designs described herein may include less complex selective etch bias process modules, which use fewer materials and enable lower costs. Also, in some embodiments, offsetting the upper and lower gate-area transistors can mitigate heat spreading.

[0010] The upper GAA transistor has a doping polarity of one or more upper channels that is opposite to the doping polarity of one or more lower channels of the lower GAA transistor. For example, in one embodiment, the upper GAA transistor includes one or more p-type channels, while the lower GAA transistor includes one or more n-type channels. In another embodiment, the p-type and n-type polarities are reversed between one or more channels of the upper GAA transistor and one or more channels of the lower GAA transistor. With an orthogonal orientation between the upper GAA transistor and the lower GAA transistor, both the upper and lower GAA transistors have their respective maximum carrier mobilities based on their orientation.

[0011] Below, a detailed description of an exemplary TFET is provided with reference to FIG. 1 , a detailed description of an exemplary GAA transistor is provided with reference to FIG. 2 , a detailed description of exemplary connections and arrangements of the GAA transistor is provided with reference to FIGS. 3-6 , a detailed description of exemplary layouts of devices using TFETs is provided with reference to FIGS. 7-14 , and a detailed description of an exemplary method of fabricating a TFET is provided with reference to FIG. 15 .

[0012] FIG. 1 is a three-dimensional view of an exemplary TFET pair 100. As shown in FIG. 1, a p-type device is vertically stacked on an n-type device. The n-type device includes at least one n-type gate 102 formed all around an n-type channel 104. Similarly, a p-type gate 106 is formed all around a p-type channel 108. Thus, the p-type channel 108 has a doping polarity that is opposite to that of the n-type channel 104 of the lower n-type device. Although a single n-type channel 104 and a single p-type channel 108 are shown, in other embodiments, the semiconductor device includes a different number of channels. In other embodiments, the channels are nanosheets.

[0013] The n-type channel 104 and n-type gate 102 are oriented in an orthogonal direction to the p-type channel 108 and p-type gate 106. In other words, the n-type channel 104 and n-type gate 102 are oriented in a direction that is 90 degrees from the direction of the p-type channel 108 and p-type gate 106. Thus, the direction of current flow of the lower n-type device through the n-type channel 104 is orthogonal to the direction of current flow of the p-type channel 108 of the upper p-type device.

[0014] 1, the p-type channel 108 does not intersect with the n-type channel 104. However, the p-type gate 106 intersects with the n-type gate 102, approximating a "T" shape.

[0015] FIG. 2 is a cross-sectional view of an exemplary transistor 200. As shown in FIG. 2, transistor 200 can be a GAA transistor. Transistor 200 can include multiple channels 202(1)-(4). In some variations, channels 202(1)-(4) can be nanosheets (e.g., of the same doping polarity). In some variations, transistor 200 can include fewer or more channels. Transistor 200 can also include a gate 206 surrounding channels 202(1)-(4). Transistor 200 can also include a metal sidewall source 212 and a metal sidewall drain 224 that contact channels 202(1)-(4) on either side. The source 212 and drain 224 provide metal regions that can offer lower resistance than if they were silicon. Thus, assuming a contact on the top surface of transistor 200, current from channel 202(4) travels farther than current from channel 202(1), but the difference in resistance between the current from channel 202(4) and the current from channel 202(1) is less than it would be if the material were, for example, silicon rather than a metal. Thus, with metal sidewalls for source 212 and drain 224, transistor 200 can provide higher performance.

[0016] FIG. 3 is a diagram of a device 300 including the example transistor 200 of FIG. 2 connected to power. As shown in FIG. 3, the transistor 200 is connected to a backside metal 0 (M0) layer 320 by a via 310. Because the source 212 is a metal sidewall contact, the metal can continue down through the via 310 directly to the backside M0 layer 320. This can provide a short, low-resistance path for providing power to the transistor 200. In comparison, an alternative design could include a via from the backside M0 layer 320 to a contact (not shown) to the frontside M0 layer (not shown) and another contact (not shown) to the top surface of the source 212. This alternative design may involve a longer, higher-resistance path, greater manufacturing complexity, and / or occupy more space than the design shown in FIG. 3.

[0017] FIG. 4 is a diagram of a design 400 including the example device 300 of FIG. 3 and an example device 402. As shown in FIG. 4, the device 402 can include a transistor 404. The transistor 404 can be a gate-array transistor including a source 412, a drain 424, a gate 406, and one or more channels 408. Similar to transistor 200, the source 412 and the drain 424 can include metal sidewall contacts. In some embodiments, the source 412 can be connected to a contact 410, which can be connected to a front M0 layer 420. In some variations, the transistor 200 and the transistor 404 can have opposite polarities. For example, the transistor 200 can be an n-channel device (e.g., connected to VSS) and the transistor 404 can be a p-channel device (e.g., connected to VDD). Thus, the backside M0 layer 320 can provide only VSS (for an n-channel device) and the frontside M0 layer 420 can provide only VDD (for a p-channel device).

[0018] FIG. 5 is a cross-sectional view of an exemplary pair of transistors 500 separated by an air gap. FIG. 6 is a top view of the design 500 shown in FIG. 5. As shown in FIGS. 5-6, the design 500 can include a transistor 200(a) and a transistor 200(b) (e.g., each instance of the transistor 200 in FIG. 2), each having a power connection to the backside M0 layer 320. As can be seen, the drain of transistor 200(a) can be adjacent to the source of transistor 200(b). In other examples, the design 500 can include the sources of two transistors or the drains of two transistors in close proximity. Because an oxide layer exists between transistors 200(a) and 200(b), no other barrier is relied upon to prevent shorting. Instead, the design 500 includes an air gap 502 between transistors 200(a) and 200(b), which can result in lower capacitance.

[0019] In one variation, transistors 200(a) and 200(b) are n-channel devices. However, design 500 can also be applied to adjacent p-channel devices. For example, device 404 in FIG. 4 can be a p-channel device, and apparatus 402 can include another p-channel device adjacent to device 404. The design can include an air gap between device 404 and the additional p-channel device.

[0020] In some variations, instead of an air gap, the design can include a non-conductive material that introduces compressive or tensile stress (i.e., between the two devices). In some examples, such a design can improve the current drive of the device.

[0021] 7 is a layer diagram 700 of an example cell layout using TFETs. A backside M0 layer may be at the base of the layout. As shown in FIG. 7, initial layers on the backside M0 layer may include through-silicon vias for n-channel local interconnects (e.g., for the source of an n-channel device).

[0022] Figure 8 is a layer diagram 800 that builds on the example cell layout of Figure 7. As shown in Figure 8, the layout can further include an n-channel local interconnect that includes two sources and connected drains, forming two n-channel GAA devices.

[0023] Figure 9 is a layer diagram 900 that builds on the exemplary cell layout of Figure 8. As shown in Figure 9, a contact is placed on the output of the n-channel drain.

[0024] Figure 10 is a layer diagram 1000 that builds on the exemplary cell layout of Figure 9. As shown in Figure 10, n-channel / p-channel gate contacts are placed on the two n-channel gates.

[0025] Figure 11 is a layer diagram 1100 that builds on the example cell layout of Figure 10. As shown in Figure 11, two p-channel devices are added, with two sources and one shared drain. The shared drain of the p-channel devices connects to the shared drain of the n-channel device (e.g., at a contact disposed on the shared n-channel drain, as shown in Figure 9). In addition, the p-channel gate of the p-channel device connects to the n-channel gate of the n-channel device (e.g., at an n-channel / p-channel gate contact disposed as shown in Figure 10).

[0026] Figure 12 is a layer diagram 1200 that builds on the exemplary cell layout of Figure 11. As shown in Figure 12, p-channel local interconnect contacts to surface M0 are added, one for a p-channel source that supplies power, and one for an output contact from the connected p-channel and n-channel drain to surface M0.

[0027] Figure 13 is a layer diagram 1300 that builds on the exemplary cell layout of Figure 12. As shown in Figure 13, a contact is added on the p-channel gate to surface M0.

[0028] Figure 14 is a layer diagram 1400 that builds on the exemplary cell layout of Figure 13. As shown in Figure 14, a surface M0 layer is added to couple the two gates with the contacts shown in Figure 13, provide the output from the output contacts shown in Figure 12, and connect the VDD line running over the p-channel source with the contact on the source shown in Figure 12.

[0029] As can be seen, the cell layouts shown in Figures 7-14 result in inverters using TFET architecture.

[0030] 15 is a flow diagram of an exemplary method for fabricating an offset cross field effect transistor. In some examples, each of the steps shown in FIG. 15 can represent a method whose construction includes and / or is represented by multiple substeps.

[0031] 15, in step 1502, the method may include arranging a first transistor and a second transistor within an integrated circuit. In some embodiments, the first transistor and the second transistor may be GAA transistors. In some embodiments, the first transistor and the second transistor may have opposite doping polarities.

[0032] In Step 1504, the method can include forming a first transistor having a first channel oriented in a first direction. In Step 1506, the method can include forming an oxide layer adjacent to the first transistor.

[0033] In step 1508, the method may include forming a second transistor adjacent to the oxide layer, the second transistor including a second channel oriented in a second direction orthogonal to the first direction. The first channel and the second channel may be formed to be laterally offset from one another such that the second channel does not intersect with the first channel. In some variations, the gate of the second channel may intersect the gate of the first channel orthogonally.

[0034] While the foregoing disclosure describes various embodiments using specific block diagrams, flow diagrams, and examples, each block diagram element, flow diagram step, operation, and / or component described and / or illustrated herein can be implemented individually and / or collectively using a wide variety of hardware, software, or firmware (or any combination thereof) configurations. Additionally, any disclosure of components stored within other components shall be considered exemplary in nature, as many other architectures may be implemented to achieve the same functionality.

[0035] In some examples, all or a portion of the example system 100 of Figure 1 may represent part of a cloud computing or network-based environment. A cloud computing environment may provide various services and applications over the Internet. These cloud-based services (e.g., software as a service, platform as a service, infrastructure as a service, etc.) may be accessible through a web browser or other remote interface. Various functionality described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

[0036] In various embodiments, all or a portion of the example system 100 of FIG. 1 can facilitate multi-tenancy within a cloud-based computing environment. In other words, the modules described herein can configure a computing system (e.g., a server) to facilitate multi-tenancy for one or more of the functions described herein. For example, one or more of the modules described herein can program a server to allow two or more clients (e.g., customers) to share an application running on the server. A server so programmed can share applications, operating systems, processing systems, and / or storage systems among multiple customers (i.e., tenants). Additionally, one or more of the modules described herein can partition data and / or configuration information of a multi-tenant application by customer, such that one customer cannot access data and / or configuration information of another customer.

[0037] According to various embodiments, all or a portion of the example system 100 of Figure 1 may be implemented within a virtual environment. For example, the modules and / or data described herein may reside and / or execute within a virtual machine. As used herein, the term "virtual machine" generally refers to any operating system environment that is abstracted from computing hardware by a virtual machine manager (e.g., a hypervisor).

[0038] In some examples, all or a portion of the example system 100 of FIG. 1 may represent a portion of a mobile computing environment. The mobile computing environment may be implemented by a wide range of mobile computing devices, including mobile phones, tablet computers, e-readers, personal digital assistants, wearable computing devices (e.g., computing devices with head-mounted displays, smart watches, etc.), one or more variations or combinations thereof, or any other suitable mobile computing device. In some examples, the mobile computing environment may have one or more different capabilities, including, for example, dependence on battery power, presenting only one foreground application at any given time, remote management capabilities, touchscreen capabilities, location and movement data (e.g., provided by a global positioning system, gyroscope, accelerometer, etc.), a restricted platform that restricts system-level configuration changes and / or limits the ability of third-party software to inspect the behavior of other applications, controls that restrict application installation (e.g., provided only from approved application stores), etc. The various capabilities described herein may be provided to and / or interact with the mobile computing environment.

[0039] The process parameters and order of steps described and / or illustrated herein are provided by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein may be shown or described in a particular order, these steps do not necessarily have to be performed in the order shown or described. The various exemplary methods described and / or illustrated herein can also omit one or more of the steps described or illustrated herein or can include additional steps in addition to those disclosed.

[0040] Although various embodiments have been described and / or illustrated herein in the context of a fully functional computing system, one or more of these exemplary embodiments may be distributed as a program product in various forms, regardless of the particular type of computer-readable medium used to actually execute the distribution. The embodiments disclosed herein may also be implemented using modules that perform certain tasks. These modules may include scripts, batch files, or other executable files that may be stored on a computer-readable storage medium or within a computing system. In some embodiments, these modules may configure a computing system to execute one or more of the exemplary embodiments disclosed herein.

[0041] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many changes and modifications are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0042] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect connections (i.e., via other elements or components). Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising," and have the same meaning.

Claims

1. 1. An integrated circuit comprising: a first transistor having a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; a second transistor adjacent to the oxide layer. the second transistor includes a second channel oriented in a direction perpendicular to the first direction; the first channel and the second channel are laterally offset such that the second channel does not intersect with the first channel. Integrated circuit.

2. the first channel comprises a first nanosheet; the second channel comprises a second nanosheet; the first transistor is a gate-all-around device; the second transistor is a gate-all-around device; 10. The integrated circuit of claim 1.

3. the first transistor comprises a third channel including a third nanosheet; 3. The integrated circuit of claim 2.

4. the first transistor includes a first gate extending in the second direction; the second transistor includes a second gate extending in the first direction so as to intersect with the first gate; 3. The integrated circuit of claim 2.

5. a vertical gate contact coupled to the first gate and the second gate; 5. The integrated circuit of claim 4.

6. a first doping polarity of the first channel is opposite to a second doping polarity of the second channel; 10. The integrated circuit of claim 1.

7. the second channel is formed on a wafer bonded to the oxide layer; 10. The integrated circuit of claim 1.

8. the first transistor comprises a first metal sidewall source and a first metal sidewall drain; 10. The integrated circuit of claim 1.

9. the second transistor comprises a second metal sidewall source and a second metal sidewall drain; the second metal sidewall source is directly connected to the front metal layer by a contact; 10. The integrated circuit of claim 1.

10. a physical memory containing computer-executable instructions; an integrated circuit configured to execute the computer-executable instructions; The integrated circuit comprises: a first transistor having a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; a second transistor adjacent to the oxide layer; the second transistor includes a second channel oriented in a direction perpendicular to the first direction; the first channel and the second channel are laterally offset such that the second channel does not intersect with the first channel. system.

11. the first channel comprises a first nanosheet; the second channel comprises a second nanosheet; the first transistor is a gate-all-around device; the second transistor is a gate-all-around device; The system of claim 10.

12. the first transistor comprises a third channel including a third nanosheet; The system of claim 11.

13. the first transistor includes a first gate extending in the second direction; the second transistor includes a second gate extending in the first direction so as to intersect with the first gate; The system of claim 11.

14. a vertical gate contact coupled to the first gate and the second gate; The system of claim 13.

15. a first doping polarity of the first channel is opposite to a second doping polarity of the second channel; The system of claim 10.

16. the second channel is formed on a wafer bonded to the oxide layer; The system of claim 10.

17. the first transistor comprises a first metal sidewall source and a first metal sidewall drain; The system of claim 10.

18. a third transistor adjacent to the first transistor; There is no diffusion break structure between the first transistor and the third transistor.

18. The system of claim 17.

19. an air gap between the first transistor and the third transistor; or a stress layer between the first transistor and the third transistor; At least one of 20. The system of claim 18.

20. 1. A method comprising: disposing a first transistor and a second transistor in an integrated circuit; forming the first transistor having a first channel oriented in a first direction; forming an oxide layer adjacent to the first transistor; forming the second transistor adjacent to the oxide layer; the second transistor comprises a second channel oriented in a second direction orthogonal to the first direction; the first channel and the second channel are laterally offset such that the second channel does not intersect with the first channel. method.

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