PCB land pad for 3-pin MOSFET component

Abstract

A printed circuit board (PCB) land pad for a three-pin metal-oxide-semiconductor field-effect transistor (MOSFET) component includes four pads, including a split pad for a drain terminal of the MOSFET component. The PCB land pad includes a first pad for connecting a gate terminal of the MOSFET component to a PCB, a second pad for connecting a source terminal of the MOSFET component to a PCB, a third pad corresponding to connecting the drain terminal of the MOSFET component to a PCB, and a fourth pad for connecting the drain terminal of the MOSFET component to a PCB.

Description

[Technical Field]

[0001] Priority application This application claims the benefit of priority to U.S. Provisional Application No. 63 / 457,581, filed April 6, 2023, and U.S. Provisional Application No. 63 / 435,505, filed December 27, 2022, all of which are incorporated herein by reference in their entirety.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to printed circuit boards (PCBs), and more particularly to PCB land pads for asymmetric three-pin metal oxide semiconductor field effect transistors (MOSFETs). [Background technology]

[0003] MOSFETs are the most widely used form of transistor used in modern electronic devices. They can be classified as N-type or P-type MOSFETs, where electrons are the primary charge carriers in N-type and holes are the primary charge carriers in P-type. Memory devices such as solid-state drives (SSDs) use MOSFETs in the form of small-outline transistors (SOTs) in addition to the billions of transistors already used inside the memory cell die. In this context, a MOSFET is primarily used to control the conductivity between its source and drain terminals depending on the amount of voltage applied to its gate terminal.

[0004] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data in and retrieve data from the memory devices.

[0005] The present disclosure will be more fully understood from the following detailed description and accompanying drawings of various embodiments of the disclosure. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 illustrates a PCB land pad for a 3-pin MOSFET according to some embodiments of the present disclosure. [Figure 2] 1 is a flow diagram of an exemplary method for assembling a PCB including at least one PCB land pad for a 3-pin MOSFET component, according to some embodiments of the present disclosure. [Figure 3] 1 is a flow diagram of an example method for manufacturing an assembled PCB based on a PCB including at least one PCB land pad for a 3-pin MOSFET component, according to some example embodiments of the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary memory subsystem, any one or more of whose components are implemented based on a PCB including at least one PCB land pad for a 3-pin MOSFET component, in accordance with some embodiments of the present disclosure. [Figure 5] FIG. 1 illustrates an exemplary machine in the form of a computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methods described herein. DETAILED DESCRIPTION OF THE INVENTION

[0007] Aspects of the present disclosure are directed to PCB land pads for asymmetric 3-pin MOSFET components. While various embodiments described herein may be extended to any assembled PCB or PCB assembly process, one or more embodiments may find particular application in the context of a PCB implementing a memory subsystem. The memory subsystem may be a storage device (e.g., a solid-state drive (SSD)), a memory module, or a combination of a storage device and a memory module. Examples of other storage devices and memory modules are described below in connection with FIG. 4. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device, for storing data. The host system may provide data to be stored in the memory subsystem and may request data to be retrieved from the memory subsystem. Typically, a memory subsystem controller receives commands or operations from the host system and translates the commands or operations into instructions or appropriate commands to achieve desired access to memory components of the memory subsystem.

[0008] The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NOT AND (NAND) memory device. Other examples of non-volatile memory devices are described below in connection with FIG. 1. A NAND memory device may include multiple NAND dies. Each die may include one or more planes, with each plane including multiple blocks. Each block includes an array containing pages (rows) and strings (columns). A string includes multiple memory cells connected in series. A memory cell ("cell") is an electronic circuit (usually a transistor) that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has various logical states that correlate to the number of bits stored. The logical states may be represented by binary values ​​such as "0" and "1," or a combination of such values.

[0009] Various electronic devices, such as memory subsystems (e.g., SSDs, DIMMs), are implemented using one or more printed circuit boards. PCB assembly generally involves a pick-and-place process, in which various circuit components are picked up from tape and reel or trays and placed at specific locations on the PCB, and a reflow process, in which a forced-convection oven is used to melt pre-placed solder material to form reliable bonds between the components and the PCB. As used herein, an assembled PCB may refer to a PCB after one or more components have been attached to it. An assembled PCB may include various circuit components soldered or otherwise connected to the PCB. Circuit components may include, for example, resistors, capacitors, inductors, transistors, fuses, integrated circuits (ICs) or chips, trim potentiometers (trimpots), electro-acoustic devices, microelectromechanical devices (MEMs), electro-optical devices, microprocessing chips, memory chips, multi-pin connectors, and various types of sensors, among others.

[0010] During the reflow process of PCB assembly, circuit components may be soldered to one or more pads on a PCB. A pad is an exposed area of ​​metal on a PCB to which a component pin is soldered. That is, a pad serves as a designated surface area for electrical contact between the component and the board. As used herein, PCB land pads include the set of pads designated for a particular component.

[0011] Generally, there are two types of pads: through-hole pads and surface-mount pads. Through-hole pads are used to attach through-hole components. Surface-mount pads are used to attach surface-mount components. One type of surface-mount pad is a solder mask-defined pad. Solder mask-defined pads are defined by an opening in a solder mask that is applied to the pad. These pads have a solder mask opening that is smaller than the area of ​​the pad that the mask covers; this is done to reduce the size of the copper pad to which the circuit component is soldered.

[0012] As mentioned above, metal-oxide-semiconductor field-effect transistors (MOSFETs) are ubiquitous in electronic devices and are widely used in memory devices such as SSDs. A MOSFET component typically includes three pins (also referred to herein as "terminals"): a gate terminal, a drain terminal, and a source terminal. Traditionally, a PCB land pad with three pads is used to connect the MOSFET component to a PCB during assembly, with each terminal of the MOSFET connected to a single pad on the PCB. Typically, the pad for the drain terminal is much larger than the pads for the source and gate terminals.

[0013] Traditional three-pad designs for MOSFET PCB land pads can result in defects in assembled PCBs. These defects are more prevalent with small MOSFET components due to PCB and component manufacturing issues. For example, traditional three-pad land pad designs for small MOSFETs can result in air gap mismatches between the PCB pad and the component's terminal connection (also referred to herein as "component terminals"). Solder failures can result from air gap mismatches, which can be further amplified by component shift toward the larger drain terminal during the PCB assembly reflow process. This component shift and uneven surface tension can cause the component to tilt and shift further toward the drain pad, resulting in a solder failure at either the MOSFET component's source or gate terminals.

[0014] Aspects of the present disclosure address the aforementioned problems with conventional PCB land pads for MOSFETs by splitting the pad for the drain terminal of the MOSFET into two pads. That is, the present disclosure relates to an improved PCB land pad for a 3-pin MOSFET that includes four pads: a first pad for connecting the gate terminal of the MOSFET to the PCB, a second pad for connecting the source terminal of the MOSFET to the PCB, and third and fourth pads for connecting the drain terminal of the MOSFET to the PCB.

[0015] Compared to traditional land pad designs, the four-pad PCB land pad distributes more uniform (correlated average) solder volume across the pad, thereby balancing the surface tension across the four corners of the MOSFET component. As a result, the MOSFET component does not shift toward the drain terminal during the reflow process. Therefore, the four-pad PCB MOSFET land pad prevents component shifting and tilting, thereby ensuring high-quality solder joints. Furthermore, the four-pad design for the MOSFET land pad is solder mask defined. The solder mask definition of the pads maintains a uniform (correlated average) standoff height across the four solder joints, which helps prevent component tilting.

[0016] Furthermore, a uniform standoff height is beneficial to the mechanical reliability of the assembly. For example, comparing a four-pad design of MOSFET land pads with a conventional MOSFET land pad, the pad sizes of the source and gate terminals of the conventional MOSFET land pads have a smaller area ratio at the current standard stencil thickness of 0.1 mm. The stencil thickness can be reduced (e.g., to 0.075 mm) to improve solder printing yield (with an area ratio better than 0.1 mm), thereby increasing the throughput and yield of the surface mount line. However, a reduction in solder volume (e.g., 25%) can affect the mechanical reliability (shear strength) of the assembly. By increasing the pad size compared to the conventional design of the MOSFET land pads, a better solder printing area ratio can be achieved, such as with a four-pad design of MOSFET land pads, without causing pad overprint (e.g., even with a 0.1 mm-thick stencil). This reduces defects by minimizing tilt and improves the mechanical reliability margin by increasing the solder content in the joint.

[0017] 1 is a diagram illustrating a PCB land pad 100 for a three-pin MOSFET component 110 having terminals on only the bottom side, according to some embodiments of the present disclosure. Also shown in FIG. 1 is an equivalent MOSFET circuit 120 corresponding to MOSFET component 110. MOSFET circuit 120 includes a source terminal 122, a gate terminal 124, and a drain terminal 126.

[0018] Unlike conventional PCB land pads for three-pin MOSFET components that include a single pad for each terminal, land pad 100 includes four pads, with the pad for drain terminal 126 being split into two. For example, as shown, land pad 100 includes source pad 102, gate pad 104, drain pad 106, and drain pad 108. In some embodiments, source pad 102, gate pad 104, drain pad 106, and drain pad 108 are uniform in size and positioned symmetrically on land pad 100 with respect to source pad 102 and gate pad 104.

[0019] In some embodiments, land pad 100 is solder mask defined. That is, during PCB assembly, a solder mask defining source pad 102, gate pad 104, and drain pads 106 and 108 of land pad 100 is applied to a copper layer prior to application of solder paste. The solder mask further defines air gap 109 separating drain pad 106 from drain pad 108, and air gap 111 between source pad 102 and gate pad 104. In some embodiments, air gap 109 and air gap 111 are identical. Additionally, the solder mask further defines air gap 113 separating gate pad 104 from drain pad 106, and air gap 115 separating source pad 102 from drain pad 108.

[0020] In some embodiments, air gaps 109 and 111 are approximately 0.15 mm, and air gaps 113 and 115 are approximately 0.3 mm, each with standard manufacturing tolerances (e.g., + / - 35 μm) applicable during PCB fabrication. Consistent with these embodiments, pads 102, 104, 106, and 108 each have a uniform length of 0.45 mm and a uniform width of 0.2 mm. For each pad 102, 104, 106, and 108, a solder paste stencil opening with a vertical length of 0.4 mm, a horizontal length of 0.165 mm, and a fillet of 0.05 mm may be used, with a horizontal gap of 0.175 mm and a vertical gap of 0.31 mm between each stencil opening.

[0021] As mentioned above, each pad is an exposed area of ​​metal on the PCB to which a component terminal is soldered, where source pad 102 is for connecting source terminal 122 of MOSFET component 110 to the PCB, gate pad 104 is for connecting gate terminal 124 of MOSFET component 110 to the PCB, and drain pads 106 and 108 are for connecting drain terminal 126 of MOSFET component 110 to the PCB.

[0022] During a placement process performed as part of PCB assembly, MOSFET component 110 is placed on land pad 100 as shown. More specifically, source terminal 122 of MOSFET component 110 is placed on source pad 102, gate terminal 124 of MOSFET component 110 is placed on gate pad 104, and drain terminal 126 is placed on drain pads 106 and 108.

[0023] During a reflow process performed as part of PCB assembly, the terminals of MOSFET component 110 are soldered to land pad 100. More specifically, source terminal 122 of MOSFET component 110 is soldered to source pad 102, gate terminal 124 of MOSFET component 110 is soldered to gate pad 104, and drain terminal 126 is soldered to drain pads 106 and 108. The split pad design of drain terminal 126 (i.e., drain pads 106 and 108) balances surface tension across the four corners of MOSFET component 110 during reflow, thereby minimizing shift of MOSFET component 110 toward the drain terminal, which is further reduced when land pad 100 is solder mask defined. Overall, the reduced shift and tilt prevents failures due to unsoldered joints in three-terminal MOSFET component 110.

[0024] 2 is a flow diagram of an exemplary method 200 for assembling a PCB including one or more PCB land pads (e.g., one or more of land pads 100) according to some embodiments of the present disclosure. The diagrams shown herein should be understood as examples only, and in various embodiments, one or more processes may be omitted. Thus, not all processes may be used in all embodiments, and other process flows are possible.

[0025] In operation 205, a solder mask is applied to the copper layer of the PCB. The solder mask insulates the copper traces to prevent them from unintentionally contacting other conductive materials and causing shorts. The solder mask defines PCB land pads (hereinafter referred to as "3-pin MOSFET land pads") for surface-mounted 3-pin MOSFET components with terminals only on the bottom side. Referring to the 3-pin MOSFET land pad, the solder mask defines four pads, of which the pad for the drain terminal of the MOSFET component is divided into two. For example, the 3-pin MOSFET land pad includes a source pad, a gate pad, and two drain pads. In some embodiments, the two drain pads are uniform in size and are positioned symmetrically with the source and gate pads on the 3-pin MOSFET land pad. In some embodiments, the solder mask defines a 0.15 mm air gap separating the first and second drain pads. Consistent with these embodiments, the solder mask further defines a 0.15 mm air gap between the source and drain pads.

[0026] Solder paste is applied to exposed copper land pads on the PCB in operation 210. As part of applying the solder paste to the PCB, a thin stainless steel or nickel stencil is placed over the PCB to allow the assembly system to apply the solder paste only to specific portions of the PCB where components will be placed in the assembled PCB (e.g., land pads).

[0027] In one example mentioned above, a mechanical fixture holds the PCB and solder stencil in place, and a dispenser places a predetermined amount of solder paste in a predetermined area. The dispenser spreads the paste across the stencil, evenly applying it to all uncovered areas. When the stencil is removed, the solder paste remains in the specific location on the PCB land pad.

[0028] The application of solder paste includes applying solder paste to the source, gate, and two drain pad regions of the 3-pin MOSFET land pad, thereby soldering the terminals of the MOSFET component to the corresponding pads. In some embodiments, a uniform (correlated average) amount of solder is applied to the source, gate, and two drain pads of the 3-pin MOSFET land pad. For example, a stencil used in applying the solder paste may have openings of uniform size for the source, gate, and two drain pads of the 3-pin MOSFET land pad. The uniform amount of solder across the pads balances surface tension across the corners of the MOSFET component, preventing the component from shifting and tilting toward the drain terminal during the reflow process.

[0029] In some embodiments, the stencil openings are configured with a 0.175 mm air gap, thus creating an air gap between the solder paste material of the source and gate pads, and between the first and second drain pads of the 3-pin MOSFET land pads.

[0030] In operation 215, a component placement process is performed. During the component placement process, one or more circuit components are placed on specific areas of the PCB. The placement of the components may be performed manually (e.g., by one or more humans) or with the assistance of a machine, such as a pick-and-place machine. A pick-and-place device is a robotic device that places surface-mount components on the PCB. In one example of a placement process, the pick-and-place device grasps the PCB with a vacuum grip and moves it to a pick-and-place station. The pick-and-place device (robot) positions and orients itself relative to the PCB at the pick-and-place station and places one or more surface-mount components on the PCB surface.

[0031] As part of the component placement process, a three-pin MOSFET component (e.g., MOSFET component 110) is placed on the land pads. More specifically, the source terminal of the MOSFET component is placed on the source pad, the gate terminal of the MOSFET component is placed on the gate pad, and the drain terminal is placed on the two drain pads.

[0032] A reflow process is performed in operation 220. The reflow process involves melting the solder in the solder paste and allowing it to cool to create a permanent solder joint between the circuit component and the PCB.

[0033] During the reflow process, the terminals of the MOSFET component 110 are soldered to the land pads 100. More specifically, the source terminal of the MOSFET component is soldered to the source pad, the gate terminal of the MOSFET component is soldered to the gate pad, and the drain terminal is soldered to first and second drain pads. The split pad design of the drain terminal (i.e., two drain pads), along with the uniformly sized and spaced source and gate pads, balances surface tension across the four corners of the MOSFET during reflow, thereby preventing the MOSFET component from shifting and tilting toward the drain terminal and causing failure due to a loose solder joint.

[0034] In an example of the reflow process performed in operation 220, a PCB, along with circuit components disposed on the PCB (including a 3-pin MOSFET component disposed on a 3-pin MOSFET land pad), is placed on a conveyor belt and moved through a reflow oven, which heats and liquefies the solder, ensuring connections are formed between the PCB and the circuit components via the land pads. The reflow oven includes a series of heaters that gradually heat the substrate to a temperature sufficient to melt the solder in the solder paste (e.g., 250 degrees Celsius or 480 degrees Fahrenheit). Once the solder is melted, the conveyor moves the PCB into a cooler, where the solder cools and re-solidifies in a controlled manner, thereby forming permanent solder joints connecting the circuit components to the PCB and resulting in an assembled PCB with electrical interconnections.

[0035] In various embodiments, the assembled PCB may wholly or partially implement a memory subsystem, a memory device for storing data from a host system, or a memory subsystem controller that can be operably coupled to one or more memory devices.

[0036] 3 is a flow diagram of an example method 300 for manufacturing an assembled PCB based on a PCB including at least one PCB land pad (e.g., land pad 100) for a 3-pin MOSFET component (having terminals only on the bottom side), according to some example embodiments of the present disclosure. Method 300 may be performed with the aid of processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed, at least in part, by a circuit design system (e.g., an electronic design automation (EDA) system). While shown in a particular sequence or order, the order of processes can be changed unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, various embodiments may omit one or more processes. Thus, not all processes are used in all embodiments. Other process flows are possible.

[0037] In operation 305, the circuit design data is configured to form (e.g., manufacture) a PCB that includes at least one PCB land pad for a surface-mounted 3-pin MOSFET component (hereinafter referred to as a "3-pin MOSFET land pad"). With reference to the 3-pin MOSFET land pad, the circuit design data defines four pads, of which the pad for the drain terminal of the MOSFET component is split into two. For example, the 3-pin MOSFET land pad includes a source pad, a gate pad, and two drain pads.

[0038] In some embodiments, the pads of the land pad are uniform in size. In some embodiments, the two drain pads are positioned symmetrically with the source and gate pads on the 3-pin MOSFET land pad. In some embodiments, the circuit design data defines a 0.15 mm gap separating the first drain pad and the second drain pad. Consistent with some of these embodiments, the circuit design data may also define a 0.15 mm gap between the source pad and the gate pad.

[0039] The circuit design data may be generated or configured by a circuit design system (e.g., an EDA system) that can assist in designing a PCB, designing a stencil, creating a pre-reflow (after solder printing and before reflow) and post-reflow inspection program, and creating a placement configuration for one or more circuit components on the PCB.

[0040] At operation 310, a PCB assembly process is performed using the circuit design data, resulting in an assembled PCB. The PCB assembly process may include any one or more of the operations of method 200 described above. As one example, the circuit design data may be used to configure or create a solder mask used in part to define the 3-pin MOSFET land pads. As another example, the circuit design data may be used to configure or create a stencil used in applying solder paste to ensure a uniform amount of solder is applied to the four pads of the 3-pin MOSFET land pads. As yet another example, the circuit design data may be used to direct or control a pick-and-place device to place a surface-mounted 3-pin MOSFET component on the 3-pin MOSFET land pads and / or to create an inspection recipe in a surface mount line to inspect the quality of the solder volume after printing and the quality of the solder joints after reflow.

[0041] 4 is a block diagram illustrating a memory subsystem 410 that may be implemented, at least in part, by an exemplary printed circuit board, in accordance with some embodiments of the present disclosure. The memory subsystem 410 may include media such as one or more volatile memory devices (e.g., memory device 440), one or more non-volatile memory devices (e.g., memory device 430), or a combination of the like.

[0042] The memory subsystem 410 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). An example of a memory module is a dual in-line memory module (DIMM), whose subclassifications include small outline DIMMs (SO-DIMMs), registered DIMMs (RDIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0043] The memory devices 430, 440 may include any combination of different types of non-volatile and / or volatile memory devices. The volatile memory devices (e.g., memory device 440) may be random access memories (RAMs), such as, but not limited to, dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0044] Some examples of nonvolatile memory devices (e.g., memory device 430) include write-in-place memories such as NAND flash memory and three-dimensional cross-point (3D cross-point) memory devices, which are cross-point arrays of nonvolatile memory cells. The cross-point array of nonvolatile memory, in conjunction with a stackable grid-like data access array, can perform bit-wise storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations that can program the nonvolatile memory cells without first erasing them. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0045] Each of the memory devices 430 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC), can store multiple bits per cell.

[0046] Although non-volatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells are described, the memory device 430 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selection memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT) MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0047] The memory subsystem controller 415 (or, for simplicity, the controller 415) can communicate with the memory device 430 to perform operations such as reading data, writing data, or erasing data in the memory device 430, and other such operations. The memory subsystem controller 415 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 415 can be a microcontroller, an application-specific logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0048] The memory subsystem controller 415 may include a processor (processing device) 417 configured to execute instructions stored in a local memory 419. In the illustrated example, the local memory 419 of the memory subsystem controller 415 includes embedded memory configured to store instructions that perform various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 410, including handling communications between the memory subsystem 410 and the host system.

[0049] In some embodiments, local memory 419 may include memory registers that store memory pointers, fetched data, etc. Local memory 419 may also include ROM for storing microcode. While the example memory subsystem 410 of FIG. 4 is shown as including a memory subsystem controller 415, in other embodiments of the present disclosure, memory subsystem 410 may not include a memory subsystem controller 415 and instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0050] Generally, memory subsystem controller 415 can receive commands or operations from a host system and translate the commands or operations into instructions or appropriate commands to achieve desired access to memory device 430 and / or memory device 440. Memory subsystem controller 415 can be responsible for other processes, such as wear leveling, garbage collection, error detection and error correction code (ECC), encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses), associated with memory device 430. Memory subsystem controller 415 can further include host interface circuitry for communicating with the host system via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory device 430 and / or memory device 440 and translate responses associated with memory device 430 and / or memory device 440 into information for the host system.

[0051] As shown, the memory subsystem controller 415 includes at least one 3-pin MOSFET component 110. As mentioned above, in some embodiments, the memory subsystem controller 415 can be implemented in whole or in part by a PCB that includes a four-pad land pad for the 3-pin MOSFET component 110. In one example, the 3-pin MOSFET component 110 of the memory subsystem controller 415 is connected (e.g., soldered) to an instance of a land pad 100 on the PCB that implements the memory subsystem controller 415 in whole or in part.

[0052] In some embodiments, memory device 430 includes a local media controller 435 that operates in conjunction with memory subsystem controller 415 to perform operations on one or more memory cells of memory device 430. Note that while FIG. 4 illustrates memory subsystem controller 415 as including at least one 3-pin MOSFET component 110, local media controller 435 may also include at least one 3-pin MOSFET component 110.

[0053] In view of the above disclosure, various examples are presented below. It should be noted that one or more features of the examples may be included in the disclosure of the present application, either alone or in combination.

[0054] Example 1. A printed circuit board (PCB) land pad for a metal oxide semiconductor field effect transistor (MOSFET) component, the PCB land pad including: a first pad for connecting a gate terminal of the MOSFET component to a PCB; a second pad for connecting a source terminal of the MOSFET component to the PCB; a corresponding third pad for connecting a drain terminal of the MOSFET component to the PCB; and a fourth pad for connecting the drain terminal of the MOSFET component to the PCB.

[0055] Example 2. The PCB land pad of Example 1, wherein the first pad, the second pad, the third pad, and the fourth pad are solder mask defined.

[0056] Example 3. The PCB land pad of any one of Examples 1 or 2, wherein the first pad and the second pad are symmetrical to the third pad and the fourth pad.

[0057] Example 4. The PCB land pad of any one of Examples 1 to 3, wherein a first void separates the third pad from the fourth pad, a second void separates the first pad from the second pad, and the first void and the second void are identical.

[0058] Example 5. The PCB land pad of any one of Examples 1 to 4, wherein the air gap is 0.15 mm.

[0059] Example 6. The PCB land pad of any one of Examples 1 to 5, wherein the MOSFET component is a three-pin surface mount component having terminals only on the bottom surface.

[0060] Example 7. The PCB land pad of any one of Examples 1 to 6, wherein each of the first pad, the second pad, the third pad, and the fourth pad comprises an exposed area of ​​copper metal on the PCB.

[0061] Example 8. An assembled printed circuit board (PCB) comprising: a PCB having land pads for a 3-pin metal oxide semiconductor field effect transistor (MOSFET) component, the land pads including a gate pad, a source pad, a first drain pad, and a second drain pad; and a 3-pin MOSFET component soldered to the land pads of the PCB, the MOSFET component having a gate terminal, a source terminal, and a drain terminal, the gate terminal soldered to the gate pad, the source terminal soldered to the source pad, and the drain terminal soldered to the first drain pad and the second drain pad.

[0062] Example 9. The assembled PCB of Example 8, wherein the land pads are solder mask defined.

[0063] Example 10. The assembled PCB of any one of Examples 8 or 9, wherein the gate pad and the source pad are symmetrical with the first drain pad and the second drain pad.

[0064] Example 11. The assembled PCB of any one of Examples 8-10, wherein an air gap separates the first drain pad from the second drain pad.

[0065] Example 12. The assembled PCB of any one of Examples 8-11, wherein a uniform amount of solder is applied to the gate pad, the source pad, the first drain pad, and the second drain pad.

[0066] Example 13. The assembled PCB of any one of Examples 8-12, wherein the MOSFET component is a three-pin surface mount component with terminals on the bottom side only.

[0067] Example 14. A method for manufacturing an assembled printed circuit board (PCB), the method including: applying a solder mask to a copper layer of a PCB, the solder mask defining land pads of a metal-oxide-semiconductor field-effect transistor (MOSFET) component, the land pads comprising a gate pad, a source pad, a first drain pad, and a second drain pad, the MOSFET component comprising a gate terminal, a source terminal, and a drain terminal; and applying a solder paste to the solder masked copper layer, the applying the solder paste defining the gate pad, the source pad, the first drain pad, and the second drain pad. placing the MOSFET component on the land pad, where placing the component on the land pad includes placing the drain terminal of the MOSFET component on the first drain pad and the second drain pad; and creating a permanent solder joint between the MOSFET component and the land pad, where creating the permanent solder joint includes melting the solder paste to solder the drain terminal to the first drain pad and the second drain pad.

[0068] Example 15. The method of example 14, further comprising configuring circuit design data for forming the PCB including the land pads for the MOSFET component.

[0069] Example 16. The method of any one of Examples 14 or 15, wherein one or more of applying the solder mask, spreading the solder paste, and placing the MOSFET components is based on the circuit design data.

[0070] Example 17. The method of any one of Examples 14-16, wherein the solder mask defines a 0.15 mm gap between the first drain pad and the second drain pad.

[0071] Example 18. The method of any one of Examples 14 to 17, wherein applying the solder paste to the gate pad, the source pad, the first drain pad, and the second drain pad includes applying a uniform amount of solder to the gate pad, the source pad, the first drain pad, and the second drain pad.

[0072] Example 19. The method of any one of Examples 14-18, wherein placing the MOSFET component on the land pad includes surface mounting the MOSFET component to the PCB.

[0073] Example 20. The method of any one of Examples 14-19, wherein the first drain pad and the second drain pad are of uniform size.

[0074] 5 illustrates an exemplary machine in the form of a computer system 500 within which a set of instructions may be executed to cause the machine to perform any one or more of the methods described herein. In some embodiments, the computer system 500 may be used to perform the operations of a controller. In alternative embodiments, the machine may be connected (e.g., networked) to other machines within a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0075] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing (serially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or sets) of instructions to perform any one or more of the methodologies described herein.

[0076] The exemplary computer system 500 includes a processing device 502, a main memory 504 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0077] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 to perform the operations and steps described herein. Computer system 500 may further include a network interface device 508 for communicating over network 520.

[0078] Data storage system 518 may include a machine-readable storage medium 524 (also known as a computer-readable medium) having stored thereon one or more sets of instructions 526, or software that embodies any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within main memory 504 and / or processing device 502 when executed by computer system 500, with main memory 504 and processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to memory subsystem 410 of FIG. 4.

[0079] In one embodiment, instructions 526 include instructions that implement functions corresponding to configuring PCB circuit design data as described herein (e.g., method 300 of FIG. 3 ). While machine-readable storage medium 524 is shown in the exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be interpreted to include a single medium or multiple media that store one or more sets of instructions. The term “machine-readable storage medium” should also be interpreted to include any medium capable of storing or encoding a set of instructions that are executable by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the preceding detailed descriptions are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] It should be recognized, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. This disclosure may refer to the operations and processes of a computer system, or similar electronic computing device, that manipulate and convert data represented as physical (electronic) quantities in the computer system's registers and memory into other data also represented as physical quantities in the computer system's memory or registers or such information storage system.

[0082] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may include a general-purpose computer that may be specially constructed for an intended purpose or that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, including, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structure of a variety of these systems may take the form set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, etc.

[0085] In the foregoing specification, embodiments of the present disclosure have been described with reference to certain exemplary embodiments thereof. It will be apparent that various changes can be made therein without departing from the broader scope of the embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A printed circuit board (PCB) land pad for a metal oxide semiconductor field effect transistor (MOSFET) component, comprising: a first pad for connecting a gate terminal of the MOSFET component to a PCB; a second pad for connecting a source terminal of the MOSFET component to the PCB; a third pad corresponding to connecting a drain terminal of the MOSFET component to the PCB; a fourth pad for connecting the drain terminal of the MOSFET component to the PCB.

2. The PCB land pad of claim 1 , wherein the first pad, the second pad, the third pad, and the fourth pad are solder mask defined.

3. The PCB land pad of claim 1 , wherein the first pad and the second pad are symmetrical to the third pad and the fourth pad.

4. a first gap separating the third pad from the fourth pad; a second gap separating the first pad from the second pad; The PCB land pad of claim 1 , wherein the first air gap and the second air gap are the same.

5. The PCB land pad of claim 4 , wherein the air gap is 0.15 mm.

6. 10. The PCB land pad of claim 1, wherein the MOSFET component is a three-pin surface mount component having terminals on the bottom side only.

7. The PCB land pad of claim 1 , wherein each of the first pad, the second pad, the third pad, and the fourth pad comprises an exposed area of ​​copper metal on a PCB.

8. 1. An assembled printed circuit board (PCB), comprising: a PCB having land pads for a three-pin metal oxide semiconductor field effect transistor (MOSFET) component, the land pads including a gate pad, a source pad, a first drain pad, and a second drain pad; a 3-pin MOSFET component soldered to the land pads of the PCB, the MOSFET component having a gate terminal, a source terminal, and a drain terminal, the gate terminal soldered to the gate pad, the source terminal soldered to the source pad, and the drain terminal soldered to the first drain pad and the second drain pad.

9. 9. The assembled PCB of claim 8, wherein said land pads are solder mask defined.

10. 9. The assembled PCB of claim 8, wherein the gate pad and the source pad are symmetrical with the first drain pad and the second drain pad.

11. 9. The assembled PCB of claim 8, wherein an air gap separates the first drain pad from the second drain pad.

12. 9. The assembled PCB of claim 8, wherein a uniform amount of solder is applied to the gate pad, the source pad, the first drain pad, and the second drain pad.

13. 9. The assembled PCB of claim 8, wherein the MOSFET component is a three-pin surface mount component having terminals on the bottom side only.

14. 1. A method for manufacturing an assembled printed circuit board (PCB), the method comprising: applying a solder mask to a copper layer of a PCB, the solder mask defining land pads of a metal oxide semiconductor field effect transistor (MOSFET) component, the land pads comprising a gate pad, a source pad, a first drain pad, and a second drain pad, the MOSFET component comprising a gate terminal, a source terminal, and a drain terminal; applying a solder paste to the solder masked copper layer, wherein applying the solder paste includes applying solder paste to the gate pad, the source pad, the first drain pad, and the second drain pad; placing the MOSFET component on the land pad, wherein placing the component on the land pad includes placing the drain terminal of the MOSFET component on the first drain pad and the second drain pad; and creating a permanent solder joint between the MOSFET component and the land pad, wherein creating the permanent solder joint comprises melting the solder paste to solder the drain terminal to the first drain pad and the second drain pad.

15. 15. The method of claim 14, further comprising configuring circuit design data for forming the PCB including the land pads for the MOSFET component.

16. 16. The method of claim 15, wherein one or more of applying the solder mask, spreading the solder paste, and placing the MOSFET components is based on the circuit design data.

17. 15. The method of claim 14, wherein the solder mask defines a gap of 0.15 mm between the first drain pad and the second drain pad.

18. 15. The method of claim 14, wherein applying the solder paste to the gate pad, the source pad, the first drain pad, and the second drain pad comprises applying a uniform amount of solder to the gate pad, the source pad, the first drain pad, and the second drain pad.

19. 15. The method of claim 14, wherein placing the MOSFET component on the land pad comprises surface mounting the MOSFET component to the PCB.

20. 15. The method of claim 14, wherein the first drain pad and the second drain pad are uniformly sized.

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