N / P Separate Strained Replacement Metal Gate (RMG) Post-Gate Cut for Performance Enhanced FINFETs

Abstract

A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate extending through the STI region. The FinFET further includes a second fin structure on the substrate extending through the STI region. The FinFET also includes a metal gate on the STI region, the first fin structure, and the second fin structure. The metal gate is comprised of a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. patent application Ser. No. 18 / 098,633, filed Jan. 18, 2023, entitled "N / P-INDEPENDENTLY STRAINED POST-REPLACEMENT METAL GATE (RMG) GATE CUT FOR PERFORMANCE ENHANCED FINFET," the disclosure of which is expressly incorporated by reference in its entirety.

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly to N / P independent strained replacement metal gate (RMG) post gate cut for performance enhanced fin-based field effect transistor (FinFET) technology. [Background technology]

[0003] As integrated circuit (IC) technology advances, device geometries are shrinking. Technological advances in IC materials and IC design have produced generations of ICs, with each generation having smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density has generally increased while feature sizes have decreased. This miniaturization process has provided benefits by increasing production efficiency and reducing associated costs. Such miniaturization has also increased the complexity of IC processing and fabrication. Moreover, achieving these advances requires similar advances in IC processing and fabrication.

[0004] In some IC designs, one advancement implemented as technology nodes shrink is the replacement of polysilicon gate electrodes with metal gate electrodes to improve device performance as design dimensions shrink. While existing methods for fabricating IC devices are generally adequate for their intended purposes, they are not completely satisfactory in all respects. For example, fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. Fin-based field effect transistors (FETs) are sometimes referred to as FinFETs.

[0005] Scaling of advanced logic complementary metal oxide semiconductor (CMOS) to FinFET technology has achieved performance-power-area (PPA) enhancements over previous process nodes. Unfortunately, conventional strain boosters are reaching their limitations, making further FinFET transistor mobility difficult at sub-7 nanometer (nm) process nodes. Therefore, new strain boosters are desired for continued performance improvement of FinFET devices. Summary of the Invention [Means for solving the problem]

[0006] A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate that extends through the STI region. The FinFET further includes a second fin structure on the substrate that extends through the STI region. The FinFET also includes a metal gate on the STI region, the first fin structure, and the second fin structure. The metal gate is comprised of a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

[0007] A method is described. The method includes replacing a dummy gate to form a metal gate over a shallow trench isolation (STI) region on a substrate and over a first fin structure and a second fin structure on the substrate. The method also includes applying a line cut to separate the metal gate to form a first sub-metal gate cut line and a second sub-metal gate cut line. The method further includes filling the first sub-metal gate cut line with a first stressor material. The method also includes filling the second sub-metal gate cut line with a second stressor material different from the first stressor material.

[0008] A method is described. The method includes replacing a dummy gate to form a metal gate over a shallow trench isolation (STI) region on a substrate and over a first fin structure and a second fin structure on the substrate. The method also includes applying a line cut to separate the metal gate to form a first sub-metal gate cut line and a second sub-metal gate cut line. The method further includes filling the first sub-metal gate cut line and the second sub-metal gate cut line with a first stressor material. The method also includes implanting ions into the first stressor material in the second sub-metal gate cut line to convert the first stressor material into a second stressor material different from the first stressor material.

[0009] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the following Detailed Description may be better understood. Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that this disclosure may readily be utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood by considering the following description in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended to define the limits of the present disclosure.

[0010] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0011] [Figure 1] 1 shows a perspective view of a semiconductor wafer. [Figure 2] 1 shows a cross section of a die. [Figure 3] 1 shows a cross-sectional view of a metal oxide semiconductor field effect transistor (MOSFET) device. [Figure 4] A vertical fin field effect transistor (FinFET) is shown. [Figure 5A] 1 is a schematic diagram illustrating an integrated circuit including fin field effect transistors (FinFETs) having independently strained N-type and P-type regions, according to some embodiments of the present disclosure. FIG. [Figure 5B] 1 is a schematic diagram illustrating an integrated circuit including fin field effect transistors (FinFETs) having independently strained N-type and P-type regions, according to some embodiments of the present disclosure. FIG. [Figure 6] 1 illustrates a layout diagram of a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 7] 1 is a flowchart illustrating a method of forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8A] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8B] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8C] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8D] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8E] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8F] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8G] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8H] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 8I] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some embodiments of the present disclosure. [Figure 9A] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9B] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9C] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9D] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9E] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9F] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 9G] 1A-1C are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some embodiments of the present disclosure. [Figure 10] FIG. 1 is a process flow diagram illustrating a method of fabricating a field effect transistor (FET) with independently strained N-type and P-type regions according to aspects of the present disclosure. [Figure 11] FIG. 1 is a process flow diagram illustrating a method of fabricating a field effect transistor (FET) with independently strained N-type and P-type regions according to aspects of the present disclosure. [Figure 12] FIG. 1 is a block diagram illustrating an exemplary wireless communication system in which an aspect of the present disclosure may be advantageously employed. [Figure 13] FIG. 1 is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of transistor structures according to one configuration. DETAILED DESCRIPTION OF THE INVENTION

[0012] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0013] As described herein, the use of the term "and / or" is intended to mean an "inclusive or," and the use of the term "or" is intended to mean an "exclusive or." As described herein, the term "exemplary" as used throughout this description means "serving as an example, instance, or illustration" and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used throughout this description means "connected electrically, mechanically, or otherwise, whether directly or indirectly through an intervening connection (e.g., a switch)," and is not necessarily limited to a physical connection. Furthermore, a connection may be such that objects are permanently connected or releasably connected. A connection may be through a switch. As described herein, the term "adjacent" as used throughout this description means "adjacent, in close proximity, next to, or in close proximity." As described herein, the term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0014] As integrated circuit (IC) technology advances, device geometries are shrinking. Technological advances in IC materials and IC design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, feature density has generally increased while feature sizes have decreased. This miniaturization process has provided benefits by increasing production efficiency and reducing associated costs. Such miniaturization has also increased the complexity of IC processing and fabrication. Achieving these advances requires similar advances in IC processing and fabrication.

[0015] Fin-based devices represent a significant advancement in IC technology over planar-based devices. Fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. A fin field-effect transistor (FinFET) is a fin-based metal-oxide-semiconductor field-effect transistor (MOSFET). Nanowire FETs also represent a significant advancement in IC technology. Gate-all-around (GAA) nanowire-based devices are another three-dimensional structure on the surface of a semiconductor substrate. Other fin-based devices include omega-gate devices and pi-gate devices. Fin-based field-effect transistors are sometimes referred to as FinFET devices.

[0016] In some IC designs, one advancement implemented as technology nodes shrink is the replacement of polysilicon gate electrodes with metal gate electrodes to improve device performance as design dimensions shrink. While existing methods for fabricating IC devices are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. For example, fin-based devices can be implemented using replacement metal gate (RMG) technology.

[0017] Advanced logic complementary metal-oxide semiconductor (CMOS) scaling for fin-based devices implemented with RMG technology has achieved performance-power-area (PPA) enhancements over previous process nodes. Unfortunately, conventional strain boosters are reaching their limitations, making further fin-based transistor mobility difficult at sub-7 nanometer (nm) process nodes. Therefore, novel strain boosters are desired for continued performance improvement of fin-based transistors.

[0018] Various aspects of the present disclosure are directed to independently strained N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) regions in a post-replacement metal gate (RMG) gate cut of a Fin-based device for performance enhancement in Fin-based field effect transistor (FinFET) technology. A process flow for fabricating FinFET devices with independently strained NMOS and PMOS regions can include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term "layer" includes films and should not be construed as indicating vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to the substrate of a diced or undiced wafer. Similarly, the terms "wafer" and "die" may be used interchangeably unless doing so destroys credibility.

[0019] According to aspects of the present disclosure, a fin field effect transistor (FinFET) having independently strained N-type and P-type regions is described. The FinFET includes a substrate having a shallow trench isolation (STI) region thereon. The FinFET also includes a first fin structure on the substrate extending through the STI region, and a second fin structure on the substrate extending through the STI region. The FinFET further includes a metal gate on the STI region, the first fin structure, and the second fin structure. In some aspects of the present disclosure, the metal gate is comprised of a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

[0020] 1 shows a perspective view of a semiconductor wafer that may be used to fabricate FinFETs with independently strained N-type and P-type regions according to embodiments of the present disclosure. Wafer 100 may be a semiconductor wafer or may be a substrate material having one or more layers of semiconductor material on its surface. If wafer 100 is a semiconductor material, it may be grown from a seed crystal using the Czochralski method, in which a seed crystal is immersed in a molten bath of semiconductor material and removed from the bath while being slowly rotated. The molten material crystallizes on the seed crystal in its crystalline orientation.

[0021] Wafer 100 may be a single material (e.g., silicon (Si), germanium (Ge)), or a composite material such as gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), a ternary material such as indium gallium arsenide (InGaAs), a quaternary material, or any material that can be a substrate material for other semiconductor materials. Many of these materials may be crystalline in nature, although polycrystalline or amorphous materials may also be used for wafer 100.

[0022] Wafer 100, or a layer coupled to wafer 100, may be provided with a material that makes wafer 100 more conductive. For example, without limitation, a silicon wafer may have phosphorus or boron added to wafer 100 to allow charge to flow within wafer 100. These additives, called dopants, provide additional charge carriers (either electrons or holes) within wafer 100, or portions of wafer 100. By selecting the areas where additional charge carriers are provided, what type of charge carriers are provided, and the amount (density) of additional charge carriers within wafer 100, different types of electronic devices may be formed within or on wafer 100.

[0023] Wafer 100 has an orientation 102 that indicates the crystalline orientation of wafer 100. Orientation 102 may be a flat edge of wafer 100, as shown in Figure 1, or may be a notch or other indicator to indicate the crystalline orientation of wafer 100. Orientation 102 may indicate Miller indices for planes of a crystal lattice within wafer 100.

[0024] Miller indices form a notation for the crystal planes in a crystal lattice. A lattice plane can be represented by three integers, h, k, and l, which are the Miller indices (hkl) for planes in the crystal. Each index represents a plane perpendicular to the (h, k, l) direction based on the reciprocal lattice vector. These integers are usually expressed in reduced form (e.g., their greatest common denominator should be 1). Miller index 100 represents a plane perpendicular to the h direction, index 010 represents a plane perpendicular to the k direction, and index 001 represents a plane perpendicular to l. For some crystals, negative numbers are used (represented as a bar above the index), and for some crystals, such as gallium nitride, four or more numbers may be employed to adequately describe different crystal planes.

[0025] Once wafer 100 has been processed as desired, wafer 100 is separated along dicing lines 104. Dicing lines 104 indicate where wafer 100 should be broken down or separated into individual pieces. Dicing lines 104 may define the outlines of the various integrated circuits being fabricated on wafer 100.

[0026] Once the dicing lines 104 are defined, the wafer 100 may be sawed or separated into individual pieces to form the dies 106. Each of the dies 106 may be an integrated circuit having multiple devices or may be a single electronic device. The physical size of the dies 106, which may also be referred to as chips or semiconductor chips, depends at least in part on the ability to separate the wafer 100 to a particular size as well as the number of individual devices the dies 106 are designed to contain.

[0027] Once the wafer 100 is separated into one or more die 106, the die 106 may be packaged in packaging to allow access to the devices and / or integrated circuits fabricated on the die 106. The packaging may include single in-line packaging, dual in-line packaging, motherboard packaging, flip chip packaging, indium dot / bump packaging, or other types of devices that provide access to the die 106. The die 106 may also be directly accessed through wire bonding, probes, or other connections without packaging the die 106 in a separate package.

[0028] 2 illustrates a cross-sectional view of die 106 of FIG. 1 that may be used to fabricate a FinFET with independently strained N-type and P-type regions according to aspects of the present disclosure. Within die 106 may be a substrate 200, which may be a semiconductor material and / or may serve as mechanical support for the electronic device. Substrate 200 may be a doped semiconductor substrate having either electron (designated N-channel) or hole (designated P-channel) charge carriers present throughout substrate 200. Subsequent doping of substrate 200 with charge carrier ions / atoms may change the charge transport capability of substrate 200.

[0029] Within substrate 200 (e.g., a semiconductor substrate) may be wells 202 and 204 of a field effect transistor (FET), or may be the fin structure of a fin-structure FET (FinFET). Wells 202 and / or 204 may also be other devices (e.g., resistors, capacitors, diodes, or other electronic devices) depending on the structure and other properties of wells 202 and / or 204 and the surrounding structure of substrate 200.

[0030] The semiconductor substrate may also have a well 206 and a well 208. The well 208 may be entirely within the well 206, which in some cases may form a bipolar junction transistor (BJT). The well 206 may also be used as an isolation well to isolate the well 208 from electric and / or magnetic fields within the die 106.

[0031] Layers (e.g., 210-214) may be added to the die 106. Layer 210 may be, for example, an oxide or insulating layer that may isolate wells (e.g., 202-208) from one another or from other devices on the die 106. In such cases, layer 210 may be silicon dioxide, a polymer, a dielectric, or another electrically insulating layer. Layer 210 may also be an interconnect layer, in which case it may include a conductive material such as copper, tungsten, aluminum, an alloy, or other conductive or metallic material.

[0032] Layer 212 may also be a dielectric layer or a conductive layer, depending on the desired device characteristics and / or the materials of the layers (e.g., 210 and 214). Layer 214 may be an encapsulating layer that may protect the layers (e.g., 210 and 212) as well as wells 202-208 and substrate 200 from external forces. For example, without limitation, layer 214 may be a layer that protects die 106 from mechanical damage, or layer 214 may be a layer of material that protects die 106 from electromagnetic or radiation damage.

[0033] The electronic devices designed on the die 106 may have many features or structural components. For example, the die 106 may be subjected to any number of methods for providing dopants in the substrate 200, wells 202-208, and, if desired, layers (e.g., 210-214). For example, but not limited to, the die 106 may be subjected to ion implantation, deposition of dopant atoms forced into the crystal lattice through a diffusion process, chemical vapor deposition, epitaxial growth, or other methods. Through selective growth, material selection, and removal of portions of the layers (e.g., 210-214), and through selective removal, material selection, and dopant concentrations of the substrate 200 and wells 202-208, many different structures and electronic devices may be formed within the scope of the present disclosure.

[0034] Additionally, the substrate 200, wells 202-208, and layers (e.g., 210-214) may be selectively removed or added through a variety of processes, including wet chemical etching, chemical mechanical planarization (CMP), plasma etching, photoresist masking, damascene processes, and other methods to create the structures and devices of the present disclosure.

[0035] FIG. 3 illustrates a cross-sectional view of a metal-oxide-semiconductor field-effect transistor (MOSFET) device 300. The MOSFET device 300 may have four input terminals. The four inputs are a source 302, a gate 304, a drain 306, and a body. The source 302 and the drain 306 may be fabricated as wells 202 and 204 in a substrate 308, or may be fabricated as areas above the substrate 308 or as part of other layers on the die 106. Such other structures may be fins or other structures that protrude from the surface of the substrate 308. Furthermore, the substrate 308 may be the substrate 200 on the die 106, but the substrate 308 may also be one or more of the layers (e.g., 210-214) coupled to the substrate 200.

[0036] MOSFET device 300 is a unipolar device because current is generated by only one type of charge carrier (e.g., either electrons or holes), depending on the type of MOSFET. MOSFET device 300 operates by controlling the amount of charge carriers in a channel 310 between a source 302 and a drain 306. A voltage Vsource 312 is applied to the source 302, a voltage Vgate 314 is applied to the gate 304, and a voltage Vdrain 316 is applied to the drain 306. A separate voltage Vsubstrate 318 may also be applied to the substrate 308, but the voltage Vsubstrate 318 may be coupled to one of the voltages Vsource 312, Vgate 314, or Vdrain 316.

[0037] To control the charge carriers in the channel 310, voltage Vgate 314 creates an electric field in the channel 310 as gate 304 accumulates charge. Charge opposite to the charge accumulating on gate 304 begins to accumulate in the channel 310. Gate dielectric 320 insulates the charge accumulating on gate 304 from source 302, drain 306, and channel 310. Gate 304 and channel 310, with gate dielectric 320 between them, form a capacitor, and as voltage Vgate 314 increases, charge carriers begin to accumulate on gate 304, which serves as one plate of the capacitor. This accumulation of charge on gate 304 attracts opposite charge carriers into the channel 310. Eventually, enough charge carriers accumulate in the channel 310 to provide a conductive path between source 302 and drain 306. This state is sometimes referred to as opening the channel of the FET.

[0038] By varying the voltages Vsource 312 and Vdrain 316 and their relationship to the voltage Vgate 314, the amount of voltage applied to the gate 304 that opens the channel 310 can be varied. For example, the voltage Vsource 312 is typically at a higher potential than the voltage Vdrain 316. Increasing the voltage difference between the voltages Vsource 312 and Vdrain 316 will change the amount of voltage Vgate 314 that is used to open the channel 310. Furthermore, a larger voltage difference will create a larger current through the channel 310 by changing the amount of electromotive force that moves charge carriers through the channel 310.

[0039] The material of the gate dielectric 320 may be silicon oxide, or may be a dielectric material or other material having a dielectric constant (k) different from that of silicon oxide. Furthermore, the gate dielectric 320 may be a combination of materials or layers of different materials. For example, the gate dielectric 320 may be aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or stacks and / or alloys of these materials. Other materials for the gate dielectric 320 may be used without departing from the scope of the present disclosure.

[0040] By varying the material for the gate dielectric 320 and the thickness of the gate dielectric 320 (e.g., the distance between the gate 304 and the channel 310), the amount of charge on the gate 304 to open the channel 310 can be varied. Also shown is symbol 322, which indicates the terminals of the MOSFET device 300. For an N-channel MOSFET (which uses electrons as charge carriers in the channel 310), an arrow pointing away from the gate 304 terminal is applied to the substrate 308 terminal in symbol 322. For a P-type MOSFET (which uses holes as charge carriers in the channel 310), an arrow pointing towards the gate 304 terminal is applied to the substrate 308 terminal in symbol 322.

[0041] In some MOSFET designs, a high-k material may be desired for the gate dielectric 320, and such designs may employ other conductive materials. For example, without limitation, a "high-k metal gate" design may employ a metal such as copper for the gate 304 terminal. Although referred to as a "metal," polycrystalline materials, alloys, or other conductive materials are contemplated as suitable materials for the gate 304, as described below.

[0042] Interconnect traces or interconnect layers are used to interconnect MOSFET device 300 or to interconnect other devices (e.g., semiconductors) within die 106. These interconnect traces may be within one or more layers (e.g., 210-214) or may be within other layers of die 106.

[0043] FIG. 4 illustrates a vertical fin field effect transistor (FinFET) 400 that operates in a manner similar to the MOSFET device 300 described with respect to FIG. 3 . However, the fin 410 in the FinFET 400 is grown on or bonded to the substrate 308 of FIG. 3 . The substrate 308 may be a semiconductor substrate or other similar support layer, composed of, for example, an oxide layer, a nitride layer, a metal oxide layer, or a silicon layer. The fin 410 includes a source 302 and a drain 306. A gate 304 is disposed on the fin 410 and the substrate 308 through a gate dielectric 320. In a FinFET structure, the physical size of the FinFET 400 may be smaller than the MOSFET device 300 structure shown in FIG. 3 . This reduction in physical size allows for more devices per unit area on the die 106.

[0044] FinFET 400 can be fabricated through processes including front-end (FEOL), middle-of-line (MOL), and back-end (BEOL). The MOL process includes the formation of gate and terminal contacts. MOL layer trenches contact the source and drain regions of FinFET 400, referred to as CA contacts.

[0045] Fin-based devices, such as the FinFET 400, represent a significant advancement in integrated circuit (IC) technology over planar-based devices. Fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. A FinFET transistor is a fin-based metal-oxide-semiconductor field-effect transistor (MOSFET). Nanowire FETs also represent a significant advancement in IC technology. A gate-all-around (GAA) nanowire-based device is another three-dimensional structure on the surface of a semiconductor substrate. Other fin-based devices include omega-gate devices and pi-gate devices. Fin-based field-effect transistors are sometimes referred to as FinFET devices.

[0046] In some IC designs, one advancement implemented as technology nodes shrink is the replacement of polysilicon gate electrodes with metal gate electrodes to improve device performance as design dimensions shrink. While existing methods for fabricating IC devices are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. For example, fin-based devices can be implemented using replacement metal gate (RMG) technology.

[0047] Advanced logic complementary metal-oxide semiconductor (CMOS) scaling for fin-based devices implemented with RMG technology has achieved performance-power-area (PPA) enhancements over previous process nodes. Unfortunately, conventional strain boosters are reaching their limitations, making further fin-based transistor mobility difficult at sub-7 nanometer (nm) process nodes. Therefore, novel strain boosters are desired for continued performance improvement of fin-based transistors.

[0048] [Table 1]

[0049] As an example, Table I lists preferred strain types according to the X, Y, and Z directions as shown in FIG. 4. In the X direction (e.g., length direction from source 302 to drain 306), tensile (T) strain is preferred for NMOS electrons, and compressive (C) strain is preferred for PMOS holes. In the Y direction (e.g., width direction), tensile (T) strain is preferred for both NMOS electrons and PMOS holes. In the Z direction (e.g., body to gate 304), compressive (C) strain is preferred for NMOS electrons, and tensile (T) strain is preferred for PMOS holes. According to aspects of the present disclosure, a FinFET having independently strained N-type and P-type regions formed during a gate cut process after a replacement metal gate (RMG), for example, as shown in FIGS. 5A and 5B, is described.

[0050] 5A and 5B are schematic diagrams illustrating an integrated circuit including a fin field effect transistor (FinFET) 500 with independently strained N-type and P-type regions according to some embodiments of the present disclosure. In this configuration, the FinFET 500 includes a substrate 502 having a shallow trench isolation (STI) region 504 thereon. In some embodiments of the present disclosure, the FinFET 500 includes a first fin structure 510 (510-1, 510-2) on the substrate 502 that extends through the STI region 504, and a second fin structure 520 (520-1, 520-2) on the substrate 502 that extends through the STI region 504.

[0051] In this example, the first fin structures 510 (510-1, 510-2) correspond to N-type (e.g., N-type metal oxide semiconductor (NMOS)) regions of the substrate 502. Similarly, the second fin structures 520 (520-1, 520-2) correspond to P-type (e.g., P-type metal oxide semiconductor (PMOS)) regions of the substrate 502. In some embodiments of the present disclosure, the NMOS channel of the substrate 502 may be composed of silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), graphene, molybdenum disulfide (MoS), and / or phosphorus. In these aspects of the disclosure, the PMOS channel of the substrate 502 may be composed of silicon (Si), germanium (Ge), silicon germanium (SiGe), indium antimonide (InSb), graphene, molybdenum disulfide (MoS), and / or phosphorus.

[0052] 5A , the FinFET 500 includes a metal gate 530 over the STI region 504, the first fin structures 510 (510-1, 510-2), and the second fin structures 520 (520-1, 520-2). In some embodiments of the present disclosure, the metal gate 530 is configured with a first sub-metal gate cut line 540 filled with a first stressor material and a second sub-metal gate cut line 550 filled with a second stressor material different from the first stressor material. In this example, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 extend through the metal gate 530, through the STI region 504, and into the substrate 502.

[0053] 5A, a first sub-metal gate cut line 540 is coupled between a first N-type metal oxide semiconductor (NMOS) region (e.g., 510-1) and a second NMOS region (e.g., 510-2). Similarly, a second sub-metal gate cut line 550 is coupled between a first P-type metal oxide semiconductor (PMOS) region (e.g., 520-1) and a second PMOS region (e.g., 520-2). In some embodiments of the present disclosure, the metal gate 530 is made of tantalum (Ta), tantalum nitride (TaN), tantalum titanium (TaTi), titanium (Ti), titanium aluminide (TiAl), titanium aluminide carbon (TiAl:C), tungsten nitride (W:C), platinum (Pt), and / or gold (Au).

[0054] In some embodiments of the present disclosure, the first stressor material and the second stressor material are selected according to the type of region (e.g., NMOS / PMOS) and orientation (e.g., X / Y / Z) using Table I. In some embodiments of the present disclosure, filler stressor materials having tensile and / or compressive strain for gate cut trenches include, but are not limited to, silicon dioxide (SiO), silicon dioxide fluorine (SiO:F), silicon dioxide nitrogen (SiO:N), silicon dioxide germanium (SiO:Ge), silicon oxynitride (SiON), silicon oxynitride fluorine (SiON:F), silicon oxynitride germanium (SiON:Ge), silicon nitride (SiN), silicon germanium nitride (SiN:Ge), hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO), germanium oxide (GeO), and / or silicon germanium oxide (SiGeO). An interlayer dielectric (ILD) layer 506 is provided on the metal gate 530 to support signal tracks 508 and power rails (e.g., VDD and VSS) that are coupled to the metal gate 530 through gate vias 532.

[0055] Figure 5B shows a FinFET 560 having a similar configuration to, and described using similar reference numerals as, FinFET 500 of Figure 5A. FinFET 560 includes a substrate 502 having an STI region 504 thereon, and first fin structures 510 (510-1, 510-2) on an N-type region of substrate 502 and extending through STI region 504. FinFET 560 also includes second fin structures 520 (520-1, 520-2) on a P-type region of substrate 502 and extending through STI region 504.

[0056] The FinFET 560 includes a metal gate 530 over the STI region 504, over the first fin structures 510 (510-1, 510-2), and over the second fin structures 520 (520-1, 520-2). In some embodiments of the present disclosure, the metal gate 530 is configured with a first sub-metal gate cut line 570 filled with a first stressor material and a second sub-metal gate cut line 580 filled with a second stressor material different from the first stressor material. In this embodiment, the first sub-metal gate cut line 570 and the second sub-metal gate cut line 580 extend through the metal gate 530 and into the STI region 504. In these embodiments of the present disclosure, the first sub-metal gate cut line 570 and the second sub-metal gate cut line 580 do not extend through the STI region 504 into the substrate 502. FinFET 560 also includes an ILD layer 506 over metal gate 530 to support signal tracks 508 coupled to metal gate 530 through gate vias 532, as well as power supply VDD and VSS power rails.

[0057] 6 illustrates a layout diagram of a FinFET 600 having independently strained N-type and P-type regions according to some embodiments of the present disclosure. Figure 6 illustrates FinFET 600 having a similar configuration to, and described using similar reference numerals as, FinFET 500 of Figure 5A and FinFET 560 of Figure 5B. In particular, FinFET 500 illustrated in Figure 5A and FinFET 560 illustrated in Figure 5B may be cross-sectional views of FinFET 600 taken along section line AA'.

[0058] 6 , a FinFET 600 includes a substrate 502 having a first fin structure 510-1 over an NMOS region. The FinFET 600 also includes a second fin structure 520-1 over a PMOS region of the FinFET 600. The FinFET 600 includes multiple metal gates 530 (530-1, 530-2, 530-3) over the first fin structure 510-1 and the second fin structure 520-1. In some embodiments of the present disclosure, the multiple metal gates 530 (530-1, 530-2, 530-3) are configured with first sub-metal gate cut lines 540 / 570 filled with a first stressor material and second sub-metal gate cut lines 550 / 580 filled with a second stressor material different from the first stressor material. The first sub-metal gate cut line 540 / 570 and the second sub-metal gate cut line 550 / 580 extend through the multiple metal gates 530 (530-1, 530-2, 530-3). The gate via 532, the signal track 508, and the power supply VDD and VSS power rails are also shown.

[0059] 7 is a flowchart illustrating a method for forming a fin field effect transistor (FinFET) with independently strained N-type and P-type regions according to some embodiments of the present disclosure. Method 700 begins at block 702, where fin / diffusion formation is performed. For example, as shown in FIG. 5A , the fin / diffusion formation process produces a first fin structure 510 (510-1, 510-2) corresponding to an NMOS region of substrate 502. Similarly, the fin / diffusion formation process produces a second fin structure 520 (520-1, 520-2) corresponding to a PMOS region of substrate 502.

[0060] At block 704, a dummy poly formation process is performed to form a dummy gate. At block 706, a source / drain (S / D) epitaxy process is performed to form source and drain regions. For example, as shown in FIG. 4, an S / D epitaxy process is performed to form the source 302 and drain 306 of the FinFET 400. At block 708, a replacement metal gate (RMG) process is performed to replace the dummy poly gate with a metal gate. For example, as shown in FIG. 5A, the FinFET 500 further includes a metal gate 530 over the STI region 504, over the first fin structure 510 (510-1, 510-2), and over the second fin structure 520 (520-1, 520-2).

[0061] In block 710, a gate cut process is performed following the replacement metal gate (RMG) process of block 708. In block 712, contacts are formed. For example, as shown in FIG. 5A, a metal gate 530 is composed of a first sub-metal gate cut line 540 filled with a first stressor material and a second sub-metal gate cut line 550 filled with a second stressor material different from the first stressor material. In this example, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 extend through the metal gate 530, through the STI region 504, and into the substrate 502. In some embodiments of the present disclosure, strain is incorporated in the deposition of a gate cut (GC) dielectric material after RMG. The strain can vary based on whether the region is an NMOS region or a PMOS region, for example, as shown in FIGS. 8A-8I. In some embodiments of the present disclosure, strain is incorporated with ion implantation into the GC-filled dielectric material after RMG, as shown, for example, in Figures 9A-9G.

[0062] 8A-8I are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) with independently strained N-type and P-type regions according to some embodiments of the present disclosure.

[0063] 8A illustrates a first step 800 in a process for forming a FinFET with independently strained N-type and P-type regions according to some embodiments of the present disclosure, showing the initial stage of the FinFET 500 of FIG. 5A after a replacement metal gate (RMG) process to form a metal gate 530 on the first fin structure 510 (510-1, 510-2) and the second fin structure 520 (520-1, 520-2).

[0064] 8B illustrates the next step 810 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In step 810, a hardmask (HM) 812 is deposited on the surface of the metal gate 530. Once the hardmask 812 is formed, a photoresist (PR) 814 is deposited on the hardmask 812. Following the formation of the photoresist 814, the photoresist 814 and the hardmask 812 are patterned to form an opening 816 in preparation for performing a first gate cut in the PMOS region of the substrate 502.

[0065] 8C illustrates a next step 820 in the process of forming a FinFET with independently strained N-type and P-type regions according to some embodiments of the present disclosure. In step 820, a gate cut trench etch is performed according to the opening 816 in the hard mask 812 and the photoresist 814. A second sub-metal gate cut line 550 is formed by etching through the metal gate 530, the STI region 504, and into the PMOS region of the substrate 502. The photoresist 814 is then stripped to expose the surface of the hard mask 812.

[0066] 8D illustrates a next step 830 in a process for forming a FinFET with independently strained N-type and P-type regions according to some embodiments of the present disclosure. In step 830, the second sub-metal gate cut line 550 is filled with a second stressor material 832, which is also deposited on the exposed surface of the hard mask 812. For example, as shown in FIGS. 5A and 8D , the second sub-metal gate cut line 550 is filled with the second stressor material 832 (shown in FIG. 8D ), such as a GC-filled P-type dielectric material after RMG, through the metal gate 530, the STI region 504, in the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0067] 8E illustrates a next step 840 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In step 840, the second stressor material 832 and hard mask 812 are stripped from the metal gate 530 using, for example, a chemical-mechanical-polishing (CMP) process. The CMP process of step 840 to strip the second stressor material 832 and hard mask 812 from the metal gate 530 completes the formation of a second sub-metal gate cut line 550 filled with the second stressor material 832.

[0068] 8F illustrates a next step 850 in the process of forming a FinFET with independently strained N-type and P-type regions according to some embodiments of the present disclosure. In step 850, a hard mask 812 is deposited on the surface of metal gate 530. Once hard mask 812 is formed, photoresist 814 is deposited on hard mask 812. Following the formation of photoresist 814, photoresist 814 and hard mask 812 are patterned to form opening 852 in preparation for performing a second gate cut in the NMOS region of substrate 502.

[0069] 8G illustrates a next step 860 in the process of forming a FinFET with independently strained N-type and P-type regions according to some embodiments of the present disclosure. In step 860, a gate cut trench etch is performed according to the openings 852 in the hard mask 812 and the photoresist 814. A first sub-metal gate cut line 540 is formed by etching through the metal gate 530, the STI region 504, and into the NMOS region of the substrate 502. The photoresist 814 is then stripped to expose the surface of the hard mask 812.

[0070] 8H illustrates a next step 870 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In step 870, the first sub-metal gate cut line 540 is filled with a first stressor material 872, which is also deposited on the exposed surface of the hard mask 812. For example, as shown in FIGS. 5A and 8H, the first sub-metal gate cut line 540 is filled with the first stressor material 872 (shown in FIG. 8H), such as a GC-filled N-type dielectric material after RMG. In this example, the first stressor material 872 is deposited within the first sub-metal gate cut line 540, through the metal gate 530, the STI region 504, into the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0071] 8I illustrates a next step 880 in a process for forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In step 880, the first stressor material 872 and hard mask 812 are stripped from the metal gate 530 using, for example, a second chemical mechanical polishing (CMP) process. The second CMP process of step 840 to strip the first stressor material 872 and hard mask 812 from the metal gate 530 completes the formation of the first sub-metal gate cut line 540 filled with the first stressor material 872. In this example, the first stressor material 872 exhibits a compressive strain direction, and the second stressor material 832 exhibits a tensile strain direction.

[0072] In the example provided in FIGS. 8A-8I , the first sub-metal gate cut line 540 is filled with a first stressor material 872, and the second sub-metal gate cut line 550 is filled with a second stressor material 832. In some embodiments of the present disclosure, the second stressor material 832 is comprised of a GC-filled P-type dielectric material after RMG that has a compressive stress to provide tensile strain in the PMOS region of the FinFET 500 of FIG. 5 . In these embodiments of the present disclosure, the first stressor material 872 is comprised of a GC-filled N-type dielectric material after RMG that has a tensile stress to provide compressive strain in the NMOS region of the FinFET 500. The process illustrated in FIGS. 8A-8I requires two CMP processes to complete the formation of the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550. Unfortunately, the application of two CMP processes introduces potential concerns about the topography of the metal gate 530 due to the different post-RMG GC-filled dielectric materials used for the first stressor material 872 and the second stressor material 832.

[0073] 9A-9G are schematic diagrams illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation according to some embodiments of the present disclosure. The process of FIG. 9A-9G is similar to the process shown in FIG. 8A-8I and will be described using similar reference numerals.

[0074] 9A illustrates a first step 900 in a process for forming a FinFET having independently strained N-type and P-type regions using ion implantation according to some embodiments of the present disclosure, showing an initial stage of the FinFET 500 of FIG. 5A after a replacement metal gate (RMG) process to form a metal gate 530 on the first fin structure 510 (510-1, 510-2) and the second fin structure 520 (520-1, 520-2).

[0075] 9B illustrates a next step 910 in a process of forming a FinFET with independently strained N-type and P-type regions using ion implantation according to some aspects of the present disclosure. In step 910, a hard mask (HM) 812 is deposited on the surface of the metal gate 530. Once the hard mask 812 is formed, a photoresist (PR) 814 is deposited on the hard mask 812. Following the formation of the photoresist 814, the photoresist 814 and the hard mask 812 are patterned to form a first opening 912 and a second opening 914. The first opening 912 and the second opening 914 are provided in preparation for etching a first sub-metal gate cut line 540 in the NMOS region and a second sub-metal gate cut line 550 in the PMOS region of the substrate 502, as shown in FIG. 9C.

[0076] 9C illustrates a next step 920 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In step 920, a gate cut trench etch is performed according to the first opening 912 and the second opening 914 in the hard mask 812 and the photoresist 814. A first sub-metal gate cut line 540 is formed by etching through the first opening 912, the metal gate 530, the STI region 504, and into the NMOS region of the substrate 502. A second sub-metal gate cut line 550 is formed by etching through the metal gate 530, the STI region 504, and into the PMOS region of the substrate 502. The photoresist 814 is then stripped to expose the surface of the hard mask 812.

[0077] 9D illustrates a next step 930 in a process of forming a FinFET with independently strained N-type and P-type regions through ion implantation according to some embodiments of the present disclosure. In step 930, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are filled with a second stressor material 832 through the first opening 912 and the second opening 914. The second stressor material 832 is also deposited on the exposed surface of the hard mask 812. For example, as shown in FIGS. 5A and 9D , the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are filled with the second stressor material 832 (e.g., a GC-filled P-type dielectric material after RMG) (shown in FIG. 9D ), which is also deposited on the surface of the hard mask 812.

[0078] 9E illustrates a next step 940 in a process for forming a FinFET with independently strained N-type and P-type regions through ion implantation according to some aspects of the present disclosure. In step 940, the second stressor material 832 and the hard mask 812 are stripped from the metal gate 530 using, for example, a chemical mechanical polishing (CMP) process. The CMP process of step 940 to strip the second stressor material 832 and the hard mask 812 from the metal gate 530 completes the formation of the second sub-metal gate cut line 550 filled with the second stressor material 832; however, the formation of the first sub-metal gate cut line 540 is incomplete due to the presence of the second stressor material 832.

[0079] 9F illustrates a next step 950 in the process of forming a FinFET with independently strained N-type and P-type regions through ion implantation according to some embodiments of the present disclosure. In step 950, photoresist 952 is deposited on the surface of metal gate 530. Following the formation of photoresist 952, photoresist 952 is patterned to form openings 954. Once openings 954 are formed, the first stressor material 872 within the first sub-metal gate cut lines 540 is implanted with a species having a larger lattice constant (e.g., germanium (Ge), argon (Ar)). An ion implantation 956 is performed to convert the second stressor material 832 to the first stressor material 872 within the NMOS region of substrate 502. In some embodiments of the present disclosure, the ion implant species include, but are not limited to, fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

[0080] 9G illustrates a next step 960 in a process for forming a FinFET with independently strained N-type and P-type regions through ion implantation according to some embodiments of the present disclosure. In step 960, photoresist 952 is stripped from metal gate 530, and a low-temperature anneal is performed. The low-temperature anneal after stripping photoresist 952 from metal gate 530 completes the formation of first sub-metal gate cut line 540 filled with first stressor material 872. The process illustrated in FIGS. 9A-9G utilizes a single chemical-mechanical polishing (CMP) process to avoid potential concerns about the topography of metal gate 530 by using the same second stressor material 832 during the CMP process illustrated in step 940 of FIG. 9E.

[0081] 9A-9G, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are both filled with a second stressor material 832. The process illustrated in FIGS. 9A-9G requires one CMP process to complete the planarization of the metal gate 530. Fortunately, the application of a single CMP process avoids potential concerns regarding the topography of the metal gate 530 by using the same post-RMG GC fill dielectric material (e.g., second stressor material 832).

[0082] 10 is a process flow diagram illustrating a method 1000 of fabricating a field effect transistor (FET) with independently strained N-type and P-type regions according to aspects of the present disclosure. The method 1000 may begin at block 1002, in which a dummy gate is replaced to form a metal gate over shallow trench isolation (STI) regions on a substrate and over first and second fin structures on the substrate. For example, as shown in block 708 of FIG. 7, a replacement metal gate (RMG) process is performed to replace the dummy poly gate with a metal gate. Furthermore, as shown in FIG. 5A, the FinFET 500 includes a metal gate 530 over the STI regions 504, the first fin structure 510 (510-1, 510-2), and the second fin structure 520 (520-1, 520-2).

[0083] In block 1004, a line cut is applied to separate the metal gate to form a first sub-metal gate cut line and a second sub-metal gate cut line. For example, as shown in block 710 of FIG. 7, a gate cut process is performed following the RMG process of block 708. Further, as shown in FIG. 5A, the metal gate 530 is composed of a first sub-metal gate cut line 540 and a second sub-metal gate cut line 550. In this embodiment, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 extend through the metal gate 530, through the STI region 504, and into the substrate 502. The metal gate 530 may be a high-k metal gate (HKMG).

[0084] In block 1006, the second sub-metal gate cut line 550 is filled with a second stressor material. For example, in step 830 of FIG. 8D , the second sub-metal gate cut line 550 is filled with a second stressor material 832, which is also deposited on the exposed surface of the hard mask 812. Further, as shown in FIGS. 5A and 8D , the second sub-metal gate cut line 550 is filled with the second stressor material 832 (shown in FIG. 8D ), such as a GC-filled P-type dielectric material after RMG, through the metal gate 530, the STI region 504, in the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0085] In block 1008, the first sub-metal gate cut line 540 is filled with a first stressor material. For example, as shown in FIG. 8H, the first sub-metal gate cut line 540 is filled with a first stressor material 872, which is also deposited on the exposed surface of the hard mask 812. Furthermore, as shown in FIGS. 5A and 8D, the first sub-metal gate cut line 540 is filled with a first stressor material 872, such as a GC-filled N-type dielectric material after RMG. In this example, the first stressor material 872 is deposited within the first sub-metal gate cut line 540, through the metal gate 530, the STI region 504, into the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0086] 11 is a process flow diagram illustrating a method 1100 of fabricating a field effect transistor (FET) with independently strained N-type and P-type regions according to aspects of the present disclosure. Blocks 1102-1106 of method 1100 correspond to blocks 1002-1006 of method 1000 of FIG. 10 and will not be further described here. In block 1108, the first sub-metal gate cut line is filled with a second stressor material. For example, as shown in FIG. 9D , the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are filled with the second stressor material 832 through the first opening 912 and the second opening 914. Furthermore, as shown in FIGS. 5A and 9D, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are filled with a second stressor material 832 (e.g., a GC-filled P-type dielectric material after RMG) (shown in FIG. 9D), which is also deposited on the surface of the hard mask 812.

[0087] In block 1110, ions are implanted into the second stressor material in the first sub-metal gate cut line to convert the second stressor material into the first stressor material. For example, as shown in FIG. 9F, a species having a larger lattice constant (e.g., germanium (Ge), argon (Ar)) is implanted into the second stressor material 832 in the first sub-metal gate cut line 540. In this example, ion implantation 956 is performed to convert the second stressor material 832 into the first stressor material 872 in the NMOS region of the substrate 502. As shown in FIG. 9G, low-temperature annealing is performed. The low-temperature annealing, after stripping the photoresist 952 from the metal gate 530, completes the formation of the first sub-metal gate cut line 540 filled with the first stressor material 872.

[0088] FIG. 12 is a block diagram illustrating an exemplary wireless communication system 1200 that may advantageously employ an aspect of the present disclosure. For illustrative purposes, FIG. 12 shows three remote units 1220, 1230, and 1250 and two base stations 1240. It will be appreciated that the wireless communication system may have more remote units and base stations. The remote units 1220, 1230, and 1250 include IC devices 1225A, 1225C, and 1225B that include the disclosed FinFETs. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed FinFETs. FIG. 12 shows forward link signals 1280 from the base station 1240 to the remote units 1220, 1230, and 1250, and reverse link signals 1290 from the remote units 1220, 1230, and 1250 to the base station 1240.

[0089] In Figure 12, remote unit 1220 is shown as a mobile phone, remote unit 1230 is shown as a portable computer, and remote unit 1250 is shown as a fixed-location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, portable data units such as handheld personal communication systems (PCS) units, personal digital assistants, or other fixed-location data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading equipment, or other devices that store or retrieve data or computer instructions, or any combination thereof. While Figure 12 illustrates remote units according to aspects of the present disclosure, the present disclosure is not limited to these illustrated example units. Aspects of the present disclosure may be suitably employed in many devices, including the disclosed FinFETs.

[0090] FIG. 13 is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of IC structures such as the FinFETs disclosed above. The design workstation 1300 includes a hard disk 1301 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 1300 also includes a display 1302 to facilitate the design of a circuit 1310 or a fin structure 1312, including a FinFET. A storage medium 1304 is provided for tangibly storing the design of the circuit 1310 or fin structure 1312. The design of the circuit 1310 or fin structure 1312 may be stored on the storage medium 1304 in a file format such as GDSII or GERBER. The storage medium 1304 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Additionally, design workstation 1300 includes a drive device 1303 for accepting input from or writing output to storage medium 1304 .

[0091] The data recorded on storage medium 1304 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous write tools such as electron beam lithography. The data may also include logic verification data, such as timing diagrams or net circuits associated with logic simulations. Providing data on storage medium 1304 facilitates the design of circuit 1310 or fin structure 1312 by reducing the number of processes for designing a semiconductor wafer.

[0092] For a firmware and / or software implementation, the methodologies may be realized with modules (e.g., procedures, functions, and so on) that perform the functions described herein. Implementing the methodologies described herein may involve the use of machine-readable media tangibly embodying instructions. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" may refer to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and should not be limited to a specific type of memory, or a specific number of memories, or to a specific type of medium on which the memory is stored.

[0093] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0094] In addition to storage on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium contained within a communications device. For example, a communications device may include a transceiver having signals indicative of instructions and data configured to cause one or more processors to implement the functions outlined in the claims.

[0095] The following numbered clauses describe example implementations. 1. A fin field effect transistor (FinFET), comprising: A substrate; a shallow trench isolation (STI) region on a substrate; a first fin structure on the substrate extending through the STI region; a second fin structure on the substrate that extends through the STI region; a metal gate on the STI region, on the first fin structure, and on the second fin structure, the metal gate including a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material. 2. The FinFET of clause 1, wherein the first stressor material comprises a compressive strain and the second stressor material comprises a tensile strain. 3. The FinFET of clause 2, wherein the first fin structure includes a P-type metal oxide semiconductor (PMOS) region and the second fin structure includes an N-type metal oxide semiconductor (NMOS) region. 4. The FinFET of any of clauses 1-3, wherein the first sub-metal gate cut line and the second sub-metal gate cut line extend through the metal gate and into the STI region. 5. The FinFET of any of clauses 1 to 3, wherein the first sub-metal gate cut line and the second sub-metal gate cut line extend through the metal gate, through the STI region, and into the substrate. 6. The FinFET of any of clauses 1 to 5, wherein the metal gate comprises a high-k metal gate. 7. The first fin structure is a first P-type metal oxide semiconductor (PMOS) region; and a second PMOS region, wherein the first sub-metal gate cut line is coupled between the first PMOS region and the second PMOS region. 8. The second fin structure is a first N-type metal oxide semiconductor (NMOS) region; a second NMOS region, wherein a second sub-metal gate cut line is coupled between the first NMOS region and the second NMOS region. 9. The FinFET of any of clauses 1-8, wherein the first stressor material and the second stressor material comprise silicon dioxide (SiO), silicon dioxide fluorine (SiO:F), silicon dioxide nitrogen (SiO:N), silicon dioxide germanium (SiO:Ge), silicon oxynitride (SiON), silicon oxynitride fluorine (SiON:F), silicon oxynitride germanium (SiON:Ge), silicon nitride (SiN), silicon germanium nitride (SiN:Ge), hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO), germanium oxide (GeOx), and / or silicon germanium oxide (SiGeOx). 10. The FinFET of any of clauses 1-8, wherein the second stressor material comprises an ion implant species comprising fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar). 11. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on the substrate and on the first fin structure and the second fin structure on the substrate; applying a line cut to separate the metal gates to form a first sub-metal gate cut line and a second sub-metal gate cut line; filling the first sub-metal gate cut line with a first stressor material; filling the second sub-metal gate cut line with a second stressor material different from the first stressor material. 12. Applying line cuts depositing a hard mask on the surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and hard mask to form an opening; Etching through the opening in the photoresist and the hard mask to form a first sub-metal gate cut line in a P-type metal oxide semiconductor (PMOS) region of the substrate, the first sub-metal gate cut line passing through the metal gate and STI region; 12. The method of clause 11, comprising stripping the photoresist to expose a surface of the hard mask. 13. Filling the first sub-metal gate cut line with a first stressor material; depositing a first stressor material within the first sub-metal gate cut line; depositing a first stressor material on the exposed surface of the hard mask; and polishing the first stressor material and the hard mask on the surface of the metal gate. 14. Applying line cuts depositing a hard mask over a surface of the metal gate and over a portion of the first stressor material; depositing a photoresist (PR) on the hard mask; patterning the photoresist and hard mask to form an opening; Etching through the opening in the photoresist and hard mask to form a second sub-metal gate cut line in an N-type metal oxide semiconductor (NMOS) region of the substrate, the second sub-metal gate cut line passing through the metal gate and STI region; 14. The method of any of clauses 11-13, comprising stripping the photoresist to expose a surface of the hard mask. 15. Filling the second sub-metal gate cut line with a second stressor material; depositing a second stressor material within the second sub-metal gate cut line; depositing a second stressor material on the exposed surface of the hard mask; and polishing the second stressor material and the hard mask on the surface of the metal gate. 16. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on the substrate and on the first fin structure and the second fin structure on the substrate; applying a line cut to separate the metal gates to form a first sub-metal gate cut line and a second sub-metal gate cut line; filling the first sub-metal gate cut line and the second sub-metal gate cut line with a first stressor material; implanting ions into the first stressor material in the second sub-metal gate cut line to transform the first stressor material into a second stressor material different from the first stressor material. 17. Applying line cuts depositing a hard mask on the surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form a first opening and a second opening; Etching through the first opening in the photoresist and the hard mask to form a first sub-metal gate cut line in a P-type metal oxide semiconductor (PMOS) region of the substrate, the first sub-metal gate cut line passing through the metal gate and STI region; Etching through the second opening in the photoresist and hard mask to form a second sub-metal gate cut line in an N-type metal oxide semiconductor (NMOS) region of the substrate, the second sub-metal gate cut line passing through the metal gate and STI region; and stripping the photoresist to expose a surface of the hard mask. 18. Filling the first sub-metal gate cut line and the second sub-metal gate cut line with a first stressor material; depositing a first stressor material within the first sub-metal gate cut line and the second sub-metal gate cut line; depositing a first stressor material on the exposed surface of the hard mask; and polishing the first stressor material and the hard mask on the surface of the metal gate. 19. Ion implantation is depositing a photoresist (PR) on a surface of the metal gate and on portions of the first stressor material; patterning the photoresist to form an opening; 19. The method of any of clauses 16-18, including implanting an ion implant species through the opening in the photoresist to convert the first stressor material in the second sub-metal gate cut line to a second stressor material. 20. The method of clause 19, wherein the ion implantation species include fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

[0096] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "above" and "below" are used in reference to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Furthermore, if placed on its side, above and below may refer to the side of the substrate or electronic device. Furthermore, the scope of the present application is not intended to be limited to the particular configurations of processes, machines, fabrication, and compositions of matter, means, methods, and steps described herein. Those skilled in the art will readily understand from this disclosure that existing or later-developed processes, machines, fabrication, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0097] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0098] The various illustrative logic blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0099] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside as discrete components in a user terminal.

[0100] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specific program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of medium.Disk and disc, as used herein, include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0101] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0102] 500 Fin Field Effect Transistor (FinFET) 502 board 504 Shallow Trench Isolation (STI) region 510 (510-1, 510-2) First fin structure 520 (520-1, 520-2) Second fin structure 530 (530-1, 530-2, 530-3) Metal Gate 540 1st Sub Metal Gate Cut Line 550 Second Sub Metal Gate Cut Line

Claims

1. A fin field effect transistor (FinFET), comprising: A substrate; a shallow trench isolation (STI) region on the substrate; a first fin structure on the substrate extending through the STI region; a second fin structure on the substrate extending through the STI region; a metal gate over the STI region, the first fin structure, and the second fin structure, the metal gate including a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

2. The FinFET of claim 1 , wherein the first stressor material comprises a compressive strain and the second stressor material comprises a tensile strain.

3. The FinFET of claim 2 , wherein the first fin structure comprises a P-type metal oxide semiconductor (PMOS) region and the second fin structure comprises an N-type metal oxide semiconductor (NMOS) region.

4. The FinFET of claim 1 , wherein the first sub-metal gate cut line and the second sub-metal gate cut line extend through the metal gate and into the STI region.

5. The FinFET of claim 1 , wherein the first sub-metal gate cut line and the second sub-metal gate cut line extend through the metal gate, through the STI region, and into the substrate.

6. The FinFET of claim 1 , wherein the metal gate comprises a high-k metal gate.

7. the first fin structure: a first P-type metal oxide semiconductor (PMOS) region; a second PMOS region, wherein the first sub-metal gate cut line is coupled between the first PMOS region and the second PMOS region.

8. the second fin structure: a first N-type metal oxide semiconductor (NMOS) region; a second NMOS region, wherein the second sub-metal gate cut line is coupled between the first NMOS region and the second NMOS region.

9. The first stressor material and the second stressor material are silicon dioxide (SiO ２ ), silicon dioxide fluoride (SiO ２ : F), silicon dioxide (SiO ２ :N), silicon germanium dioxide (SiO ２ :Ge), silicon oxynitride (SiON), silicon fluoride oxynitride (SiON:F), silicon germanium oxynitride (SiON:Ge), silicon nitride (SiN), silicon germanium nitride (SiN:Ge), hafnium oxide (HfO ２ ), hafnium zirconium oxide (HfZrO ２ ), zirconium oxide (ZrO ２ ), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO ２ ), germanium oxide (GeOx), and / or silicon germanium oxide (SiGeOx).

10. The FinFET of claim 1 , wherein the second stressor material comprises an ion implant species comprising fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

11. 1. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on the substrate and on the first fin structure and the second fin structure on the substrate; applying a line cut to separate the metal gates to form a first sub-metal gate cut line and a second sub-metal gate cut line; filling the first sub-metal gate cut line with a first stressor material; filling the second sub-metal gate cut line with a second stressor material different from the first stressor material.

12. applying the line cut, depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form the first sub-metal gate cut line through the metal gate and the STI region in a P-type metal oxide semiconductor (PMOS) region of the substrate; and stripping the photoresist to expose a surface of the hard mask.

13. filling the first sub-metal gate cut line with the first stressor material; depositing the first stressor material within the first sub-metal gate cut line; depositing the first stressor material on the exposed surface of the hard mask; and polishing the first stressor material and the hard mask on the surface of the metal gate.

14. applying the line cut, depositing a hard mask over a surface of the metal gate and over a portion of the first stressor material; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form the second sub-metal gate cut line in an N-type metal oxide semiconductor (NMOS) region of the substrate, the second sub-metal gate cut line passing through the metal gate and the STI region; and stripping the photoresist to expose a surface of the hard mask.

15. filling the second sub-metal gate cut line with the second stressor material; depositing the second stressor material within the second sub-metal gate cut line; depositing the second stressor material on the exposed surface of the hard mask; and polishing the second stressor material and the hard mask on the surface of the metal gate.

16. 1. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on the substrate and on the first fin structure and the second fin structure on the substrate; applying a line cut to separate the metal gates to form a first sub-metal gate cut line and a second sub-metal gate cut line; filling the first sub-metal gate cut line and the second sub-metal gate cut line with a first stressor material; implanting ions into the first stressor material in the second sub-metal gate cut line to transform the first stressor material into a second stressor material different from the first stressor material.

17. applying the line cut, depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form a first opening and a second opening; etching through the photoresist and the first opening in the hard mask to form the first sub-metal gate cut line in a P-type metal oxide semiconductor (PMOS) region of the substrate, the first sub-metal gate cut line passing through the metal gate and the STI region; etching through the photoresist and the second opening in the hard mask to form the second sub-metal gate cut line in an N-type metal oxide semiconductor (NMOS) region of the substrate, the second sub-metal gate cut line passing through the metal gate and the STI region; and stripping the photoresist to expose a surface of the hard mask.

18. filling the first sub-metal gate cut line and the second sub-metal gate cut line with the first stressor material; depositing the first stressor material within the first sub-metal gate cut line and the second sub-metal gate cut line; depositing the first stressor material on the exposed surface of the hard mask; and polishing the first stressor material and the hard mask on the surface of the metal gate.

19. Injecting ions depositing a photoresist (PR) on a surface of the metal gate and on portions of the first stressor material; patterning the photoresist to form an opening; 17. The method of claim 16, further comprising: implanting an ion implant species through the opening in the photoresist to convert the first stressor material in the second sub-metal gate cut line to the second stressor material.

20. 20. The method of claim 19, wherein the ion implant species include fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

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